-------------------------------------------------------------------------------
-- Title      : ni_exclude_in
-- Project    : Network Interface (NI) for the ALICE TRD TRAP2
-------------------------------------------------------------------------------
-- File       : ni_exclude_in.vhd
-- Author     : Rolf Schneider  <rolf.schneider@kip.uni-heidelberg.de>
-- Company    : University Heidelberg - KIP
-- Last update: 2003-04-29
-- Platform   : Synopsys - v2003.03
-------------------------------------------------------------------------------
-- Description: exlude max two Bits from incoming 10 bit data word
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/02/27  1.0      schneide        Created
-------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
entity ni_exclude_in is
  generic (
    width    : integer := 10;                           -- word width incl. spare & parity bit
    depth    : integer := 4;                            -- position selection word width
    inv_bits : integer := 0);                           -- position selection word width
  port (
    din      : in  std_logic_vector(width-1 downto 0);  -- data in
    sel_s    : in  std_logic_vector(depth-1 downto 0);  -- the spare bit position,
                                                        -- will be selected out first ("1001")
    sel_p    : in  std_logic_vector(depth-1 downto 0);  -- the parity bit position,
                                                        -- will be selected out next ("1000")
    dout     : out std_logic_vector(width-3 downto 0);  -- data out
    prty_bit : out std_logic);                          -- parity bit output
end ni_exclude_in;

----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture v of ni_exclude_in is

  -- SIGNALS ---------------------------------------------------------------------------------------
  signal q1pass  : std_logic_vector(width-2 downto 0);
  signal q2pass  : std_logic_vector(width-3 downto 0);
  signal parity  : std_logic;
  signal xordin  : std_logic_vector(din'range);
  signal din_cor : std_logic_vector(din'range);

  -- STRUCTURE -------------------------------------------------------------------------------------
begin

ib: if inv_bits=1 generate
  xordin <= "1110111111";
end generate;

ibn: if inv_bits /=1 generate
  xordin <= "0000000000";
end generate;

  din_cor <= din xor xordin;
  -- cut spare bit out of incoming width bit data word at position sel_s
  -- result q1pass is a width-1 bit word
  U_excl_spare: process(din_cor, sel_s)
  begin
    for i in q1pass'range loop
      if i < unsigned(sel_s) then q1pass(i) <= din_cor(i);
                             else q1pass(i) <= din_cor(i+1); end if;
    end loop;
  end process;

  -- cut parity bit out of data word q1pass at position sel_p
  -- result is a width-2 bit word + parity bit
  U_excl_prty: process(q1pass, sel_p)
  begin
    parity <= q1pass(q1pass'high);
    for i in q2pass'range loop
      if i < unsigned(sel_p) then q2pass(i) <= q1pass(i);
                             else q2pass(i) <= q1pass(i+1); end if;
      if i = unsigned(sel_p) then parity    <= q1pass(i); end if;
    end loop;
  end process;

  -- set entity outputs
  prty_bit <= parity;
  dout <= q2pass;

end;