library IEEE; use IEEE.std_logic_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; entity ni2res is generic (with_mid_reg : Integer := 1; inv_bits : integer := 0); port ( clk : in std_logic; pureset_n : in std_logic; -- asynchronous reset reset_n : in std_logic; -- asynchronous reset ena_anlg : in std_logic; -- enable TLK & LTC strobe : in std_logic; -- incoming DDR strobe signal lvds_data_in : in std_logic_vector( 9 downto 0); -- incoming DDR data sync. to strobe sel_s : in std_logic_vector( 3 downto 0); sel_p : in std_logic_vector( 3 downto 0); testpatt : in std_logic; naddr : out std_logic_vector(14 downto 0); pcnt : out std_logic_vector(13 downto 0); valid : out std_logic; rdata : out std_logic_vector(15 downto 0) -- data output, sync. to internal clk ); end ni2res; architecture a of ni2res is component counter is GENERIC (N : Integer := 10; CLIP : Integer := 1); port ( clk : in std_logic; clk_en : in std_logic; sclr : in std_logic; aclr_n : in std_logic; Q : out std_logic_vector(N-1 downto 0) ); end component; component ni_resync is generic( width : integer := 10; -- width of the external interface with_out_reg : integer := 1); port( clk : in std_logic; -- internal clock clear_n : in std_logic; -- synchronous clear strobe : in std_logic; -- incoming DDR strobe signal data_in : in std_logic_vector(width-1 downto 0); -- incoming DDR data sync. to strobe valid : out std_logic; -- outgoing data valid signal data_out : out std_logic_vector((2*width)-1 downto 0)); -- data output, sync. to internal clk end component; component ni_exclude_in is generic ( width : integer := 10; -- word width incl. spare & parity bit depth : integer := 4; -- position selection word width inv_bits : integer := 0); port ( din : in std_logic_vector(width-1 downto 0); -- data in sel_s : in std_logic_vector(depth-1 downto 0); -- the spare bit position, -- will be selected out first ("1001") sel_p : in std_logic_vector(depth-1 downto 0); -- the parity bit position, -- will be selected out next ("1000") dout : out std_logic_vector(width-3 downto 0); -- data out prty_bit : out std_logic); -- parity bit output end component; component reg_clr is generic(Ndata : Integer := 32); port ( clk : in std_logic; ce : in std_logic; rst_n : in std_logic; d : in std_logic_vector(Ndata-1 downto 0); q : out std_logic_vector(Ndata-1 downto 0) ); end component; component patt_reg is generic (dir : Integer := 0); port ( clk : in std_logic; ce : in std_logic; tge : in std_logic; tgm : in std_logic; -- test generator mode rst_n : in std_logic; sclrn : in std_logic; d : in std_logic_vector(7 downto 0); q : out std_logic_vector(7 downto 0) ); end component; signal data_out : std_logic_vector(19 downto 0); --signal data_sdr : std_logic_vector(19 downto 0); signal rdata_pos : std_logic_vector( 7 downto 0); signal rdata_neg : std_logic_vector( 7 downto 0); signal rdata_neg_or : std_logic_vector( 7 downto 0); signal rdata_pos_or : std_logic_vector( 7 downto 0); signal par_cnt_pos : std_logic_vector(pcnt'length / 2 -1 downto 0); signal par_cnt_neg : std_logic_vector(pcnt'length / 2 -1 downto 0); signal ce_prty_bit_neg : std_logic; signal ce_prty_bit_pos : std_logic; signal prty_bit_neg_r : std_logic; signal prty_bit_pos_r : std_logic; signal prty_bit_pos : std_logic; signal prty_bit_neg : std_logic; --signal valid0 : std_logic; signal valid1 : std_logic; signal valid2 : std_logic; signal LogH : std_logic; signal LogL : std_logic; --signal clear : std_logic; signal pattvalid : std_logic; signal pattcount : std_logic_vector(4 downto 0); begin LogH <= '1'; LogL <= '0'; -- clear <= not reset_n; nires: ni_resync generic map( width => 10, with_out_reg => with_mid_reg) port map( clk => clk, clear_n => reset_n, strobe => strobe, data_in => lvds_data_in, valid => valid1, -- valid => valid0, -- data_out => data_sdr); data_out => data_out); -- mreg: if with_mid_reg = 1 generate -- rg_mid: reg_clr -- generic map(Ndata => 20) -- port map(clk => clk, -- ce => LogH, -- rst_n => LogH, -- d => data_sdr, -- q => data_out -- ); -- -- mreg_we: process(clk) -- begin -- if clk'event and clk= '1' then -- valid1 <= valid0; -- end if; -- end process; -- end generate; -- -- nmreg: if with_mid_reg /= 1 generate -- data_out <= data_sdr; -- valid1 <= valid0; -- end generate; excl_pos: ni_exclude_in generic map(inv_bits => inv_bits) port map( din => data_out(9 downto 0), sel_s => sel_s, -- will be selected out first ("1001") sel_p => sel_p, -- will be selected out next ("1000") dout => rdata_pos, prty_bit => prty_bit_pos); excl_neg: ni_exclude_in generic map(inv_bits => inv_bits) port map( din => data_out(19 downto 10), sel_s => sel_s, -- will be selected out first ("1001") sel_p => sel_p, -- will be selected out next ("1000") dout => rdata_neg, prty_bit => prty_bit_neg); --rg_pos: reg_clr --generic map(Ndata => 8) --port map(clk => clk, -- ce => valid1, -- rst_n => LogH, -- d => rdata_pos, -- q => rdata_pos_or -- ); -- --rg_neg: reg_clr --generic map(Ndata => 8) --port map(clk => clk, -- ce => valid1, -- rst_n => LogH, -- d => rdata_neg, -- q => rdata_neg_or -- ); -- rg_pos: patt_reg generic map(dir => 0) port map(clk => clk, ce => valid1, tge => valid2, tgm => testpatt, rst_n => pureset_n, sclrn => ena_anlg, d => rdata_pos, q => rdata_pos_or ); rg_neg: patt_reg generic map(dir => 1) port map(clk => clk, ce => valid1, tge => valid2, tgm => testpatt, rst_n => pureset_n, sclrn => ena_anlg, d => rdata_neg, q => rdata_neg_or ); rdata <= rdata_neg_or & rdata_pos_or; pattvalid <= '0' when pattcount = "00000" else '1'; process(clk) begin if clk'event and clk= '1' then if testpatt='1' then valid2 <= pattvalid and ena_anlg; else valid2 <= valid1 and ena_anlg; end if; pattcount <= pattcount + 1; prty_bit_neg_r <= prty_bit_neg; prty_bit_pos_r <= prty_bit_pos; ce_prty_bit_neg <= valid2 and (prty_bit_neg_r xor rdata_neg_or(7) xor rdata_neg_or(6) xor rdata_neg_or(5) xor rdata_neg_or(4) xor rdata_neg_or(3) xor rdata_neg_or(2) xor rdata_neg_or(1) xor rdata_neg_or(0) ); ce_prty_bit_pos <= valid2 and (prty_bit_pos_r xor rdata_pos_or(7) xor rdata_pos_or(6) xor rdata_pos_or(5) xor rdata_pos_or(4) xor rdata_pos_or(3) xor rdata_pos_or(2) xor rdata_pos_or(1) xor rdata_pos_or(0) ); end if; end process; valid <= valid2; pcntpos: counter GENERIC map(N => par_cnt_pos'length, CLIP => 1) port map( clk => clk, clk_en => ce_prty_bit_pos, sclr => LogL, aclr_n => reset_n, Q => par_cnt_pos ); pcntneg: counter GENERIC map(N => par_cnt_neg'length, CLIP => 1) port map( clk => clk, clk_en => ce_prty_bit_neg, sclr => LogL, aclr_n => reset_n, Q => par_cnt_neg ); cnttot: counter GENERIC map(N => naddr'length, CLIP => 0) port map( clk => clk, clk_en => valid2, sclr => LogL, aclr_n => reset_n, Q => naddr ); pcnt <= par_cnt_pos & par_cnt_neg; end;