LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

-- Configuration IO space

-- config reg 0 at write addresses 0,2,4,6, read address 4
-- bits     reset value
-- 3..0     8           position of the parity bit, from 0 to 9 (in TRAP default 8)
-- 7..4     9           position of the spare bit, from 0 to 9 (in TRAP default 9)
--                      or
--                      when 10 => PRBSEN of TLK2501 is high (test pattern in TLK)
--                      when 11 => WP pin of EEPROM is low and writing to EEPROM is possible
--                      when 12 => the CPLD sends a test pattern to the TLK2501
--                      when 14 => SD2ANL of the TLK2501 & LTC is 0
--                      (power off for TLK2501 and LTC)
-- Note:
--  1) writing to conf reg 0 clears the resynchronization unit
--  2) as far as input RESET is low, the power to the TLK and LTC is off

entity sercnf is
     generic (version  : Integer := 0;
              hamming0 : Integer := 0; -- 4 bit low
              hamming1 : Integer := 0; -- 4 bit high
              hamming8 : Integer := 0); -- 8bit

port(
    DISABLE  : in    std_logic;
    TCK      : in    std_logic;
    TDI      : in    std_logic;
    TDO      : out   std_logic;
    TDO_oe   : out   std_logic;
    TMS      : in    std_logic;
    reset_n  : in    std_logic;
    rstout_n : out   std_logic;
    pparit   : out   std_logic_vector(3 downto 0);
    pspare   : out   std_logic_vector(3 downto 0);
    SD2ANL   : out   std_logic;
    PRBSEN   : out   std_logic;
    TSTPATT  : out   std_logic;
    WP_EEP   : out   std_logic;
    rd0      : in    std_logic_vector(7 downto 0);
    rd1      : in    std_logic_vector(7 downto 0);
    rd2      : in    std_logic_vector(7 downto 0);
    rd3      : in    std_logic_vector(7 downto 0)
    );
end sercnf;

architecture a of sercnf is

component hamm_enc_4b is

port(
     data : in std_logic_vector(3 downto 0);
     code : out std_logic_vector(6 downto 0)
    );
end component;

component hamm_dec_4b is

port(
    code : in std_logic_vector(6 downto 0);
    data : out std_logic_vector(3 downto 0);
    status   : out   std_logic
    );
end component;

component hamm_enc_8b is
        port
                (
                        data : in std_logic_vector(7 downto 0);
                        code : out std_logic_vector(11 downto 0)
                );
end component;

component hamm_dec_8b is
        port
                (
                        code : in std_logic_vector(11 downto 0);
                        data : out std_logic_vector(7 downto 0);
                        status : out std_logic
                );
end component;

signal cmdreg        : std_logic_vector(3 downto 0);
signal shreg         : std_logic_vector(7 downto 0);
signal creg0i        : std_logic_vector(3 downto 0);
signal creg1i        : std_logic_vector(3 downto 0);
signal creg0_ini     : std_logic_vector(3 downto 0);
signal creg1_ini     : std_logic_vector(3 downto 0);
signal shreg_hm0     : std_logic_vector(3+3*hamming0 downto 0);
signal shreg_hm1     : std_logic_vector(3+3*hamming1 downto 0);
signal creg0hm       : std_logic_vector(3+3*hamming0 downto 0);
signal creg1hm       : std_logic_vector(3+3*hamming1 downto 0);
signal creg0_ini_hm  : std_logic_vector(3+3*hamming0 downto 0);
signal creg1_ini_hm  : std_logic_vector(3+3*hamming1 downto 0);

signal creg_hm       : std_logic_vector(11 downto 0);
signal creg_ini_hm   : std_logic_vector(11 downto 0);
signal creg_ini      : std_logic_vector( 7 downto 0);
signal creg_i        : std_logic_vector( 7 downto 0);
signal shreg_hm      : std_logic_vector(11 downto 0);

signal status   : std_logic_vector(1 downto 0);
signal ver      : std_logic_vector(5 downto 0);
signal read_byte: std_logic_vector(7 downto 0);
signal read_bit : std_logic;
signal TDIi     : std_logic;
signal TMSi     : std_logic;
signal rstout_n_i : std_logic;

signal bitcnt   : std_logic_vector(2 downto 0);

begin
    creg0_ini <= "1000"; -- parity pos 8
    creg1_ini <= "1001"; -- spare  pos 9
    TMSi <= TMS or DISABLE;
    -- only for simulation!
    with TDI select
    TDIi <= '1' when '1' | 'H',
            '0' when '0',
            '-' when others;

    process(TCK)
    begin
        if TCK'event and TCK='1' then
            shreg <= TDIi & shreg(shreg'high downto shreg'low+1); -- shift right, LSB first
        end if;
    end process;

    process(TCK, TMSi)
    begin
        if TMSi='0' then bitcnt <= (others => '0');
                         rstout_n_i <= '1';
        elsif TCK'event and TCK='0' then
            bitcnt <= bitcnt + 1;
            if bitcnt="001" and cmdreg(cmdreg'high)='1' then
                rstout_n_i <= '0';
            end if;
            if bitcnt="111" then
                rstout_n_i <= '1';
            end if;
        end if;
    end process;

    rstout_n <= rstout_n_i and reset_n;


    process(TMSi, reset_n, creg0_ini_hm, creg1_ini_hm, creg_ini_hm)
    begin
        if reset_n = '0' then
            creg0hm <= creg0_ini_hm;
            creg1hm <= creg1_ini_hm;
            creg_hm <= creg_ini_hm;
            cmdreg <= "0111";
        elsif TMSi'event and TMSi='1' then
            -- command
            if TDIi = '1' then
                cmdreg <= shreg(shreg'high downto shreg'high-cmdreg'length+1);
            -- DATA
            else
                if cmdreg(cmdreg'high)='1' then
                -- write
                case cmdreg(cmdreg'high-1 downto cmdreg'low) is
                when  "000" | "010" | "100" | "110" =>
                                                    creg0hm <= shreg_hm0;
                                                    creg1hm <= shreg_hm1;
                                                    creg_hm <= shreg_hm;
                when  "001" | "011" | "101" | "111" => NULL;
                when others => creg0hm <= (others => '-');
                               creg1hm <= (others => '-');
                               creg_hm <= (others => '-');
                end case;
                -- else read
                end if;
                cmdreg(cmdreg'high) <= '0';
            end if;
        end if;
    end process;

    ver <= conv_std_logic_vector(version,6);

    with cmdreg(cmdreg'high-1 downto cmdreg'low) select
    read_byte <= rd0    when "000",
                 rd1    when "001",
                 rd2    when "010",
                 rd3    when "011",
                 creg1i & creg0i when "100",
                 creg1i & creg0i when "101",
                 status & ver    when "110",
                 status & ver    when "111",
                 (others => '-') when others;

    with bitcnt select
    read_bit  <= read_byte(0) when "000",
                 read_byte(1) when "001",
                 read_byte(2) when "010",
                 read_byte(3) when "011",
                 read_byte(4) when "100",
                 read_byte(5) when "101",
                 read_byte(6) when "110",
                 read_byte(7) when "111",
                 '-'          when others;

    TDO    <= read_bit;
    TDO_oe <= TCK and TMSi;

whm0: if (hamming0 = 1) and (hamming8 /= 1) generate

henc0: hamm_enc_4b
port map(
    data   => creg0_ini,
    code   => creg0_ini_hm
    );

henci0: hamm_enc_4b
port map(
    data   => shreg(3 downto 0),
    code   => shreg_hm0
    );

hdec0: hamm_dec_4b

port map(
    code   => creg0hm,
    data  => creg0i,
    status   => status(0)
    );

end generate;


whm1: if (hamming1 = 1) and (hamming8 /= 1) generate

henc1: hamm_enc_4b

port map(
    data   => creg1_ini,
    code   => creg1_ini_hm
    );

henci1: hamm_enc_4b

port map(
    data   => shreg(7 downto 4),
    code   => shreg_hm1
    );

hdec1: hamm_dec_4b

port map(
    code   => creg1hm,
    data   => creg1i,
    status   => status(1)
    );

end generate;

nhm0: if (hamming0 /= 1) and (hamming8 /= 1) generate

   shreg_hm0 <= shreg(3 downto 0);
   creg0i <= creg0hm;
   creg0_ini_hm <= creg0_ini;

end generate;

nhm1: if (hamming1 /= 1) and (hamming8 /= 1) generate

   shreg_hm1 <= shreg(7 downto 4);
   creg1i <= creg1hm;
   creg1_ini_hm <= creg1_ini;

end generate;

hm8: if hamming8 = 1 generate

    creg_ini <= creg1_ini & creg0_ini;

henc8: hamm_enc_8b
port map(
    data   => creg_ini,
    code   => creg_ini_hm
    );

henci8: hamm_enc_8b

port map(
    data   => shreg,
    code   => shreg_hm
    );

hdec8: hamm_dec_8b

port map(
    code   => creg_hm,
    data   => creg_i,
    status   => open
    );
    status <= "00";

    creg1i <= creg_i(7 downto 4); -- for readback
    creg0i <= creg_i(3 downto 0);

end generate;

    pparit <= creg0i;
    pspare <= creg1i;

--  if 14 then SD2ANL of the TLK2501 & LTC is 0
--    SD2ANL  <= '0' when creg1i = "1110" else reset_n;
    SD2ANL  <= '0' when creg1i = "1110" else '1';

--  if 12, the CPLD sends a test pattern to the TLK2501
    TSTPATT <= '1' when creg1i = "1100" else '0';

--  if 11, WP pin of EEPROM is low and writing to EEPROM is possible
    WP_EEP  <= '0' when creg1i = "1011" else '1';

--  if 10, PRBSEN of TLK2501 is high (test pattern in TLK)
    PRBSEN  <= '1' when creg1i = "1010" else '0';

end;