library ieee;
use ieee.std_logic_1164.all;

entity hamm_enc_8b is
        port
                (
                        data : in std_logic_vector(7 downto 0);
                        code : out std_logic_vector(11 downto 0)
                );
end hamm_enc_8b;


architecture Behavioural of hamm_enc_8b is
signal hamming : std_logic_vector(3 downto 0);
begin
----------------------------------------------------------------------
-- HAMMING ENCODER (12,8)
----------------------------------------------------------------------
  -- HAMMING BITS -------------------------------------------------------------
  hamming(0) <=     data( 0) xor data( 1) xor data( 3) xor data( 4)
                xor data( 6) ;
  hamming(1) <=     data( 0) xor data( 2) xor data( 3) xor data( 5)
                xor data( 6) ;
  hamming(2) <=     data( 1) xor data( 2) xor data( 3) xor data( 7)
                ;
  hamming(3) <=     data( 4) xor data( 5) xor data( 6) xor data( 7)
                ;

  -- OUTPUT CODE --------------------------------------------------------------
  code <= data( 7) & data( 6) & data( 5) & data( 4) & hamming(3) & data( 3) & data( 2) & data( 1) & hamming(2) & data( 0) & hamming(1) & hamming(0) ;
end Behavioural;