------------------------------------------------------------------------------------------------------------------ -- -- Projekt I2C SLAVE -- mit Anschluss an existierendes Design -- -- Autor Jörg Betz -- -- Datum 13.09.2005 -- -- -- Info top- entity -- -- -- Historie ------------------------------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.i2c_syn_pkg.all; entity top is generic (version : integer range 1 to 256 := 1); port ( clk_t : in std_logic; reset_t : in std_logic; -- active LOW -- I2C Takt und Daten (SDA ist open Drain) scl_t : in std_logic; sda_t : inout std_logic; -- Multiplexer- Eingänge I_1_t : in std_logic_vector(7 downto 0); I_2_t : in std_logic_vector(7 downto 0); I_3_t : in std_logic_vector(7 downto 0); I_4_t : in std_logic_vector(7 downto 0); -- Output- Register reg_1 : out std_logic_vector(7 downto 0); reg_2 : out std_logic_vector(7 downto 0) ); end; architecture behave of top is -- Multiplexer Eingänge signal I_0_t : std_logic_vector(7 downto 0); signal I_5_t : std_logic_vector(7 downto 0); signal I_6_t : std_logic_vector(7 downto 0); constant slv_adr_t : SLV_ADR_TYPE := 100; -- interne TX-Buffer- Signale signal tx_data_i : BYTE; signal tx_wr_i : std_logic; signal tx_empty_i : std_logic; -- interne RX_Buffer- Signale signal rx_vld_i : std_logic; signal rx_data_i : BYTE; signal rx_ack_i : std_logic; -- internes Signal für Ausgang Multiplexer signal y_i : std_logic_vector(7 downto 0); -- interne Output- Register signal reg_1_i : std_logic_vector(7 downto 0); signal reg_2_i : std_logic_vector(7 downto 0); -- Reset signal reset :std_logic; signal s_i :std_logic_vector(2 downto 0); signal so_i: std_logic; signal busy_write_i: std_logic; signal tmp : std_logic; -- Komponenten Deklaration: component i2c_slave generic (SDA_DELAY : integer range 1 to 16); port ( clk : in std_logic; reset : in std_logic; scl : in std_logic; sda : inout std_logic; slv_adr : in SLV_ADR_TYPE; tx_data : in BYTE; tx_wr : in std_logic; tx_empty : out std_logic; rx_data : out BYTE; rx_vld : buffer std_logic; rx_ack : in std_logic; busy : out std_logic; busy_write : out std_logic ); end component; component multiplexer port ( I_0 : in std_logic_vector (7 downto 0); I_1 : in std_logic_vector (7 downto 0); I_2 : in std_logic_vector (7 downto 0); I_3 : in std_logic_vector (7 downto 0); I_4 : in std_logic_vector (7 downto 0); I_5 : in std_logic_vector (7 downto 0); I_6 : in std_logic_vector (7 downto 0); s : in std_logic_vector (2 downto 0); y : out std_logic_vector (7 downto 0) ); end component; begin --reset <= not(reset_t); reset <= reset_t; I_0_t <= conv_std_logic_vector(version,8); I_5_t <= reg_1_i; I_6_t <= reg_2_i; -- Instanziierung der Komponenten BUS_System: i2c_slave generic map (SDA_DELAY => 5) port map ( clk => clk_t, reset => reset, scl => scl_t, sda => sda_t, slv_adr => slv_adr_t, tx_data => tx_data_i, tx_wr => tx_wr_i, tx_empty => tx_empty_i, rx_data => rx_data_i, rx_vld => rx_vld_i, rx_ack => rx_ack_i, busy => open, busy_write => busy_write_i); Mult: multiplexer port map( I_0 => I_0_t, I_1 => I_1_t, I_2 => I_2_t, I_3 => I_3_t, I_4 => I_4_t, I_5 => I_5_t, I_6 => I_6_t, s => s_i, y => y_i); process(clk_t, reset) begin if reset = '1' then rx_ack_i <= '0'; s_i <= "000"; elsif rising_edge(clk_t) then if rx_vld_i = '1' then rx_ack_i <= '1'; s_i <= rx_data_i (2 downto 0); -- letzen 3 Bits von rx_data werden an Multiplexer übertragen else rx_ack_i <= '0'; S_i <= s_i; end if; end if; end process; process(clk_t, reset) begin if reset = '1' then tx_wr_i <= '0'; tx_data_i <= "00000000"; elsif rising_edge(clk_t) then if tx_empty_i = '1' then -- wenn tx- Buffer leer: Einlesen eines neuen Wertes. tx_wr_i <= '1'; else tx_wr_i <= '0'; end if; tx_data_i <= y_i; -- Zuweisung mit jeder steigenden Flanke end if; -- --> Einlesen in Transfer_Buffer erfolgt 3 clk nachdem ld_tx_shiftreg_q gesetzt wurde end process; -- Select für Output- Register process (clk_t, reset) begin if reset = '1' then so_i <= '0'; tmp <= '0'; elsif rising_edge(clk_t) then if (busy_write_i = '1') then if (tmp = '0'and rx_vld_i = '1') then so_i <= rx_data_i(0); tmp <= '1'; else so_i <= so_i; end if; else tmp <= '0'; end if; else so_i <= so_i; end if; end process; -- Flipflop Register 1 process (rx_vld_i, reset) begin if reset = '1' then reg_1_i <= (others => '0'); elsif rising_edge(rx_vld_i) then if (tmp = '1' and so_i = '0' ) then reg_1_i <= rx_data_i; else reg_1_i <= reg_1_i; end if; end if; end process; reg_1 <= reg_1_i; -- Flipflop Register 2 process (rx_vld_i, reset) begin if reset = '1' then reg_2_i <= (others => '0'); elsif rising_edge(rx_vld_i) then if (tmp = '1' and so_i = '1' ) then reg_2_i <= rx_data_i; else reg_2_i <= reg_2_i; end if; end if; end process; reg_2 <= reg_2_i; end behave;