LIBRARY IEEE;
library trap2;
USE IEEE.STD_LOGIC_1164.all;

entity top_testbench is
generic(
    period_time_cpld : time    := 8 ns; -- or 8.32 ns
    Ntrackl          : Integer :=   10; -- 16 bit words tracklet data
    Ndata            : Integer := 1024; -- 16 bit words raw data
    IdlePeriod       : Integer :=   25; --
    Nt               : Integer :=   12; -- bits in the timer
    TimeT2D          : integer :=  250; -- clocks delay from tracklet to raw data (in 125MHz)
    PatternId        : Integer :=    0  -- from 0 to 15
       );
end top_testbench;

architecture struct of top_testbench is

component top_ni is
generic(
        Ntrackl       : Integer :=   10; -- 16 bit words tracklet data
        Ndata         : Integer := 1023; -- 16 bit words raw data
        IdlePeriod    : Integer :=   25; --
        Nt            : Integer :=   12; -- bits in the timer
        TimeT2D       : integer :=  250; -- clocks delay from tracklet to raw data (in 125MHz)
        PatternId     : Integer :=    0  -- from 0 to 15
        );
  port (
           -- pin 3, SD2x
           reset_n              : in    std_logic;
           start                : in    std_logic;
           -- pin 89 the serializer clock, must be not slower than NI_STR
           clk                  : in    std_logic; -- is the clock
           -- to/from TLK2501
           -- pin 44
           TESTEN               : out   std_logic; -- must be low
           -- pin 47
           PRBSEN               : out std_logic;
           -- pin 48
           LCKREFN              : out std_logic; -- must be low for transmitter only
           -- pin 49
           ENABLE               : out std_logic;
           -- pin 53
           LOOPEN               : out std_logic;
           -- pin 50
           TX_ER                : out std_logic;
           -- pin 54
           TX_EN                : out   std_logic;
           -- pins 55, 56, 58, 59, 60, 61, 64, 65, 67, 69, 70, 71, 72, 78, 79, 80
           -- bit  15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
           TXD                  : out   std_logic_vector(15 downto 0);

           -- pin 84
           EN                   : out std_logic;
           -- pin 3
           SD2ANL               : out   std_logic;
           -- I2C
           SCL                  : out   std_logic;
           SDA                  : inout std_logic;

           jTDO                 : out   std_logic
  );
end component;

----------------------------------------------------
-- top_pad signals
----------------------------------------------------
signal  clk_cpld        : std_logic := '0';
signal  start           : std_logic;
signal  RST_n           : std_logic;
signal  TX_EN           : STD_LOGIC;
signal  TX_DATA         : STD_LOGIC_VECTOR(15 downto 0);

begin
 rst_n <= '0' after    0 ns,
          '1' after  500 ns,
          '0' after  1000 ns,
          '1' after  1500 ns;

 start <= '0' after     0 ns,
          '1' after     2 us,
          '0' after     3 us,
          '1' after     5 us,
          '0' after     8 us;

 clk_cpld <= not clk_cpld after period_time_cpld/2;

cpld: top_ni
generic map(
    Ntrackl          => Ntrackl,
    Ndata            => Ndata,
    IdlePeriod       => IdlePeriod,
    Nt               => Nt,
    TimeT2D          => TimeT2D,
    PatternId        => PatternId)
  port map(
    reset_n      => rst_n,
    start        => start,
    clk          => clk_cpld,
    TX_EN        => TX_EN,
    TXD          => TX_DATA
  );

end;