onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider PADS
add wave -noupdate -format Logic /top_testbench/top_pad_inst/rst_n
add wave -noupdate -format Logic /top_testbench/top_pad_inst/clk_adc_in_a
add wave -noupdate -format Logic /top_testbench/top_pad_inst/clk_dig_in_a
add wave -noupdate -format Logic /top_testbench/top_pad_inst/pretrigin_a
add wave -noupdate -format Logic -label SDA /top_testbench/top_pad_inst/sebd1
add wave -noupdate -format Logic -label SCL /top_testbench/top_pad_inst/sebd0
add wave -noupdate -format Logic /top_testbench/top_pad_inst/sebd2
add wave -noupdate -format Logic /top_testbench/top_pad_inst/out_rng
add wave -noupdate -format Logic /top_testbench/top_pad_inst/ser0_din_a
add wave -noupdate -format Logic /top_testbench/top_pad_inst/ser0_dout_a
add wave -noupdate -format Logic /top_testbench/top_pad_inst/ser1_din_a
add wave -noupdate -format Logic /top_testbench/top_pad_inst/ser1_dout_a
add wave -noupdate -divider CPLD
add wave -noupdate -format Logic /top_testbench/cpld/jtck
add wave -noupdate -format Logic /top_testbench/cpld/jtdi
add wave -noupdate -format Logic /top_testbench/cpld/jtms
add wave -noupdate -format Logic /top_testbench/cpld/jtdo
add wave -noupdate -format Logic /top_testbench/clk_cpld
add wave -noupdate -format Logic /top_testbench/tx_en
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/tx_data
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/ni_p4_d_a
add wave -noupdate -format Logic /top_testbench/top_pad_inst/ni_p4_strb_a
add wave -noupdate -format Logic /top_testbench/top_pad_inst/ni_p4_ctrl_a
add wave -noupdate -format Logic /top_testbench/top_pad_inst/ni_p_ctrl_a
add wave -noupdate -format Logic /top_testbench/cpld/ni_str
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/cpld/ni_d
add wave -noupdate -format Logic /top_testbench/cpld/clk
add wave -noupdate -format Logic /top_testbench/cpld/tx_en
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/cpld/txd
add wave -noupdate -format Logic /top_testbench/cpld/ni_strpin
add wave -noupdate -format Logic /top_testbench/cpld/clkpin
add wave -noupdate -format Logic /top_testbench/cpld/ni_d_7xpin
add wave -noupdate -format Logic /top_testbench/cpld/ni_d_6xpin
add wave -noupdate -format Logic /top_testbench/cpld/ni_d_5xpin
add wave -noupdate -format Logic /top_testbench/cpld/ni_d_4xpin
add wave -noupdate -format Logic /top_testbench/cpld/ni_d_3xpin
add wave -noupdate -format Logic /top_testbench/cpld/ni_d_2xpin
add wave -noupdate -format Logic /top_testbench/cpld/ni_d_1xpin
add wave -noupdate -format Logic /top_testbench/cpld/ni_d_0xpin
add wave -noupdate -format Logic /top_testbench/cpld/testen
add wave -noupdate -format Logic /top_testbench/cpld/prbsen
add wave -noupdate -format Logic /top_testbench/cpld/lckrefn
add wave -noupdate -format Logic /top_testbench/cpld/enable
add wave -noupdate -format Logic /top_testbench/cpld/loopen
add wave -noupdate -format Logic /top_testbench/cpld/tx_er
add wave -noupdate -format Logic /top_testbench/cpld/en
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/ce
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/d
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/clk
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/q
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/ce_ipd
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/d_ipd
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/clk_ipd
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/clk_dly
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/d_clk_dly
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/ce_clk_dly
add wave -noupdate -format Logic /top_testbench/cpld/ff_en_i_1/r
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/ce
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/d
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/clk
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/q
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/ce_ipd
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/d_ipd
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/clk_ipd
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/clk_dly
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/d_clk_dly
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/ce_clk_dly
add wave -noupdate -format Logic /top_testbench/cpld/ff_enable_i_1/r
add wave -noupdate -divider {Global SM}
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_low_powr
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_test_chk
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_wait_pre
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_preproc
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_tr_proc
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_tr_send
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_wait_l1
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_zero_sp
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_full_rd
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/st_clear_st
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/irq_acq
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/irq_tst
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/irq_raw
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/irq_clr
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/i2/rst_n
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/i2/start
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/i2/clk
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/i2/q
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/i2/cnt
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/i2/q_i
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/i2/old_start
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/en_clk_mimd
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/counter
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/slow_clk
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/cpu_done
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/slow_clk1
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/slow_clk2
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/slow_clk_pos
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/cntdrift
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/eodriftt
add wave -noupdate -divider GBUS
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/clk_gbusw_tp
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/ck/clk_gbusr_tp
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/gbus_wr_e
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/gbus_addr
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/gbus_dout
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/gbus_d_in
add wave -noupdate -divider IMEM
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/clk_mimd0_tp
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/imem0addr
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/imem0dout
add wave -noupdate -format Literal -label {PRF of CPU0} -radix hexadecimal -expand /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/cpu0_inst/pipe2_inst/prf_inst1/prf_out
add wave -noupdate -format Literal -radix hexadecimal -expand /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/const_inst/cpu0constants
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/const_inst/common_consts
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/clk_gbus
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/clk
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/cpu_clk_en
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/reset_n
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/we
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/addr
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/datain
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/dataout
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_req_soft
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_allow_ext
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_req_hard
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/clear_mask
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/stored_irqs
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/cli_sti_irt
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/shadowflags
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/shadowpc
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/return_from_int
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/nop
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_ip
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/take_int_ip
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/wake_up_req
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/current_state
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/next_state
add wave -noupdate -format Literal -expand /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/ip_mem
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/mask_mem
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/syncreg
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/syncreg_h
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/syncreg_l
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_pointer
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/currentlownumber
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/subaddr
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/ce_n
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/wei
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_allow
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/h_int
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/l_int
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/we_ch
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/we_cl
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/inter_ip_l
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/inter_ip_h
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/cl
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/cl_mask_int
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/cl_mask_cpu
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/cl_mask
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_soft_effec
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_hard_effec
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_hard_effec_i
add wave -noupdate -format Literal /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/int_req
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/delete_all_req
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/delete_low_req
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/rst_irq_pup_n
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/mimd/irq0_ctrl/rst_irq_n
add wave -noupdate -divider SCSN
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/bus_addr
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/bus_dout
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/bus_din
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/bus_ack
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/bus_req
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/bus_we
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/chiprst_n
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/reset_n
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/clk
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/ser0_din
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/ser1_din
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/ser0_dout
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/net_int/ser1_dout
add wave -noupdate -divider GSM
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/start_sim
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/pretr_dec
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/pretrigg1
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/cmd_pretrig
add wave -noupdate -format Literal -radix unsigned /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/cpu_delay
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/cpu_en
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/prep_rdy
add wave -noupdate -format Literal -radix unsigned /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/cntdrift
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/slow_clk_pos
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/clk_mimd0_tp
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/clk_mimd1_tp
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/clk_mimd2_tp
add wave -noupdate -format Logic /top_testbench/top_pad_inst/itrap2top/clk_mimd3_tp
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/a_state
add wave -noupdate -format Literal -radix hexadecimal /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/s2/counter
add wave -noupdate -format Literal -expand /top_testbench/top_pad_inst/itrap2top/fl/cc/top_sm_inst/rej_state
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {751872 ns} 0} {{Cursor 2} {2225262 ns} 0} {{Cursor 3} {25 ns} 0} {{Cursor 4} {1 ns} 0}
WaveRestoreZoom {1845275 ns} {1845384 ns}
configure wave -namecolwidth 262
configure wave -valuecolwidth 84
configure wave -justifyvalue right
configure wave -signalnamewidth 2
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0