LIBRARY IEEE; library trap2; USE IEEE.STD_LOGIC_1164.all; entity top_testbench is generic( period_time : time := 8.32 ns; -- or 8.32 ns period_time_cpld : time := 8 ns; -- or 8.32 ns scsn_ring : integer := 0 ); end top_testbench; architecture struct of top_testbench is component top_pad port( RST_n : in std_logic; -- LVCMOS IRQ_n : in std_logic; -- LVCMOS TCK : in std_logic; -- JTAG pins LVCMOS TDI : in std_logic; -- LVCMOS TMS : in std_logic; -- LVCMOS TDO : out std_logic; -- LVCMOS SER0_DIN_A : inout std_logic; -- Serial link 0 LVDSIN SER0_DIN_B : inout std_logic; -- Serial link 0 LVDSIN SER0_DOUT_A : inout std_logic; -- LVDSOUT SER0_DOUT_B : inout std_logic; -- LVDSOUT SER1_DIN_A : inout std_logic; -- Serial link 1 LVDSIN SER1_DIN_B : inout std_logic; -- Serial link 1 LVDSIN SER1_DOUT_A : inout std_logic; -- LVDSOUT SER1_DOUT_B : inout std_logic; -- LVDSOUT NI_P0_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P0_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P0_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P0_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P0_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P0_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P0_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P0_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P0_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P0_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P1_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P1_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P1_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P1_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P1_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P1_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P1_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P1_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P1_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P1_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P2_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P2_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P2_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P2_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P2_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P2_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P2_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P2_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P2_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P2_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P3_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P3_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSIN NI_P3_STRB_A : inout std_logic; -- Strobe LVDSIN NI_P3_STRB_B : inout std_logic; -- Strobe LVDSIN NI_P3_CTRL_A : inout std_logic; -- Control LVDSOUT NI_P3_CTRL_B : inout std_logic; -- Control LVDSOUT NI_P3_CLKout_A : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P3_CLKout_B : inout std_logic; -- clock out to up-stream MCM LVDSOUT NI_P3_PREout_A : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P3_PREout_B : inout std_logic; -- pretrigger out to up... LVDSOUT NI_P4_D_A : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSOUT NI_P4_D_B : inout std_logic_vector(9 downto 0); -- Network Interface Data LVDSOUT NI_P4_STRB_A : inout std_logic; -- Strobe LVDSOUT NI_P4_STRB_B : inout std_logic; -- Strobe LVDSOUT NI_P4_CTRL_A : inout std_logic; -- Control LVDSIN NI_P4_CTRL_B : inout std_logic; -- Control LVDSIN NI_P_CTRL_A : inout STD_LOGIC; -- ctrl/data swich for opt. transmitter LVDSOUT NI_P_CTRL_B : inout STD_LOGIC; -- LVDSOUT CLK_ADC_IN_A : inout std_logic; -- ADC fast clock (120MHz) LVDSIN CLK_ADC_IN_B : inout std_logic; -- LVDSIN CLK_DIG_IN_A : inout std_logic; -- Digital Clock (120MHz) LVDSIN CLK_DIG_IN_B : inout std_logic; -- (second PLL) LVDSIN PRETRIGin_A : inout std_logic; -- Pretrigger LVDSIN PRETRIGin_B : inout std_logic; -- LVDSIN SEL_CLK : in std_logic_vector(3 downto 0); -- CLK120 divide ratio/Bypass LVCMOS SEBD0 : inout std_logic; -- PIO 0 SEBD1 : inout std_logic; -- PIO 1 SEBD2 : inout std_logic; -- PIO 2 OUT_RNG : in std_logic -- outer padring only LVCMOS ); end component; component ser_int -- the serial master generic ( wait_delay : integer := 100; init_delay : integer := 4095 ); port ( reset_n : in std_logic; clk : in std_logic; ready : in std_logic; ser0din : in std_logic; ser0dout : out std_logic; PRE : out std_logic); end component; component ni_sniffer is generic ( filename : string := "ni_sniff.txt"; -- output filename sel_p : integer := 8; -- position of partiy bit (pass 1) sel_s : integer := 9; -- position of spare bit (pass 2) ol : boolean := FALSE); -- optical link output mode (clk/ctrl) port ( strobe : in std_logic; -- strobe signal (clk in ol mode) data : in std_logic_vector(9 downto 0); -- data incl. partiy & strobe ctrl_out : in std_logic; -- ctrl output to OASE ctrl_in : in std_logic); -- ctrl input of output port end component; component top_ni is port ( -- NI_CTR : in std_logic; -- low means valid data FAULT : in std_logic; jTCK : in std_logic; jTDI : in std_logic; jTDO : out std_logic; jTMS : in std_logic; -- disable JTAG, enable I2C DIS_JTG : in std_logic; -- I2C SCL : out std_logic; SDA : inout std_logic; NI_STR : in std_logic; reset_n : in std_logic; clk : in std_logic; TESTEN : inout std_logic; PRBSEN : inout std_logic; LCKREFN : inout std_logic; ENABLE : inout std_logic; LOOPEN : inout std_logic; TX_ER : inout std_logic; EN : inout std_logic; NI_D : in std_logic_vector(9 downto 0); TX_EN : out std_logic; TXD : out std_logic_vector(15 downto 0) -- LED : out std_logic_vector(10 downto 5) ); end component; -- I2C test component component top is generic (version : integer range 1 to 256 := 1); port ( clk_t : in std_logic; reset_t : in std_logic; -- active LOW -- I2C Takt und Daten (SDA ist open Drain) scl_t : in std_logic; sda_t : inout std_logic; -- Multiplexer- Eingänge I_1_t : in std_logic_vector(7 downto 0); I_2_t : in std_logic_vector(7 downto 0); I_3_t : in std_logic_vector(7 downto 0); I_4_t : in std_logic_vector(7 downto 0); -- Output- Register reg_1 : out std_logic_vector(7 downto 0); reg_2 : out std_logic_vector(7 downto 0) ); end component; ---------------------------------------------------- -- top_pad signals ---------------------------------------------------- signal CLK_in : std_logic := '0'; signal rst_sertb_n : std_logic; signal IRQ_n : std_logic; signal RST_n : std_logic; ----------------------- signal TCK : std_logic; signal TDI : std_logic; signal TMS : std_logic; signal TDO : std_logic; ----------------------- signal SER0_DIN_A : std_logic; signal SER0_DIN_B : std_logic; signal SER0_DOUT_A : std_logic; signal SER0_DOUT_B : std_logic; signal SER1_DIN_A : std_logic; signal SER1_DIN_B : std_logic; signal SER1_DOUT_A : std_logic; signal SER1_DOUT_B : std_logic; ----------------------- signal NI_P0_D_A : std_logic_vector(9 downto 0); signal NI_P0_D_B : std_logic_vector(9 downto 0); signal NI_P0_STRB_A : std_logic; signal NI_P0_STRB_B : std_logic; signal NI_P0_CTRL_A : std_logic; signal NI_P0_CTRL_B : std_logic; signal NI_P0_CLKout_A : std_logic; signal NI_P0_CLKout_B : std_logic; signal NI_P0_PREout_A : std_logic; signal NI_P0_PREout_B : std_logic; signal NI_P1_D_A : std_logic_vector(9 downto 0); signal NI_P1_D_B : std_logic_vector(9 downto 0); signal NI_P1_STRB_A : std_logic; signal NI_P1_STRB_B : std_logic; signal NI_P1_CTRL_A : std_logic; signal NI_P1_CTRL_B : std_logic; signal NI_P1_CLKout_A : std_logic; signal NI_P1_CLKout_B : std_logic; signal NI_P1_PREout_A : std_logic; signal NI_P1_PREout_B : std_logic; signal NI_P2_D_A : std_logic_vector(9 downto 0); signal NI_P2_D_B : std_logic_vector(9 downto 0); signal NI_P2_STRB_A : std_logic; signal NI_P2_STRB_B : std_logic; signal NI_P2_CTRL_A : std_logic; signal NI_P2_CTRL_B : std_logic; signal NI_P2_CLKout_A : std_logic; signal NI_P2_CLKout_B : std_logic; signal NI_P2_PREout_A : std_logic; signal NI_P2_PREout_B : std_logic; signal NI_P3_D_A : std_logic_vector(9 downto 0); signal NI_P3_D_B : std_logic_vector(9 downto 0); signal NI_P3_STRB_A : std_logic; signal NI_P3_STRB_B : std_logic; signal NI_P3_CTRL_A : std_logic; signal NI_P3_CTRL_B : std_logic; signal NI_P3_CLKout_A : std_logic; signal NI_P3_CLKout_B : std_logic; signal NI_P3_PREout_A : std_logic; signal NI_P3_PREout_B : std_logic; signal NI_P4_D_A : std_logic_vector(9 downto 0); signal NI_P4_D_B : std_logic_vector(9 downto 0); signal NI_P4_STRB_A : std_logic; signal NI_P4_STRB_B : std_logic; signal NI_P4_CTRL_A : std_logic; signal NI_P4_CTRL_B : std_logic; signal NI_P_CTRL_A : std_logic; signal NI_P_CTRL_B : std_logic; --------------------------- signal CLK_ADC_IN_A : std_logic; signal CLK_ADC_IN_B : std_logic; signal CLK_DIG_IN_A : std_logic; signal CLK_DIG_IN_B : std_logic; signal PRETRIGin_A : std_logic; signal PRETRIGin_B : std_logic; signal SEL_CLK : std_logic_vector(3 downto 0); signal OUT_RNG : std_logic; signal SEBD0 : std_logic; -- PIO 0 signal SEBD1 : std_logic; -- PIO 1 signal SEBD2 : std_logic; -- PIO 2 signal sniff_p_d_out : STD_LOGIC_VECTOR(9 downto 0); signal sniff_p_d_out_cor : STD_LOGIC_VECTOR(9 downto 0); signal xordin : STD_LOGIC_VECTOR(9 downto 0); signal ordin : STD_LOGIC_VECTOR(9 downto 0); signal sniff_p_ctrl : STD_LOGIC; signal NI_P4_STRB_A_i : STD_LOGIC; signal strb_en : STD_LOGIC := '0'; signal start_ni_i : STD_LOGIC; signal pre_sc : STD_LOGIC; signal clk_cpld : STD_LOGIC := '0'; signal TX_EN : STD_LOGIC; signal TX_DATA : STD_LOGIC_VECTOR(15 downto 0); signal TX_LED : STD_LOGIC_VECTOR( 5 downto 0); signal SCL : std_logic; signal SDA : std_logic; signal rst_i2c : std_logic; signal DIS_JTG : std_logic; signal jTDO : std_logic; signal rst_n_cpld : std_logic; begin ------------------------------------------------------- -- top_pad part ------------------------------------------------------- ------------------------------------ -- clock ------------------------------------ CLK_DIG_IN_A <= '1'; CLK_DIG_IN_B <= not CLK_DIG_IN_A; CLK_ADC_IN_A <= clk_in; CLK_ADC_IN_B <= not CLK_ADC_IN_A; SEL_CLK <= "HHHH"; OUT_RNG <= '1'; SEBD0 <= 'H'; SEBD1 <= 'H'; SEBD2 <= 'H'; -- JTAG stimuli frozen TCK <= '0'; TDI <= '0'; TMS <= '0'; TDO <= 'H'; top_pad_inst: top_pad PORT MAP( RST_n => RST_n, -- in LVCMOS IRQ_n => IRQ_n, -- in LVCMOS TCK => TCK, -- in JTAG pins LVCMOS TDI => TDI, -- in LVCMOS TMS => TMS, -- in LVCMOS TDO => TDO, -- out LVCMOS SER0_DIN_A => SER0_DIN_A, -- inout Serial link 0 LVDSIN SER0_DIN_B => SER0_DIN_B, -- inout Serial link 0 LVDSIN SER0_DOUT_A => SER0_DOUT_A, -- inout LVDSOUT SER0_DOUT_B => SER0_DOUT_B, -- inout LVDSOUT SER1_DIN_A => SER1_DIN_A, -- inout Serial link 1 LVDSIN SER1_DIN_B => SER1_DIN_B, -- inout Serial link 1 LVDSIN SER1_DOUT_A => SER1_DOUT_A, -- inout LVDSOUT SER1_DOUT_B => SER1_DOUT_B, -- input LVDSOUT NI_P0_D_A => NI_P0_D_A, -- inout Network Interface Data LVDSIN NI_P0_D_B => NI_P0_D_B, -- inout Network Interface Data LVDSIN NI_P0_STRB_A => NI_P0_STRB_A, -- inout Strobe LVDSIN NI_P0_STRB_B => NI_P0_STRB_B, -- inout Strobe LVDSIN NI_P0_CTRL_A => NI_P0_CTRL_A, -- inout Control LVDSOUT NI_P0_CTRL_B => NI_P0_CTRL_B, -- inout Control LVDSOUT NI_P0_CLKout_A => NI_P0_CLKout_A, -- inout clock out to up-stream MCM LVDSOUT NI_P0_CLKout_B => NI_P0_CLKout_B, -- inout clock out to up-stream MCM LVDSOUT NI_P0_PREout_A => NI_P0_PREout_A, -- inout pretrigger out to up... LVDSOUT NI_P0_PREout_B => NI_P0_PREout_B, -- inout pretrigger out to up... LVDSOUT NI_P1_D_A => NI_P1_D_A, -- inout Network Interface Data LVDSIN NI_P1_D_B => NI_P1_D_B, -- inout Network Interface Data LVDSIN NI_P1_STRB_A => NI_P1_STRB_A, -- inout Strobe LVDSIN NI_P1_STRB_B => NI_P1_STRB_B, -- inout Strobe LVDSIN NI_P1_CTRL_A => NI_P1_CTRL_A, -- inout Control LVDSOUT NI_P1_CTRL_B => NI_P1_CTRL_B, -- inout Control LVDSOUT NI_P1_CLKout_A => NI_P1_CLKout_A, -- inout clock out to up-stream MCM LVDSOUT NI_P1_CLKout_B => NI_P1_CLKout_B, -- inout clock out to up-stream MCM LVDSOUT NI_P1_PREout_A => NI_P1_PREout_A, -- inout pretrigger out to up... LVDSOUT NI_P1_PREout_B => NI_P1_PREout_B, -- inout pretrigger out to up... LVDSOUT NI_P2_D_A => NI_P2_D_A, -- inout Network Interface Data LVDSIN NI_P2_D_B => NI_P2_D_B, -- inout Network Interface Data LVDSIN NI_P2_STRB_A => NI_P2_STRB_A, -- inout Strobe LVDSIN NI_P2_STRB_B => NI_P2_STRB_B, -- inout Strobe LVDSIN NI_P2_CTRL_A => NI_P2_CTRL_A, -- inout Control LVDSOUT NI_P2_CTRL_B => NI_P2_CTRL_B, -- inout Control LVDSOUT NI_P2_CLKout_A => NI_P2_CLKout_A, -- inout clock out to up-stream MCM LVDSOUT NI_P2_CLKout_B => NI_P2_CLKout_B, -- inout clock out to up-stream MCM LVDSOUT NI_P2_PREout_A => NI_P2_PREout_A, -- inout pretrigger out to up... LVDSOUT NI_P2_PREout_B => NI_P2_PREout_B, -- inout pretrigger out to up... LVDSOUT NI_P3_D_A => NI_P3_D_A, -- inout Network Interface Data LVDSIN NI_P3_D_B => NI_P3_D_B, -- inout Network Interface Data LVDSIN NI_P3_STRB_A => NI_P3_STRB_A, -- inout Strobe LVDSIN NI_P3_STRB_B => NI_P3_STRB_B, -- inout Strobe LVDSIN NI_P3_CTRL_A => NI_P3_CTRL_A, -- inout Control LVDSOUT NI_P3_CTRL_B => NI_P3_CTRL_B, -- inout Control LVDSOUT NI_P3_CLKout_A => NI_P3_CLKout_A, -- inout clock out to up-stream MCM LVDSOUT NI_P3_CLKout_B => NI_P3_CLKout_B, -- inout clock out to up-stream MCM LVDSOUT NI_P3_PREout_A => NI_P3_PREout_A, -- inout pretrigger out to up... LVDSOUT NI_P3_PREout_B => NI_P3_PREout_B, -- inout pretrigger out to up... LVDSOUT NI_P4_D_A => NI_P4_D_A, -- inout Network Interface Data LVDSOUT NI_P4_D_B => NI_P4_D_B, -- inout Network Interface Data LVDSOUT NI_P4_STRB_A => NI_P4_STRB_A, -- inout Strobe LVDSOUT NI_P4_STRB_B => NI_P4_STRB_B, -- inout Strobe LVDSOUT NI_P4_CTRL_A => NI_P4_CTRL_A, -- inout Control LVDSIN NI_P4_CTRL_B => NI_P4_CTRL_B, -- inout Control LVDSIN NI_P_CTRL_A => NI_P_CTRL_A, -- inout ctrl/data swich for opt. transmitter LVDSOUT NI_P_CTRL_B => NI_P_CTRL_B, -- inout LVDSOUT CLK_ADC_IN_A => CLK_ADC_IN_A, -- inout ADC fast clock (120MHz) LVDSIN CLK_ADC_IN_B => CLK_ADC_IN_B, -- inout LVDSIN CLK_DIG_IN_A => CLK_DIG_IN_A, -- inout Digital Clock (120MHz) LVDSIN CLK_DIG_IN_B => CLK_DIG_IN_B, -- inout (second PLL) LVDSIN PRETRIGin_A => PRETRIGin_A, -- inout Pretrigger LVDSIN PRETRIGin_B => PRETRIGin_B, -- inout LVDSIN SEL_CLK => SEL_CLK, -- in CLK120 divide ratio/Bypass LVCMOS SEBD0 => SEBD0, SEBD1 => SEBD1, SEBD2 => SEBD2, OUT_RNG => OUT_RNG -- in outer padring only LVCMOS ); -------------------------------------------- -- SCSN (MCM NIF) -------------------------------------------- r0s: if scsn_ring=0 generate SER0_DIN_B <= not SER0_DIN_A; -- diff signal emulation SER1_DIN_A <= '0'; -- The second serial link not in use SER1_DIN_B <= not SER1_DIN_A; -- diff signal emulation si0: ser_int -- SCSN feed (our master mockup) generic map( wait_delay => 140, init_delay => 5000 ) port map( reset_n => rst_sertb_n, clk => clk_in, -- 120MHz ready => '1', ser0din => SER0_DOUT_A, ser0dout => SER0_DIN_A, PRE => pre_sc ); end generate; r1s: if scsn_ring=1 generate SER1_DIN_B <= not SER1_DIN_A; -- diff signal emulation SER0_DIN_A <= '0'; -- The second serial link not in use SER0_DIN_B <= not SER0_DIN_A; -- diff signal emulation si1: ser_int -- SCSN feed (our master mockup) generic map( wait_delay => 140, init_delay => 5000 ) port map( reset_n => rst_sertb_n, clk => clk_in, -- 120MHz ready => '1', ser0din => SER1_DOUT_A, ser0dout => SER1_DIN_A, PRE => pre_sc ); end generate; -------------------------------------------- -- Pretrigger Stuff -------------------------------------------- PRETRIGin_A <= pre_sc; PRETRIGin_B <= not pre_sc; rst_n <= '0' after 0 ns, '1' after 500 ns, '0' after 1000 ns, '1' after 1500 ns, '1' after 25 us; IRQ_n <= '1' after 0 ns; clk_in <= not clk_in after period_time/2; clk_cpld <= not clk_cpld after period_time_cpld/2; rst_sertb_n <= rst_n; -------------------------------------------- -- NI -------------------------------------------- NI_P4_CTRL_A <= '1'; NI_P4_CTRL_B <= not NI_P4_CTRL_A; sniff_p_d_out <= transport NI_P4_D_A after 1.5 ns; sniff_p_ctrl <= transport NI_P_CTRL_A after 1 ns; strb_en <= '1'; -- emulate error -- NI_P4_STRB_A_i <= '0' when NI_P4_STRB_A'stable(period_time) -- else NI_P4_STRB_A when strb_en='1' -- else 'Z'; NI_P4_STRB_A_i <= NI_P4_STRB_A when strb_en='1' else 'Z'; ni_sn: ni_sniffer generic map( -- sel_p : integer := 8; -- position of partiy bit (pass 1) -- sel_s : integer := 9; -- position of spare bit (pass 2) filename => "ni.out", ol => FALSE) -- optical link output mode (clk/ctrl) port map( strobe => NI_P4_STRB_A_i, -- strobe signal (clk in ol mode) data => sniff_p_d_out, -- data incl. partiy & strobe ctrl_out => sniff_p_ctrl, -- ctrl output to OASE ctrl_in => NI_P4_CTRL_A); -- ctrl input of output port SCL <= 'H'; SDA <= 'H'; DIS_JTG <= '0' after 0 ns, '1' after 600 us; -- SEBD2 <= 'H' when jTDO='1' else 'L' when jTDO='0' else jTDO; SEBD2 <= jTDO; ordin <= "0000000000"; -- to emulate error rst_n_cpld <= '0' after 0 ns, '1' after 300 us; sniff_p_d_out_cor <= sniff_p_d_out or ordin; cpld: top_ni port map( FAULT => '1', jTCK => SEBD0, jTDI => SEBD2, jTDO => jTDO, jTMS => SEBD1, -- disable JTAG, enable I2C DIS_JTG => DIS_JTG, -- I2C SCL => SCL, SDA => SDA, NI_STR => NI_P4_STRB_A_i, reset_n => rst_n_cpld, clk => clk_cpld, TESTEN => open, PRBSEN => open, LCKREFN => open, ENABLE => open, LOOPEN => open, TX_ER => open, EN => open, NI_D => sniff_p_d_out_cor, TX_EN => TX_EN, TXD => TX_DATA ); rst_i2c <= not rst_n; i2ct: top port map ( clk_t => clk_cpld, reset_t=> rst_i2c, -- I2C Takt und Daten (SDA ist open Drain) scl_t => SCL, sda_t => SDA, -- Multiplexer- Eingänge I_1_t => "00010001", I_2_t => "00100010", I_3_t => "01000100", I_4_t => "10001000", -- Output- Register reg_1 => open, reg_2 => open ); end;