// switch and reset test of DUT
//
//  0       only the local scsn slave
//  1       the local and the other fpga slave
//  2       the local, the other fpga slave and the 4 traps for ni test
//  3       the local and the DUT
//  4       the local, the DUT and the 4 traps for ni test
//  5       the local and the WT
//  6       the local and the 4 traps for ni test
//  7       the local, the other fpga and the WT
//             In cases without DUT in the chain, bit3 of the switch determines
//             the static value to SCSN0 input of DUT (useful for JTAG tests)

include src/chip_def.tcs
include src/scsn_ids.tcs

restrict WAFER;
// wafer tester only!
write 0x4400, 0; // fpga2 only
reset;  // FPGA only
wait 20;
write 0x4400, 7; // fpga2-fpga1-WDUT
// here the reset output config of the fpga1
write fpga1, 0x6000, (f_false_bit << 0) | (f_parit_bit << 4) | (rst_inv << 8) | (rst_opend << 9);
// exclude and parity bits in FPGA design, reset conf and reset read back
// check if the pull up of the reset is seen
expect fpga1, 0x6000, (f_false_bit << 0) | (f_parit_bit << 4) | (rst_inv << 8) | (rst_opend << 9) | (1 << 10);
restrict 1;

// IN ALL CASES!
reset dut
nop;

// SOME COMMON PARAMETERS
// reduce power
write ADCEN,  0;      // now filter preprocessor can be switched off,
// the filter clock is absolutely necessary for writing into the event buffers!!!
//write FILCLK, 0;      // now filter preprocessor can be switched off,
write PRECLK, 0;      //   ... but we need some clocks!!!
// different setting gave worse performance, power problem?
write ARBTIM, 1000b
// enable hamming correction
write MEMCOR, 0x1FF
//write MEMCOR, 0x0
// DMEM conf
write DMDELA, 8
write DMDELS, 11