include src/chip_def.tcs
include src/scsn_ids.tcs

include src/cpu0_labels.tcs

write 0xA04, 0x112
expect dut, 0x0A04, 0x30000320

restrict WAFER
// WAFER TESTER ONLY
// clear the ni-input in FPGA
write   fpga1, 0x6002, 0
// number of words
expect  fpga1, 0x6002, 0
// number of parity errors
expect  fpga1, 0x6003, 0
// END WAFER TESTER ONLY
restrict 1

write dut, 0xC01, npackets
// pretrigger
write 0xA04, 0x512
//pretrigger 1
//write fpga2, 0x4008, 1

nop
nop
nop
nop
write 0xA04, 0x012;     // low power

write dut,      IA0+irq_tst, lbl_TST_cpu0;   // set int_clr start addr for cpu0
cmd = 0000b;            // read at address 0
write srv_command, cmd;      // read 0
write 0xA04, 0x212;     // start
wait 15
expect 1, srv_outdata, 0x88

cmd = 0001b;            // read at address 1
write srv_command, cmd;      // read 0
write 0xA04, 0x212;     // start
wait 15
expect 1, srv_outdata, 0x80

cmd = 0010b;            // read at address 2
write srv_command, cmd;      // read 0
write 0xA04, 0x212;     // start
wait 15
expect 1, srv_outdata, 0x80

cmd = 0011b;            // read at address 3
write srv_command, cmd;      // read 0
write 0xA04, 0x212;     // start
wait 15
expect 1, srv_outdata, 0x80

cmd = 0100b;            // read at address 4
write srv_command, cmd;      // read 0
write 0xA04, 0x212;     // start
wait 15
expect 1, srv_outdata, reg4

//cmd = 0101b;            // read at address 5
//write srv_command, cmd;      // read 0
//write 0xA04, 0x212;     // start
//wait 15
//expect 1, srv_outdata, reg5

write dut,      IA0+irq_tst, lbl_LPW_cpu0;   // set int_clr start addr for cpu0