const WAFER = 0;
const nchips = 1;

const nwords = 63;
const npackets = 1;

const cnt_mode = 1;
//const simple_test_n  = 0xFFFF; // or 0
//const simple_test_n  = 0xFFFF0000; // or 0
//const simple_test_n  = 0x0000FFFF; // or 0
const simple_test_n  = 0xFFFF;

const oase_mode  = 0; // 1 or 0

const root_flag  = 1; // 1 or 0

const L0time= 0x00004050;
const L1time= 0x00004230+100;   // the start of readout, no confirm, used only internally
const L2time= 0x00004230+24+100; // this is for ALICE the L1A

const nsig_tr = 0xAAAA;
const nsig_rr = 0x0000;
const irq_clr = 0; // Note irq_clr is 4 in trap2!
const irq_acq = 2;
const irq_raw = 4;
const irq_tst = 1;

// all delays can be from 0 to 7

// configuration for DUT -> FPGA readout
// all delays:    min .best. max
const f_ctrl_delay = 3;  // 2 .3. 4 stable

const f_data_delay0 = 3; //
const f_data_delay1 = 3; //
const f_data_delay2 = 3; //
const f_data_delay3 = 3; //
const f_data_delay4 = 3; //   3..6
const f_data_delay5 = 3; //
const f_data_delay6 = 3; //
const f_data_delay7 = 3; //
const f_data_delay8 = 3; //
const f_data_delay9 = 3; //

const f_strb_delay = 3; //
const f_false_bit  = 8; // 0..9
const f_parit_bit  = 9; // 0..9


// FPGA only
const xor_mask  = 0x3FF;
const and_mask  = 0x3FF;
const  or_mask  = 0x000;

const rst_inv = 0; // must be 0 if no additional reset inverter is soldered
const rst_opend = 1; // if open drain the pull up in the TRAP can be measured.

sel_s = 8; // bits 7..4
sel_p = 9; // bits 3..0
reg4 = sel_p | (sel_s << 4);

TX_ER   = 0; // bit 0
TESTEN  = 0; // bit 1
PRBSEN  = 0; // bit 2
LCKREFN = 0; // bit 3
ENABLE  = 1; // bit 4
LOOPEN  = 0; // bit 5
EN      = 1; // bit 6
ALL_OE  = 1; // bit 7

//reg5 = TX_ER | (TESTEN << 1) | (PRBSEN << 2) | (LCKREFN << 3) | (ENABLE << 4) | (LOOPEN << 5) | (EN << 6) | (ALL_OE << 7);


const srv_command = 0xF0F0;
const srv_indata  = 0xF0F1;
const srv_outdata = 0xF0F2;