Analysis & Synthesis report for top Wed Jan 03 14:40:55 2007 Version 6.0 Build 178 04/27/2006 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis RAM Summary 8. General Register Statistics 9. Source assignments for ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_4og1:auto_generated 10. Source assignments for ni2dpm_12:ni_ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_4og1:auto_generated 11. Parameter Settings for User Entity Instance: ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component 12. Parameter Settings for User Entity Instance: ni2dpm_12:ni_ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component 13. Parameter Settings for User Entity Instance: pll120:PLL|altpll:altpll_component 14. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2006 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-----------------------------------------+ ; Analysis & Synthesis Status ; Successful - Wed Jan 03 14:40:55 2007 ; ; Quartus II Version ; 6.0 Build 178 04/27/2006 SJ Web Edition ; ; Revision Name ; top ; ; Top-level Entity Name ; top ; ; Family ; Cyclone ; ; Total logic elements ; 3,936 ; ; Total pins ; 82 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 65,536 ; ; Total PLLs ; 1 ; +-----------------------------+-----------------------------------------+ +--------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +--------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +--------------------------------------------------------------------+--------------------+--------------------+ ; Device ; EP1C6Q240C6 ; ; ; Top-level entity name ; top ; top ; ; Family name ; Cyclone ; Stratix ; ; Type of Retiming Performed During Resynthesis ; Full ; ; ; Resynthesis Optimization Effort ; Normal ; ; ; Physical Synthesis Level for Resynthesis ; Normal ; ; ; Use Generated Physical Constraints File ; On ; ; ; Use smart compilation ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; State Machine Processing ; Auto ; Auto ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique -- Cyclone ; Balanced ; Balanced ; ; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Remove Duplicate Logic ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Perform gate-level register retiming ; Off ; Off ; ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto Shift Register Replacement ; On ; On ; ; Auto Clock Enable Replacement ; On ; On ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM Block Balancing ; On ; On ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Enable M512 Memory Blocks ; On ; On ; ; Maximum Number of M512 Memory Blocks ; Unlimited ; Unlimited ; ; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ; ; Maximum Number of M-RAM Memory Blocks ; Unlimited ; Unlimited ; ; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; +--------------------------------------------------------------------+--------------------+--------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------+ ; ni_dpram.vhd ; yes ; User VHDL File ; M:/REFERENCE/SIM/PROJECTS/mcm_tester.svn/quartus_wlvds/ni_dpram.vhd ; ; pll120.vhd ; yes ; User VHDL File ; M:/REFERENCE/SIM/PROJECTS/mcm_tester.svn/quartus_wlvds/pll120.vhd ; ; top.edf ; yes ; User EDIF File ; M:/REFERENCE/SIM/PROJECTS/mcm_tester.svn/quartus_wlvds/top.edf ; ; altsyncram.tdf ; yes ; Megafunction ; d:/quartus60/libraries/megafunctions/altsyncram.tdf ; ; stratix_ram_block.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/stratix_ram_block.inc ; ; lpm_mux.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/lpm_mux.inc ; ; lpm_decode.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/lpm_decode.inc ; ; aglobal60.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/aglobal60.inc ; ; altsyncram.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/altsyncram.inc ; ; a_rdenreg.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/a_rdenreg.inc ; ; altrom.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/altrom.inc ; ; altram.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/altram.inc ; ; altdpram.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/altdpram.inc ; ; altqpram.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/altqpram.inc ; ; db/altsyncram_4og1.tdf ; yes ; Auto-Generated Megafunction ; M:/REFERENCE/SIM/PROJECTS/mcm_tester.svn/quartus_wlvds/db/altsyncram_4og1.tdf ; ; altpll.tdf ; yes ; Megafunction ; d:/quartus60/libraries/megafunctions/altpll.tdf ; ; stratix_pll.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/stratix_pll.inc ; ; stratixii_pll.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/stratixii_pll.inc ; ; cycloneii_pll.inc ; yes ; Other ; d:/quartus60/libraries/megafunctions/cycloneii_pll.inc ; +----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+------------------------------------------+ ; Total logic elements ; 3936 ; ; -- Combinational with no register ; 2069 ; ; -- Register only ; 1156 ; ; -- Combinational with a register ; 711 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 1584 ; ; -- 3 input functions ; 472 ; ; -- 2 input functions ; 648 ; ; -- 1 input functions ; 66 ; ; -- 0 input functions ; 4 ; ; -- Combinational cells for routing ; 6 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 3575 ; ; -- arithmetic mode ; 361 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 3 ; ; -- synchronous clear/load mode ; 1006 ; ; -- asynchronous clear/load mode ; 609 ; ; ; ; ; Total registers ; 1867 ; ; Total logic cells in carry chains ; 447 ; ; I/O pins ; 82 ; ; Total memory bits ; 65536 ; ; Total PLLs ; 1 ; ; Maximum fan-out node ; pll120:PLL|altpll:altpll_component|_clk0 ; ; Maximum fan-out ; 1518 ; ; Total fan-out ; 16032 ; ; Average fan-out ; 3.97 ; +---------------------------------------------+------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +-------------------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; +-------------------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------------------+ ; |top ; 3936 (260) ; 1867 ; 65536 ; 0 ; 82 ; 0 ; 2069 (70) ; 1156 (165) ; 711 (25) ; 447 (14) ; 0 (0) ; |top ; ; |clkpre_counter:cp| ; 850 (492) ; 375 ; 0 ; 0 ; 0 ; 0 ; 475 (230) ; 99 (74) ; 276 (188) ; 215 (190) ; 0 (0) ; |top|clkpre_counter:cp ; ; |pre_dec:pdec| ; 55 (55) ; 14 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 4 (4) ; 10 (10) ; 4 (4) ; 0 (0) ; |top|clkpre_counter:cp|pre_dec:pdec ; ; |pre_dec_unfolded0:pcnt0_dec| ; 69 (69) ; 20 ; 0 ; 0 ; 0 ; 0 ; 49 (49) ; 4 (4) ; 16 (16) ; 4 (4) ; 0 (0) ; |top|clkpre_counter:cp|pre_dec_unfolded0:pcnt0_dec ; ; |pre_dec_unfolded0:pcnt1_dec| ; 69 (69) ; 20 ; 0 ; 0 ; 0 ; 0 ; 49 (49) ; 4 (4) ; 16 (16) ; 4 (4) ; 0 (0) ; |top|clkpre_counter:cp|pre_dec_unfolded0:pcnt1_dec ; ; |pre_dec_unfolded0:pcnt2_dec| ; 69 (69) ; 20 ; 0 ; 0 ; 0 ; 0 ; 49 (49) ; 4 (4) ; 16 (16) ; 4 (4) ; 0 (0) ; |top|clkpre_counter:cp|pre_dec_unfolded0:pcnt2_dec ; ; |pre_dec_unfolded0:pcnt3_dec| ; 69 (69) ; 20 ; 0 ; 0 ; 0 ; 0 ; 49 (49) ; 4 (4) ; 16 (16) ; 4 (4) ; 0 (0) ; |top|clkpre_counter:cp|pre_dec_unfolded0:pcnt3_dec ; ; |pre_enc:pend| ; 27 (27) ; 19 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 5 (5) ; 14 (14) ; 5 (5) ; 0 (0) ; |top|clkpre_counter:cp|pre_enc:pend ; ; |general_config_2_8_notri:nic_notri| ; 284 (284) ; 117 ; 0 ; 0 ; 0 ; 0 ; 167 (167) ; 55 (55) ; 62 (62) ; 50 (50) ; 0 (0) ; |top|general_config_2_8_notri:nic_notri ; ; |gio_devices:gio| ; 144 (144) ; 42 ; 0 ; 0 ; 0 ; 0 ; 102 (102) ; 4 (4) ; 38 (38) ; 0 (0) ; 0 (0) ; |top|gio_devices:gio ; ; |jtag_master_1_notri:jtag_dut_notri| ; 414 (172) ; 247 ; 0 ; 0 ; 0 ; 0 ; 167 (48) ; 210 (103) ; 37 (21) ; 14 (0) ; 0 (0) ; |top|jtag_master_1_notri:jtag_dut_notri ; ; |jtag_recv_2:jtgrcv| ; 152 (152) ; 74 ; 0 ; 0 ; 0 ; 0 ; 78 (78) ; 74 (74) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|jtag_master_1_notri:jtag_dut_notri|jtag_recv_2:jtgrcv ; ; |jtag_tms:jtgtms| ; 90 (90) ; 49 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 33 (33) ; 16 (16) ; 14 (14) ; 0 (0) ; |top|jtag_master_1_notri:jtag_dut_notri|jtag_tms:jtgtms ; ; |jtag_master_2_notri:jtag_ni_dn_notri| ; 415 (173) ; 249 ; 0 ; 0 ; 0 ; 0 ; 166 (47) ; 213 (106) ; 36 (20) ; 14 (0) ; 0 (0) ; |top|jtag_master_2_notri:jtag_ni_dn_notri ; ; |jtag_recv_2:jtgrcv| ; 152 (152) ; 74 ; 0 ; 0 ; 0 ; 0 ; 78 (78) ; 74 (74) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|jtag_master_2_notri:jtag_ni_dn_notri|jtag_recv_2:jtgrcv ; ; |jtag_tms:jtgtms| ; 90 (90) ; 49 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 33 (33) ; 16 (16) ; 14 (14) ; 0 (0) ; |top|jtag_master_2_notri:jtag_ni_dn_notri|jtag_tms:jtgtms ; ; |jtag_master_2_notri:jtag_ni_up_notri| ; 415 (173) ; 249 ; 0 ; 0 ; 0 ; 0 ; 166 (47) ; 213 (106) ; 36 (20) ; 14 (0) ; 0 (0) ; |top|jtag_master_2_notri:jtag_ni_up_notri ; ; |jtag_recv_2:jtgrcv| ; 152 (152) ; 74 ; 0 ; 0 ; 0 ; 0 ; 78 (78) ; 74 (74) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|jtag_master_2_notri:jtag_ni_up_notri|jtag_recv_2:jtgrcv ; ; |jtag_tms:jtgtms| ; 90 (90) ; 49 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 33 (33) ; 16 (16) ; 14 (14) ; 0 (0) ; |top|jtag_master_2_notri:jtag_ni_up_notri|jtag_tms:jtgtms ; ; |mcm_nw_apl:scsn_slave_nw_apl| ; 156 (156) ; 50 ; 0 ; 0 ; 0 ; 0 ; 106 (106) ; 34 (34) ; 16 (16) ; 6 (6) ; 0 (0) ; |top|mcm_nw_apl:scsn_slave_nw_apl ; ; |mcm_nw_bittiming_4_2_7_7_2:scsn_slave_nw_dll_bt0| ; 73 (73) ; 17 ; 0 ; 0 ; 0 ; 0 ; 56 (56) ; 1 (1) ; 16 (16) ; 9 (9) ; 0 (0) ; |top|mcm_nw_bittiming_4_2_7_7_2:scsn_slave_nw_dll_bt0 ; ; |mcm_nw_bittiming_4_2_7_7_2:scsn_slave_nw_dll_bt1| ; 73 (73) ; 17 ; 0 ; 0 ; 0 ; 0 ; 56 (56) ; 1 (1) ; 16 (16) ; 9 (9) ; 0 (0) ; |top|mcm_nw_bittiming_4_2_7_7_2:scsn_slave_nw_dll_bt1 ; ; |mcm_nw_inbuf_69_4_7:scsn_slave_nw_dll_ib0| ; 107 (107) ; 92 ; 0 ; 0 ; 0 ; 0 ; 15 (15) ; 69 (69) ; 23 (23) ; 7 (7) ; 0 (0) ; |top|mcm_nw_inbuf_69_4_7:scsn_slave_nw_dll_ib0 ; ; |mcm_nw_inbuf_69_4_7:scsn_slave_nw_dll_ib1| ; 107 (107) ; 92 ; 0 ; 0 ; 0 ; 0 ; 15 (15) ; 69 (69) ; 23 (23) ; 7 (7) ; 0 (0) ; |top|mcm_nw_inbuf_69_4_7:scsn_slave_nw_dll_ib1 ; ; |mcm_nw_nwl:scsn_slave_nw_nwl| ; 348 (92) ; 16 ; 0 ; 0 ; 0 ; 0 ; 332 (86) ; 1 (1) ; 15 (5) ; 16 (0) ; 0 (0) ; |top|mcm_nw_nwl:scsn_slave_nw_nwl ; ; |mcm_nw_nwsl:sl0| ; 128 (128) ; 5 ; 0 ; 0 ; 0 ; 0 ; 123 (123) ; 0 (0) ; 5 (5) ; 8 (8) ; 0 (0) ; |top|mcm_nw_nwl:scsn_slave_nw_nwl|mcm_nw_nwsl:sl0 ; ; |mcm_nw_nwsl:sl1| ; 128 (128) ; 5 ; 0 ; 0 ; 0 ; 0 ; 123 (123) ; 0 (0) ; 5 (5) ; 8 (8) ; 0 (0) ; |top|mcm_nw_nwl:scsn_slave_nw_nwl|mcm_nw_nwsl:sl1 ; ; |mcm_nw_sendtiming_4_7_63:scsn_slave_nw_dll_st0| ; 52 (52) ; 20 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 20 (20) ; 12 (12) ; 0 (0) ; |top|mcm_nw_sendtiming_4_7_63:scsn_slave_nw_dll_st0 ; ; |mcm_nw_sendtiming_4_7_63:scsn_slave_nw_dll_st1| ; 52 (52) ; 20 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 20 (20) ; 12 (12) ; 0 (0) ; |top|mcm_nw_sendtiming_4_7_63:scsn_slave_nw_dll_st1 ; ; |ni2dpm_12:ni_ni_neg| ; 93 (93) ; 37 ; 32768 ; 0 ; 0 ; 0 ; 56 (56) ; 11 (11) ; 26 (26) ; 24 (24) ; 0 (0) ; |top|ni2dpm_12:ni_ni_neg ; ; |ni_dpram:dpram| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2dpm_12:ni_ni_neg|ni_dpram:dpram ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component ; ; |altsyncram_4og1:auto_generated| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_4og1:auto_generated ; ; |ni2dpm_12:ni_ni_pos| ; 93 (93) ; 37 ; 32768 ; 0 ; 0 ; 0 ; 56 (56) ; 11 (11) ; 26 (26) ; 24 (24) ; 0 (0) ; |top|ni2dpm_12:ni_ni_pos ; ; |ni_dpram:dpram| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2dpm_12:ni_ni_pos|ni_dpram:dpram ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2dpm_12:ni_ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component ; ; |altsyncram_4og1:auto_generated| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2dpm_12:ni_ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_4og1:auto_generated ; ; |pll120:PLL| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|pll120:PLL ; ; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|pll120:PLL|altpll:altpll_component ; +-------------------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ ; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; +--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ ; ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_4og1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096 ; 8 ; 2048 ; 16 ; 32768 ; None ; ; ni2dpm_12:ni_ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_4og1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096 ; 8 ; 2048 ; 16 ; 32768 ; None ; +--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 1867 ; ; Number of registers using Synchronous Clear ; 463 ; ; Number of registers using Synchronous Load ; 543 ; ; Number of registers using Asynchronous Clear ; 609 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 1228 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_4og1:auto_generated ; +---------------------------------+--------------------+------+------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for ni2dpm_12:ni_ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_4og1:auto_generated ; +---------------------------------+--------------------+------+------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------------------------+--------------------+------+------------------------------------------------------------+ ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; +---------------------------------+--------------------+------+------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component ; +------------------------------------+-----------------+----------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+-----------------+----------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 8 ; Integer ; ; WIDTHAD_A ; 12 ; Integer ; ; NUMWORDS_A ; 4096 ; Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; CLEAR0 ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; CLEAR0 ; Untyped ; ; INDATA_ACLR_A ; CLEAR0 ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 16 ; Integer ; ; WIDTHAD_B ; 11 ; Integer ; ; NUMWORDS_B ; 2048 ; Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; CLOCK1 ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; DEVICE_FAMILY ; Cyclone ; Untyped ; ; CBXI_PARAMETER ; altsyncram_4og1 ; Untyped ; +------------------------------------+-----------------+----------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: ni2dpm_12:ni_ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component ; +------------------------------------+-----------------+----------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+-----------------+----------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 8 ; Integer ; ; WIDTHAD_A ; 12 ; Integer ; ; NUMWORDS_A ; 4096 ; Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; CLEAR0 ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; CLEAR0 ; Untyped ; ; INDATA_ACLR_A ; CLEAR0 ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 16 ; Integer ; ; WIDTHAD_B ; 11 ; Integer ; ; NUMWORDS_B ; 2048 ; Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; CLOCK1 ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; DEVICE_FAMILY ; Cyclone ; Untyped ; ; CBXI_PARAMETER ; altsyncram_4og1 ; Untyped ; +------------------------------------+-----------------+----------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pll120:PLL|altpll:altpll_component ; +-------------------------------+-------------------+-----------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------------------+-----------------------------+ ; OPERATION_MODE ; NORMAL ; Untyped ; ; PLL_TYPE ; AUTO ; Untyped ; ; QUALIFY_CONF_DONE ; OFF ; Untyped ; ; COMPENSATE_CLOCK ; CLK0 ; Untyped ; ; SCAN_CHAIN ; LONG ; Untyped ; ; PRIMARY_CLOCK ; INCLK0 ; Untyped ; ; INCLK0_INPUT_FREQUENCY ; 13888 ; Integer ; ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; ; GATE_LOCK_SIGNAL ; NO ; Untyped ; ; GATE_LOCK_COUNTER ; 0 ; Untyped ; ; LOCK_HIGH ; 1 ; Untyped ; ; LOCK_LOW ; 1 ; Untyped ; ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; ; SKIP_VCO ; OFF ; Untyped ; ; SWITCH_OVER_COUNTER ; 0 ; Untyped ; ; SWITCH_OVER_TYPE ; AUTO ; Untyped ; ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; ; BANDWIDTH ; 0 ; Untyped ; ; BANDWIDTH_TYPE ; AUTO ; Untyped ; ; SPREAD_FREQUENCY ; 0 ; Untyped ; ; DOWN_SPREAD ; 0 ; Untyped ; ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; ; CLK5_MULTIPLY_BY ; 1 ; Untyped ; ; CLK4_MULTIPLY_BY ; 1 ; Untyped ; ; CLK3_MULTIPLY_BY ; 1 ; Untyped ; ; CLK2_MULTIPLY_BY ; 1 ; Untyped ; ; CLK1_MULTIPLY_BY ; 1 ; Untyped ; ; CLK0_MULTIPLY_BY ; 5 ; Integer ; ; CLK5_DIVIDE_BY ; 1 ; Untyped ; ; CLK4_DIVIDE_BY ; 1 ; Untyped ; ; CLK3_DIVIDE_BY ; 1 ; Untyped ; ; CLK2_DIVIDE_BY ; 1 ; Untyped ; ; CLK1_DIVIDE_BY ; 1 ; Untyped ; ; CLK0_DIVIDE_BY ; 3 ; Integer ; ; CLK5_PHASE_SHIFT ; 0 ; Untyped ; ; CLK4_PHASE_SHIFT ; 0 ; Untyped ; ; CLK3_PHASE_SHIFT ; 0 ; Untyped ; ; CLK2_PHASE_SHIFT ; 0 ; Untyped ; ; CLK1_PHASE_SHIFT ; 0 ; Untyped ; ; CLK0_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_TIME_DELAY ; 0 ; Untyped ; ; CLK4_TIME_DELAY ; 0 ; Untyped ; ; CLK3_TIME_DELAY ; 0 ; Untyped ; ; CLK2_TIME_DELAY ; 0 ; Untyped ; ; CLK1_TIME_DELAY ; 0 ; Untyped ; ; CLK0_TIME_DELAY ; 0 ; Untyped ; ; CLK5_DUTY_CYCLE ; 50 ; Untyped ; ; CLK4_DUTY_CYCLE ; 50 ; Untyped ; ; CLK3_DUTY_CYCLE ; 50 ; Untyped ; ; CLK2_DUTY_CYCLE ; 50 ; Untyped ; ; CLK1_DUTY_CYCLE ; 50 ; Untyped ; ; CLK0_DUTY_CYCLE ; 50 ; Integer ; ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK0_MULTIPLY_BY ; 5 ; Integer ; ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK0_DIVIDE_BY ; 3 ; Integer ; ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK0_DUTY_CYCLE ; 50 ; Integer ; ; VCO_MULTIPLY_BY ; 0 ; Untyped ; ; VCO_DIVIDE_BY ; 0 ; Untyped ; ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; ; VCO_MIN ; 0 ; Untyped ; ; VCO_MAX ; 0 ; Untyped ; ; VCO_CENTER ; 0 ; Untyped ; ; PFD_MIN ; 0 ; Untyped ; ; PFD_MAX ; 0 ; Untyped ; ; M_INITIAL ; 0 ; Untyped ; ; M ; 0 ; Untyped ; ; N ; 1 ; Untyped ; ; M2 ; 1 ; Untyped ; ; N2 ; 1 ; Untyped ; ; SS ; 1 ; Untyped ; ; C0_HIGH ; 0 ; Untyped ; ; C1_HIGH ; 0 ; Untyped ; ; C2_HIGH ; 0 ; Untyped ; ; C3_HIGH ; 0 ; Untyped ; ; C4_HIGH ; 0 ; Untyped ; ; C5_HIGH ; 0 ; Untyped ; ; C0_LOW ; 0 ; Untyped ; ; C1_LOW ; 0 ; Untyped ; ; C2_LOW ; 0 ; Untyped ; ; C3_LOW ; 0 ; Untyped ; ; C4_LOW ; 0 ; Untyped ; ; C5_LOW ; 0 ; Untyped ; ; C0_INITIAL ; 0 ; Untyped ; ; C1_INITIAL ; 0 ; Untyped ; ; C2_INITIAL ; 0 ; Untyped ; ; C3_INITIAL ; 0 ; Untyped ; ; C4_INITIAL ; 0 ; Untyped ; ; C5_INITIAL ; 0 ; Untyped ; ; C0_MODE ; BYPASS ; Untyped ; ; C1_MODE ; BYPASS ; Untyped ; ; C2_MODE ; BYPASS ; Untyped ; ; C3_MODE ; BYPASS ; Untyped ; ; C4_MODE ; BYPASS ; Untyped ; ; C5_MODE ; BYPASS ; Untyped ; ; C0_PH ; 0 ; Untyped ; ; C1_PH ; 0 ; Untyped ; ; C2_PH ; 0 ; Untyped ; ; C3_PH ; 0 ; Untyped ; ; C4_PH ; 0 ; Untyped ; ; C5_PH ; 0 ; Untyped ; ; L0_HIGH ; 1 ; Untyped ; ; L1_HIGH ; 1 ; Untyped ; ; G0_HIGH ; 1 ; Untyped ; ; G1_HIGH ; 1 ; Untyped ; ; G2_HIGH ; 1 ; Untyped ; ; G3_HIGH ; 1 ; Untyped ; ; E0_HIGH ; 1 ; Untyped ; ; E1_HIGH ; 1 ; Untyped ; ; E2_HIGH ; 1 ; Untyped ; ; E3_HIGH ; 1 ; Untyped ; ; L0_LOW ; 1 ; Untyped ; ; L1_LOW ; 1 ; Untyped ; ; G0_LOW ; 1 ; Untyped ; ; G1_LOW ; 1 ; Untyped ; ; G2_LOW ; 1 ; Untyped ; ; G3_LOW ; 1 ; Untyped ; ; E0_LOW ; 1 ; Untyped ; ; E1_LOW ; 1 ; Untyped ; ; E2_LOW ; 1 ; Untyped ; ; E3_LOW ; 1 ; Untyped ; ; L0_INITIAL ; 1 ; Untyped ; ; L1_INITIAL ; 1 ; Untyped ; ; G0_INITIAL ; 1 ; Untyped ; ; G1_INITIAL ; 1 ; Untyped ; ; G2_INITIAL ; 1 ; Untyped ; ; G3_INITIAL ; 1 ; Untyped ; ; E0_INITIAL ; 1 ; Untyped ; ; E1_INITIAL ; 1 ; Untyped ; ; E2_INITIAL ; 1 ; Untyped ; ; E3_INITIAL ; 1 ; Untyped ; ; L0_MODE ; BYPASS ; Untyped ; ; L1_MODE ; BYPASS ; Untyped ; ; G0_MODE ; BYPASS ; Untyped ; ; G1_MODE ; BYPASS ; Untyped ; ; G2_MODE ; BYPASS ; Untyped ; ; G3_MODE ; BYPASS ; Untyped ; ; E0_MODE ; BYPASS ; Untyped ; ; E1_MODE ; BYPASS ; Untyped ; ; E2_MODE ; BYPASS ; Untyped ; ; E3_MODE ; BYPASS ; Untyped ; ; L0_PH ; 0 ; Untyped ; ; L1_PH ; 0 ; Untyped ; ; G0_PH ; 0 ; Untyped ; ; G1_PH ; 0 ; Untyped ; ; G2_PH ; 0 ; Untyped ; ; G3_PH ; 0 ; Untyped ; ; E0_PH ; 0 ; Untyped ; ; E1_PH ; 0 ; Untyped ; ; E2_PH ; 0 ; Untyped ; ; E3_PH ; 0 ; Untyped ; ; M_PH ; 0 ; Untyped ; ; C1_USE_CASC_IN ; 0 ; Untyped ; ; C2_USE_CASC_IN ; 0 ; Untyped ; ; C3_USE_CASC_IN ; 0 ; Untyped ; ; C4_USE_CASC_IN ; 0 ; Untyped ; ; C5_USE_CASC_IN ; 0 ; Untyped ; ; CLK0_COUNTER ; G0 ; Untyped ; ; CLK1_COUNTER ; G0 ; Untyped ; ; CLK2_COUNTER ; G0 ; Untyped ; ; CLK3_COUNTER ; G0 ; Untyped ; ; CLK4_COUNTER ; G0 ; Untyped ; ; CLK5_COUNTER ; G0 ; Untyped ; ; L0_TIME_DELAY ; 0 ; Untyped ; ; L1_TIME_DELAY ; 0 ; Untyped ; ; G0_TIME_DELAY ; 0 ; Untyped ; ; G1_TIME_DELAY ; 0 ; Untyped ; ; G2_TIME_DELAY ; 0 ; Untyped ; ; G3_TIME_DELAY ; 0 ; Untyped ; ; E0_TIME_DELAY ; 0 ; Untyped ; ; E1_TIME_DELAY ; 0 ; Untyped ; ; E2_TIME_DELAY ; 0 ; Untyped ; ; E3_TIME_DELAY ; 0 ; Untyped ; ; M_TIME_DELAY ; 0 ; Untyped ; ; N_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_COUNTER ; E3 ; Untyped ; ; EXTCLK2_COUNTER ; E2 ; Untyped ; ; EXTCLK1_COUNTER ; E1 ; Untyped ; ; EXTCLK0_COUNTER ; E0 ; Untyped ; ; ENABLE0_COUNTER ; L0 ; Untyped ; ; ENABLE1_COUNTER ; L0 ; Untyped ; ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; ; LOOP_FILTER_R ; 1.000000 ; Untyped ; ; LOOP_FILTER_C ; 5 ; Untyped ; ; VCO_POST_SCALE ; 0 ; Untyped ; ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; INTENDED_DEVICE_FAMILY ; Cyclone ; Untyped ; ; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ; ; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_LOCKED ; PORT_CONNECTIVITY ; Untyped ; ; M_TEST_SOURCE ; 5 ; Untyped ; ; C0_TEST_SOURCE ; 5 ; Untyped ; ; C1_TEST_SOURCE ; 5 ; Untyped ; ; C2_TEST_SOURCE ; 5 ; Untyped ; ; C3_TEST_SOURCE ; 5 ; Untyped ; ; C4_TEST_SOURCE ; 5 ; Untyped ; ; C5_TEST_SOURCE ; 5 ; Untyped ; ; DEVICE_FAMILY ; Cyclone ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +-------------------------------+-------------------+-----------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition Info: Processing started: Wed Jan 03 14:40:27 2007 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top Info: Found 2 design units, including 1 entities, in source file ni_dpram.vhd Info: Found design unit 1: ni_dpram-SYN Info: Found entity 1: ni_dpram Info: Found 2 design units, including 1 entities, in source file pll120.vhd Info: Found design unit 1: pll120-SYN Info: Found entity 1: pll120 Info: Found 18 design units, including 18 entities, in source file top.edf Info: Found entity 1: clkpre_counter Info: Found entity 2: general_config_2_8_notri Info: Found entity 3: gio_devices Info: Found entity 4: jtag_master_1_notri Info: Found entity 5: jtag_master_2_notri Info: Found entity 6: jtag_recv_2 Info: Found entity 7: jtag_tms Info: Found entity 8: mcm_nw_apl Info: Found entity 9: mcm_nw_bittiming_4_2_7_7_2 Info: Found entity 10: mcm_nw_inbuf_69_4_7 Info: Found entity 11: mcm_nw_nwl Info: Found entity 12: mcm_nw_nwsl Info: Found entity 13: mcm_nw_sendtiming_4_7_63 Info: Found entity 14: ni2dpm_12 Info: Found entity 15: pre_dec Info: Found entity 16: pre_dec_unfolded0 Info: Found entity 17: pre_enc Info: Found entity 18: top Info: Elaborating entity "top" for the top level hierarchy Info: Elaborating entity "clkpre_counter" for hierarchy "clkpre_counter:cp" Info: Elaborating entity "pre_dec_unfolded0" for hierarchy "clkpre_counter:cp|pre_dec_unfolded0:pcnt0_dec" Info: Elaborating entity "pre_dec" for hierarchy "clkpre_counter:cp|pre_dec:pdec" Info: Elaborating entity "pre_enc" for hierarchy "clkpre_counter:cp|pre_enc:pend" Info: Elaborating entity "gio_devices" for hierarchy "gio_devices:gio" Info: Elaborating entity "jtag_master_1_notri" for hierarchy "jtag_master_1_notri:jtag_dut_notri" Info: Elaborating entity "jtag_recv_2" for hierarchy "jtag_master_1_notri:jtag_dut_notri|jtag_recv_2:jtgrcv" Info: Elaborating entity "jtag_tms" for hierarchy "jtag_master_1_notri:jtag_dut_notri|jtag_tms:jtgtms" Info: Elaborating entity "jtag_master_2_notri" for hierarchy "jtag_master_2_notri:jtag_ni_dn_notri" Info: Elaborating entity "ni2dpm_12" for hierarchy "ni2dpm_12:ni_ni_neg" Info: Elaborating entity "ni_dpram" for hierarchy "ni2dpm_12:ni_ni_neg|ni_dpram:dpram" Info: Found 1 design units, including 1 entities, in source file d:/quartus60/libraries/megafunctions/altsyncram.tdf Info: Found entity 1: altsyncram Info: Elaborating entity "altsyncram" for hierarchy "ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component" Info: Elaborated megafunction instantiation "ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4og1.tdf Info: Found entity 1: altsyncram_4og1 Info: Elaborating entity "altsyncram_4og1" for hierarchy "ni2dpm_12:ni_ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_4og1:auto_generated" Info: Elaborating entity "general_config_2_8_notri" for hierarchy "general_config_2_8_notri:nic_notri" Info: Elaborating entity "pll120" for hierarchy "pll120:PLL" Info: Found 1 design units, including 1 entities, in source file d:/quartus60/libraries/megafunctions/altpll.tdf Info: Found entity 1: altpll Info: Elaborating entity "altpll" for hierarchy "pll120:PLL|altpll:altpll_component" Info: Elaborated megafunction instantiation "pll120:PLL|altpll:altpll_component" Info: Elaborating entity "mcm_nw_apl" for hierarchy "mcm_nw_apl:scsn_slave_nw_apl" Info: Elaborating entity "mcm_nw_bittiming_4_2_7_7_2" for hierarchy "mcm_nw_bittiming_4_2_7_7_2:scsn_slave_nw_dll_bt0" Info: Elaborating entity "mcm_nw_inbuf_69_4_7" for hierarchy "mcm_nw_inbuf_69_4_7:scsn_slave_nw_dll_ib0" Info: Elaborating entity "mcm_nw_sendtiming_4_7_63" for hierarchy "mcm_nw_sendtiming_4_7_63:scsn_slave_nw_dll_st0" Info: Elaborating entity "mcm_nw_nwl" for hierarchy "mcm_nw_nwl:scsn_slave_nw_nwl" Info: Elaborating entity "mcm_nw_nwsl" for hierarchy "mcm_nw_nwl:scsn_slave_nw_nwl|mcm_nw_nwsl:sl0" Warning: Output pins are stuck at VCC or GND Warning: Pin "PC_0_OUT" stuck at GND Info: Found the following redundant logic cells in design Info: Logic cell "clkpre_counter:cp|pre_dec:pdec|nx117" Info: Logic cell "mcm_nw_nwl:scsn_slave_nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_60" Info: Logic cell "mcm_nw_nwl:scsn_slave_nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_60" Info: Logic cell "mcm_nw_bittiming_4_2_7_7_2:scsn_slave_nw_dll_bt0|nx142" Info: Logic cell "mcm_nw_bittiming_4_2_7_7_2:scsn_slave_nw_dll_bt1|nx142" Info: Logic cell "jtag_master_1_notri:jtag_dut_notri|jtag_tms:jtgtms|nx476" Info: Logic cell "jtag_master_1_notri:jtag_dut_notri|jtag_tms:jtgtms|c_mid_1" Info: Logic cell "jtag_master_2_notri:jtag_ni_dn_notri|jtag_tms:jtgtms|nx476" Info: Logic cell "jtag_master_2_notri:jtag_ni_dn_notri|jtag_tms:jtgtms|c_mid_1" Info: Logic cell "jtag_master_2_notri:jtag_ni_up_notri|jtag_tms:jtgtms|nx476" Info: Logic cell "jtag_master_2_notri:jtag_ni_up_notri|jtag_tms:jtgtms|c_mid_1" Info: Logic cell "clkpre_counter:cp|pre_dec_unfolded0:pcnt1_dec|nx117" Info: Logic cell "clkpre_counter:cp|pre_dec_unfolded0:pcnt3_dec|nx117" Info: Logic cell "clkpre_counter:cp|pre_dec_unfolded0:pcnt0_dec|nx117" Info: Logic cell "clkpre_counter:cp|pre_dec_unfolded0:pcnt2_dec|nx117" Warning: Output port clk0 of PLL "pll120:PLL|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "AD_SYNC_IN[0]" Warning: No output dependent on input pin "PC_0_IN" Info: Implemented 4035 device resources after synthesis - the final resource count might be different Info: Implemented 39 input pins Info: Implemented 29 output pins Info: Implemented 14 bidirectional pins Info: Implemented 3936 logic cells Info: Implemented 16 RAM segments Info: Implemented 1 ClockLock PLLs Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings Info: Processing ended: Wed Jan 03 14:40:54 2007 Info: Elapsed time: 00:00:29