Analysis & Synthesis report for top Mon Oct 10 11:51:17 2005 Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis RAM Summary 8. General Register Statistics 9. Parameter Settings for User Entity Instance: ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component 10. Parameter Settings for User Entity Instance: pll120:PLL|altpll:altpll_component 11. Parameter Settings for User Entity Instance: ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component 12. Parameter Settings for User Entity Instance: ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component 13. Analysis & Synthesis Equations 14. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2005 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-----------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Mon Oct 10 11:51:17 2005 ; ; Quartus II Version ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ; ; Revision Name ; top ; ; Top-level Entity Name ; top ; ; Family ; Cyclone ; ; Total logic elements ; 3,151 ; ; Total pins ; 108 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 81,920 ; ; Total PLLs ; 1 ; +-----------------------------+-----------------------------------------------+ +---------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +--------------------------------------------------------------------+--------------+---------------+ ; Option ; Setting ; Default Value ; +--------------------------------------------------------------------+--------------+---------------+ ; Device ; EP1C6Q240C6 ; ; ; Top-level entity name ; top ; top ; ; Family name ; Cyclone ; Stratix ; ; Type of Retiming Performed During Resynthesis ; Full ; ; ; Resynthesis Optimization Effort ; Normal ; ; ; Physical Synthesis Level for Resynthesis ; Normal ; ; ; Use Generated Physical Constraints File ; On ; ; ; Use smart compilation ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; off ; off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; State Machine Processing ; Auto ; Auto ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique -- Cyclone ; Balanced ; Balanced ; ; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Remove Duplicate Logic ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Perform gate-level register retiming ; Off ; Off ; ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto Shift Register Replacement ; On ; On ; ; Auto Clock Enable Replacement ; On ; On ; ; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ; ; Auto RAM Block Balancing ; On ; On ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Enable M512 Memory Blocks ; On ; On ; ; Maximum Number of M512 Memory Blocks ; -1 ; -1 ; ; Maximum Number of M4K Memory Blocks ; -1 ; -1 ; ; Maximum Number of M-RAM Memory Blocks ; -1 ; -1 ; ; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +--------------------------------------------------------------------+--------------+---------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------+ ; pasaadc_ram.vhd ; yes ; User VHDL File ; M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_wadcdac/pasaadc_ram.vhd ; ; pll120.vhd ; yes ; User VHDL File ; M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_wadcdac/pll120.vhd ; ; top.edf ; yes ; User EDIF File ; M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_wadcdac/top.edf ; ; altsyncram.tdf ; yes ; Megafunction ; d:/quartus50/libraries/megafunctions/altsyncram.tdf ; ; stratix_ram_block.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/stratix_ram_block.inc ; ; lpm_mux.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/lpm_mux.inc ; ; lpm_decode.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/lpm_decode.inc ; ; aglobal50.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/aglobal50.inc ; ; altsyncram.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/altsyncram.inc ; ; a_rdenreg.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/a_rdenreg.inc ; ; altrom.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/altrom.inc ; ; altram.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/altram.inc ; ; altdpram.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/altdpram.inc ; ; altqpram.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/altqpram.inc ; ; db/altsyncram_hl61.tdf ; yes ; Auto-Generated Megafunction ; M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_wadcdac/db/altsyncram_hl61.tdf ; ; altpll.tdf ; yes ; Megafunction ; d:/quartus50/libraries/megafunctions/altpll.tdf ; ; stratix_pll.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/stratix_pll.inc ; ; stratixii_pll.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/stratixii_pll.inc ; ; cycloneii_pll.inc ; yes ; Other ; d:/quartus50/libraries/megafunctions/cycloneii_pll.inc ; ; ni_dpram.vhd ; yes ; Other ; M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_wadcdac/ni_dpram.vhd ; ; db/altsyncram_oj71.tdf ; yes ; Auto-Generated Megafunction ; M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_wadcdac/db/altsyncram_oj71.tdf ; +----------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------+ +------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +-----------------------------------+------------------------------------------+ ; Resource ; Usage ; +-----------------------------------+------------------------------------------+ ; Total logic elements ; 3151 ; ; Total combinational functions ; 2177 ; ; -- Total 4-input functions ; 1166 ; ; -- Total 3-input functions ; 347 ; ; -- Total 2-input functions ; 403 ; ; -- Total 1-input functions ; 253 ; ; -- Total 0-input functions ; 8 ; ; Combinational cells for routing ; 2 ; ; Total registers ; 1446 ; ; Total logic cells in carry chains ; 381 ; ; I/O pins ; 108 ; ; Total memory bits ; 81920 ; ; Total PLLs ; 1 ; ; Maximum fan-out node ; pll120:PLL|altpll:altpll_component|_clk0 ; ; Maximum fan-out ; 1399 ; ; Total fan-out ; 12929 ; ; Average fan-out ; 3.93 ; +-----------------------------------+------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +----------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ; +----------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------+ ; |top ; 3151 (1) ; 1446 ; 81920 ; 108 ; 0 ; 1705 (1) ; 975 (0) ; 471 (0) ; 381 (0) ; |top ; ; |ADC_DAC_1_notri:adcdac_notri| ; 1564 (6) ; 785 ; 16384 ; 0 ; 0 ; 779 (2) ; 543 (2) ; 242 (2) ; 216 (0) ; |top|ADC_DAC_1_notri:adcdac_notri ; ; |DDS:ddsi| ; 331 (331) ; 156 ; 0 ; 0 ; 0 ; 175 (175) ; 119 (119) ; 37 (37) ; 6 (6) ; |top|ADC_DAC_1_notri:adcdac_notri|DDS:ddsi ; ; |TLV5630_16:slow_dac2| ; 46 (46) ; 37 ; 0 ; 0 ; 0 ; 9 (9) ; 20 (20) ; 17 (17) ; 8 (8) ; |top|ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2 ; ; |digpot4:dgi_0_dgpot| ; 50 (50) ; 25 ; 0 ; 0 ; 0 ; 25 (25) ; 8 (8) ; 17 (17) ; 29 (29) ; |top|ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot ; ; |digpot4:dgi_1_dgpot| ; 50 (50) ; 25 ; 0 ; 0 ; 0 ; 25 (25) ; 8 (8) ; 17 (17) ; 29 (29) ; |top|ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot ; ; |digpot4:dgi_2_dgpot| ; 50 (50) ; 25 ; 0 ; 0 ; 0 ; 25 (25) ; 8 (8) ; 17 (17) ; 29 (29) ; |top|ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot ; ; |digpot4:dgi_3_dgpot| ; 50 (50) ; 25 ; 0 ; 0 ; 0 ; 25 (25) ; 8 (8) ; 17 (17) ; 29 (29) ; |top|ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot ; ; |gio_devices_adc:gio| ; 110 (110) ; 13 ; 0 ; 0 ; 0 ; 97 (97) ; 4 (4) ; 9 (9) ; 0 (0) ; |top|ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio ; ; |pasaadc:padc| ; 71 (71) ; 33 ; 16384 ; 0 ; 0 ; 38 (38) ; 20 (20) ; 13 (13) ; 10 (10) ; |top|ADC_DAC_1_notri:adcdac_notri|pasaadc:padc ; ; |pasaadc_ram:adcram| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component ; ; |altsyncram_hl61:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated ; ; |seradc_auto:power_adc| ; 425 (380) ; 222 ; 0 ; 0 ; 0 ; 203 (197) ; 173 (160) ; 49 (23) ; 62 (58) ; |top|ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc ; ; |TLV2548:adc| ; 45 (45) ; 39 ; 0 ; 0 ; 0 ; 6 (6) ; 13 (13) ; 26 (26) ; 4 (4) ; |top|ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc ; ; |seradc_auto_unfolded0:sc_adc| ; 375 (330) ; 220 ; 0 ; 0 ; 0 ; 155 (149) ; 173 (160) ; 47 (21) ; 14 (10) ; |top|ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc ; ; |TLV2548:adc| ; 45 (45) ; 39 ; 0 ; 0 ; 0 ; 6 (6) ; 13 (13) ; 26 (26) ; 4 (4) ; |top|ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc ; ; |mcm_network_interface:scsn_slave| ; 1233 (0) ; 514 ; 0 ; 0 ; 0 ; 719 (0) ; 370 (0) ; 144 (0) ; 92 (0) ; |top|mcm_network_interface:scsn_slave ; ; |mcm_nw_apl:nw_apl| ; 160 (156) ; 50 ; 0 ; 0 ; 0 ; 110 (110) ; 38 (34) ; 12 (12) ; 6 (6) ; |top|mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl ; ; |hamm_reg_4_0_1_unfolded0:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1 ; ; |mcm_nw_dll_4_2_7_63_69_4_7:nw_dll| ; 690 (4) ; 442 ; 0 ; 0 ; 0 ; 248 (4) ; 316 (0) ; 126 (0) ; 70 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll ; ; |mcm_nw_bittiming_4_2_7_7_2:bt0| ; 79 (49) ; 17 ; 0 ; 0 ; 0 ; 62 (45) ; 5 (1) ; 12 (3) ; 9 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0 ; ; |hamm_reg_4_0_1:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1 ; ; |mcm_nw_destuffing_7:destuff_in| ; 10 (10) ; 6 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 6 (6) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in ; ; |mcm_nw_timer_4_2:timer_in| ; 16 (16) ; 3 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 3 (3) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in ; ; |mcm_nw_bittiming_4_2_7_7_2:bt1| ; 79 (49) ; 17 ; 0 ; 0 ; 0 ; 62 (45) ; 5 (1) ; 12 (3) ; 9 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1 ; ; |hamm_reg_4_0_1:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1 ; ; |mcm_nw_destuffing_7:destuff_in| ; 10 (10) ; 6 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 6 (6) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in ; ; |mcm_nw_timer_4_2:timer_in| ; 16 (16) ; 3 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 3 (3) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in ; ; |mcm_nw_inbuf_69_4_7:ib0| ; 107 (107) ; 92 ; 0 ; 0 ; 0 ; 15 (15) ; 69 (69) ; 23 (23) ; 7 (7) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0 ; ; |mcm_nw_inbuf_69_4_7:ib1| ; 107 (107) ; 92 ; 0 ; 0 ; 0 ; 15 (15) ; 69 (69) ; 23 (23) ; 7 (7) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1 ; ; |mcm_nw_outbuf_69_7:ob0| ; 102 (102) ; 92 ; 0 ; 0 ; 0 ; 10 (10) ; 81 (81) ; 11 (11) ; 7 (7) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0 ; ; |mcm_nw_outbuf_69_7:ob1| ; 102 (102) ; 92 ; 0 ; 0 ; 0 ; 10 (10) ; 81 (81) ; 11 (11) ; 7 (7) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1 ; ; |mcm_nw_sendtiming_4_7_63:st0| ; 55 (16) ; 20 ; 0 ; 0 ; 0 ; 35 (15) ; 3 (0) ; 17 (1) ; 12 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0 ; ; |hamm_reg_3_0_1:h1| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|hamm_reg_3_0_1:h1 ; ; |mcm_nw_stuffing_7:stuff_in| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in ; ; |mcm_nw_timer_4_0:timer_in| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in ; ; |mcm_nw_timer_63_63:sleeptimer| ; 17 (17) ; 7 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 7 (7) ; 6 (6) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer ; ; |mcm_nw_sendtiming_4_7_63:st1| ; 55 (16) ; 20 ; 0 ; 0 ; 0 ; 35 (15) ; 3 (0) ; 17 (1) ; 12 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1 ; ; |hamm_reg_3_0_1:h1| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|hamm_reg_3_0_1:h1 ; ; |mcm_nw_stuffing_7:stuff_in| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in ; ; |mcm_nw_timer_4_0:timer_in| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in ; ; |mcm_nw_timer_63_63:sleeptimer| ; 17 (17) ; 7 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 7 (7) ; 6 (6) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer ; ; |mcm_nw_nwl:nw_nwl| ; 375 (106) ; 16 ; 0 ; 0 ; 0 ; 359 (103) ; 12 (1) ; 4 (2) ; 16 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl ; ; |hamm_reg_3_0_1_unfolded0:h1| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|hamm_reg_3_0_1_unfolded0:h1 ; ; |mcm_nw_nwsl:sl0| ; 133 (129) ; 5 ; 0 ; 0 ; 0 ; 128 (128) ; 4 (0) ; 1 (1) ; 8 (8) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0 ; ; |hamm_reg_4_0_1:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1 ; ; |mcm_nw_nwsl:sl1| ; 133 (129) ; 5 ; 0 ; 0 ; 0 ; 128 (128) ; 4 (0) ; 1 (1) ; 8 (8) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1 ; ; |hamm_reg_4_0_1:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1 ; ; |mcm_nw_pl_1:nw_pl| ; 8 (8) ; 6 ; 0 ; 0 ; 0 ; 2 (2) ; 4 (4) ; 2 (2) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl ; ; |ni2io_wt:wt_ni| ; 353 (147) ; 147 ; 65536 ; 0 ; 0 ; 206 (96) ; 62 (40) ; 85 (11) ; 73 (9) ; |top|ni2io_wt:wt_ni ; ; |clk_counter:scnt| ; 26 (10) ; 24 ; 0 ; 0 ; 0 ; 2 (2) ; 2 (2) ; 22 (6) ; 16 (0) ; |top|ni2io_wt:wt_ni|clk_counter:scnt ; ; |counter_8:cnt_c| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; |top|ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c ; ; |counter_8:cnt_s| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; |top|ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s ; ; |ni2io:ni| ; 180 (0) ; 72 ; 65536 ; 0 ; 0 ; 108 (0) ; 20 (0) ; 52 (0) ; 48 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni ; ; |ni2dpm_12:ni_neg| ; 90 (20) ; 36 ; 32768 ; 0 ; 0 ; 54 (18) ; 10 (0) ; 26 (2) ; 24 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg ; ; |counter_12:parc| ; 12 (12) ; 12 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 12 (12) ; 12 (12) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc ; ; |counter_12:wa_p| ; 12 (12) ; 12 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 12 (12) ; 12 (12) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p ; ; |ni_dpram:dpram| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component ; ; |altsyncram_oj71:auto_generated| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated ; ; |ni_exclude_in_10_4:ex_p| ; 36 (36) ; 0 ; 0 ; 0 ; 0 ; 36 (36) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p ; ; |reg_clr_10:rg1p| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p ; ; |ni2dpm_12:ni_pos| ; 90 (20) ; 36 ; 32768 ; 0 ; 0 ; 54 (18) ; 10 (0) ; 26 (2) ; 24 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos ; ; |counter_12:parc| ; 12 (12) ; 12 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 12 (12) ; 12 (12) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc ; ; |counter_12:wa_p| ; 12 (12) ; 12 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 12 (12) ; 12 (12) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p ; ; |ni_dpram:dpram| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component ; ; |altsyncram_oj71:auto_generated| ; 0 (0) ; 0 ; 32768 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated ; ; |ni_exclude_in_10_4:ex_p| ; 36 (36) ; 0 ; 0 ; 0 ; 0 ; 36 (36) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p ; ; |reg_clr_10:rg1p| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; |top|ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p ; ; |pll120:PLL| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|pll120:PLL ; ; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|pll120:PLL|altpll:altpll_component ; +----------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ ; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; +----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ ; ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024 ; 16 ; 512 ; 32 ; 16384 ; None ; ; ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096 ; 8 ; 2048 ; 16 ; 32768 ; None ; ; ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096 ; 8 ; 2048 ; 16 ; 32768 ; None ; +----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 1446 ; ; Number of registers using Synchronous Clear ; 257 ; ; Number of registers using Synchronous Load ; 321 ; ; Number of registers using Asynchronous Clear ; 577 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 1094 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +-------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component ; +------------------------------------+-----------------+------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+-----------------+------------------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 16 ; Integer ; ; WIDTHAD_A ; 10 ; Integer ; ; NUMWORDS_A ; 1024 ; Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; NONE ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; NONE ; Untyped ; ; INDATA_ACLR_A ; NONE ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 32 ; Integer ; ; WIDTHAD_B ; 9 ; Integer ; ; NUMWORDS_B ; 512 ; Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; CLOCK1 ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; DEVICE_FAMILY ; Cyclone ; Untyped ; ; CBXI_PARAMETER ; altsyncram_hl61 ; Untyped ; +------------------------------------+-----------------+------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pll120:PLL|altpll:altpll_component ; +-------------------------------+-------------------+-----------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------------------+-----------------------------+ ; OPERATION_MODE ; NORMAL ; Untyped ; ; PLL_TYPE ; AUTO ; Untyped ; ; QUALIFY_CONF_DONE ; OFF ; Untyped ; ; COMPENSATE_CLOCK ; CLK0 ; Untyped ; ; SCAN_CHAIN ; LONG ; Untyped ; ; PRIMARY_CLOCK ; INCLK0 ; Untyped ; ; INCLK0_INPUT_FREQUENCY ; 13888 ; Integer ; ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; ; GATE_LOCK_SIGNAL ; NO ; Untyped ; ; GATE_LOCK_COUNTER ; 0 ; Untyped ; ; LOCK_HIGH ; 1 ; Untyped ; ; LOCK_LOW ; 1 ; Untyped ; ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; ; SKIP_VCO ; OFF ; Untyped ; ; SWITCH_OVER_COUNTER ; 0 ; Untyped ; ; SWITCH_OVER_TYPE ; AUTO ; Untyped ; ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; ; BANDWIDTH ; 0 ; Untyped ; ; BANDWIDTH_TYPE ; AUTO ; Untyped ; ; SPREAD_FREQUENCY ; 0 ; Untyped ; ; DOWN_SPREAD ; 0 ; Untyped ; ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; ; CLK5_MULTIPLY_BY ; 1 ; Untyped ; ; CLK4_MULTIPLY_BY ; 1 ; Untyped ; ; CLK3_MULTIPLY_BY ; 1 ; Untyped ; ; CLK2_MULTIPLY_BY ; 1 ; Untyped ; ; CLK1_MULTIPLY_BY ; 5 ; Integer ; ; CLK0_MULTIPLY_BY ; 5 ; Integer ; ; CLK5_DIVIDE_BY ; 1 ; Untyped ; ; CLK4_DIVIDE_BY ; 1 ; Untyped ; ; CLK3_DIVIDE_BY ; 1 ; Untyped ; ; CLK2_DIVIDE_BY ; 1 ; Untyped ; ; CLK1_DIVIDE_BY ; 12 ; Integer ; ; CLK0_DIVIDE_BY ; 3 ; Integer ; ; CLK5_PHASE_SHIFT ; 0 ; Untyped ; ; CLK4_PHASE_SHIFT ; 0 ; Untyped ; ; CLK3_PHASE_SHIFT ; 0 ; Untyped ; ; CLK2_PHASE_SHIFT ; 0 ; Untyped ; ; CLK1_PHASE_SHIFT ; 0 ; Untyped ; ; CLK0_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_TIME_DELAY ; 0 ; Untyped ; ; CLK4_TIME_DELAY ; 0 ; Untyped ; ; CLK3_TIME_DELAY ; 0 ; Untyped ; ; CLK2_TIME_DELAY ; 0 ; Untyped ; ; CLK1_TIME_DELAY ; 0 ; Untyped ; ; CLK0_TIME_DELAY ; 0 ; Untyped ; ; CLK5_DUTY_CYCLE ; 50 ; Untyped ; ; CLK4_DUTY_CYCLE ; 50 ; Untyped ; ; CLK3_DUTY_CYCLE ; 50 ; Untyped ; ; CLK2_DUTY_CYCLE ; 50 ; Untyped ; ; CLK1_DUTY_CYCLE ; 50 ; Integer ; ; CLK0_DUTY_CYCLE ; 50 ; Integer ; ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; ; VCO_MULTIPLY_BY ; 0 ; Untyped ; ; VCO_DIVIDE_BY ; 0 ; Untyped ; ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; ; VCO_MIN ; 0 ; Untyped ; ; VCO_MAX ; 0 ; Untyped ; ; VCO_CENTER ; 0 ; Untyped ; ; PFD_MIN ; 0 ; Untyped ; ; PFD_MAX ; 0 ; Untyped ; ; M_INITIAL ; 0 ; Untyped ; ; M ; 0 ; Untyped ; ; N ; 1 ; Untyped ; ; M2 ; 1 ; Untyped ; ; N2 ; 1 ; Untyped ; ; SS ; 1 ; Untyped ; ; C0_HIGH ; 0 ; Untyped ; ; C1_HIGH ; 0 ; Untyped ; ; C2_HIGH ; 0 ; Untyped ; ; C3_HIGH ; 0 ; Untyped ; ; C4_HIGH ; 0 ; Untyped ; ; C5_HIGH ; 0 ; Untyped ; ; C0_LOW ; 0 ; Untyped ; ; C1_LOW ; 0 ; Untyped ; ; C2_LOW ; 0 ; Untyped ; ; C3_LOW ; 0 ; Untyped ; ; C4_LOW ; 0 ; Untyped ; ; C5_LOW ; 0 ; Untyped ; ; C0_INITIAL ; 0 ; Untyped ; ; C1_INITIAL ; 0 ; Untyped ; ; C2_INITIAL ; 0 ; Untyped ; ; C3_INITIAL ; 0 ; Untyped ; ; C4_INITIAL ; 0 ; Untyped ; ; C5_INITIAL ; 0 ; Untyped ; ; C0_MODE ; BYPASS ; Untyped ; ; C1_MODE ; BYPASS ; Untyped ; ; C2_MODE ; BYPASS ; Untyped ; ; C3_MODE ; BYPASS ; Untyped ; ; C4_MODE ; BYPASS ; Untyped ; ; C5_MODE ; BYPASS ; Untyped ; ; C0_PH ; 0 ; Untyped ; ; C1_PH ; 0 ; Untyped ; ; C2_PH ; 0 ; Untyped ; ; C3_PH ; 0 ; Untyped ; ; C4_PH ; 0 ; Untyped ; ; C5_PH ; 0 ; Untyped ; ; L0_HIGH ; 1 ; Untyped ; ; L1_HIGH ; 1 ; Untyped ; ; G0_HIGH ; 1 ; Untyped ; ; G1_HIGH ; 1 ; Untyped ; ; G2_HIGH ; 1 ; Untyped ; ; G3_HIGH ; 1 ; Untyped ; ; E0_HIGH ; 1 ; Untyped ; ; E1_HIGH ; 1 ; Untyped ; ; E2_HIGH ; 1 ; Untyped ; ; E3_HIGH ; 1 ; Untyped ; ; L0_LOW ; 1 ; Untyped ; ; L1_LOW ; 1 ; Untyped ; ; G0_LOW ; 1 ; Untyped ; ; G1_LOW ; 1 ; Untyped ; ; G2_LOW ; 1 ; Untyped ; ; G3_LOW ; 1 ; Untyped ; ; E0_LOW ; 1 ; Untyped ; ; E1_LOW ; 1 ; Untyped ; ; E2_LOW ; 1 ; Untyped ; ; E3_LOW ; 1 ; Untyped ; ; L0_INITIAL ; 1 ; Untyped ; ; L1_INITIAL ; 1 ; Untyped ; ; G0_INITIAL ; 1 ; Untyped ; ; G1_INITIAL ; 1 ; Untyped ; ; G2_INITIAL ; 1 ; Untyped ; ; G3_INITIAL ; 1 ; Untyped ; ; E0_INITIAL ; 1 ; Untyped ; ; E1_INITIAL ; 1 ; Untyped ; ; E2_INITIAL ; 1 ; Untyped ; ; E3_INITIAL ; 1 ; Untyped ; ; L0_MODE ; BYPASS ; Untyped ; ; L1_MODE ; BYPASS ; Untyped ; ; G0_MODE ; BYPASS ; Untyped ; ; G1_MODE ; BYPASS ; Untyped ; ; G2_MODE ; BYPASS ; Untyped ; ; G3_MODE ; BYPASS ; Untyped ; ; E0_MODE ; BYPASS ; Untyped ; ; E1_MODE ; BYPASS ; Untyped ; ; E2_MODE ; BYPASS ; Untyped ; ; E3_MODE ; BYPASS ; Untyped ; ; L0_PH ; 0 ; Untyped ; ; L1_PH ; 0 ; Untyped ; ; G0_PH ; 0 ; Untyped ; ; G1_PH ; 0 ; Untyped ; ; G2_PH ; 0 ; Untyped ; ; G3_PH ; 0 ; Untyped ; ; E0_PH ; 0 ; Untyped ; ; E1_PH ; 0 ; Untyped ; ; E2_PH ; 0 ; Untyped ; ; E3_PH ; 0 ; Untyped ; ; M_PH ; 0 ; Untyped ; ; C1_USE_CASC_IN ; 0 ; Untyped ; ; C2_USE_CASC_IN ; 0 ; Untyped ; ; C3_USE_CASC_IN ; 0 ; Untyped ; ; C4_USE_CASC_IN ; 0 ; Untyped ; ; C5_USE_CASC_IN ; 0 ; Untyped ; ; CLK0_COUNTER ; G0 ; Untyped ; ; CLK1_COUNTER ; G0 ; Untyped ; ; CLK2_COUNTER ; G0 ; Untyped ; ; CLK3_COUNTER ; G0 ; Untyped ; ; CLK4_COUNTER ; G0 ; Untyped ; ; CLK5_COUNTER ; G0 ; Untyped ; ; L0_TIME_DELAY ; 0 ; Untyped ; ; L1_TIME_DELAY ; 0 ; Untyped ; ; G0_TIME_DELAY ; 0 ; Untyped ; ; G1_TIME_DELAY ; 0 ; Untyped ; ; G2_TIME_DELAY ; 0 ; Untyped ; ; G3_TIME_DELAY ; 0 ; Untyped ; ; E0_TIME_DELAY ; 0 ; Untyped ; ; E1_TIME_DELAY ; 0 ; Untyped ; ; E2_TIME_DELAY ; 0 ; Untyped ; ; E3_TIME_DELAY ; 0 ; Untyped ; ; M_TIME_DELAY ; 0 ; Untyped ; ; N_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_COUNTER ; E3 ; Untyped ; ; EXTCLK2_COUNTER ; E2 ; Untyped ; ; EXTCLK1_COUNTER ; E1 ; Untyped ; ; EXTCLK0_COUNTER ; E0 ; Untyped ; ; ENABLE0_COUNTER ; L0 ; Untyped ; ; ENABLE1_COUNTER ; L0 ; Untyped ; ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; ; LOOP_FILTER_R ; 1.000000 ; Untyped ; ; LOOP_FILTER_C ; 5 ; Untyped ; ; VCO_POST_SCALE ; 0 ; Untyped ; ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; INTENDED_DEVICE_FAMILY ; Cyclone ; Untyped ; ; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ; ; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; ; M_TEST_SOURCE ; 5 ; Untyped ; ; C0_TEST_SOURCE ; 5 ; Untyped ; ; C1_TEST_SOURCE ; 5 ; Untyped ; ; C2_TEST_SOURCE ; 5 ; Untyped ; ; C3_TEST_SOURCE ; 5 ; Untyped ; ; C4_TEST_SOURCE ; 5 ; Untyped ; ; C5_TEST_SOURCE ; 5 ; Untyped ; ; DEVICE_FAMILY ; Cyclone ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +-------------------------------+-------------------+-----------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component ; +------------------------------------+-----------------+-------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+-----------------+-------------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 8 ; Integer ; ; WIDTHAD_A ; 12 ; Integer ; ; NUMWORDS_A ; 4096 ; Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; CLEAR0 ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; CLEAR0 ; Untyped ; ; INDATA_ACLR_A ; CLEAR0 ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 16 ; Integer ; ; WIDTHAD_B ; 11 ; Integer ; ; NUMWORDS_B ; 2048 ; Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; CLOCK1 ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; DEVICE_FAMILY ; Cyclone ; Untyped ; ; CBXI_PARAMETER ; altsyncram_oj71 ; Untyped ; +------------------------------------+-----------------+-------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component ; +------------------------------------+-----------------+-------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------+-----------------+-------------------------------------------------------------------------------+ ; BYTE_SIZE_BLOCK ; 8 ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ; OPERATION_MODE ; DUAL_PORT ; Untyped ; ; WIDTH_A ; 8 ; Integer ; ; WIDTHAD_A ; 12 ; Integer ; ; NUMWORDS_A ; 4096 ; Integer ; ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; ; ADDRESS_ACLR_A ; CLEAR0 ; Untyped ; ; OUTDATA_ACLR_A ; NONE ; Untyped ; ; WRCONTROL_ACLR_A ; CLEAR0 ; Untyped ; ; INDATA_ACLR_A ; CLEAR0 ; Untyped ; ; BYTEENA_ACLR_A ; NONE ; Untyped ; ; WIDTH_B ; 16 ; Integer ; ; WIDTHAD_B ; 11 ; Integer ; ; NUMWORDS_B ; 2048 ; Integer ; ; INDATA_REG_B ; CLOCK1 ; Untyped ; ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; ; ADDRESS_REG_B ; CLOCK1 ; Untyped ; ; OUTDATA_REG_B ; CLOCK1 ; Untyped ; ; BYTEENA_REG_B ; CLOCK1 ; Untyped ; ; INDATA_ACLR_B ; NONE ; Untyped ; ; WRCONTROL_ACLR_B ; NONE ; Untyped ; ; ADDRESS_ACLR_B ; NONE ; Untyped ; ; OUTDATA_ACLR_B ; NONE ; Untyped ; ; RDCONTROL_ACLR_B ; NONE ; Untyped ; ; BYTEENA_ACLR_B ; NONE ; Untyped ; ; WIDTH_BYTEENA_A ; 1 ; Integer ; ; WIDTH_BYTEENA_B ; 1 ; Untyped ; ; RAM_BLOCK_TYPE ; AUTO ; Untyped ; ; BYTE_SIZE ; 8 ; Untyped ; ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; ; INIT_FILE ; UNUSED ; Untyped ; ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; ; MAXIMUM_DEPTH ; 0 ; Untyped ; ; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; ; DEVICE_FAMILY ; Cyclone ; Untyped ; ; CBXI_PARAMETER ; altsyncram_oj71 ; Untyped ; +------------------------------------+-----------------+-------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------+ ; Analysis & Synthesis Equations ; +--------------------------------+ The equations can be found in M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_wadcdac/top.map.eqn. +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version Info: Processing started: Mon Oct 10 11:50:47 2005 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top Info: Found 2 design units, including 1 entities, in source file pasaadc_ram.vhd Info: Found design unit 1: pasaadc_ram-SYN Info: Found entity 1: pasaadc_ram Info: Found 2 design units, including 1 entities, in source file pasadac_ram.vhd Info: Found design unit 1: pasadac_ram-SYN Info: Found entity 1: pasadac_ram Info: Found 2 design units, including 1 entities, in source file pll120.vhd Info: Found design unit 1: pll120-SYN Info: Found entity 1: pll120 Info: Found 37 design units, including 37 entities, in source file top.edf Info: Found entity 1: ADC_DAC_1_notri Info: Found entity 2: clk_counter Info: Found entity 3: counter_12 Info: Found entity 4: counter_8 Info: Found entity 5: DDS Info: Found entity 6: digpot4 Info: Found entity 7: gio_devices_adc Info: Found entity 8: hamm_reg_3_0_1 Info: Found entity 9: hamm_reg_3_0_1_unfolded0 Info: Found entity 10: hamm_reg_4_0_1 Info: Found entity 11: hamm_reg_4_0_1_unfolded0 Info: Found entity 12: mcm_network_interface Info: Found entity 13: mcm_nw_apl Info: Found entity 14: mcm_nw_bittiming_4_2_7_7_2 Info: Found entity 15: mcm_nw_destuffing_7 Info: Found entity 16: mcm_nw_dll_4_2_7_63_69_4_7 Info: Found entity 17: mcm_nw_inbuf_69_4_7 Info: Found entity 18: mcm_nw_nwl Info: Found entity 19: mcm_nw_nwsl Info: Found entity 20: mcm_nw_outbuf_69_7 Info: Found entity 21: mcm_nw_pl_1 Info: Found entity 22: mcm_nw_sendtiming_4_7_63 Info: Found entity 23: mcm_nw_stuffing_7 Info: Found entity 24: mcm_nw_timer_4_0 Info: Found entity 25: mcm_nw_timer_4_2 Info: Found entity 26: mcm_nw_timer_63_63 Info: Found entity 27: ni2dpm_12 Info: Found entity 28: ni2io Info: Found entity 29: ni2io_wt Info: Found entity 30: ni_exclude_in_10_4 Info: Found entity 31: pasaadc Info: Found entity 32: reg_clr_10 Info: Found entity 33: seradc_auto Info: Found entity 34: seradc_auto_unfolded0 Info: Found entity 35: TLV2548 Info: Found entity 36: TLV5630_16 Info: Found entity 37: top Info: Elaborating entity "top" for the top level hierarchy Info: Elaborating entity "ADC_DAC_1_notri" for hierarchy "ADC_DAC_1_notri:adcdac_notri" Info: Elaborating entity "DDS" for hierarchy "ADC_DAC_1_notri:adcdac_notri|DDS:ddsi" Info: Elaborating entity "digpot4" for hierarchy "ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot" Info: Elaborating entity "gio_devices_adc" for hierarchy "ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio" Info: Elaborating entity "pasaadc" for hierarchy "ADC_DAC_1_notri:adcdac_notri|pasaadc:padc" Info: Elaborating entity "pasaadc_ram" for hierarchy "ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram" Info: Found 1 design units, including 1 entities, in source file d:/quartus50/libraries/megafunctions/altsyncram.tdf Info: Found entity 1: altsyncram Info: Elaborating entity "altsyncram" for hierarchy "ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hl61.tdf Info: Found entity 1: altsyncram_hl61 Info: Elaborating entity "altsyncram_hl61" for hierarchy "ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated" Info: Elaborating entity "seradc_auto" for hierarchy "ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc" Info: Elaborating entity "TLV2548" for hierarchy "ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc" Info: Elaborating entity "seradc_auto_unfolded0" for hierarchy "ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc" Info: Elaborating entity "TLV5630_16" for hierarchy "ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2" Info: Elaborating entity "pll120" for hierarchy "pll120:PLL" Info: Found 1 design units, including 1 entities, in source file d:/quartus50/libraries/megafunctions/altpll.tdf Info: Found entity 1: altpll Info: Elaborating entity "altpll" for hierarchy "pll120:PLL|altpll:altpll_component" Info: Elaborating entity "mcm_network_interface" for hierarchy "mcm_network_interface:scsn_slave" Info: Elaborating entity "mcm_nw_apl" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl" Info: Elaborating entity "hamm_reg_4_0_1_unfolded0" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1" Info: Elaborating entity "mcm_nw_dll_4_2_7_63_69_4_7" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll" Info: Elaborating entity "mcm_nw_bittiming_4_2_7_7_2" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0" Info: Elaborating entity "mcm_nw_destuffing_7" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in" Info: Elaborating entity "hamm_reg_4_0_1" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1" Info: Elaborating entity "mcm_nw_timer_4_2" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in" Info: Elaborating entity "mcm_nw_inbuf_69_4_7" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0" Info: Elaborating entity "mcm_nw_outbuf_69_7" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0" Info: Elaborating entity "mcm_nw_sendtiming_4_7_63" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0" Info: Elaborating entity "hamm_reg_3_0_1" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|hamm_reg_3_0_1:h1" Info: Elaborating entity "mcm_nw_timer_63_63" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer" Info: Elaborating entity "mcm_nw_stuffing_7" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in" Info: Elaborating entity "mcm_nw_timer_4_0" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in" Info: Elaborating entity "mcm_nw_nwl" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl" Info: Elaborating entity "hamm_reg_3_0_1_unfolded0" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|hamm_reg_3_0_1_unfolded0:h1" Info: Elaborating entity "mcm_nw_nwsl" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0" Info: Elaborating entity "mcm_nw_pl_1" for hierarchy "mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl" Info: Elaborating entity "ni2io_wt" for hierarchy "ni2io_wt:wt_ni" Info: Elaborating entity "ni2io" for hierarchy "ni2io_wt:wt_ni|ni2io:ni" Info: Elaborating entity "ni2dpm_12" for hierarchy "ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg" Info: Using design file ni_dpram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: ni_dpram-SYN Info: Found entity 1: ni_dpram Info: Elaborating entity "ni_dpram" for hierarchy "ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram" Info: Elaborating entity "altsyncram" for hierarchy "ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_oj71.tdf Info: Found entity 1: altsyncram_oj71 Info: Elaborating entity "altsyncram_oj71" for hierarchy "ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated" Info: Elaborating entity "ni_exclude_in_10_4" for hierarchy "ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p" Info: Elaborating entity "counter_12" for hierarchy "ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc" Info: Elaborating entity "reg_clr_10" for hierarchy "ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p" Info: Elaborating entity "clk_counter" for hierarchy "ni2io_wt:wt_ni|clk_counter:scnt" Info: Elaborating entity "counter_8" for hierarchy "ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c" Warning: Output pins are stuck at VCC or GND Warning: Pin "PA_VDD" stuck at VCC Warning: Pin "PasaDAC1_CLK" stuck at GND Warning: Pin "PasaDAC2_CLK" stuck at GND Warning: Pin "PasaDAC_D[0]" stuck at GND Warning: Pin "PasaDAC_D[1]" stuck at GND Warning: Pin "PasaDAC_D[2]" stuck at GND Warning: Pin "PasaDAC_D[3]" stuck at GND Warning: Pin "PasaDAC_D[4]" stuck at GND Warning: Pin "PasaDAC_D[5]" stuck at GND Warning: Pin "PasaDAC_D[6]" stuck at GND Warning: Pin "PasaDAC_D[7]" stuck at GND Warning: Pin "PasaDAC_D[8]" stuck at GND Warning: Pin "PasaDAC_D[9]" stuck at GND Warning: Pin "PasaDAC_D[10]" stuck at GND Warning: Pin "PasaDAC_D[11]" stuck at GND Warning: Pin "PasaDAC_D[12]" stuck at GND Warning: Pin "PasaDAC_D[13]" stuck at GND Warning: Pin "PasaDAC_Sleep" stuck at VCC Warning: Pin "VGND[0]" stuck at GND Warning: Pin "VGND[1]" stuck at GND Warning: Pin "VGND[2]" stuck at GND Info: Found the following redundant logic cells in design Info: Logic cell "ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|b_0_dup_240" Info: Logic cell "ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|b_1_dup_418" Info: Logic cell "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx149" Info: Logic cell "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx149" Info: Logic cell "ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx1229" Info: Logic cell "ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx1229" Info: Logic cell "mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_60" Info: Logic cell "mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_60" Info: Logic cell "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx142" Info: Logic cell "mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx142" Warning: Design contains 5 input pin(s) that do not drive logic Warning: No output dependent on input pin "MSply_ADC_INTn" Warning: No output dependent on input pin "PA_SCLK" Warning: No output dependent on input pin "PA_SDAT" Warning: No output dependent on input pin "PA_SSTR" Warning: No output dependent on input pin "SC_ADC_INTn" Info: Implemented 3292 device resources after synthesis - the final resource count might be different Info: Implemented 37 input pins Info: Implemented 70 output pins Info: Implemented 1 bidirectional pins Info: Implemented 3151 logic cells Info: Implemented 32 RAM segments Info: Implemented 1 ClockLock PLLs Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings Info: Processing ended: Mon Oct 10 11:51:17 2005 Info: Elapsed time: 00:00:31