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Please refer to the -- applicable agreement for further details. --B1_AD_SYNC_OUT_0 is ADC_DAC_1_notri:adcdac_notri|AD_SYNC_OUT_0 --operation mode is normal B1_AD_SYNC_OUT_0_lut_out = AD_SYNC_IN[0]; B1_AD_SYNC_OUT_0 = DFFEAS(B1_AD_SYNC_OUT_0_lut_out, S1__clk1, VCC, , , , , , ); --B1_AD_SYNC_OUT_1 is ADC_DAC_1_notri:adcdac_notri|AD_SYNC_OUT_1 --operation mode is normal B1_AD_SYNC_OUT_1_lut_out = AD_SYNC_IN[1]; B1_AD_SYNC_OUT_1 = DFFEAS(B1_AD_SYNC_OUT_1_lut_out, S1__clk1, VCC, , , , , , ); --F1_NOT_DDS_CSn is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_DDS_CSn --operation mode is normal F1_NOT_DDS_CSn_lut_out = F1_flag2send # F1_NOT_sm_top_0; F1_NOT_DDS_CSn = DFFEAS(F1_NOT_DDS_CSn_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --F1_DDS_FSK is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|DDS_FSK --operation mode is normal F1_DDS_FSK_lut_out = V1_request_26; F1_DDS_FSK = DFFEAS(F1_DDS_FSK_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx429, , , , ); --F1_NOT_DDS_IORST is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_DDS_IORST --operation mode is normal F1_NOT_DDS_IORST_lut_out = F1_flag2send; F1_NOT_DDS_IORST = DFFEAS(F1_NOT_DDS_IORST_lut_out, S1__clk1, T1_chipRST_n, , !F1_NOT_sm_top_0, , , , ); --F1_DDS_MCLK is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|DDS_MCLK --operation mode is normal F1_DDS_MCLK = S1__clk1 & F1_config_1; --F1_DDS_MRST is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|DDS_MRST --operation mode is normal F1_DDS_MRST = F1_config_0 # !T1_chipRST_n; --F1_DDS_SCLK is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|DDS_SCLK --operation mode is normal F1_DDS_SCLK_lut_out = F1_sm_sr_4 # F1_sm_sr_1; F1_DDS_SCLK = DFFEAS(F1_DDS_SCLK_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, , , , ); --F1_DDS_SDI is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|DDS_SDI --operation mode is normal F1_DDS_SDI_lut_out = F1_sm_sr_3 & F1_byte_send_7 # !F1_sm_sr_3 & (F1_DDS_SDI); F1_DDS_SDI = DFFEAS(F1_DDS_SDI_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, , , , ); --F1_DDS_ShKey is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|DDS_ShKey --operation mode is normal F1_DDS_ShKey_lut_out = V1_request_27; F1_DDS_ShKey = DFFEAS(F1_DDS_ShKey_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx429, , , , ); --F1_DDS_UDCLK is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|DDS_UDCLK --operation mode is normal F1_DDS_UDCLK = F1_config_2 # F1_config_3 & !F1_NOT_udclk; --R1_RDY is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDY --operation mode is normal R1_RDY_lut_out = !K1_ce_adc & !R1_nx60; R1_RDY = DFFEAS(R1_RDY_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_NOT_ADC_nCSStrt is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_ADC_nCSStrt --operation mode is normal K1_NOT_ADC_nCSStrt_lut_out = K1_sm_2; K1_NOT_ADC_nCSStrt = DFFEAS(K1_NOT_ADC_nCSStrt_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R1_ADC_SCLK is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|ADC_SCLK --operation mode is normal R1_ADC_SCLK_lut_out = R1_sm_2; R1_ADC_SCLK = DFFEAS(R1_ADC_SCLK_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R1_ADC_SDI is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|ADC_SDI --operation mode is normal R1_ADC_SDI_lut_out = K1_cmd_adc_1 & (R1_datasr_14 & R1_ADC_SCLK # !R1_nx60) # !K1_cmd_adc_1 & R1_datasr_14 & (R1_ADC_SCLK); R1_ADC_SDI = DFFEAS(R1_ADC_SDI_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --J1_PAADC_CLK is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|PAADC_CLK --operation mode is normal J1_PAADC_CLK = S1__clk1 $ J1_cfr_5; --J1_PAADC_Msel is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|PAADC_Msel --operation mode is normal J1_PAADC_Msel_lut_out = V1_request_29; J1_PAADC_Msel = DFFEAS(J1_PAADC_Msel_lut_out, S1__clk1, T1_chipRST_n, , J1_wren_cfr, , , , ); --J1_PAADC_MuxA_0 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|PAADC_MuxA_0 --operation mode is normal J1_PAADC_MuxA_0_lut_out = V1_request_31; J1_PAADC_MuxA_0 = DFFEAS(J1_PAADC_MuxA_0_lut_out, S1__clk1, T1_chipRST_n, , J1_wren_cfr, , , , ); --J1_PAADC_MuxA_1 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|PAADC_MuxA_1 --operation mode is normal J1_PAADC_MuxA_1_lut_out = V1_request_30; J1_PAADC_MuxA_1 = DFFEAS(J1_PAADC_MuxA_1_lut_out, S1__clk1, T1_chipRST_n, , J1_wren_cfr, , , , ); --J1_PAADC_MuxnRS is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|PAADC_MuxnRS --operation mode is normal J1_PAADC_MuxnRS_lut_out = V1_request_27; J1_PAADC_MuxnRS = DFFEAS(J1_PAADC_MuxnRS_lut_out, S1__clk1, T1_chipRST_n, , J1_wren_cfr, , , , ); --J1_PAADC_STDP is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|PAADC_STDP --operation mode is normal J1_PAADC_STDP = !J1_sm & J1_cfr_3; --G1_NOT_CSn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|NOT_CSn --operation mode is normal G1_NOT_CSn_lut_out = T1_rd_wr_oase # G1_nx544 # !V1_request_24 # !H1_ce_digpot; G1_NOT_CSn = DFFEAS(G1_NOT_CSn_lut_out, S1__clk1, T1_chipRST_n, , G1_nx337, , , , ); --G2_NOT_CSn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|NOT_CSn --operation mode is normal G2_NOT_CSn_lut_out = T1_rd_wr_oase # G2_nx544 # !V1_request_16 # !H1_ce_digpot; G2_NOT_CSn = DFFEAS(G2_NOT_CSn_lut_out, S1__clk1, T1_chipRST_n, , G2_nx337, , , , ); --G3_NOT_CSn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|NOT_CSn --operation mode is normal G3_NOT_CSn_lut_out = T1_rd_wr_oase # G3_nx544 # !V1_request_8 # !H1_ce_digpot; G3_NOT_CSn = DFFEAS(G3_NOT_CSn_lut_out, S1__clk1, T1_chipRST_n, , G3_nx337, , , , ); --G4_NOT_CSn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|NOT_CSn --operation mode is normal G4_NOT_CSn_lut_out = T1_rd_wr_oase # G4_nx544 # !V1_request_0 # !H1_ce_digpot; G4_NOT_CSn = DFFEAS(G4_NOT_CSn_lut_out, S1__clk1, T1_chipRST_n, , G4_nx337, , , , ); --G1_NOT_INCn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|NOT_INCn --operation mode is normal G1_NOT_INCn_lut_out = G1_cnt_6 # G1_cnt_0 # !G1_nx572 # !G1_cnt_5; G1_NOT_INCn = DFFEAS(G1_NOT_INCn_lut_out, S1__clk1, T1_chipRST_n, , G1_NOT_nx149, , , , ); --G2_NOT_INCn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|NOT_INCn --operation mode is normal G2_NOT_INCn_lut_out = G2_cnt_6 # G2_cnt_0 # !G2_nx572 # !G2_cnt_5; G2_NOT_INCn = DFFEAS(G2_NOT_INCn_lut_out, S1__clk1, T1_chipRST_n, , G2_NOT_nx149, , , , ); --G3_NOT_INCn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|NOT_INCn --operation mode is normal G3_NOT_INCn_lut_out = G3_cnt_6 # G3_cnt_0 # !G3_nx572 # !G3_cnt_5; G3_NOT_INCn = DFFEAS(G3_NOT_INCn_lut_out, S1__clk1, T1_chipRST_n, , G3_NOT_nx149, , , , ); --G4_NOT_INCn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|NOT_INCn --operation mode is normal G4_NOT_INCn_lut_out = G4_cnt_6 # G4_cnt_0 # !G4_nx572 # !G4_cnt_5; G4_NOT_INCn = DFFEAS(G4_NOT_INCn_lut_out, S1__clk1, T1_chipRST_n, , G4_NOT_nx149, , , , ); --G1_NOT_UDn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|NOT_UDn --operation mode is normal G1_NOT_UDn_lut_out = !G1_nx66; G1_NOT_UDn = DFFEAS(G1_NOT_UDn_lut_out, S1__clk1, T1_chipRST_n, , G1_NOT_nx79, , , , ); --G2_NOT_UDn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|NOT_UDn --operation mode is normal G2_NOT_UDn_lut_out = !G2_nx66; G2_NOT_UDn = DFFEAS(G2_NOT_UDn_lut_out, S1__clk1, T1_chipRST_n, , G2_NOT_nx79, , , , ); --G3_NOT_UDn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|NOT_UDn --operation mode is normal G3_NOT_UDn_lut_out = !G3_nx66; G3_NOT_UDn = DFFEAS(G3_NOT_UDn_lut_out, S1__clk1, T1_chipRST_n, , G3_NOT_nx79, , , , ); --G4_NOT_UDn is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|NOT_UDn --operation mode is normal G4_NOT_UDn_lut_out = !G4_nx66; G4_NOT_UDn = DFFEAS(G4_NOT_UDn_lut_out, S1__clk1, T1_chipRST_n, , G4_NOT_nx79, , , , ); --R2_RDY is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDY --operation mode is normal R2_RDY_lut_out = !L1_ce_adc & !R2_nx60; R2_RDY = DFFEAS(R2_RDY_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_NOT_ADC_nCSStrt is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_ADC_nCSStrt --operation mode is normal L1_NOT_ADC_nCSStrt_lut_out = L1_sm_2; L1_NOT_ADC_nCSStrt = DFFEAS(L1_NOT_ADC_nCSStrt_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R2_ADC_SCLK is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|ADC_SCLK --operation mode is normal R2_ADC_SCLK_lut_out = R2_sm_2; R2_ADC_SCLK = DFFEAS(R2_ADC_SCLK_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R2_ADC_SDI is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|ADC_SDI --operation mode is normal R2_ADC_SDI_lut_out = L1_cmd_adc_1 & (R2_datasr_14 & R2_ADC_SCLK # !R2_nx60) # !L1_cmd_adc_1 & R2_datasr_14 & (R2_ADC_SCLK); R2_ADC_SDI = DFFEAS(R2_ADC_SDI_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --U1_d0_to_pl is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|d0_to_pl --operation mode is normal U1_d0_to_pl = V1_bridge & (BB2_data_out_to_pl) # !V1_bridge & BB1_data_out_to_pl; --U1_d1_to_pl is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|d1_to_pl --operation mode is normal U1_d1_to_pl = V1_bridge & BB1_data_out_to_pl # !V1_bridge & (BB2_data_out_to_pl); --M1_SSTR is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|SSTR --operation mode is normal M1_SSTR_lut_out = M1_SERREG_3 # M1_SERREG_1 & M1_NOT_CNT_FF_4 & M1_nx142; M1_SSTR = DFFEAS(M1_SSTR_lut_out, S1__clk1, T1_chipRST_n, , M1_cnt_div, , , , ); --M1_NOT_LDACn is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|NOT_LDACn --operation mode is normal M1_NOT_LDACn_lut_out = M1_PQ_16 & (M1_SERREG_5 & M1_SL # !M1_SERREG_5 & (M1_SERREG_4)); M1_NOT_LDACn = DFFEAS(M1_NOT_LDACn_lut_out, S1__clk1, T1_chipRST_n, , M1_cnt_div, , , , ); --M1_SCLK is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|SCLK --operation mode is normal M1_SCLK_lut_out = !M1_SERREG_3 & !M1_SERREG_2; M1_SCLK = DFFEAS(M1_SCLK_lut_out, S1__clk1, T1_chipRST_n, , M1_cnt_div, , , , ); --M1_SDAT is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|SDAT --operation mode is normal M1_SDAT = M1_PQ_15 & M1_nx116; --S1__clk0 is pll120:PLL|altpll:altpll_component|_clk0 S1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(GND), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(CLK_gen), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA()); --S1__clk1 is pll120:PLL|altpll:altpll_component|_clk1 S1__clk1 = PLL.CLK1(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(GND), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(CLK_gen), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA()); --F1_NOT_nx479 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx479 --operation mode is normal F1_NOT_nx479 = H1_ce_dds & !T1_rd_wr_oase & V1_request_48 & F1_nx859; --F1_flag2send is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|flag2send --operation mode is normal F1_flag2send = DFFEAS(F1_NOT_nx479, S1__clk1, T1_chipRST_n, , , , , , ); --F1_NOT_sm_top_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_sm_top_0 --operation mode is normal F1_NOT_sm_top_0_lut_out = F1_nx839 & (F1_flag2send # F1_NOT_sm_top_0); F1_NOT_sm_top_0 = DFFEAS(F1_NOT_sm_top_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --T1_chipRST_n is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|chipRST_n --operation mode is normal T1_chipRST_n_lut_out = X1_data_out_2 # !X1_data_out_0 # !X1_data_out_1 # !X1_data_out_3; T1_chipRST_n = DFFEAS(T1_chipRST_n_lut_out, S1__clk0, VCC, , , , , , ); --V1_request_26 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_26 --operation mode is normal V1_request_26 = V1_select_rq & (Z2_data_out_26) # !V1_select_rq & Z1_data_out_26; --F1_NOT_nx429 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx429 --operation mode is normal F1_NOT_nx429 = V1_request_46 & !V1_request_47 & !V1_request_48 & F1_nx8; --F1_config_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|config_1 --operation mode is normal F1_config_1_lut_out = V1_request_30; F1_config_1 = DFFEAS(F1_config_1_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx429, , , , ); --F1_config_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|config_0 --operation mode is normal F1_config_0_lut_out = V1_request_31; F1_config_0 = DFFEAS(F1_config_0_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx429, , , , ); --F1_sm_sr_4 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_sr_4 --operation mode is normal F1_sm_sr_4_lut_out = F1_sm_sr_3; F1_sm_sr_4 = DFFEAS(F1_sm_sr_4_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, , , , ); --F1_sm_sr_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_sr_1 --operation mode is normal F1_sm_sr_1_lut_out = F1_nx842 # F1_start_sm & F1_read_flag & !F1_nx538; F1_sm_sr_1 = DFFEAS(F1_sm_sr_1_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, , , , ); --F1_clkdivs is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|clkdivs --operation mode is normal F1_clkdivs_lut_out = !F1_start_sm & !F1_nx538 # !F1_clkdivs; F1_clkdivs = DFFEAS(F1_clkdivs_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --F1_sm_sr_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_sr_3 --operation mode is normal F1_sm_sr_3_lut_out = F1_sm_sr_4 & (!F1_nx538 & F1_nx845 # !F1_nx843) # !F1_sm_sr_4 & !F1_nx538 & (F1_nx845); F1_sm_sr_3 = DFFEAS(F1_sm_sr_3_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, , , , ); --F1_byte_send_7 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_send_7 --operation mode is normal F1_byte_send_7_lut_out = F1_nx753 # F1_nx754 # F1_nx755 # F1_nx756; F1_byte_send_7 = DFFEAS(F1_byte_send_7_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2817, , , , ); --V1_request_27 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_27 --operation mode is normal V1_request_27 = V1_select_rq & (Z2_data_out_27) # !V1_select_rq & Z1_data_out_27; --F1_config_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|config_3 --operation mode is normal F1_config_3_lut_out = V1_request_28; F1_config_3 = DFFEAS(F1_config_3_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx429, , , , ); --F1_config_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|config_2 --operation mode is normal F1_config_2_lut_out = V1_request_29; F1_config_2 = DFFEAS(F1_config_2_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx429, , , , ); --F1_NOT_udclk is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_udclk --operation mode is normal F1_NOT_udclk_lut_out = F1_sm_top_1; F1_NOT_udclk = DFFEAS(F1_NOT_udclk_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx1490, , , , ); --K1_ce_adc is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|ce_adc --operation mode is normal K1_ce_adc_lut_out = K1_sm_6 # K1_modgen_select_223_nx2 # K1_send_cfr & !K1_nx692; K1_ce_adc = DFFEAS(K1_ce_adc_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R1_nx60 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|nx60 --operation mode is normal R1_nx60_lut_out = !R1_sm_4 & (K1_ce_adc # R1_nx60); R1_nx60 = DFFEAS(R1_nx60_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_sm_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|sm_2 --operation mode is normal K1_sm_2_lut_out = K1_nx988 # !K1_send_cfr & K1_start_cyc & !K1_nx692; K1_sm_2 = DFFEAS(K1_sm_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R1_sm_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|sm_2 --operation mode is normal R1_sm_2_lut_out = R1_sm_1 # R1_ADC_SCLK & (R1_nx95 # R1_nx96); R1_sm_2 = DFFEAS(R1_sm_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_cmd_adc_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cmd_adc_1 --operation mode is normal K1_cmd_adc_1_lut_out = VCC; K1_cmd_adc_1 = DFFEAS(K1_cmd_adc_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R1_datasr_14 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_14 --operation mode is normal R1_datasr_14_lut_out = K1_cmd_adc_2 & (R1_datasr_13 & R1_ADC_SCLK # !R1_nx60) # !K1_cmd_adc_2 & R1_datasr_13 & (R1_ADC_SCLK); R1_datasr_14 = DFFEAS(R1_datasr_14_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --R1_NOT_nx214 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|NOT_nx214 --operation mode is normal R1_NOT_nx214 = R1_nx60 & (R1_ADC_SCLK) # !R1_nx60 & K1_ce_adc; --J1_cfr_5 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|cfr_5 --operation mode is normal J1_cfr_5_lut_out = V1_request_26; J1_cfr_5 = DFFEAS(J1_cfr_5_lut_out, S1__clk1, T1_chipRST_n, , J1_wren_cfr, , , , ); --V1_request_29 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_29 --operation mode is normal V1_request_29 = V1_select_rq & (Z2_data_out_29) # !V1_select_rq & Z1_data_out_29; --J1_wren_cfr is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wren_cfr --operation mode is normal J1_wren_cfr = H1_ce_pasa_adc & !T1_rd_wr_oase & V1_request_38; --V1_request_31 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_31 --operation mode is normal V1_request_31 = V1_select_rq & (Z2_data_out_31) # !V1_select_rq & Z1_data_out_31; --V1_bridge_buffered is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|bridge_buffered --operation mode is normal V1_bridge_buffered = DFFEAS(V1_request_31, S1__clk0, VCC, , V1_nx771, , , , ); --V1_request_30 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_30 --operation mode is normal V1_request_30 = V1_select_rq & (Z2_data_out_30) # !V1_select_rq & Z1_data_out_30; --J1_sm is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|sm --operation mode is normal J1_sm_lut_out = J1_sm & (J1_nx78) # !J1_sm & J1_start_s; J1_sm = DFFEAS(J1_sm_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --J1_cfr_3 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|cfr_3 --operation mode is normal J1_cfr_3_lut_out = V1_request_28; J1_cfr_3 = DFFEAS(J1_cfr_3_lut_out, S1__clk1, T1_chipRST_n, , J1_wren_cfr, , , , ); --T1_rd_wr_oase is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|rd_wr_oase --operation mode is normal T1_rd_wr_oase_lut_out = V1_request_52 # V1_request_50 # !V1_request_49 # !V1_request_51; T1_rd_wr_oase = DFFEAS(T1_rd_wr_oase_lut_out, S1__clk0, VCC, , , , , , ); --H1_ce_digpot is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ce_digpot --operation mode is normal H1_ce_digpot_lut_out = V1_request_41 & V1_request_42 & !H1_modgen_eq_90_nx22 & H1_nx155; H1_ce_digpot = DFFEAS(H1_ce_digpot_lut_out, S1__clk1, VCC, , , , , !T1_bus_req, ); --V1_request_24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_24 --operation mode is normal V1_request_24 = V1_select_rq & (Z2_data_out_24) # !V1_select_rq & Z1_data_out_24; --G1_nx544 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx544 --operation mode is normal G1_nx544_lut_out = G1_nx66 # G1_nx68; G1_nx544 = DFFEAS(G1_nx544_lut_out, S1__clk1, T1_chipRST_n, , G1_nx65, , , , ); --G1_nx337 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx337 --operation mode is normal G1_nx337 = G1_nx544 # !T1_rd_wr_oase & H1_ce_digpot & V1_request_24; --V1_request_16 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_16 --operation mode is normal V1_request_16 = V1_select_rq & (Z2_data_out_16) # !V1_select_rq & Z1_data_out_16; --G2_nx544 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx544 --operation mode is normal G2_nx544_lut_out = G2_nx66 # G2_nx68; G2_nx544 = DFFEAS(G2_nx544_lut_out, S1__clk1, T1_chipRST_n, , G2_nx65, , , , ); --G2_nx337 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx337 --operation mode is normal G2_nx337 = G2_nx544 # !T1_rd_wr_oase & H1_ce_digpot & V1_request_16; --V1_request_8 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_8 --operation mode is normal V1_request_8 = V1_select_rq & (Z2_data_out_8) # !V1_select_rq & Z1_data_out_8; --G3_nx544 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx544 --operation mode is normal G3_nx544_lut_out = G3_nx66 # G3_nx68; G3_nx544 = DFFEAS(G3_nx544_lut_out, S1__clk1, T1_chipRST_n, , G3_nx65, , , , ); --G3_nx337 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx337 --operation mode is normal G3_nx337 = G3_nx544 # !T1_rd_wr_oase & H1_ce_digpot & V1_request_8; --V1_request_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_0 --operation mode is normal V1_request_0 = V1_select_rq & (Z2_data_out_0) # !V1_select_rq & Z1_data_out_0; --G4_nx544 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx544 --operation mode is normal G4_nx544_lut_out = G4_nx66 # G4_nx68; G4_nx544 = DFFEAS(G4_nx544_lut_out, S1__clk1, T1_chipRST_n, , G4_nx65, , , , ); --G4_nx337 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx337 --operation mode is normal G4_nx337 = G4_nx544 # !T1_rd_wr_oase & H1_ce_digpot & V1_request_0; --G1_cnt_6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_6 --operation mode is normal G1_cnt_6_carry_eqn = G1_cnt_nx32; G1_cnt_6_lut_out = G1_cnt_6 $ (!G1_cnt_6_carry_eqn); G1_cnt_6 = DFFEAS(G1_cnt_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_cnt_5 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_5 --operation mode is arithmetic G1_cnt_5_carry_eqn = G1_cnt_nx28; G1_cnt_5_lut_out = G1_cnt_5 $ (G1_cnt_5_carry_eqn); G1_cnt_5 = DFFEAS(G1_cnt_5_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_cnt_nx32 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_nx32 --operation mode is arithmetic G1_cnt_nx32 = CARRY(!G1_cnt_nx28 # !G1_cnt_5); --G1_cnt_0 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_0 --operation mode is arithmetic G1_cnt_0_lut_out = !G1_cnt_0; G1_cnt_0 = DFFEAS(G1_cnt_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_cnt_nx6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_nx6 --operation mode is arithmetic G1_cnt_nx6 = CARRY(G1_cnt_0); --G1_nx572 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx572 --operation mode is normal G1_nx572 = !G1_cnt_4 & !G1_cnt_3 & !G1_cnt_2 & !G1_cnt_1; --G1_NOT_nx149 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|NOT_nx149 --operation mode is normal G1_NOT_nx149 = !G1_nx571 & G1_nx572 & (G1_nx544 # !G1_cnt_6); --G2_cnt_6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_6 --operation mode is normal G2_cnt_6_carry_eqn = G2_cnt_nx32; G2_cnt_6_lut_out = G2_cnt_6 $ (!G2_cnt_6_carry_eqn); G2_cnt_6 = DFFEAS(G2_cnt_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_cnt_5 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_5 --operation mode is arithmetic G2_cnt_5_carry_eqn = G2_cnt_nx28; G2_cnt_5_lut_out = G2_cnt_5 $ (G2_cnt_5_carry_eqn); G2_cnt_5 = DFFEAS(G2_cnt_5_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_cnt_nx32 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_nx32 --operation mode is arithmetic G2_cnt_nx32 = CARRY(!G2_cnt_nx28 # !G2_cnt_5); --G2_cnt_0 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_0 --operation mode is arithmetic G2_cnt_0_lut_out = !G2_cnt_0; G2_cnt_0 = DFFEAS(G2_cnt_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_cnt_nx6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_nx6 --operation mode is arithmetic G2_cnt_nx6 = CARRY(G2_cnt_0); --G2_nx572 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx572 --operation mode is normal G2_nx572 = !G2_cnt_4 & !G2_cnt_3 & !G2_cnt_2 & !G2_cnt_1; --G2_NOT_nx149 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|NOT_nx149 --operation mode is normal G2_NOT_nx149 = !G2_nx571 & G2_nx572 & (G2_nx544 # !G2_cnt_6); --G3_cnt_6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_6 --operation mode is normal G3_cnt_6_carry_eqn = G3_cnt_nx32; G3_cnt_6_lut_out = G3_cnt_6 $ (!G3_cnt_6_carry_eqn); G3_cnt_6 = DFFEAS(G3_cnt_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_cnt_5 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_5 --operation mode is arithmetic G3_cnt_5_carry_eqn = G3_cnt_nx28; G3_cnt_5_lut_out = G3_cnt_5 $ (G3_cnt_5_carry_eqn); G3_cnt_5 = DFFEAS(G3_cnt_5_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_cnt_nx32 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_nx32 --operation mode is arithmetic G3_cnt_nx32 = CARRY(!G3_cnt_nx28 # !G3_cnt_5); --G3_cnt_0 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_0 --operation mode is arithmetic G3_cnt_0_lut_out = !G3_cnt_0; G3_cnt_0 = DFFEAS(G3_cnt_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_cnt_nx6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_nx6 --operation mode is arithmetic G3_cnt_nx6 = CARRY(G3_cnt_0); --G3_nx572 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx572 --operation mode is normal G3_nx572 = !G3_cnt_4 & !G3_cnt_3 & !G3_cnt_2 & !G3_cnt_1; --G3_NOT_nx149 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|NOT_nx149 --operation mode is normal G3_NOT_nx149 = !G3_nx571 & G3_nx572 & (G3_nx544 # !G3_cnt_6); --G4_cnt_6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_6 --operation mode is normal G4_cnt_6_carry_eqn = G4_cnt_nx32; G4_cnt_6_lut_out = G4_cnt_6 $ (!G4_cnt_6_carry_eqn); G4_cnt_6 = DFFEAS(G4_cnt_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_cnt_5 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_5 --operation mode is arithmetic G4_cnt_5_carry_eqn = G4_cnt_nx28; G4_cnt_5_lut_out = G4_cnt_5 $ (G4_cnt_5_carry_eqn); G4_cnt_5 = DFFEAS(G4_cnt_5_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_cnt_nx32 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_nx32 --operation mode is arithmetic G4_cnt_nx32 = CARRY(!G4_cnt_nx28 # !G4_cnt_5); --G4_cnt_0 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_0 --operation mode is arithmetic G4_cnt_0_lut_out = !G4_cnt_0; G4_cnt_0 = DFFEAS(G4_cnt_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_cnt_nx6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_nx6 --operation mode is arithmetic G4_cnt_nx6 = CARRY(G4_cnt_0); --G4_nx572 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx572 --operation mode is normal G4_nx572 = !G4_cnt_4 & !G4_cnt_3 & !G4_cnt_2 & !G4_cnt_1; --G4_NOT_nx149 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|NOT_nx149 --operation mode is normal G4_NOT_nx149 = !G4_nx571 & G4_nx572 & (G4_nx544 # !G4_cnt_6); --G1_nx66 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx66 --operation mode is normal G1_nx66_carry_eqn = G1_modgen_gt_453_nx30; G1_nx66 = G1_B_6 & !G1_nx574 & !G1_nx66_carry_eqn # !G1_B_6 & (!G1_nx66_carry_eqn # !G1_nx574); --G1_NOT_nx79 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|NOT_nx79 --operation mode is normal G1_NOT_nx79 = G1_nx65 & (G1_nx66 # G1_nx68); --G2_nx66 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx66 --operation mode is normal G2_nx66_carry_eqn = G2_modgen_gt_453_nx30; G2_nx66 = G2_B_6 & !G2_nx574 & !G2_nx66_carry_eqn # !G2_B_6 & (!G2_nx66_carry_eqn # !G2_nx574); --G2_NOT_nx79 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|NOT_nx79 --operation mode is normal G2_NOT_nx79 = G2_nx65 & (G2_nx66 # G2_nx68); --G3_nx66 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx66 --operation mode is normal G3_nx66_carry_eqn = G3_modgen_gt_453_nx30; G3_nx66 = G3_B_6 & !G3_nx574 & !G3_nx66_carry_eqn # !G3_B_6 & (!G3_nx66_carry_eqn # !G3_nx574); --G3_NOT_nx79 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|NOT_nx79 --operation mode is normal G3_NOT_nx79 = G3_nx65 & (G3_nx66 # G3_nx68); --G4_nx66 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx66 --operation mode is normal G4_nx66_carry_eqn = G4_modgen_gt_453_nx30; G4_nx66 = G4_B_6 & !G4_nx574 & !G4_nx66_carry_eqn # !G4_B_6 & (!G4_nx66_carry_eqn # !G4_nx574); --G4_NOT_nx79 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|NOT_nx79 --operation mode is normal G4_NOT_nx79 = G4_nx65 & (G4_nx66 # G4_nx68); --L1_ce_adc is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|ce_adc --operation mode is normal L1_ce_adc_lut_out = L1_sm_6 # L1_modgen_select_223_nx2 # L1_send_cfr & !L1_nx637; L1_ce_adc = DFFEAS(L1_ce_adc_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R2_nx60 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|nx60 --operation mode is normal R2_nx60_lut_out = !R2_sm_4 & (L1_ce_adc # R2_nx60); R2_nx60 = DFFEAS(R2_nx60_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_sm_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|sm_2 --operation mode is normal L1_sm_2_lut_out = L1_nx905 # !L1_send_cfr & L1_start_cyc & !L1_nx637; L1_sm_2 = DFFEAS(L1_sm_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R2_sm_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|sm_2 --operation mode is normal R2_sm_2_lut_out = R2_sm_1 # R2_ADC_SCLK & (R2_nx95 # R2_nx96); R2_sm_2 = DFFEAS(R2_sm_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_cmd_adc_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cmd_adc_1 --operation mode is normal L1_cmd_adc_1_lut_out = VCC; L1_cmd_adc_1 = DFFEAS(L1_cmd_adc_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R2_datasr_14 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_14 --operation mode is normal R2_datasr_14_lut_out = L1_cmd_adc_2 & (R2_datasr_13 & R2_ADC_SCLK # !R2_nx60) # !L1_cmd_adc_2 & R2_datasr_13 & (R2_ADC_SCLK); R2_datasr_14 = DFFEAS(R2_datasr_14_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --R2_NOT_nx214 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|NOT_nx214 --operation mode is normal R2_NOT_nx214 = R2_nx60 & (R2_ADC_SCLK) # !R2_nx60 & L1_ce_adc; --V1_bridge is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|bridge --operation mode is normal V1_bridge_lut_out = V1_bridge_buffered; V1_bridge = DFFEAS(V1_bridge_lut_out, S1__clk0, VCC, , V1_nx777, , , , ); --BB1_data_out_to_pl is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|data_out_to_pl --operation mode is normal BB1_data_out_to_pl_lut_out = HB1_stuffed_data_out & (FB1_data_out_1 # !FB1_data_out_2 & FB1_data_out_0); BB1_data_out_to_pl = DFFEAS(BB1_data_out_to_pl_lut_out, S1__clk0, VCC, , , , , , ); --BB2_data_out_to_pl is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|data_out_to_pl --operation mode is normal BB2_data_out_to_pl_lut_out = HB2_stuffed_data_out & (FB2_data_out_1 # !FB2_data_out_2 & FB2_data_out_0); BB2_data_out_to_pl = DFFEAS(BB2_data_out_to_pl_lut_out, S1__clk0, VCC, , , , , , ); --M1_SERREG_3 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|SERREG_3 --operation mode is normal M1_SERREG_3_lut_out = M1_SERREG_1 & M1_NOT_CNT_FF_4 & M1_nx142; M1_SERREG_3 = DFFEAS(M1_SERREG_3_lut_out, S1__clk1, T1_chipRST_n, , M1_cnt_div, , , , ); --M1_SERREG_1 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|SERREG_1 --operation mode is normal M1_SERREG_1_lut_out = M1_SERREG_2; M1_SERREG_1 = DFFEAS(M1_SERREG_1_lut_out, S1__clk1, T1_chipRST_n, , M1_cnt_div, , , , ); --M1_NOT_CNT_FF_4 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|NOT_CNT_FF_4 --operation mode is normal M1_NOT_CNT_FF_4_lut_out = M1_nx116; M1_NOT_CNT_FF_4 = DFFEAS(M1_NOT_CNT_FF_4_lut_out, S1__clk1, T1_chipRST_n, , M1_NOT_nx413, , , , ); --M1_nx142 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|nx142 --operation mode is normal M1_nx142 = !M1_CNT_FF_3 & !M1_CNT_FF_2 & !M1_CNT_FF_1 & !M1_CNT_FF_0; --M1_cnt_div is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|cnt_div --operation mode is normal M1_cnt_div_lut_out = M1_dcounter_nx23 & M1_dcounter_nx30 & M1_dcounter_nx38 & M1_dcounter_nx45; M1_cnt_div = DFFEAS(M1_cnt_div_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --M1_PQ_16 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_16 --operation mode is normal M1_PQ_16_lut_out = V1_request_15; M1_PQ_16 = DFFEAS(M1_PQ_16_lut_out, S1__clk1, VCC, , M1_NOT_nx154, , , , ); --M1_nx52 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|nx52 --operation mode is normal M1_nx52 = H1_ce_2sdac & !T1_rd_wr_oase; --M1_SL is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|SL --operation mode is normal M1_SL = DFFEAS(M1_nx52, S1__clk1, VCC, , M1_nx521, , , , ); --M1_SERREG_5 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|SERREG_5 --operation mode is normal M1_SERREG_5_lut_out = M1_SERREG_4 # M1_SL & M1_SERREG_5; M1_SERREG_5 = DFFEAS(M1_SERREG_5_lut_out, S1__clk1, T1_chipRST_n, , M1_cnt_div, , , , ); --M1_SERREG_4 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|SERREG_4 --operation mode is normal M1_SERREG_4_lut_out = M1_SERREG_3; M1_SERREG_4 = DFFEAS(M1_SERREG_4_lut_out, S1__clk1, T1_chipRST_n, , M1_cnt_div, , , , ); --M1_SERREG_2 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|SERREG_2 --operation mode is normal M1_SERREG_2_lut_out = M1_nx143 # M1_nx144 # M1_CNT_FF_3 & M1_SERREG_1; M1_SERREG_2 = DFFEAS(M1_SERREG_2_lut_out, S1__clk1, T1_chipRST_n, , M1_cnt_div, , , , ); --M1_PQ_15 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_15 --operation mode is normal M1_PQ_15_lut_out = V1_request_16; M1_PQ_15 = DFFEAS(M1_PQ_15_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_14, , , M1_SERREG_1); --M1_nx116 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|nx116 --operation mode is normal M1_nx116_lut_out = M1_SL # !M1_SERREG_5 & M1_nx116; M1_nx116 = DFFEAS(M1_nx116_lut_out, S1__clk1, T1_chipRST_n, , M1_cnt_div, , , , ); --B1_VMCM_Shdwn_a is ADC_DAC_1_notri:adcdac_notri|VMCM_Shdwn_a --operation mode is normal B1_VMCM_Shdwn_a_lut_out = !K1_cl_0 & !K1_cl_1 & V1_request_31; B1_VMCM_Shdwn_a = DFFEAS(B1_VMCM_Shdwn_a_lut_out, S1__clk1, T1_chipRST_n, , B1_nx682, , , , ); --B1_VMCM_Shdwn_d is ADC_DAC_1_notri:adcdac_notri|VMCM_Shdwn_d --operation mode is normal B1_VMCM_Shdwn_d_lut_out = !K1_cl_1 & V1_request_30; B1_VMCM_Shdwn_d = DFFEAS(B1_VMCM_Shdwn_d_lut_out, S1__clk1, T1_chipRST_n, , B1_nx684, , , , ); --H1_ce_dds is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ce_dds --operation mode is normal H1_ce_dds_lut_out = V1_request_39 & !V1_request_40 & H1_nx155; H1_ce_dds = DFFEAS(H1_ce_dds_lut_out, S1__clk1, VCC, , , , , !T1_bus_req, ); --V1_request_48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_48 --operation mode is normal V1_request_48 = V1_select_rq & (Z2_data_out_48) # !V1_select_rq & Z1_data_out_48; --F1_nx859 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx859 --operation mode is normal F1_nx859 = !V1_request_46 & !V1_request_47; --F1_nx839 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx839 --operation mode is normal F1_nx839 = F1_byte_counter_2 # F1_byte_counter_1 # F1_byte_counter_0 # !F1_sm_top_6; --X1_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1|data_out_3 --operation mode is normal X1_data_out_3_lut_out = T1_next_state_3; X1_data_out_3 = DFFEAS(X1_data_out_3_lut_out, S1__clk0, VCC, , , , , , ); --X1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1|data_out_2 --operation mode is normal X1_data_out_2_lut_out = T1_next_state_2; X1_data_out_2 = DFFEAS(X1_data_out_2_lut_out, S1__clk0, VCC, , , , , , ); --X1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1|data_out_1 --operation mode is normal X1_data_out_1_lut_out = T1_next_state_1; X1_data_out_1 = DFFEAS(X1_data_out_1_lut_out, S1__clk0, VCC, , , , , , ); --X1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1|data_out_0 --operation mode is normal X1_data_out_0_lut_out = T1_next_state_0; X1_data_out_0 = DFFEAS(X1_data_out_0_lut_out, S1__clk0, VCC, , , , , , ); --Z1_data_out_26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_26 --operation mode is normal Z1_data_out_26_lut_out = Z1_data_out_25; Z1_data_out_26 = DFFEAS(Z1_data_out_26_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_26 --operation mode is normal Z2_data_out_26_lut_out = Z2_data_out_25; Z2_data_out_26 = DFFEAS(Z2_data_out_26_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_select_rq is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|select_rq --operation mode is normal V1_select_rq_lut_out = V1_nx229 # !KB1_data_out_0 & LB2_request_valid & !V1_nx233; V1_select_rq = DFFEAS(V1_select_rq_lut_out, S1__clk0, VCC, , , , , , ); --V1_request_46 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_46 --operation mode is normal V1_request_46 = V1_select_rq & (Z2_data_out_46) # !V1_select_rq & Z1_data_out_46; --V1_request_47 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_47 --operation mode is normal V1_request_47 = V1_select_rq & (Z2_data_out_47) # !V1_select_rq & Z1_data_out_47; --F1_nx8 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx8 --operation mode is normal F1_nx8 = H1_ce_dds & !T1_rd_wr_oase; --F1_start_sm is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|start_sm --operation mode is normal F1_start_sm_lut_out = F1_sm_top_4 # F1_sm_top_2 # F1_flag2send & !F1_NOT_sm_top_0; F1_start_sm = DFFEAS(F1_start_sm_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx1511, , , , ); --F1_read_flag is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|read_flag --operation mode is normal F1_read_flag_lut_out = F1_sm_top_4; F1_read_flag = DFFEAS(F1_read_flag_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx1526, , , , ); --F1_nx538 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx538 --operation mode is normal F1_nx538_lut_out = !F1_sm_sr_5 & (F1_start_sm # F1_nx538); F1_nx538 = DFFEAS(F1_nx538_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, , , , ); --F1_nx842 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx842 --operation mode is normal F1_nx842 = F1_sm_sr_2 & (!F1_bit_counter_0 # !F1_bit_counter_1 # !F1_bit_counter_2); --F1_nx843 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx843 --operation mode is normal F1_nx843 = F1_bit_counter_2 & F1_bit_counter_1 & F1_bit_counter_0; --F1_nx845 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx845 --operation mode is normal F1_nx845 = F1_start_sm & !F1_read_flag; --F1_nx753 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx753 --operation mode is normal F1_nx753 = F1_sm_sr_4 & (F1_byte_send_6 # F1_bytes2send_31 & F1_nx798) # !F1_sm_sr_4 & F1_bytes2send_31 & (F1_nx798); --F1_nx754 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx754 --operation mode is normal F1_nx754 = F1_bytes2send_47 & (F1_nx794 # F1_bytes2send_23 & F1_nx799) # !F1_bytes2send_47 & F1_bytes2send_23 & (F1_nx799); --F1_nx755 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx755 --operation mode is normal F1_nx755 = F1_bytes2send_39 & (F1_nx796 # F1_iword2send_7 & F1_nx793) # !F1_bytes2send_39 & F1_iword2send_7 & F1_nx793; --F1_nx756 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx756 --operation mode is normal F1_nx756 = F1_bytes2send_15 & (F1_nx795 # F1_bytes2send_7 & F1_nx797) # !F1_bytes2send_15 & F1_bytes2send_7 & (F1_nx797); --F1_NOT_nx2817 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx2817 --operation mode is normal F1_NOT_nx2817 = F1_clkdivs & (F1_nx538 & F1_sm_sr_4 # !F1_nx538 & (F1_nx845)); --Z1_data_out_27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_27 --operation mode is normal Z1_data_out_27_lut_out = Z1_data_out_26; Z1_data_out_27 = DFFEAS(Z1_data_out_27_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_27 --operation mode is normal Z2_data_out_27_lut_out = Z2_data_out_26; Z2_data_out_27 = DFFEAS(Z2_data_out_27_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_request_28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_28 --operation mode is normal V1_request_28 = V1_select_rq & (Z2_data_out_28) # !V1_select_rq & Z1_data_out_28; --F1_sm_top_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_top_1 --operation mode is normal F1_sm_top_1_lut_out = F1_sm_top_1 & (F1_flag2send & !F1_NOT_sm_top_0 # !F1_sm_sr_5) # !F1_sm_top_1 & (F1_flag2send & !F1_NOT_sm_top_0); F1_sm_top_1 = DFFEAS(F1_sm_top_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --F1_NOT_nx1490 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx1490 --operation mode is normal F1_NOT_nx1490 = F1_NOT_sm_top_0 & (F1_sm_top_6 # F1_sm_top_1) # !F1_NOT_sm_top_0 & (!F1_flag2send); --K1_sm_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|sm_6 --operation mode is normal K1_sm_6_lut_out = K1_sm_5 & K1_b_3 & !K1_ix38_ix21_nx8; K1_sm_6 = DFFEAS(K1_sm_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_nx538 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx538 --operation mode is normal K1_nx538 = H1_ce_psply_adc & !T1_rd_wr_oase & V1_request_46 & !V1_request_47; --K1_send_cfr is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|send_cfr --operation mode is normal K1_send_cfr = DFFEAS(K1_nx538, S1__clk1, T1_chipRST_n, , , , , , ); --K1_modgen_select_223_nx2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_select_223_nx2 --operation mode is normal K1_modgen_select_223_nx2 = K1_sm_4 & (!K1_counter_0 # !K1_counter_1 # !K1_counter_2); --K1_nx692 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx692 --operation mode is normal K1_nx692_lut_out = K1_sm_7 & !R1_RDY & (K1_start_cyc # K1_nx899) # !K1_sm_7 & (K1_start_cyc # K1_nx899); K1_nx692 = DFFEAS(K1_nx692_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R1_sm_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|sm_4 --operation mode is normal R1_sm_4_lut_out = !R1_counter_1 & !R1_counter_0 & R1_ADC_SCLK & !R1_nx95; R1_sm_4 = DFFEAS(R1_sm_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_start_cyc is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|start_cyc --operation mode is normal K1_start_cyc_lut_out = K1_cfr_12 # H1_ce_psply_adc & !T1_rd_wr_oase & !V1_request_46; K1_start_cyc = DFFEAS(K1_start_cyc_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_nx988 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx988 --operation mode is normal K1_nx988 = K1_b_3 & K1_sm_5 & (K1_ix38_ix21_nx8) # !K1_b_3 & (K1_sm_2); --R1_modgen_select_195_nx4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|modgen_select_195_nx4 --operation mode is normal R1_modgen_select_195_nx4 = K1_ce_adc & !R1_nx60; --R1_sm_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|sm_1 --operation mode is normal R1_sm_1 = DFFEAS(R1_modgen_select_195_nx4, S1__clk1, T1_chipRST_n, , , , , , ); --R1_nx95 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|nx95 --operation mode is normal R1_nx95 = R1_counter_3 # R1_counter_2; --R1_nx96 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|nx96 --operation mode is normal R1_nx96 = R1_counter_1 # R1_counter_0; --K1_cmd_adc_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cmd_adc_2 --operation mode is normal K1_cmd_adc_2_lut_out = K1_nx692; K1_cmd_adc_2 = DFFEAS(K1_cmd_adc_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R1_datasr_13 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_13 --operation mode is normal R1_datasr_13_lut_out = K1_cmd_adc_1 & (R1_datasr_12 & R1_ADC_SCLK # !R1_nx60) # !K1_cmd_adc_1 & R1_datasr_12 & (R1_ADC_SCLK); R1_datasr_13 = DFFEAS(R1_datasr_13_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --Z1_data_out_29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_29 --operation mode is normal Z1_data_out_29_lut_out = Z1_data_out_28; Z1_data_out_29 = DFFEAS(Z1_data_out_29_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_29 --operation mode is normal Z2_data_out_29_lut_out = Z2_data_out_28; Z2_data_out_29 = DFFEAS(Z2_data_out_29_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --H1_ce_pasa_adc is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ce_pasa_adc --operation mode is normal H1_ce_pasa_adc_lut_out = !V1_request_33 & V1_request_34 & V1_request_37 & !H1_nx156; H1_ce_pasa_adc = DFFEAS(H1_ce_pasa_adc_lut_out, S1__clk1, VCC, , , , , !T1_bus_req, ); --V1_request_38 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_38 --operation mode is normal V1_request_38 = V1_select_rq & (Z2_data_out_38) # !V1_select_rq & Z1_data_out_38; --Z1_data_out_31 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_31 --operation mode is normal Z1_data_out_31_lut_out = Z1_data_out_30; Z1_data_out_31 = DFFEAS(Z1_data_out_31_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_31 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_31 --operation mode is normal Z2_data_out_31_lut_out = Z2_data_out_30; Z2_data_out_31 = DFFEAS(Z2_data_out_31_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_nx771 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx771 --operation mode is normal V1_nx771 = T1_bridge_alter & (KB1_data_out_1 $ !KB1_data_out_0 # !KB1_data_out_2); --Z1_data_out_30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_30 --operation mode is normal Z1_data_out_30_lut_out = Z1_data_out_29; Z1_data_out_30 = DFFEAS(Z1_data_out_30_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_30 --operation mode is normal Z2_data_out_30_lut_out = Z2_data_out_29; Z2_data_out_30 = DFFEAS(Z2_data_out_30_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --J1_start_s is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|start_s --operation mode is normal J1_start_s_lut_out = J1_io_start # AD_SYNC_IN[1] & !J1_NOT_cfr_6; J1_start_s = DFFEAS(J1_start_s_lut_out, S1__clk1, VCC, , , , , , ); --J1_nx78 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|nx78 --operation mode is normal J1_nx78 = J1_nx79 # J1_nx80 # !J1_samples_0 # !J1_samples_1; --V1_request_52 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_52 --operation mode is normal V1_request_52 = V1_select_rq & (Z2_data_out_52) # !V1_select_rq & Z1_data_out_52; --V1_request_51 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_51 --operation mode is normal V1_request_51 = V1_select_rq & (Z2_data_out_51) # !V1_select_rq & Z1_data_out_51; --V1_request_50 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_50 --operation mode is normal V1_request_50 = V1_select_rq & (Z2_data_out_50) # !V1_select_rq & Z1_data_out_50; --V1_request_49 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_49 --operation mode is normal V1_request_49 = V1_select_rq & (Z2_data_out_49) # !V1_select_rq & Z1_data_out_49; --V1_request_41 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_41 --operation mode is normal V1_request_41 = V1_select_rq & (Z2_data_out_41) # !V1_select_rq & Z1_data_out_41; --V1_request_42 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_42 --operation mode is normal V1_request_42 = V1_select_rq & (Z2_data_out_42) # !V1_select_rq & Z1_data_out_42; --H1_modgen_eq_90_nx22 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|modgen_eq_90_nx22 --operation mode is normal H1_modgen_eq_90_nx22 = V1_request_39 # V1_request_40; --H1_nx155 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx155 --operation mode is normal H1_nx155 = !V1_request_37 & !V1_request_38 & !H1_modgen_eq_95_nx24 & !H1_nx156; --T1_bus_req is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|bus_req --operation mode is normal T1_bus_req_lut_out = !T1_current_state_dp_2 & T1_current_state_dp_0 & T1_nx426; T1_bus_req = DFFEAS(T1_bus_req_lut_out, S1__clk0, VCC, , T1_nx410, , , , ); --Z1_data_out_24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_24 --operation mode is normal Z1_data_out_24_lut_out = Z1_data_out_23; Z1_data_out_24 = DFFEAS(Z1_data_out_24_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_24 --operation mode is normal Z2_data_out_24_lut_out = Z2_data_out_23; Z2_data_out_24 = DFFEAS(Z2_data_out_24_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G1_nx68 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx68 --operation mode is normal G1_nx68_carry_eqn = G1_modgen_gt_455_nx30; G1_nx68 = G1_nx574 & (G1_B_6 # !G1_nx68_carry_eqn) # !G1_nx574 & G1_B_6 & !G1_nx68_carry_eqn; --G1_nx65 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx65 --operation mode is normal G1_nx65 = G1_cnt_6 & !G1_cnt_5 & !G1_cnt_0 & G1_nx572; --Z1_data_out_16 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_16 --operation mode is normal Z1_data_out_16_lut_out = Z1_data_out_15; Z1_data_out_16 = DFFEAS(Z1_data_out_16_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_16 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_16 --operation mode is normal Z2_data_out_16_lut_out = Z2_data_out_15; Z2_data_out_16 = DFFEAS(Z2_data_out_16_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G2_nx68 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx68 --operation mode is normal G2_nx68_carry_eqn = G2_modgen_gt_455_nx30; G2_nx68 = G2_nx574 & (G2_B_6 # !G2_nx68_carry_eqn) # !G2_nx574 & G2_B_6 & !G2_nx68_carry_eqn; --G2_nx65 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx65 --operation mode is normal G2_nx65 = G2_cnt_6 & !G2_cnt_5 & !G2_cnt_0 & G2_nx572; --Z1_data_out_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_8 --operation mode is normal Z1_data_out_8_lut_out = Z1_data_out_7; Z1_data_out_8 = DFFEAS(Z1_data_out_8_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_8 --operation mode is normal Z2_data_out_8_lut_out = Z2_data_out_7; Z2_data_out_8 = DFFEAS(Z2_data_out_8_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G3_nx68 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx68 --operation mode is normal G3_nx68_carry_eqn = G3_modgen_gt_455_nx30; G3_nx68 = G3_nx574 & (G3_B_6 # !G3_nx68_carry_eqn) # !G3_nx574 & G3_B_6 & !G3_nx68_carry_eqn; --G3_nx65 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx65 --operation mode is normal G3_nx65 = G3_cnt_6 & !G3_cnt_5 & !G3_cnt_0 & G3_nx572; --Z1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_0 --operation mode is normal Z1_data_out_0_lut_out = CB1_data_out; Z1_data_out_0 = DFFEAS(Z1_data_out_0_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_0 --operation mode is normal Z2_data_out_0_lut_out = CB2_data_out; Z2_data_out_0 = DFFEAS(Z2_data_out_0_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G4_nx68 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx68 --operation mode is normal G4_nx68_carry_eqn = G4_modgen_gt_455_nx30; G4_nx68 = G4_nx574 & (G4_B_6 # !G4_nx68_carry_eqn) # !G4_nx574 & G4_B_6 & !G4_nx68_carry_eqn; --G4_nx65 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx65 --operation mode is normal G4_nx65 = G4_cnt_6 & !G4_cnt_5 & !G4_cnt_0 & G4_nx572; --G1_cnt_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_4 --operation mode is arithmetic G1_cnt_4_carry_eqn = G1_cnt_nx24; G1_cnt_4_lut_out = G1_cnt_4 $ (!G1_cnt_4_carry_eqn); G1_cnt_4 = DFFEAS(G1_cnt_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_cnt_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_nx28 --operation mode is arithmetic G1_cnt_nx28 = CARRY(G1_cnt_4 & (!G1_cnt_nx24)); --G1_cnt_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_3 --operation mode is arithmetic G1_cnt_3_carry_eqn = G1_cnt_nx18; G1_cnt_3_lut_out = G1_cnt_3 $ (G1_cnt_3_carry_eqn); G1_cnt_3 = DFFEAS(G1_cnt_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_cnt_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_nx24 --operation mode is arithmetic G1_cnt_nx24 = CARRY(!G1_cnt_nx18 # !G1_cnt_3); --G1_cnt_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_2 --operation mode is arithmetic G1_cnt_2_carry_eqn = G1_cnt_nx12; G1_cnt_2_lut_out = G1_cnt_2 $ (!G1_cnt_2_carry_eqn); G1_cnt_2 = DFFEAS(G1_cnt_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_cnt_nx18 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_nx18 --operation mode is arithmetic G1_cnt_nx18 = CARRY(G1_cnt_2 & (!G1_cnt_nx12)); --G1_cnt_1 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_1 --operation mode is arithmetic G1_cnt_1_carry_eqn = G1_cnt_nx6; G1_cnt_1_lut_out = G1_cnt_1 $ (G1_cnt_1_carry_eqn); G1_cnt_1 = DFFEAS(G1_cnt_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_cnt_nx12 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|cnt_nx12 --operation mode is arithmetic G1_cnt_nx12 = CARRY(!G1_cnt_nx6 # !G1_cnt_1); --G1_nx571 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx571 --operation mode is normal G1_nx571 = G1_cnt_0 # !G1_cnt_5; --G2_cnt_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_4 --operation mode is arithmetic G2_cnt_4_carry_eqn = G2_cnt_nx24; G2_cnt_4_lut_out = G2_cnt_4 $ (!G2_cnt_4_carry_eqn); G2_cnt_4 = DFFEAS(G2_cnt_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_cnt_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_nx28 --operation mode is arithmetic G2_cnt_nx28 = CARRY(G2_cnt_4 & (!G2_cnt_nx24)); --G2_cnt_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_3 --operation mode is arithmetic G2_cnt_3_carry_eqn = G2_cnt_nx18; G2_cnt_3_lut_out = G2_cnt_3 $ (G2_cnt_3_carry_eqn); G2_cnt_3 = DFFEAS(G2_cnt_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_cnt_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_nx24 --operation mode is arithmetic G2_cnt_nx24 = CARRY(!G2_cnt_nx18 # !G2_cnt_3); --G2_cnt_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_2 --operation mode is arithmetic G2_cnt_2_carry_eqn = G2_cnt_nx12; G2_cnt_2_lut_out = G2_cnt_2 $ (!G2_cnt_2_carry_eqn); G2_cnt_2 = DFFEAS(G2_cnt_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_cnt_nx18 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_nx18 --operation mode is arithmetic G2_cnt_nx18 = CARRY(G2_cnt_2 & (!G2_cnt_nx12)); --G2_cnt_1 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_1 --operation mode is arithmetic G2_cnt_1_carry_eqn = G2_cnt_nx6; G2_cnt_1_lut_out = G2_cnt_1 $ (G2_cnt_1_carry_eqn); G2_cnt_1 = DFFEAS(G2_cnt_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_cnt_nx12 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|cnt_nx12 --operation mode is arithmetic G2_cnt_nx12 = CARRY(!G2_cnt_nx6 # !G2_cnt_1); --G2_nx571 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx571 --operation mode is normal G2_nx571 = G2_cnt_0 # !G2_cnt_5; --G3_cnt_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_4 --operation mode is arithmetic G3_cnt_4_carry_eqn = G3_cnt_nx24; G3_cnt_4_lut_out = G3_cnt_4 $ (!G3_cnt_4_carry_eqn); G3_cnt_4 = DFFEAS(G3_cnt_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_cnt_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_nx28 --operation mode is arithmetic G3_cnt_nx28 = CARRY(G3_cnt_4 & (!G3_cnt_nx24)); --G3_cnt_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_3 --operation mode is arithmetic G3_cnt_3_carry_eqn = G3_cnt_nx18; G3_cnt_3_lut_out = G3_cnt_3 $ (G3_cnt_3_carry_eqn); G3_cnt_3 = DFFEAS(G3_cnt_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_cnt_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_nx24 --operation mode is arithmetic G3_cnt_nx24 = CARRY(!G3_cnt_nx18 # !G3_cnt_3); --G3_cnt_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_2 --operation mode is arithmetic G3_cnt_2_carry_eqn = G3_cnt_nx12; G3_cnt_2_lut_out = G3_cnt_2 $ (!G3_cnt_2_carry_eqn); G3_cnt_2 = DFFEAS(G3_cnt_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_cnt_nx18 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_nx18 --operation mode is arithmetic G3_cnt_nx18 = CARRY(G3_cnt_2 & (!G3_cnt_nx12)); --G3_cnt_1 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_1 --operation mode is arithmetic G3_cnt_1_carry_eqn = G3_cnt_nx6; G3_cnt_1_lut_out = G3_cnt_1 $ (G3_cnt_1_carry_eqn); G3_cnt_1 = DFFEAS(G3_cnt_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_cnt_nx12 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|cnt_nx12 --operation mode is arithmetic G3_cnt_nx12 = CARRY(!G3_cnt_nx6 # !G3_cnt_1); --G3_nx571 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx571 --operation mode is normal G3_nx571 = G3_cnt_0 # !G3_cnt_5; --G4_cnt_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_4 --operation mode is arithmetic G4_cnt_4_carry_eqn = G4_cnt_nx24; G4_cnt_4_lut_out = G4_cnt_4 $ (!G4_cnt_4_carry_eqn); G4_cnt_4 = DFFEAS(G4_cnt_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_cnt_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_nx28 --operation mode is arithmetic G4_cnt_nx28 = CARRY(G4_cnt_4 & (!G4_cnt_nx24)); --G4_cnt_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_3 --operation mode is arithmetic G4_cnt_3_carry_eqn = G4_cnt_nx18; G4_cnt_3_lut_out = G4_cnt_3 $ (G4_cnt_3_carry_eqn); G4_cnt_3 = DFFEAS(G4_cnt_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_cnt_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_nx24 --operation mode is arithmetic G4_cnt_nx24 = CARRY(!G4_cnt_nx18 # !G4_cnt_3); --G4_cnt_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_2 --operation mode is arithmetic G4_cnt_2_carry_eqn = G4_cnt_nx12; G4_cnt_2_lut_out = G4_cnt_2 $ (!G4_cnt_2_carry_eqn); G4_cnt_2 = DFFEAS(G4_cnt_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_cnt_nx18 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_nx18 --operation mode is arithmetic G4_cnt_nx18 = CARRY(G4_cnt_2 & (!G4_cnt_nx12)); --G4_cnt_1 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_1 --operation mode is arithmetic G4_cnt_1_carry_eqn = G4_cnt_nx6; G4_cnt_1_lut_out = G4_cnt_1 $ (G4_cnt_1_carry_eqn); G4_cnt_1 = DFFEAS(G4_cnt_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_cnt_nx12 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|cnt_nx12 --operation mode is arithmetic G4_cnt_nx12 = CARRY(!G4_cnt_nx6 # !G4_cnt_1); --G4_nx571 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx571 --operation mode is normal G4_nx571 = G4_cnt_0 # !G4_cnt_5; --G1_B_6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_6 --operation mode is normal G1_B_6_carry_eqn = G1_B_nx45; G1_B_6_lut_out = G1_B_6 $ (!G1_B_6_carry_eqn); G1_B_6 = DFFEAS(G1_B_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_nx574 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx574 --operation mode is normal G1_nx574_lut_out = !V1_request_25; G1_nx574 = DFFEAS(G1_nx574_lut_out, S1__clk1, T1_chipRST_n, , G1_nx12, , , G1_NOT_nx14, ); --G1_modgen_gt_453_nx30 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_453_nx30 --operation mode is arithmetic G1_modgen_gt_453_nx30 = CARRY(G1_B_5 & (G1_nx579 # !G1_modgen_gt_453_nx28) # !G1_B_5 & G1_nx579 & !G1_modgen_gt_453_nx28); --G2_B_6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_6 --operation mode is normal G2_B_6_carry_eqn = G2_B_nx45; G2_B_6_lut_out = G2_B_6 $ (!G2_B_6_carry_eqn); G2_B_6 = DFFEAS(G2_B_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_nx574 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx574 --operation mode is normal G2_nx574_lut_out = !V1_request_17; G2_nx574 = DFFEAS(G2_nx574_lut_out, S1__clk1, T1_chipRST_n, , G2_nx12, , , G2_NOT_nx14, ); --G2_modgen_gt_453_nx30 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_453_nx30 --operation mode is arithmetic G2_modgen_gt_453_nx30 = CARRY(G2_B_5 & (G2_nx579 # !G2_modgen_gt_453_nx28) # !G2_B_5 & G2_nx579 & !G2_modgen_gt_453_nx28); --G3_B_6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_6 --operation mode is normal G3_B_6_carry_eqn = G3_B_nx45; G3_B_6_lut_out = G3_B_6 $ (!G3_B_6_carry_eqn); G3_B_6 = DFFEAS(G3_B_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_nx574 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx574 --operation mode is normal G3_nx574_lut_out = !V1_request_9; G3_nx574 = DFFEAS(G3_nx574_lut_out, S1__clk1, T1_chipRST_n, , G3_nx12, , , G3_NOT_nx14, ); --G3_modgen_gt_453_nx30 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_453_nx30 --operation mode is arithmetic G3_modgen_gt_453_nx30 = CARRY(G3_B_5 & (G3_nx579 # !G3_modgen_gt_453_nx28) # !G3_B_5 & G3_nx579 & !G3_modgen_gt_453_nx28); --G4_B_6 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_6 --operation mode is normal G4_B_6_carry_eqn = G4_B_nx45; G4_B_6_lut_out = G4_B_6 $ (!G4_B_6_carry_eqn); G4_B_6 = DFFEAS(G4_B_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_nx574 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx574 --operation mode is normal G4_nx574_lut_out = !V1_request_1; G4_nx574 = DFFEAS(G4_nx574_lut_out, S1__clk1, T1_chipRST_n, , G4_nx12, , , G4_NOT_nx14, ); --G4_modgen_gt_453_nx30 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_453_nx30 --operation mode is arithmetic G4_modgen_gt_453_nx30 = CARRY(G4_B_5 & (G4_nx579 # !G4_modgen_gt_453_nx28) # !G4_B_5 & G4_nx579 & !G4_modgen_gt_453_nx28); --L1_sm_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|sm_6 --operation mode is normal L1_sm_6_lut_out = L1_sm_5 & L1_b_3 & !L1_ix38_ix21_nx8; L1_sm_6 = DFFEAS(L1_sm_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_nx538 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx538 --operation mode is normal L1_nx538 = H1_ce_sc_adc & !T1_rd_wr_oase & V1_request_46 & !V1_request_47; --L1_send_cfr is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|send_cfr --operation mode is normal L1_send_cfr = DFFEAS(L1_nx538, S1__clk1, T1_chipRST_n, , , , , , ); --L1_modgen_select_223_nx2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|modgen_select_223_nx2 --operation mode is normal L1_modgen_select_223_nx2 = L1_sm_4 & (!L1_counter_0 # !L1_counter_1 # !L1_counter_2); --L1_nx637 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx637 --operation mode is normal L1_nx637_lut_out = L1_sm_7 & !R2_RDY & (L1_start_cyc # L1_nx816) # !L1_sm_7 & (L1_start_cyc # L1_nx816); L1_nx637 = DFFEAS(L1_nx637_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R2_sm_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|sm_4 --operation mode is normal R2_sm_4_lut_out = !R2_counter_1 & !R2_counter_0 & R2_ADC_SCLK & !R2_nx95; R2_sm_4 = DFFEAS(R2_sm_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_start_cyc is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|start_cyc --operation mode is normal L1_start_cyc_lut_out = L1_cfr_12 # H1_ce_sc_adc & !T1_rd_wr_oase & !V1_request_46; L1_start_cyc = DFFEAS(L1_start_cyc_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_nx905 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx905 --operation mode is normal L1_nx905 = L1_b_3 & L1_sm_5 & (L1_ix38_ix21_nx8) # !L1_b_3 & (L1_sm_2); --R2_modgen_select_195_nx4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|modgen_select_195_nx4 --operation mode is normal R2_modgen_select_195_nx4 = L1_ce_adc & !R2_nx60; --R2_sm_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|sm_1 --operation mode is normal R2_sm_1 = DFFEAS(R2_modgen_select_195_nx4, S1__clk1, T1_chipRST_n, , , , , , ); --R2_nx95 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|nx95 --operation mode is normal R2_nx95 = R2_counter_3 # R2_counter_2; --R2_nx96 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|nx96 --operation mode is normal R2_nx96 = R2_counter_1 # R2_counter_0; --L1_cmd_adc_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cmd_adc_2 --operation mode is normal L1_cmd_adc_2_lut_out = L1_nx637; L1_cmd_adc_2 = DFFEAS(L1_cmd_adc_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --R2_datasr_13 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_13 --operation mode is normal R2_datasr_13_lut_out = L1_cmd_adc_1 & (R2_datasr_12 & R2_ADC_SCLK # !R2_nx60) # !L1_cmd_adc_1 & R2_datasr_12 & (R2_ADC_SCLK); R2_datasr_13 = DFFEAS(R2_datasr_13_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --V1_nx777 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx777 --operation mode is normal V1_nx777 = KB1_data_out_2 & (KB1_data_out_1 $ KB1_data_out_0); --FB1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|hamm_reg_3_0_1:h1|data_out_2 --operation mode is normal FB1_data_out_2_lut_out = BB1_next_state_2; FB1_data_out_2 = DFFEAS(FB1_data_out_2_lut_out, S1__clk0, VCC, , , , , , ); --FB1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|hamm_reg_3_0_1:h1|data_out_1 --operation mode is normal FB1_data_out_1_lut_out = BB1_next_state_1; FB1_data_out_1 = DFFEAS(FB1_data_out_1_lut_out, S1__clk0, VCC, , , , , , ); --FB1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|hamm_reg_3_0_1:h1|data_out_0 --operation mode is normal FB1_data_out_0_lut_out = BB1_next_state_0; FB1_data_out_0 = DFFEAS(FB1_data_out_0_lut_out, S1__clk0, VCC, , , , , , ); --HB1_stuffed_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|stuffed_data_out --operation mode is normal HB1_stuffed_data_out_lut_out = BB1_stuffing_strobe_in & (HB1_NOT_nx118 & (!HB1_data) # !HB1_NOT_nx118 & BB1_stuffing_data_in); HB1_stuffed_data_out = DFFEAS(HB1_stuffed_data_out_lut_out, S1__clk0, VCC, , HB1_nx120, , , , ); --FB2_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|hamm_reg_3_0_1:h1|data_out_2 --operation mode is normal FB2_data_out_2_lut_out = BB2_next_state_2; FB2_data_out_2 = DFFEAS(FB2_data_out_2_lut_out, S1__clk0, VCC, , , , , , ); --FB2_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|hamm_reg_3_0_1:h1|data_out_1 --operation mode is normal FB2_data_out_1_lut_out = BB2_next_state_1; FB2_data_out_1 = DFFEAS(FB2_data_out_1_lut_out, S1__clk0, VCC, , , , , , ); --FB2_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|hamm_reg_3_0_1:h1|data_out_0 --operation mode is normal FB2_data_out_0_lut_out = BB2_next_state_0; FB2_data_out_0 = DFFEAS(FB2_data_out_0_lut_out, S1__clk0, VCC, , , , , , ); --HB2_stuffed_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|stuffed_data_out --operation mode is normal HB2_stuffed_data_out_lut_out = BB2_stuffing_strobe_in & (HB2_NOT_nx118 & (!HB2_data) # !HB2_NOT_nx118 & BB2_stuffing_data_in); HB2_stuffed_data_out = DFFEAS(HB2_stuffed_data_out_lut_out, S1__clk0, VCC, , HB2_nx120, , , , ); --M1_NOT_nx413 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|NOT_nx413 --operation mode is normal M1_NOT_nx413 = M1_cnt_div & (M1_SERREG_2 # !M1_nx116); --M1_CNT_FF_3 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|CNT_FF_3 --operation mode is normal M1_CNT_FF_3_carry_eqn = M1_CNT_FF_nx21; M1_CNT_FF_3_lut_out = M1_CNT_FF_3 $ (!M1_CNT_FF_3_carry_eqn); M1_CNT_FF_3 = DFFEAS(M1_CNT_FF_3_lut_out, S1__clk1, T1_chipRST_n, , M1_NOT_nx413, , , !M1_SERREG_2, ); --M1_CNT_FF_2 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|CNT_FF_2 --operation mode is arithmetic M1_CNT_FF_2_carry_eqn = M1_CNT_FF_nx16; M1_CNT_FF_2_lut_out = M1_CNT_FF_2 $ (M1_CNT_FF_2_carry_eqn); M1_CNT_FF_2 = DFFEAS(M1_CNT_FF_2_lut_out, S1__clk1, T1_chipRST_n, , M1_NOT_nx413, , , !M1_SERREG_2, ); --M1_CNT_FF_nx21 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|CNT_FF_nx21 --operation mode is arithmetic M1_CNT_FF_nx21 = CARRY(M1_CNT_FF_2 # !M1_CNT_FF_nx16); --M1_CNT_FF_1 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|CNT_FF_1 --operation mode is arithmetic M1_CNT_FF_1_carry_eqn = M1_CNT_FF_nx10; M1_CNT_FF_1_lut_out = M1_CNT_FF_1 $ (!M1_CNT_FF_1_carry_eqn); M1_CNT_FF_1 = DFFEAS(M1_CNT_FF_1_lut_out, S1__clk1, T1_chipRST_n, , M1_NOT_nx413, , , !M1_SERREG_2, ); --M1_CNT_FF_nx16 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|CNT_FF_nx16 --operation mode is arithmetic M1_CNT_FF_nx16 = CARRY(!M1_CNT_FF_1 & (!M1_CNT_FF_nx10)); --M1_CNT_FF_0 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|CNT_FF_0 --operation mode is arithmetic M1_CNT_FF_0_lut_out = !M1_CNT_FF_0; M1_CNT_FF_0 = DFFEAS(M1_CNT_FF_0_lut_out, S1__clk1, T1_chipRST_n, , M1_NOT_nx413, , , !M1_SERREG_2, ); --M1_CNT_FF_nx10 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|CNT_FF_nx10 --operation mode is arithmetic M1_CNT_FF_nx10 = CARRY(M1_CNT_FF_0); --M1_dcounter_nx23 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|dcounter_nx23 --operation mode is normal M1_dcounter_nx23_carry_eqn = M1_dcounter_nx20; M1_dcounter_nx23_lut_out = M1_dcounter_nx23 $ (!M1_dcounter_nx23_carry_eqn); M1_dcounter_nx23 = DFFEAS(M1_dcounter_nx23_lut_out, S1__clk1, T1_chipRST_n, , , ~GND, , , M1_LOAD); --M1_dcounter_nx30 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|dcounter_nx30 --operation mode is arithmetic M1_dcounter_nx30_carry_eqn = M1_dcounter_nx15; M1_dcounter_nx30_lut_out = M1_dcounter_nx30 $ (M1_dcounter_nx30_carry_eqn); M1_dcounter_nx30 = DFFEAS(M1_dcounter_nx30_lut_out, S1__clk1, T1_chipRST_n, , , ~GND, , , M1_LOAD); --M1_dcounter_nx20 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|dcounter_nx20 --operation mode is arithmetic M1_dcounter_nx20 = CARRY(!M1_dcounter_nx15 # !M1_dcounter_nx30); --M1_dcounter_nx38 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|dcounter_nx38 --operation mode is arithmetic M1_dcounter_nx38_carry_eqn = M1_dcounter_nx9; M1_dcounter_nx38_lut_out = M1_dcounter_nx38 $ (!M1_dcounter_nx38_carry_eqn); M1_dcounter_nx38 = DFFEAS(M1_dcounter_nx38_lut_out, S1__clk1, T1_chipRST_n, , , ~GND, , , M1_LOAD); --M1_dcounter_nx15 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|dcounter_nx15 --operation mode is arithmetic M1_dcounter_nx15 = CARRY(M1_dcounter_nx38 & (!M1_dcounter_nx9)); --M1_dcounter_nx45 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|dcounter_nx45 --operation mode is arithmetic M1_dcounter_nx45_lut_out = !M1_dcounter_nx45; M1_dcounter_nx45 = DFFEAS(M1_dcounter_nx45_lut_out, S1__clk1, T1_chipRST_n, , , ~GND, , , M1_LOAD); --M1_dcounter_nx9 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|dcounter_nx9 --operation mode is arithmetic M1_dcounter_nx9 = CARRY(!M1_dcounter_nx45); --V1_request_15 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_15 --operation mode is normal V1_request_15 = V1_select_rq & (Z2_data_out_15) # !V1_select_rq & Z1_data_out_15; --M1_NOT_nx154 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|NOT_nx154 --operation mode is normal M1_NOT_nx154 = H1_ce_2sdac & !T1_rd_wr_oase & !M1_SERREG_1 & !M1_nx116; --H1_ce_2sdac is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ce_2sdac --operation mode is normal H1_ce_2sdac_lut_out = !V1_request_39 & V1_request_40 & H1_nx155; H1_ce_2sdac = DFFEAS(H1_ce_2sdac_lut_out, S1__clk1, VCC, , , , , !T1_bus_req, ); --M1_nx521 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|nx521 --operation mode is normal M1_nx521 = M1_nx116 # H1_ce_2sdac & !T1_rd_wr_oase; --M1_nx143 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|nx143 --operation mode is normal M1_nx143 = M1_SERREG_1 & (M1_CNT_FF_2 # M1_CNT_FF_1 # M1_CNT_FF_0); --M1_nx144 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|nx144 --operation mode is normal M1_nx144 = M1_SL & (M1_SERREG_1 & !M1_NOT_CNT_FF_4 # !M1_nx116) # !M1_SL & M1_SERREG_1 & !M1_NOT_CNT_FF_4; --M1_PQ_14 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_14 --operation mode is normal M1_PQ_14_lut_out = V1_request_17; M1_PQ_14 = DFFEAS(M1_PQ_14_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_13, , , M1_SERREG_1); --M1_NOT_nx150 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|NOT_nx150 --operation mode is normal M1_NOT_nx150 = M1_SERREG_1 & M1_cnt_div # !M1_SERREG_1 & (M1_nx52 & !M1_nx116); --K1_cl_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cl_0 --operation mode is normal K1_cl_0_lut_out = K1_nx2777 # K1_nx2783; K1_cl_0 = DFFEAS(K1_cl_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_cl_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cl_1 --operation mode is normal K1_cl_1_lut_out = K1_nx2780 # K1_nx2786; K1_cl_1 = DFFEAS(K1_cl_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --B1_nx682 is ADC_DAC_1_notri:adcdac_notri|nx682 --operation mode is normal B1_nx682 = K1_cl_0 # K1_cl_1 # !T1_rd_wr_oase & H1_ce_shutdn; --B1_nx684 is ADC_DAC_1_notri:adcdac_notri|nx684 --operation mode is normal B1_nx684 = K1_cl_1 # !T1_rd_wr_oase & H1_ce_shutdn; --E1_wrst_n is ni2io_wt:wt_ni|wrst_n --operation mode is normal E1_wrst_n = E1_cnt_rst_7 $ !E1_NOT_rst_inv; --E1_wrst_n_oe is ni2io_wt:wt_ni|wrst_n_oe --operation mode is normal E1_wrst_n_oe = E1_cnt_rst_7 $ E1_NOT_rst_inv # !E1_rst_opend; --V1_request_39 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_39 --operation mode is normal V1_request_39 = V1_select_rq & (Z2_data_out_39) # !V1_select_rq & Z1_data_out_39; --V1_request_40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_40 --operation mode is normal V1_request_40 = V1_select_rq & (Z2_data_out_40) # !V1_select_rq & Z1_data_out_40; --Z1_data_out_48 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_48 --operation mode is normal Z1_data_out_48_lut_out = Z1_data_out_47; Z1_data_out_48 = DFFEAS(Z1_data_out_48_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_48 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_48 --operation mode is normal Z2_data_out_48_lut_out = Z2_data_out_47; Z2_data_out_48 = DFFEAS(Z2_data_out_48_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --F1_sm_top_6 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_top_6 --operation mode is normal F1_sm_top_6_lut_out = F1_nx847 # F1_sm_top_6 & (F1_byte_counter_0 # F1_nx784); F1_sm_top_6 = DFFEAS(F1_sm_top_6_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --F1_byte_counter_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_counter_2 --operation mode is normal F1_byte_counter_2_lut_out = F1_nx749 # F1_nx837 # F1_b_0 & F1_nx840; F1_byte_counter_2 = DFFEAS(F1_byte_counter_2_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx1467, , , , ); --F1_byte_counter_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_counter_1 --operation mode is normal F1_byte_counter_1_lut_out = F1_nx749 # F1_nx750 # F1_nx838 # F1_nx849; F1_byte_counter_1 = DFFEAS(F1_byte_counter_1_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx1467, , , , ); --F1_byte_counter_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_counter_0 --operation mode is normal F1_byte_counter_0_lut_out = F1_nx749 # F1_nx848 # F1_b_0_dup_240 & F1_nx840; F1_byte_counter_0 = DFFEAS(F1_byte_counter_0_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx1467, , , , ); --T1_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|next_state_3 --operation mode is normal T1_next_state_3 = T1_nx412 # T1_nx437 # T1_nx414 & T1_nx424; --T1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|next_state_2 --operation mode is normal T1_next_state_2 = T1_nx415 # T1_nx417 # T1_nx431 # T1_nx435; --T1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|next_state_1 --operation mode is normal T1_next_state_1 = T1_nx419 # T1_nx420 # T1_nx421 # T1_nx430; --T1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|next_state_0 --operation mode is normal T1_next_state_0 = T1_nx422 # T1_nx427 # T1_nx407 & T1_nx429; --Z1_data_out_25 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_25 --operation mode is normal Z1_data_out_25_lut_out = Z1_data_out_24; Z1_data_out_25 = DFFEAS(Z1_data_out_25_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Y1_buffer_flush_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|buffer_flush_n --operation mode is normal Y1_buffer_flush_n = DB1_data_out_3 # DB1_data_out_2 # DB1_data_out_0; --Z1_NOT_nx676 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|NOT_nx676 --operation mode is normal Z1_NOT_nx676 = Z1_nx285 # Z1_nx277 & !Z1_nx286 # !Y1_buffer_flush_n; --Z2_data_out_25 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_25 --operation mode is normal Z2_data_out_25_lut_out = Z2_data_out_24; Z2_data_out_25 = DFFEAS(Z2_data_out_25_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Y2_buffer_flush_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|buffer_flush_n --operation mode is normal Y2_buffer_flush_n = DB2_data_out_3 # DB2_data_out_2 # DB2_data_out_0; --Z2_NOT_nx676 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|NOT_nx676 --operation mode is normal Z2_NOT_nx676 = Z2_nx285 # Z2_nx277 & !Z2_nx286 # !Y2_buffer_flush_n; --KB1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|hamm_reg_3_0_1_unfolded0:h1|data_out_0 --operation mode is normal KB1_data_out_0_lut_out = V1_next_state_0; KB1_data_out_0 = DFFEAS(KB1_data_out_0_lut_out, S1__clk0, VCC, , , , , , ); --LB2_request_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|request_valid --operation mode is normal LB2_request_valid = !DB4_data_out_3 & !DB4_data_out_2 & DB4_data_out_1 & !DB4_data_out_0; --V1_nx229 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx229 --operation mode is normal V1_nx229 = !KB1_data_out_0 & (KB1_data_out_2 & (!KB1_data_out_1) # !KB1_data_out_2 & T1_bridge_alter & KB1_data_out_1); --V1_nx233 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx233 --operation mode is normal V1_nx233 = !KB1_data_out_1 & LB1_request_valid; --Z1_data_out_46 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_46 --operation mode is normal Z1_data_out_46_lut_out = Z1_data_out_45; Z1_data_out_46 = DFFEAS(Z1_data_out_46_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_46 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_46 --operation mode is normal Z2_data_out_46_lut_out = Z2_data_out_45; Z2_data_out_46 = DFFEAS(Z2_data_out_46_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_47 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_47 --operation mode is normal Z1_data_out_47_lut_out = Z1_data_out_46; Z1_data_out_47 = DFFEAS(Z1_data_out_47_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_47 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_47 --operation mode is normal Z2_data_out_47_lut_out = Z2_data_out_46; Z2_data_out_47 = DFFEAS(Z2_data_out_47_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --F1_sm_top_4 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_top_4 --operation mode is normal F1_sm_top_4_lut_out = F1_nx751 # F1_clkdivs & F1_nx841; F1_sm_top_4 = DFFEAS(F1_sm_top_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --F1_sm_top_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_top_2 --operation mode is normal F1_sm_top_2_lut_out = F1_nx752 # F1_nx846 # F1_sm_top_2 & F1_nx800; F1_sm_top_2 = DFFEAS(F1_sm_top_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --F1_NOT_nx1511 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx1511 --operation mode is normal F1_NOT_nx1511 = F1_nx792 # F1_NOT_sm_top_0 & (F1_nx791) # !F1_NOT_sm_top_0 & F1_flag2send; --F1_NOT_nx1526 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx1526 --operation mode is normal F1_NOT_nx1526 = F1_NOT_sm_top_0 & (F1_sm_top_4 # F1_sm_top_2) # !F1_NOT_sm_top_0 & (F1_flag2send); --F1_sm_sr_5 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_sr_5 --operation mode is normal F1_sm_sr_5_lut_out = F1_nx843 & (F1_sm_sr_4 # F1_sm_sr_2); F1_sm_sr_5 = DFFEAS(F1_sm_sr_5_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, , , , ); --F1_sm_sr_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_sr_2 --operation mode is normal F1_sm_sr_2_lut_out = F1_sm_sr_1; F1_sm_sr_2 = DFFEAS(F1_sm_sr_2_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, , , , ); --F1_bit_counter_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bit_counter_2 --operation mode is normal F1_bit_counter_2_lut_out = F1_bit_counter_2; F1_bit_counter_2 = DFFEAS(F1_bit_counter_2_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, F1_nx2672, , , F1_nx2701); --F1_bit_counter_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bit_counter_1 --operation mode is normal F1_bit_counter_1_lut_out = F1_bit_counter_1; F1_bit_counter_1 = DFFEAS(F1_bit_counter_1_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, F1_nx2685, , , F1_nx2701); --F1_bit_counter_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bit_counter_0 --operation mode is normal F1_bit_counter_0_lut_out = F1_bit_counter_0; F1_bit_counter_0 = DFFEAS(F1_bit_counter_0_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, F1_nx2698, , , F1_nx2701); --F1_bytes2send_31 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_31 --operation mode is normal F1_bytes2send_31_lut_out = F1_bytes2send_31; F1_bytes2send_31 = DFFEAS(F1_bytes2send_31_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_0, , , F1_a_1); --F1_byte_send_6 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_send_6 --operation mode is normal F1_byte_send_6_lut_out = F1_nx757 # F1_nx758 # F1_nx759 # F1_nx760; F1_byte_send_6 = DFFEAS(F1_byte_send_6_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2817, , , , ); --F1_nx798 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx798 --operation mode is normal F1_nx798 = F1_byte_counter_2 & !F1_byte_counter_1 & !F1_byte_counter_0 & !F1_nx538; --F1_bytes2send_47 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_47 --operation mode is normal F1_bytes2send_47_lut_out = F1_bytes2send_47; F1_bytes2send_47 = DFFEAS(F1_bytes2send_47_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_16, , , F1_a_3); --F1_bytes2send_23 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_23 --operation mode is normal F1_bytes2send_23_lut_out = F1_bytes2send_23; F1_bytes2send_23 = DFFEAS(F1_bytes2send_23_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_8, , , F1_a_1); --F1_nx794 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx794 --operation mode is normal F1_nx794 = F1_byte_counter_2 & F1_byte_counter_1 & !F1_byte_counter_0 & !F1_nx538; --F1_nx799 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx799 --operation mode is normal F1_nx799 = F1_byte_counter_1 & F1_byte_counter_0 & !F1_nx538; --F1_bytes2send_39 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_39 --operation mode is normal F1_bytes2send_39_lut_out = V1_request_24; F1_bytes2send_39 = DFFEAS(F1_bytes2send_39_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx479, , , , ); --F1_iword2send_7 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|iword2send_7 --operation mode is normal F1_iword2send_7_lut_out = F1_iword2send_7; F1_iword2send_7 = DFFEAS(F1_iword2send_7_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_8, , , F1_a_3); --F1_nx793 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx793 --operation mode is normal F1_nx793 = !F1_byte_counter_2 & !F1_byte_counter_1 & !F1_byte_counter_0 & !F1_nx538; --F1_nx796 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx796 --operation mode is normal F1_nx796 = F1_byte_counter_2 & !F1_byte_counter_1 & F1_byte_counter_0 & !F1_nx538; --F1_bytes2send_15 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_15 --operation mode is normal F1_bytes2send_15_lut_out = F1_bytes2send_15; F1_bytes2send_15 = DFFEAS(F1_bytes2send_15_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_16, , , F1_a_1); --F1_bytes2send_7 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_7 --operation mode is normal F1_bytes2send_7_lut_out = V1_request_24; F1_bytes2send_7 = DFFEAS(F1_bytes2send_7_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx543, , , , ); --F1_nx795 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx795 --operation mode is normal F1_nx795 = !F1_byte_counter_2 & F1_byte_counter_1 & !F1_byte_counter_0 & !F1_nx538; --F1_nx797 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx797 --operation mode is normal F1_nx797 = !F1_byte_counter_2 & !F1_byte_counter_1 & F1_byte_counter_0 & !F1_nx538; --Z1_data_out_28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_28 --operation mode is normal Z1_data_out_28_lut_out = Z1_data_out_27; Z1_data_out_28 = DFFEAS(Z1_data_out_28_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_28 --operation mode is normal Z2_data_out_28_lut_out = Z2_data_out_27; Z2_data_out_28 = DFFEAS(Z2_data_out_28_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --K1_sm_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|sm_5 --operation mode is normal K1_sm_5_lut_out = K1_sm_2; K1_sm_5 = DFFEAS(K1_sm_5_lut_out, S1__clk1, T1_chipRST_n, , K1_b_3, , , , ); --K1_b_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|b_3 --operation mode is normal K1_b_3 = !K1_timer_6 & !K1_timer_5 & !K1_timer_4 & !K1_nx901; --K1_ix38_ix21_nx8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|ix38_ix21_nx8 --operation mode is normal K1_ix38_ix21_nx8 = K1_counter_2 # K1_counter_1 # K1_counter_0; --H1_ce_psply_adc is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ce_psply_adc --operation mode is normal H1_ce_psply_adc_lut_out = !H1_modgen_eq_90_nx22 & !H1_modgen_eq_95_nx24 & !H1_nx156 & H1_nx217; H1_ce_psply_adc = DFFEAS(H1_ce_psply_adc_lut_out, S1__clk1, VCC, , , , , !T1_bus_req, ); --K1_sm_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|sm_4 --operation mode is normal K1_sm_4_lut_out = K1_sm_3 & !K1_ce_adc & R1_RDY; K1_sm_4 = DFFEAS(K1_sm_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_counter_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|counter_2 --operation mode is normal K1_counter_2_carry_eqn = K1_counter_nx16; K1_counter_2_lut_out = K1_counter_2 $ (!K1_counter_2_carry_eqn); K1_counter_2 = DFFEAS(K1_counter_2_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1355, , , K1_nx1346, ); --K1_counter_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|counter_1 --operation mode is arithmetic K1_counter_1_carry_eqn = K1_counter_nx9; K1_counter_1_lut_out = K1_counter_1 $ (K1_counter_1_carry_eqn); K1_counter_1 = DFFEAS(K1_counter_1_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1355, , , K1_nx1346, ); --K1_counter_nx16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|counter_nx16 --operation mode is arithmetic K1_counter_nx16 = CARRY(!K1_counter_nx9 # !K1_counter_1); --K1_counter_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|counter_0 --operation mode is arithmetic K1_counter_0_lut_out = K1_counter_0 $ K1_nx5; K1_counter_0 = DFFEAS(K1_counter_0_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1355, , , K1_nx1346, ); --K1_counter_nx9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|counter_nx9 --operation mode is arithmetic K1_counter_nx9 = CARRY(K1_counter_0 & K1_nx5); --K1_sm_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|sm_7 --operation mode is normal K1_sm_7_lut_out = K1_sm_1 # K1_modgen_select_210_nx2 # K1_sm_7 & !R1_RDY; K1_sm_7 = DFFEAS(K1_sm_7_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_nx899 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx899 --operation mode is normal K1_nx899 = K1_send_cfr # K1_nx692; --R1_counter_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|counter_1 --operation mode is arithmetic R1_counter_1_carry_eqn = R1_counter_nx10; R1_counter_1_lut_out = R1_counter_1 $ (!R1_counter_1_carry_eqn); R1_counter_1 = DFFEAS(R1_counter_1_lut_out, S1__clk1, T1_chipRST_n, , R1_NOT_nx499, , , !R1_sm_2, ); --R1_counter_nx16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|counter_nx16 --operation mode is arithmetic R1_counter_nx16 = CARRY(!R1_counter_1 & (!R1_counter_nx10)); --R1_counter_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|counter_0 --operation mode is arithmetic R1_counter_0_lut_out = !R1_counter_0; R1_counter_0 = DFFEAS(R1_counter_0_lut_out, S1__clk1, T1_chipRST_n, , R1_NOT_nx499, , , !R1_sm_2, ); --R1_counter_nx10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|counter_nx10 --operation mode is arithmetic R1_counter_nx10 = CARRY(R1_counter_0); --K1_cfr_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_12 --operation mode is normal K1_cfr_12_lut_out = V1_request_19; K1_cfr_12 = DFFEAS(K1_cfr_12_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_counter_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|counter_3 --operation mode is normal R1_counter_3_carry_eqn = R1_counter_nx21; R1_counter_3_lut_out = R1_counter_3 $ (!R1_counter_3_carry_eqn); R1_counter_3 = DFFEAS(R1_counter_3_lut_out, S1__clk1, T1_chipRST_n, , R1_NOT_nx499, , , !R1_sm_2, ); --R1_counter_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|counter_2 --operation mode is arithmetic R1_counter_2_carry_eqn = R1_counter_nx16; R1_counter_2_lut_out = R1_counter_2 $ (R1_counter_2_carry_eqn); R1_counter_2 = DFFEAS(R1_counter_2_lut_out, S1__clk1, T1_chipRST_n, , R1_NOT_nx499, , , !R1_sm_2, ); --R1_counter_nx21 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|counter_nx21 --operation mode is arithmetic R1_counter_nx21 = CARRY(R1_counter_2 # !R1_counter_nx16); --R1_datasr_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_12 --operation mode is normal R1_datasr_12_lut_out = R1_datasr_11 & R1_ADC_SCLK; R1_datasr_12 = DFFEAS(R1_datasr_12_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --V1_request_33 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_33 --operation mode is normal V1_request_33 = V1_select_rq & (Z2_data_out_33) # !V1_select_rq & Z1_data_out_33; --V1_request_34 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_34 --operation mode is normal V1_request_34 = V1_select_rq & (Z2_data_out_34) # !V1_select_rq & Z1_data_out_34; --V1_request_37 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_37 --operation mode is normal V1_request_37 = V1_select_rq & (Z2_data_out_37) # !V1_select_rq & Z1_data_out_37; --H1_nx156 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx156 --operation mode is normal H1_nx156 = V1_request_35 # !V1_request_36; --Z1_data_out_38 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_38 --operation mode is normal Z1_data_out_38_lut_out = Z1_data_out_37; Z1_data_out_38 = DFFEAS(Z1_data_out_38_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_38 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_38 --operation mode is normal Z2_data_out_38_lut_out = Z2_data_out_37; Z2_data_out_38 = DFFEAS(Z2_data_out_38_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --T1_bridge_alter is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|bridge_alter --operation mode is normal T1_bridge_alter = V1_request_valid & !X1_data_out_3 & !X1_data_out_2 & !T1_ix34_ix34_nx8; --KB1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|hamm_reg_3_0_1_unfolded0:h1|data_out_2 --operation mode is normal KB1_data_out_2_lut_out = V1_next_state_2; KB1_data_out_2 = DFFEAS(KB1_data_out_2_lut_out, S1__clk0, VCC, , , , , , ); --KB1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|hamm_reg_3_0_1_unfolded0:h1|data_out_1 --operation mode is normal KB1_data_out_1_lut_out = V1_next_state_1; KB1_data_out_1 = DFFEAS(KB1_data_out_1_lut_out, S1__clk0, VCC, , , , , , ); --J1_io_start is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|io_start --operation mode is normal J1_io_start_lut_out = H1_ce_pasa_adc & !T1_rd_wr_oase & V1_request_38 & V1_request_24; J1_io_start = DFFEAS(J1_io_start_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --J1_NOT_cfr_6 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|NOT_cfr_6 --operation mode is normal J1_NOT_cfr_6_lut_out = !V1_request_25; J1_NOT_cfr_6 = DFFEAS(J1_NOT_cfr_6_lut_out, S1__clk1, T1_chipRST_n, , J1_wren_cfr, , , , ); --J1_samples_1 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_1 --operation mode is arithmetic J1_samples_1_carry_eqn = J1_samples_nx5; J1_samples_1_lut_out = J1_samples_1 $ (J1_samples_1_carry_eqn); J1_samples_1 = DFFEAS(J1_samples_1_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_nx11 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_nx11 --operation mode is arithmetic J1_samples_nx11 = CARRY(!J1_samples_nx5 # !J1_samples_1); --J1_samples_0 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_0 --operation mode is arithmetic J1_samples_0_lut_out = !J1_samples_0; J1_samples_0 = DFFEAS(J1_samples_0_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_nx5 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_nx5 --operation mode is arithmetic J1_samples_nx5 = CARRY(J1_samples_0); --J1_nx79 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|nx79 --operation mode is normal J1_nx79 = !J1_samples_6 # !J1_samples_7 # !J1_samples_8 # !J1_samples_9; --J1_nx80 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|nx80 --operation mode is normal J1_nx80 = !J1_samples_2 # !J1_samples_3 # !J1_samples_4 # !J1_samples_5; --Z1_data_out_52 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_52 --operation mode is normal Z1_data_out_52_lut_out = Z1_data_out_51; Z1_data_out_52 = DFFEAS(Z1_data_out_52_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_52 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_52 --operation mode is normal Z2_data_out_52_lut_out = Z2_data_out_51; Z2_data_out_52 = DFFEAS(Z2_data_out_52_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_51 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_51 --operation mode is normal Z1_data_out_51_lut_out = Z1_data_out_50; Z1_data_out_51 = DFFEAS(Z1_data_out_51_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_51 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_51 --operation mode is normal Z2_data_out_51_lut_out = Z2_data_out_50; Z2_data_out_51 = DFFEAS(Z2_data_out_51_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_50 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_50 --operation mode is normal Z1_data_out_50_lut_out = Z1_data_out_49; Z1_data_out_50 = DFFEAS(Z1_data_out_50_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_50 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_50 --operation mode is normal Z2_data_out_50_lut_out = Z2_data_out_49; Z2_data_out_50 = DFFEAS(Z2_data_out_50_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_49 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_49 --operation mode is normal Z1_data_out_49_lut_out = Z1_data_out_48; Z1_data_out_49 = DFFEAS(Z1_data_out_49_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_49 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_49 --operation mode is normal Z2_data_out_49_lut_out = Z2_data_out_48; Z2_data_out_49 = DFFEAS(Z2_data_out_49_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_41 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_41 --operation mode is normal Z1_data_out_41_lut_out = Z1_data_out_40; Z1_data_out_41 = DFFEAS(Z1_data_out_41_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_41 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_41 --operation mode is normal Z2_data_out_41_lut_out = Z2_data_out_40; Z2_data_out_41 = DFFEAS(Z2_data_out_41_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_42 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_42 --operation mode is normal Z1_data_out_42_lut_out = Z1_data_out_41; Z1_data_out_42 = DFFEAS(Z1_data_out_42_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_42 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_42 --operation mode is normal Z2_data_out_42_lut_out = Z2_data_out_41; Z2_data_out_42 = DFFEAS(Z2_data_out_42_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --H1_modgen_eq_95_nx24 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|modgen_eq_95_nx24 --operation mode is normal H1_modgen_eq_95_nx24 = V1_request_33 # !V1_request_34; --T1_current_state_dp_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|current_state_dp_2 --operation mode is normal T1_current_state_dp_2_lut_out = H1_bus_ack & !T1_current_state_dp_2 & !T1_current_state_dp_0 & T1_bus_req; T1_current_state_dp_2 = DFFEAS(T1_current_state_dp_2_lut_out, S1__clk0, VCC, , , , , , ); --T1_current_state_dp_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|current_state_dp_0 --operation mode is normal T1_current_state_dp_0_lut_out = T1_current_state_dp_2 # T1_current_state_dp_0 & (!T1_nx426) # !T1_current_state_dp_0 & !T1_bus_req; T1_current_state_dp_0 = DFFEAS(T1_current_state_dp_0_lut_out, S1__clk0, VCC, , , , , , ); --T1_nx426 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx426 --operation mode is normal T1_nx426 = !T1_req_reg & T1_cfg_req & !T1_bus_req; --T1_nx410 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx410 --operation mode is normal T1_nx410 = H1_bus_ack # T1_current_state_dp_2 # T1_current_state_dp_0; --Z1_data_out_23 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_23 --operation mode is normal Z1_data_out_23_lut_out = Z1_data_out_22; Z1_data_out_23 = DFFEAS(Z1_data_out_23_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_23 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_23 --operation mode is normal Z2_data_out_23_lut_out = Z2_data_out_22; Z2_data_out_23 = DFFEAS(Z2_data_out_23_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G1_modgen_gt_455_nx30 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_455_nx30 --operation mode is arithmetic G1_modgen_gt_455_nx30 = CARRY(G1_nx579 & !G1_B_5 & !G1_modgen_gt_455_nx28 # !G1_nx579 & (!G1_modgen_gt_455_nx28 # !G1_B_5)); --Z1_data_out_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_15 --operation mode is normal Z1_data_out_15_lut_out = Z1_data_out_14; Z1_data_out_15 = DFFEAS(Z1_data_out_15_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_15 --operation mode is normal Z2_data_out_15_lut_out = Z2_data_out_14; Z2_data_out_15 = DFFEAS(Z2_data_out_15_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G2_modgen_gt_455_nx30 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_455_nx30 --operation mode is arithmetic G2_modgen_gt_455_nx30 = CARRY(G2_nx579 & !G2_B_5 & !G2_modgen_gt_455_nx28 # !G2_nx579 & (!G2_modgen_gt_455_nx28 # !G2_B_5)); --Z1_data_out_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_7 --operation mode is normal Z1_data_out_7_lut_out = Z1_data_out_6; Z1_data_out_7 = DFFEAS(Z1_data_out_7_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_7 --operation mode is normal Z2_data_out_7_lut_out = Z2_data_out_6; Z2_data_out_7 = DFFEAS(Z2_data_out_7_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G3_modgen_gt_455_nx30 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_455_nx30 --operation mode is arithmetic G3_modgen_gt_455_nx30 = CARRY(G3_nx579 & !G3_B_5 & !G3_modgen_gt_455_nx28 # !G3_nx579 & (!G3_modgen_gt_455_nx28 # !G3_B_5)); --CB1_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|data_out --operation mode is normal CB1_data_out_lut_out = W1_d0_to_dll # !Y1_buffer_flush_n; CB1_data_out = DFFEAS(CB1_data_out_lut_out, S1__clk0, VCC, , CB1_nx90, , , , ); --CB2_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|data_out --operation mode is normal CB2_data_out_lut_out = W1_d1_to_dll # !Y2_buffer_flush_n; CB2_data_out = DFFEAS(CB2_data_out_lut_out, S1__clk0, VCC, , CB2_nx90, , , , ); --G4_modgen_gt_455_nx30 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_455_nx30 --operation mode is arithmetic G4_modgen_gt_455_nx30 = CARRY(G4_nx579 & !G4_B_5 & !G4_modgen_gt_455_nx28 # !G4_nx579 & (!G4_modgen_gt_455_nx28 # !G4_B_5)); --G1_B_5 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_5 --operation mode is arithmetic G1_B_5_carry_eqn = G1_B_nx35; G1_B_5_lut_out = G1_B_5 $ (G1_B_5_carry_eqn); G1_B_5 = DFFEAS(G1_B_5_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_B_nx45 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_nx45 --operation mode is arithmetic G1_B_nx45 = CARRY(G1_B_5 $ !G1_NOT_UDn # !G1_B_nx35); --V1_request_25 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_25 --operation mode is normal V1_request_25 = V1_select_rq & (Z2_data_out_25) # !V1_select_rq & Z1_data_out_25; --G1_NOT_nx14 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|NOT_nx14 --operation mode is normal G1_NOT_nx14 = V1_request_26 & V1_request_25 & G1_nx573; --G1_nx12 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx12 --operation mode is normal G1_nx12 = !T1_rd_wr_oase & H1_ce_digpot & !V1_request_24; --G1_nx579 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx579 --operation mode is normal G1_nx579_lut_out = !V1_request_26; G1_nx579 = DFFEAS(G1_nx579_lut_out, S1__clk1, T1_chipRST_n, , G1_nx12, , , G1_NOT_nx14, ); --G1_modgen_gt_453_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_453_nx28 --operation mode is arithmetic G1_modgen_gt_453_nx28 = CARRY(G1_B_4 & G1_a_4 & !G1_modgen_gt_453_nx26 # !G1_B_4 & (G1_a_4 # !G1_modgen_gt_453_nx26)); --G2_B_5 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_5 --operation mode is arithmetic G2_B_5_carry_eqn = G2_B_nx35; G2_B_5_lut_out = G2_B_5 $ (G2_B_5_carry_eqn); G2_B_5 = DFFEAS(G2_B_5_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_B_nx45 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_nx45 --operation mode is arithmetic G2_B_nx45 = CARRY(G2_B_5 $ !G2_NOT_UDn # !G2_B_nx35); --V1_request_17 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_17 --operation mode is normal V1_request_17 = V1_select_rq & (Z2_data_out_17) # !V1_select_rq & Z1_data_out_17; --G2_NOT_nx14 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|NOT_nx14 --operation mode is normal G2_NOT_nx14 = V1_request_18 & V1_request_17 & G2_nx573; --G2_nx12 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx12 --operation mode is normal G2_nx12 = !T1_rd_wr_oase & H1_ce_digpot & !V1_request_16; --G2_nx579 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx579 --operation mode is normal G2_nx579_lut_out = !V1_request_18; G2_nx579 = DFFEAS(G2_nx579_lut_out, S1__clk1, T1_chipRST_n, , G2_nx12, , , G2_NOT_nx14, ); --G2_modgen_gt_453_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_453_nx28 --operation mode is arithmetic G2_modgen_gt_453_nx28 = CARRY(G2_B_4 & G2_a_4 & !G2_modgen_gt_453_nx26 # !G2_B_4 & (G2_a_4 # !G2_modgen_gt_453_nx26)); --G3_B_5 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_5 --operation mode is arithmetic G3_B_5_carry_eqn = G3_B_nx35; G3_B_5_lut_out = G3_B_5 $ (G3_B_5_carry_eqn); G3_B_5 = DFFEAS(G3_B_5_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_B_nx45 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_nx45 --operation mode is arithmetic G3_B_nx45 = CARRY(G3_B_5 $ !G3_NOT_UDn # !G3_B_nx35); --V1_request_9 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_9 --operation mode is normal V1_request_9 = V1_select_rq & (Z2_data_out_9) # !V1_select_rq & Z1_data_out_9; --G3_NOT_nx14 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|NOT_nx14 --operation mode is normal G3_NOT_nx14 = V1_request_10 & V1_request_9 & G3_nx573; --G3_nx12 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx12 --operation mode is normal G3_nx12 = !T1_rd_wr_oase & H1_ce_digpot & !V1_request_8; --G3_nx579 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx579 --operation mode is normal G3_nx579_lut_out = !V1_request_10; G3_nx579 = DFFEAS(G3_nx579_lut_out, S1__clk1, T1_chipRST_n, , G3_nx12, , , G3_NOT_nx14, ); --G3_modgen_gt_453_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_453_nx28 --operation mode is arithmetic G3_modgen_gt_453_nx28 = CARRY(G3_B_4 & G3_a_4 & !G3_modgen_gt_453_nx26 # !G3_B_4 & (G3_a_4 # !G3_modgen_gt_453_nx26)); --G4_B_5 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_5 --operation mode is arithmetic G4_B_5_carry_eqn = G4_B_nx35; G4_B_5_lut_out = G4_B_5 $ (G4_B_5_carry_eqn); G4_B_5 = DFFEAS(G4_B_5_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_B_nx45 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_nx45 --operation mode is arithmetic G4_B_nx45 = CARRY(G4_B_5 $ !G4_NOT_UDn # !G4_B_nx35); --V1_request_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_1 --operation mode is normal V1_request_1 = V1_select_rq & (Z2_data_out_1) # !V1_select_rq & Z1_data_out_1; --G4_NOT_nx14 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|NOT_nx14 --operation mode is normal G4_NOT_nx14 = V1_request_2 & V1_request_1 & G4_nx573; --G4_nx12 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx12 --operation mode is normal G4_nx12 = !T1_rd_wr_oase & H1_ce_digpot & !V1_request_0; --G4_nx579 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx579 --operation mode is normal G4_nx579_lut_out = !V1_request_2; G4_nx579 = DFFEAS(G4_nx579_lut_out, S1__clk1, T1_chipRST_n, , G4_nx12, , , G4_NOT_nx14, ); --G4_modgen_gt_453_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_453_nx28 --operation mode is arithmetic G4_modgen_gt_453_nx28 = CARRY(G4_B_4 & G4_a_4 & !G4_modgen_gt_453_nx26 # !G4_B_4 & (G4_a_4 # !G4_modgen_gt_453_nx26)); --L1_sm_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|sm_5 --operation mode is normal L1_sm_5_lut_out = L1_sm_2; L1_sm_5 = DFFEAS(L1_sm_5_lut_out, S1__clk1, T1_chipRST_n, , L1_b_3, , , , ); --L1_b_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|b_3 --operation mode is normal L1_b_3 = !L1_timer_6 & !L1_timer_5 & !L1_timer_4 & !L1_nx818; --L1_ix38_ix21_nx8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|ix38_ix21_nx8 --operation mode is normal L1_ix38_ix21_nx8 = L1_counter_2 # L1_counter_1 # L1_counter_0; --H1_ce_sc_adc is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ce_sc_adc --operation mode is normal H1_ce_sc_adc_lut_out = V1_request_39 & V1_request_40 & H1_nx155; H1_ce_sc_adc = DFFEAS(H1_ce_sc_adc_lut_out, S1__clk1, VCC, , , , , !T1_bus_req, ); --L1_sm_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|sm_4 --operation mode is normal L1_sm_4_lut_out = L1_sm_3 & !L1_ce_adc & R2_RDY; L1_sm_4 = DFFEAS(L1_sm_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_counter_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|counter_2 --operation mode is normal L1_counter_2_carry_eqn = L1_counter_nx16; L1_counter_2_lut_out = L1_counter_2 $ (!L1_counter_2_carry_eqn); L1_counter_2 = DFFEAS(L1_counter_2_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1355, , , L1_nx1346, ); --L1_counter_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|counter_1 --operation mode is arithmetic L1_counter_1_carry_eqn = L1_counter_nx9; L1_counter_1_lut_out = L1_counter_1 $ (L1_counter_1_carry_eqn); L1_counter_1 = DFFEAS(L1_counter_1_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1355, , , L1_nx1346, ); --L1_counter_nx16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|counter_nx16 --operation mode is arithmetic L1_counter_nx16 = CARRY(!L1_counter_nx9 # !L1_counter_1); --L1_counter_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|counter_0 --operation mode is arithmetic L1_counter_0_lut_out = L1_counter_0 $ L1_nx5; L1_counter_0 = DFFEAS(L1_counter_0_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1355, , , L1_nx1346, ); --L1_counter_nx9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|counter_nx9 --operation mode is arithmetic L1_counter_nx9 = CARRY(L1_counter_0 & L1_nx5); --L1_sm_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|sm_7 --operation mode is normal L1_sm_7_lut_out = L1_sm_1 # L1_modgen_select_210_nx2 # L1_sm_7 & !R2_RDY; L1_sm_7 = DFFEAS(L1_sm_7_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_nx816 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx816 --operation mode is normal L1_nx816 = L1_send_cfr # L1_nx637; --R2_counter_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_1 --operation mode is arithmetic R2_counter_1_carry_eqn = R2_counter_nx10; R2_counter_1_lut_out = R2_counter_1 $ (!R2_counter_1_carry_eqn); R2_counter_1 = DFFEAS(R2_counter_1_lut_out, S1__clk1, T1_chipRST_n, , R2_NOT_nx499, , , !R2_sm_2, ); --R2_counter_nx16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_nx16 --operation mode is arithmetic R2_counter_nx16 = CARRY(!R2_counter_1 & (!R2_counter_nx10)); --R2_counter_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_0 --operation mode is arithmetic R2_counter_0_lut_out = !R2_counter_0; R2_counter_0 = DFFEAS(R2_counter_0_lut_out, S1__clk1, T1_chipRST_n, , R2_NOT_nx499, , , !R2_sm_2, ); --R2_counter_nx10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_nx10 --operation mode is arithmetic R2_counter_nx10 = CARRY(R2_counter_0); --L1_cfr_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_12 --operation mode is normal L1_cfr_12_lut_out = V1_request_19; L1_cfr_12 = DFFEAS(L1_cfr_12_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_counter_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_3 --operation mode is normal R2_counter_3_carry_eqn = R2_counter_nx21; R2_counter_3_lut_out = R2_counter_3 $ (!R2_counter_3_carry_eqn); R2_counter_3 = DFFEAS(R2_counter_3_lut_out, S1__clk1, T1_chipRST_n, , R2_NOT_nx499, , , !R2_sm_2, ); --R2_counter_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_2 --operation mode is arithmetic R2_counter_2_carry_eqn = R2_counter_nx16; R2_counter_2_lut_out = R2_counter_2 $ (R2_counter_2_carry_eqn); R2_counter_2 = DFFEAS(R2_counter_2_lut_out, S1__clk1, T1_chipRST_n, , R2_NOT_nx499, , , !R2_sm_2, ); --R2_counter_nx21 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_nx21 --operation mode is arithmetic R2_counter_nx21 = CARRY(R2_counter_2 # !R2_counter_nx16); --R2_datasr_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_12 --operation mode is normal R2_datasr_12_lut_out = R2_datasr_11 & R2_ADC_SCLK; R2_datasr_12 = DFFEAS(R2_datasr_12_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --BB1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|next_state_2 --operation mode is normal BB1_next_state_2 = FB1_data_out_2 & !FB1_data_out_1 & !GB1_event # !FB1_data_out_2 & (BB1_nx27); --BB1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|next_state_1 --operation mode is normal BB1_next_state_1 = BB1_nx28 # !FB1_data_out_2 & FB1_data_out_0; --BB1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|next_state_0 --operation mode is normal BB1_next_state_0 = BB1_nx29 # JB1_event_async & BB1_nx30; --BB1_stuffing_data_in is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|stuffing_data_in --operation mode is normal BB1_stuffing_data_in = AB1_data_out # !FB1_data_out_2 & !FB1_data_out_1 & FB1_data_out_0; --BB1_stuffing_strobe_in is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|stuffing_strobe_in --operation mode is normal BB1_stuffing_strobe_in = BB1_nx26 # !AB1_buffer_empty & JB1_event_async; --HB1_data is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|data --operation mode is normal HB1_data_lut_out = HB1_NOT_nx118 & (!HB1_data) # !HB1_NOT_nx118 & BB1_stuffing_data_in; HB1_data = DFFEAS(HB1_data_lut_out, S1__clk0, VCC, , BB1_stuffing_strobe_in, , , , ); --HB1_NOT_nx118 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|NOT_nx118 --operation mode is normal HB1_NOT_nx118 = BB1_stuffing_start_n & HB1_state_2 & HB1_state_1 & HB1_state_0; --HB1_stuff_bit_inserted is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|stuff_bit_inserted --operation mode is normal HB1_stuff_bit_inserted = DFFEAS(HB1_NOT_nx118, S1__clk0, VCC, , BB1_stuffing_strobe_in, , , , ); --HB1_nx120 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|nx120 --operation mode is normal HB1_nx120 = BB1_stuffing_strobe_in # !BB1_stuffing_start_n; --BB2_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|next_state_2 --operation mode is normal BB2_next_state_2 = FB2_data_out_2 & !FB2_data_out_1 & !GB2_event # !FB2_data_out_2 & (BB2_nx27); --BB2_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|next_state_1 --operation mode is normal BB2_next_state_1 = BB2_nx28 # !FB2_data_out_2 & FB2_data_out_0; --BB2_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|next_state_0 --operation mode is normal BB2_next_state_0 = BB2_nx29 # JB2_event_async & BB2_nx30; --BB2_stuffing_data_in is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|stuffing_data_in --operation mode is normal BB2_stuffing_data_in = AB2_data_out # !FB2_data_out_2 & !FB2_data_out_1 & FB2_data_out_0; --BB2_stuffing_strobe_in is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|stuffing_strobe_in --operation mode is normal BB2_stuffing_strobe_in = BB2_nx26 # !AB2_buffer_empty & JB2_event_async; --HB2_data is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|data --operation mode is normal HB2_data_lut_out = HB2_NOT_nx118 & (!HB2_data) # !HB2_NOT_nx118 & BB2_stuffing_data_in; HB2_data = DFFEAS(HB2_data_lut_out, S1__clk0, VCC, , BB2_stuffing_strobe_in, , , , ); --HB2_NOT_nx118 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|NOT_nx118 --operation mode is normal HB2_NOT_nx118 = BB2_stuffing_start_n & HB2_state_2 & HB2_state_1 & HB2_state_0; --HB2_stuff_bit_inserted is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|stuff_bit_inserted --operation mode is normal HB2_stuff_bit_inserted = DFFEAS(HB2_NOT_nx118, S1__clk0, VCC, , BB2_stuffing_strobe_in, , , , ); --HB2_nx120 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|nx120 --operation mode is normal HB2_nx120 = BB2_stuffing_strobe_in # !BB2_stuffing_start_n; --M1_LOAD is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|LOAD --operation mode is normal M1_LOAD = !M1_SL & !M1_nx116; --M1_PQ_13 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_13 --operation mode is normal M1_PQ_13_lut_out = V1_request_18; M1_PQ_13 = DFFEAS(M1_PQ_13_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_12, , , M1_SERREG_1); --K1_nx2777 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx2777 --operation mode is normal K1_nx2777_carry_eqn = K1_modgen_gt_268_nx50; K1_nx2777 = K1_NOT_climits_a_11 & (K1_adc_last_4_11 # K1_nx2777_carry_eqn) # !K1_NOT_climits_a_11 & K1_adc_last_4_11 & K1_nx2777_carry_eqn; --K1_nx2783 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx2783 --operation mode is normal K1_nx2783_carry_eqn = K1_modgen_gt_270_nx50; K1_nx2783 = K1_NOT_climits_d_11 & (K1_adc_last_6_11 # K1_nx2783_carry_eqn) # !K1_NOT_climits_d_11 & K1_adc_last_6_11 & K1_nx2783_carry_eqn; --K1_nx2780 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx2780 --operation mode is normal K1_nx2780_carry_eqn = K1_modgen_gt_269_nx50; K1_nx2780 = K1_NOT_climits_a_23 & (K1_adc_last_5_11 # K1_nx2780_carry_eqn) # !K1_NOT_climits_a_23 & K1_adc_last_5_11 & K1_nx2780_carry_eqn; --K1_nx2786 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx2786 --operation mode is normal K1_nx2786_carry_eqn = K1_modgen_gt_271_nx50; K1_nx2786 = K1_NOT_climits_d_23 & (K1_adc_last_7_11 # K1_nx2786_carry_eqn) # !K1_NOT_climits_d_23 & K1_adc_last_7_11 & K1_nx2786_carry_eqn; --H1_ce_shutdn is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ce_shutdn --operation mode is normal H1_ce_shutdn_lut_out = V1_request_41 & !V1_request_42 & !H1_modgen_eq_90_nx22 & H1_nx155; H1_ce_shutdn = DFFEAS(H1_ce_shutdn_lut_out, S1__clk1, VCC, , , , , !T1_bus_req, ); --E1_cnt_rst_7 is ni2io_wt:wt_ni|cnt_rst_7 --operation mode is arithmetic E1_cnt_rst_7_carry_eqn = E1_cnt_rst_nx46; E1_cnt_rst_7_lut_out = E1_cnt_rst_7 $ (E1_cnt_rst_7_carry_eqn); E1_cnt_rst_7 = DFFEAS(E1_cnt_rst_7_lut_out, S1__clk1, T1_chipRST_n, , , , , !E1_NOT_rst_start, ); --E1_cnt_rst_nx50 is ni2io_wt:wt_ni|cnt_rst_nx50 --operation mode is arithmetic E1_cnt_rst_nx50 = CARRY(!E1_cnt_rst_nx46 # !E1_cnt_rst_7); --E1_NOT_rst_inv is ni2io_wt:wt_ni|NOT_rst_inv --operation mode is normal E1_NOT_rst_inv_lut_out = E1_NOT_rst_inv; E1_NOT_rst_inv = DFFEAS(E1_NOT_rst_inv_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L451, , , E1_nx398); --E1_rst_opend is ni2io_wt:wt_ni|rst_opend --operation mode is normal E1_rst_opend_lut_out = E1_rst_opend; E1_rst_opend = DFFEAS(E1_rst_opend_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_22, , , E1_nx398); --Z1_data_out_39 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_39 --operation mode is normal Z1_data_out_39_lut_out = Z1_data_out_38; Z1_data_out_39 = DFFEAS(Z1_data_out_39_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_39 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_39 --operation mode is normal Z2_data_out_39_lut_out = Z2_data_out_38; Z2_data_out_39 = DFFEAS(Z2_data_out_39_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_40 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_40 --operation mode is normal Z1_data_out_40_lut_out = Z1_data_out_39; Z1_data_out_40 = DFFEAS(Z1_data_out_40_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_40 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_40 --operation mode is normal Z2_data_out_40_lut_out = Z2_data_out_39; Z2_data_out_40 = DFFEAS(Z2_data_out_40_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --F1_nx784 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx784 --operation mode is normal F1_nx784 = F1_byte_counter_2 # F1_byte_counter_1; --F1_nx847 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx847 --operation mode is normal F1_nx847 = F1_byte_counter_0 & !F1_nx784 & F1_nx788 & !F1_nx790; --F1_b_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|b_0 --operation mode is normal F1_b_0_carry_eqn = F1_result_dec_339_nx18; F1_b_0 = F1_byte_counter_2 $ (F1_b_0_carry_eqn); --F1_nx749 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx749 --operation mode is normal F1_nx749 = F1_byte_counter_0 & !F1_nx784 & (F1_sm_top_5 # F1_sm_top_3); --F1_nx837 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx837 --operation mode is normal F1_nx837 = F1_nx803 & (F1_iword2send_2 & (F1_iword2send_0 # !F1_iword2send_1) # !F1_iword2send_2 & F1_iword2send_1); --F1_nx840 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx840 --operation mode is normal F1_nx840 = F1_sm_top_6 # F1_sm_top_5 # F1_sm_top_3; --F1_NOT_nx1467 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx1467 --operation mode is normal F1_NOT_nx1467 = !F1_nx791 & F1_nx839 & (F1_nx850 # !F1_nx790); --F1_nx750 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx750 --operation mode is normal F1_nx750 = F1_iword2send_0 & F1_b_0_dup_234 & F1_nx788 # !F1_iword2send_0 & (F1_nx803 # F1_b_0_dup_234 & F1_nx788); --F1_nx838 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx838 --operation mode is normal F1_nx838 = F1_sm_top_1 & (F1_iword2send_3 & (F1_iword2send_2 # F1_nx789) # !F1_iword2send_3 & !F1_iword2send_2); --F1_nx849 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx849 --operation mode is normal F1_nx849 = F1_sm_top_6 & F1_b_0_dup_234; --F1_b_0_dup_240 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|b_0_dup_240 --operation mode is normal F1_b_0_dup_240 = !F1_byte_counter_0; --F1_nx848 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx848 --operation mode is normal F1_nx848 = F1_sm_top_1 & !F1_nx789 & (F1_iword2send_3 $ F1_iword2send_2); --T1_nx412 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx412 --operation mode is normal T1_nx412 = T1_nx413 # T1_nx439 # T1_nx407 & !T1_nx429; --T1_nx414 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx414 --operation mode is normal T1_nx414 = !V1_request_49 & V1_request_valid & !X1_data_out_0 & !T1_nx399; --T1_nx424 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx424 --operation mode is normal T1_nx424 = V1_request_52 $ V1_request_51 # !V1_request_50; --T1_nx437 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx437 --operation mode is normal T1_nx437 = T1_nx438 & (X1_data_out_3 # V1_request_49 & T1_nx400); --T1_nx415 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx415 --operation mode is normal T1_nx415 = V1_request_52 & V1_request_51 & !X1_data_out_1 & T1_nx405; --T1_nx417 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx417 --operation mode is normal T1_nx417 = X1_data_out_2 & (T1_nx401) # !X1_data_out_2 & !T1_a_2_dup_231 & (!T1_ix34_ix32_nx8); --T1_nx431 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx431 --operation mode is normal T1_nx431 = X1_data_out_3 & (X1_data_out_2 & X1_data_out_1 & !X1_data_out_0 # !X1_data_out_2 & (X1_data_out_0)); --T1_nx435 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx435 --operation mode is normal T1_nx435 = T1_nx418 # T1_nx436 # !T1_ix34_ix32_nx8 & T1_nx416; --T1_nx419 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx419 --operation mode is normal T1_nx419 = T1_nx431 # !X1_data_out_3 & T1_a_2_dup_231 & !T1_ix34_ix32_nx8; --T1_nx420 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx420 --operation mode is normal T1_nx420 = T1_nx436 # X1_data_out_1 & !X1_data_out_0 & T1_nx401; --T1_nx421 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx421 --operation mode is normal T1_nx421 = !T1_a_2_dup_231 & T1_nx408 & (!X1_data_out_1 # !H1_bus_dout_0); --T1_nx430 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx430 --operation mode is normal T1_nx430 = T1_nx432 & (T1_nx433 # T1_nx434) # !T1_nx432 & T1_nx406 & (T1_nx434); --T1_nx407 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx407 --operation mode is normal T1_nx407 = X1_data_out_3 & X1_data_out_2 & X1_data_out_1 & X1_data_out_0; --T1_nx422 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx422 --operation mode is normal T1_nx422 = !X1_data_out_3 & X1_data_out_0 & T1_a_2_dup_231 & T1_nx399; --T1_nx427 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx427 --operation mode is normal T1_nx427 = T1_nx423 # !V1_request_49 & !T1_nx399 & T1_nx428; --T1_nx429 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx429 --operation mode is normal T1_nx429 = !V1_request_50 & V1_request_valid & (V1_request_52 # V1_request_51); --DB1_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1|data_out_3 --operation mode is normal DB1_data_out_3_lut_out = Y1_next_state_3; DB1_data_out_3 = DFFEAS(DB1_data_out_3_lut_out, S1__clk0, VCC, , , , , , ); --DB1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1|data_out_2 --operation mode is normal DB1_data_out_2_lut_out = Y1_next_state_2; DB1_data_out_2 = DFFEAS(DB1_data_out_2_lut_out, S1__clk0, VCC, , , , , , ); --DB1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1|data_out_0 --operation mode is normal DB1_data_out_0_lut_out = Y1_next_state_0; DB1_data_out_0 = DFFEAS(DB1_data_out_0_lut_out, S1__clk0, VCC, , , , , , ); --Z1_nx277 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx277 --operation mode is normal Z1_nx277 = CB1_strobe_out & !Z1_bitcounter_5 & !Z1_bitcounter_3 & !Z1_bitcounter_4; --Z1_nx285 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx285 --operation mode is normal Z1_nx285 = CB1_strobe_out & !Z1_bitcounter_6; --Z1_nx286 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx286 --operation mode is normal Z1_nx286 = Z1_bitcounter_2 & (Z1_bitcounter_1 # Z1_bitcounter_0); --DB2_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1|data_out_3 --operation mode is normal DB2_data_out_3_lut_out = Y2_next_state_3; DB2_data_out_3 = DFFEAS(DB2_data_out_3_lut_out, S1__clk0, VCC, , , , , , ); --DB2_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1|data_out_2 --operation mode is normal DB2_data_out_2_lut_out = Y2_next_state_2; DB2_data_out_2 = DFFEAS(DB2_data_out_2_lut_out, S1__clk0, VCC, , , , , , ); --DB2_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1|data_out_0 --operation mode is normal DB2_data_out_0_lut_out = Y2_next_state_0; DB2_data_out_0 = DFFEAS(DB2_data_out_0_lut_out, S1__clk0, VCC, , , , , , ); --Z2_nx277 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx277 --operation mode is normal Z2_nx277 = CB2_strobe_out & !Z2_bitcounter_5 & !Z2_bitcounter_3 & !Z2_bitcounter_4; --Z2_nx285 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx285 --operation mode is normal Z2_nx285 = CB2_strobe_out & !Z2_bitcounter_6; --Z2_nx286 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx286 --operation mode is normal Z2_nx286 = Z2_bitcounter_2 & (Z2_bitcounter_1 # Z2_bitcounter_0); --V1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|next_state_0 --operation mode is normal V1_next_state_0 = V1_nx227 # T1_bridge_alter & !KB1_data_out_2 & KB1_data_out_0; --DB4_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1|data_out_3 --operation mode is normal DB4_data_out_3_lut_out = LB2_next_state_3; DB4_data_out_3 = DFFEAS(DB4_data_out_3_lut_out, S1__clk0, VCC, , , , , , ); --DB4_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1|data_out_2 --operation mode is normal DB4_data_out_2_lut_out = LB2_next_state_2; DB4_data_out_2 = DFFEAS(DB4_data_out_2_lut_out, S1__clk0, VCC, , , , , , ); --DB4_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1|data_out_1 --operation mode is normal DB4_data_out_1_lut_out = LB2_next_state_1; DB4_data_out_1 = DFFEAS(DB4_data_out_1_lut_out, S1__clk0, VCC, , , , , , ); --DB4_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1|data_out_0 --operation mode is normal DB4_data_out_0_lut_out = LB2_next_state_0; DB4_data_out_0 = DFFEAS(DB4_data_out_0_lut_out, S1__clk0, VCC, , , , , , ); --LB1_request_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|request_valid --operation mode is normal LB1_request_valid = !DB3_data_out_3 & !DB3_data_out_2 & DB3_data_out_1 & !DB3_data_out_0; --Z1_data_out_45 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_45 --operation mode is normal Z1_data_out_45_lut_out = Z1_data_out_44; Z1_data_out_45 = DFFEAS(Z1_data_out_45_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_45 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_45 --operation mode is normal Z2_data_out_45_lut_out = Z2_data_out_44; Z2_data_out_45 = DFFEAS(Z2_data_out_45_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --F1_nx751 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx751 --operation mode is normal F1_nx751 = F1_sm_top_4 & (F1_nx800 # F1_sm_sr_5 & !F1_nx786) # !F1_sm_top_4 & F1_sm_sr_5 & !F1_nx786; --F1_nx841 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx841 --operation mode is normal F1_nx841 = F1_sm_top_5 & F1_sm_sr_5 & (F1_nx784 # !F1_byte_counter_0); --F1_nx752 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx752 --operation mode is normal F1_nx752 = F1_sm_top_3 & !F1_nx790 & (F1_nx784 # !F1_byte_counter_0); --F1_nx800 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx800 --operation mode is normal F1_nx800 = F1_nx538 # !F1_clkdivs; --F1_nx846 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx846 --operation mode is normal F1_nx846 = F1_sm_top_1 & F1_sm_sr_5 & !F1_iword2send_7; --F1_nx791 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx791 --operation mode is normal F1_nx791 = F1_sm_top_4 # F1_sm_top_2; --F1_nx792 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx792 --operation mode is normal F1_nx792 = F1_sm_sr_3 # F1_sm_sr_1; --F1_nx2672 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2672 --operation mode is normal F1_nx2672 = F1_b_1_dup_404 & (F1_sm_sr_3 # F1_sm_sr_1) # !F1_nx538; --F1_nx2701 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2701 --operation mode is normal F1_nx2701 = F1_sm_sr_3 # F1_sm_sr_1 # !F1_nx538; --F1_nx2685 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2685 --operation mode is normal F1_nx2685 = F1_b_1_dup_411 & (F1_sm_sr_3 # F1_sm_sr_1) # !F1_nx538; --F1_nx2698 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2698 --operation mode is normal F1_nx2698 = F1_b_1_dup_418 & (F1_sm_sr_3 # F1_sm_sr_1) # !F1_nx538; --F1_a_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|a_1 --operation mode is normal F1_a_1 = !V1_request_46 & !V1_request_47 & !V1_request_48; --F1_nx757 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx757 --operation mode is normal F1_nx757 = F1_sm_sr_4 & (F1_byte_send_5 # F1_bytes2send_30 & F1_nx798) # !F1_sm_sr_4 & F1_bytes2send_30 & (F1_nx798); --F1_nx758 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx758 --operation mode is normal F1_nx758 = F1_bytes2send_46 & (F1_nx794 # F1_bytes2send_22 & F1_nx799) # !F1_bytes2send_46 & F1_bytes2send_22 & (F1_nx799); --F1_nx759 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx759 --operation mode is normal F1_nx759 = F1_bytes2send_38 & (F1_nx796 # F1_iword2send_6 & F1_nx793) # !F1_bytes2send_38 & F1_iword2send_6 & F1_nx793; --F1_nx760 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx760 --operation mode is normal F1_nx760 = F1_bytes2send_14 & (F1_nx795 # F1_bytes2send_6 & F1_nx797) # !F1_bytes2send_14 & F1_bytes2send_6 & (F1_nx797); --F1_a_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|a_3 --operation mode is normal F1_a_3 = !V1_request_46 & !V1_request_47 & V1_request_48; --F1_NOT_nx543 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx543 --operation mode is normal F1_NOT_nx543 = H1_ce_dds & !T1_rd_wr_oase & !V1_request_48 & F1_nx859; --K1_timer_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_6 --operation mode is normal K1_timer_6_lut_out = K1_nx898 # K1_nx1223 & K1_nx897 # !K1_nx692; K1_timer_6 = DFFEAS(K1_timer_6_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1369, , , , ); --K1_timer_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_5 --operation mode is normal K1_timer_5_lut_out = K1_nx898 # K1_nx1224 & K1_nx897 # !K1_nx692; K1_timer_5 = DFFEAS(K1_timer_5_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1369, , , , ); --K1_timer_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_4 --operation mode is normal K1_timer_4_lut_out = K1_nx898 # K1_nx1225 & K1_nx897 # !K1_nx692; K1_timer_4 = DFFEAS(K1_timer_4_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1369, , , , ); --K1_nx901 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx901 --operation mode is normal K1_nx901 = K1_timer_3 # K1_timer_2 # K1_timer_1 # K1_timer_0; --H1_nx217 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx217 --operation mode is normal H1_nx217 = !V1_request_37 & V1_request_38; --K1_sm_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|sm_3 --operation mode is normal K1_sm_3_lut_out = K1_sm_6 # K1_modgen_select_223_nx2 # K1_sm_3 & K1_nx900; K1_sm_3 = DFFEAS(K1_sm_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_nx1346 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx1346 --operation mode is normal K1_nx1346 = K1_sm_6 # !K1_nx692; --K1_NOT_nx1355 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx1355 --operation mode is normal K1_NOT_nx1355 = !K1_modgen_select_210_nx2 & K1_nx992 & (K1_b_3 # !K1_sm_2); --K1_nx5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx5 --operation mode is normal K1_nx5 = K1_sm_4 # K1_sm_2; --K1_sm_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|sm_1 --operation mode is normal K1_sm_1_lut_out = K1_send_cfr & !K1_nx692; K1_sm_1 = DFFEAS(K1_sm_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --K1_modgen_select_210_nx2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_select_210_nx2 --operation mode is normal K1_modgen_select_210_nx2 = K1_sm_4 & K1_counter_2 & K1_counter_1 & K1_counter_0; --R1_NOT_nx499 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|NOT_nx499 --operation mode is normal R1_NOT_nx499 = !R1_sm_4 & !R1_ADC_SCLK; --V1_request_19 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_19 --operation mode is normal V1_request_19 = V1_select_rq & (Z2_data_out_19) # !V1_select_rq & Z1_data_out_19; --R1_datasr_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_11 --operation mode is normal R1_datasr_11_lut_out = K1_cfr_11 & (R1_nx94 # R1_datasr_10 & R1_ADC_SCLK) # !K1_cfr_11 & R1_datasr_10 & R1_ADC_SCLK; R1_datasr_11 = DFFEAS(R1_datasr_11_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --Z1_data_out_33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_33 --operation mode is normal Z1_data_out_33_lut_out = Z1_data_out_32; Z1_data_out_33 = DFFEAS(Z1_data_out_33_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_33 --operation mode is normal Z2_data_out_33_lut_out = Z2_data_out_32; Z2_data_out_33 = DFFEAS(Z2_data_out_33_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_34 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_34 --operation mode is normal Z1_data_out_34_lut_out = Z1_data_out_33; Z1_data_out_34 = DFFEAS(Z1_data_out_34_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_34 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_34 --operation mode is normal Z2_data_out_34_lut_out = Z2_data_out_33; Z2_data_out_34 = DFFEAS(Z2_data_out_34_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_37 --operation mode is normal Z1_data_out_37_lut_out = Z1_data_out_36; Z1_data_out_37 = DFFEAS(Z1_data_out_37_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_37 --operation mode is normal Z2_data_out_37_lut_out = Z2_data_out_36; Z2_data_out_37 = DFFEAS(Z2_data_out_37_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_request_35 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_35 --operation mode is normal V1_request_35 = V1_select_rq & (Z2_data_out_35) # !V1_select_rq & Z1_data_out_35; --V1_request_36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_36 --operation mode is normal V1_request_36 = V1_select_rq & (Z2_data_out_36) # !V1_select_rq & Z1_data_out_36; --V1_request_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_valid --operation mode is normal V1_request_valid = V1_nx228 # KB1_data_out_0 & LB1_request_valid & V1_nx230; --T1_ix34_ix34_nx8 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|ix34_ix34_nx8 --operation mode is normal T1_ix34_ix34_nx8 = X1_data_out_0 # !X1_data_out_1; --V1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|next_state_2 --operation mode is normal V1_next_state_2 = KB1_data_out_2 & (V1_nx223) # !KB1_data_out_2 & KB1_data_out_1 & V1_nx222; --V1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|next_state_1 --operation mode is normal V1_next_state_1 = KB1_data_out_0 & !KB1_data_out_2 & (V1_nx226) # !KB1_data_out_0 & (V1_nx224); --J1_samples_9 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_9 --operation mode is normal J1_samples_9_carry_eqn = J1_samples_nx49; J1_samples_9_lut_out = J1_samples_9 $ (J1_samples_9_carry_eqn); J1_samples_9 = DFFEAS(J1_samples_9_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_8 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_8 --operation mode is arithmetic J1_samples_8_carry_eqn = J1_samples_nx45; J1_samples_8_lut_out = J1_samples_8 $ (!J1_samples_8_carry_eqn); J1_samples_8 = DFFEAS(J1_samples_8_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_nx49 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_nx49 --operation mode is arithmetic J1_samples_nx49 = CARRY(J1_samples_8 & (!J1_samples_nx45)); --J1_samples_7 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_7 --operation mode is arithmetic J1_samples_7_carry_eqn = J1_samples_nx41; J1_samples_7_lut_out = J1_samples_7 $ (J1_samples_7_carry_eqn); J1_samples_7 = DFFEAS(J1_samples_7_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_nx45 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_nx45 --operation mode is arithmetic J1_samples_nx45 = CARRY(!J1_samples_nx41 # !J1_samples_7); --J1_samples_6 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_6 --operation mode is arithmetic J1_samples_6_carry_eqn = J1_samples_nx37; J1_samples_6_lut_out = J1_samples_6 $ (!J1_samples_6_carry_eqn); J1_samples_6 = DFFEAS(J1_samples_6_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_nx41 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_nx41 --operation mode is arithmetic J1_samples_nx41 = CARRY(J1_samples_6 & (!J1_samples_nx37)); --J1_samples_5 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_5 --operation mode is arithmetic J1_samples_5_carry_eqn = J1_samples_nx29; J1_samples_5_lut_out = J1_samples_5 $ (J1_samples_5_carry_eqn); J1_samples_5 = DFFEAS(J1_samples_5_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_nx37 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_nx37 --operation mode is arithmetic J1_samples_nx37 = CARRY(!J1_samples_nx29 # !J1_samples_5); --J1_samples_4 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_4 --operation mode is arithmetic J1_samples_4_carry_eqn = J1_samples_nx23; J1_samples_4_lut_out = J1_samples_4 $ (!J1_samples_4_carry_eqn); J1_samples_4 = DFFEAS(J1_samples_4_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_nx29 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_nx29 --operation mode is arithmetic J1_samples_nx29 = CARRY(J1_samples_4 & (!J1_samples_nx23)); --J1_samples_3 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_3 --operation mode is arithmetic J1_samples_3_carry_eqn = J1_samples_nx17; J1_samples_3_lut_out = J1_samples_3 $ (J1_samples_3_carry_eqn); J1_samples_3 = DFFEAS(J1_samples_3_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_nx23 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_nx23 --operation mode is arithmetic J1_samples_nx23 = CARRY(!J1_samples_nx17 # !J1_samples_3); --J1_samples_2 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_2 --operation mode is arithmetic J1_samples_2_carry_eqn = J1_samples_nx11; J1_samples_2_lut_out = J1_samples_2 $ (!J1_samples_2_carry_eqn); J1_samples_2 = DFFEAS(J1_samples_2_lut_out, S1__clk1, VCC, , , , , !J1_sm, ); --J1_samples_nx17 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|samples_nx17 --operation mode is arithmetic J1_samples_nx17 = CARRY(J1_samples_2 & (!J1_samples_nx11)); --H1_bus_ack is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_ack --operation mode is normal H1_bus_ack_regcasc_in = H1_ix0_nx24; H1_bus_ack = DFFEAS(H1_bus_ack_regcasc_in, S1__clk1, VCC, , , , , , ); --T1_req_reg is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|req_reg --operation mode is normal T1_req_reg_lut_out = T1_cfg_req; T1_req_reg = DFFEAS(T1_req_reg_lut_out, S1__clk0, VCC, , , , , , ); --T1_cfg_req is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|cfg_req --operation mode is normal T1_cfg_req_lut_out = X1_data_out_3 # X1_data_out_0 # !X1_data_out_2 & X1_data_out_1; T1_cfg_req = DFFEAS(T1_cfg_req_lut_out, S1__clk0, VCC, , T1_nx1105, , , , ); --Z1_data_out_22 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_22 --operation mode is normal Z1_data_out_22_lut_out = Z1_data_out_21; Z1_data_out_22 = DFFEAS(Z1_data_out_22_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_22 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_22 --operation mode is normal Z2_data_out_22_lut_out = Z2_data_out_21; Z2_data_out_22 = DFFEAS(Z2_data_out_22_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G1_modgen_gt_455_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_455_nx28 --operation mode is arithmetic G1_modgen_gt_455_nx28 = CARRY(G1_a_4 & G1_B_4 & !G1_modgen_gt_455_nx26 # !G1_a_4 & (G1_B_4 # !G1_modgen_gt_455_nx26)); --Z1_data_out_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_14 --operation mode is normal Z1_data_out_14_lut_out = Z1_data_out_13; Z1_data_out_14 = DFFEAS(Z1_data_out_14_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_14 --operation mode is normal Z2_data_out_14_lut_out = Z2_data_out_13; Z2_data_out_14 = DFFEAS(Z2_data_out_14_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G2_modgen_gt_455_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_455_nx28 --operation mode is arithmetic G2_modgen_gt_455_nx28 = CARRY(G2_a_4 & G2_B_4 & !G2_modgen_gt_455_nx26 # !G2_a_4 & (G2_B_4 # !G2_modgen_gt_455_nx26)); --Z1_data_out_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_6 --operation mode is normal Z1_data_out_6_lut_out = Z1_data_out_5; Z1_data_out_6 = DFFEAS(Z1_data_out_6_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_6 --operation mode is normal Z2_data_out_6_lut_out = Z2_data_out_5; Z2_data_out_6 = DFFEAS(Z2_data_out_6_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G3_modgen_gt_455_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_455_nx28 --operation mode is arithmetic G3_modgen_gt_455_nx28 = CARRY(G3_a_4 & G3_B_4 & !G3_modgen_gt_455_nx26 # !G3_a_4 & (G3_B_4 # !G3_modgen_gt_455_nx26)); --W1_d0_to_dll is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|d0_to_dll --operation mode is normal W1_d0_to_dll_lut_out = W1_SAMPLES0_1 & W1_SAMPLES0_0; W1_d0_to_dll = DFFEAS(W1_d0_to_dll_lut_out, S1__clk0, VCC, , W1_nx181, , , , ); --CB1_nx90 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|nx90 --operation mode is normal CB1_nx90 = Y1_s_to_ds # !Y1_buffer_flush_n; --W1_d1_to_dll is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|d1_to_dll --operation mode is normal W1_d1_to_dll_lut_out = W1_SAMPLES1_1 & W1_SAMPLES1_0; W1_d1_to_dll = DFFEAS(W1_d1_to_dll_lut_out, S1__clk0, VCC, , W1_nx183, , , , ); --CB2_nx90 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|nx90 --operation mode is normal CB2_nx90 = Y2_s_to_ds # !Y2_buffer_flush_n; --G4_modgen_gt_455_nx28 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_455_nx28 --operation mode is arithmetic G4_modgen_gt_455_nx28 = CARRY(G4_a_4 & G4_B_4 & !G4_modgen_gt_455_nx26 # !G4_a_4 & (G4_B_4 # !G4_modgen_gt_455_nx26)); --G1_B_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_4 --operation mode is arithmetic G1_B_4_carry_eqn = G1_B_nx25; G1_B_4_lut_out = G1_B_4 $ (!G1_B_4_carry_eqn); G1_B_4 = DFFEAS(G1_B_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_B_nx35 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_nx35 --operation mode is arithmetic G1_B_nx35 = CARRY(!G1_B_nx25 & (G1_B_4 $ G1_NOT_UDn)); --G1_nx573 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx573 --operation mode is normal G1_nx573 = V1_request_27 # V1_request_28 # V1_request_29; --G1_a_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|a_4 --operation mode is normal G1_a_4_lut_out = V1_request_27; G1_a_4 = DFFEAS(G1_a_4_lut_out, S1__clk1, T1_chipRST_n, , G1_nx12, , , G1_NOT_nx14, ); --G1_modgen_gt_453_nx26 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_453_nx26 --operation mode is arithmetic G1_modgen_gt_453_nx26 = CARRY(G1_B_3 & (!G1_modgen_gt_453_nx24 # !G1_a_3) # !G1_B_3 & !G1_a_3 & !G1_modgen_gt_453_nx24); --G2_B_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_4 --operation mode is arithmetic G2_B_4_carry_eqn = G2_B_nx25; G2_B_4_lut_out = G2_B_4 $ (!G2_B_4_carry_eqn); G2_B_4 = DFFEAS(G2_B_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_B_nx35 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_nx35 --operation mode is arithmetic G2_B_nx35 = CARRY(!G2_B_nx25 & (G2_B_4 $ G2_NOT_UDn)); --Z1_data_out_17 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_17 --operation mode is normal Z1_data_out_17_lut_out = Z1_data_out_16; Z1_data_out_17 = DFFEAS(Z1_data_out_17_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_17 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_17 --operation mode is normal Z2_data_out_17_lut_out = Z2_data_out_16; Z2_data_out_17 = DFFEAS(Z2_data_out_17_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_request_18 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_18 --operation mode is normal V1_request_18 = V1_select_rq & (Z2_data_out_18) # !V1_select_rq & Z1_data_out_18; --G2_nx573 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx573 --operation mode is normal G2_nx573 = V1_request_19 # V1_request_20 # V1_request_21; --G2_a_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|a_4 --operation mode is normal G2_a_4_lut_out = V1_request_19; G2_a_4 = DFFEAS(G2_a_4_lut_out, S1__clk1, T1_chipRST_n, , G2_nx12, , , G2_NOT_nx14, ); --G2_modgen_gt_453_nx26 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_453_nx26 --operation mode is arithmetic G2_modgen_gt_453_nx26 = CARRY(G2_B_3 & (!G2_modgen_gt_453_nx24 # !G2_a_3) # !G2_B_3 & !G2_a_3 & !G2_modgen_gt_453_nx24); --G3_B_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_4 --operation mode is arithmetic G3_B_4_carry_eqn = G3_B_nx25; G3_B_4_lut_out = G3_B_4 $ (!G3_B_4_carry_eqn); G3_B_4 = DFFEAS(G3_B_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_B_nx35 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_nx35 --operation mode is arithmetic G3_B_nx35 = CARRY(!G3_B_nx25 & (G3_B_4 $ G3_NOT_UDn)); --Z1_data_out_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_9 --operation mode is normal Z1_data_out_9_lut_out = Z1_data_out_8; Z1_data_out_9 = DFFEAS(Z1_data_out_9_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_9 --operation mode is normal Z2_data_out_9_lut_out = Z2_data_out_8; Z2_data_out_9 = DFFEAS(Z2_data_out_9_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_request_10 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_10 --operation mode is normal V1_request_10 = V1_select_rq & (Z2_data_out_10) # !V1_select_rq & Z1_data_out_10; --G3_nx573 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx573 --operation mode is normal G3_nx573 = V1_request_11 # V1_request_12 # V1_request_13; --G3_a_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|a_4 --operation mode is normal G3_a_4_lut_out = V1_request_11; G3_a_4 = DFFEAS(G3_a_4_lut_out, S1__clk1, T1_chipRST_n, , G3_nx12, , , G3_NOT_nx14, ); --G3_modgen_gt_453_nx26 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_453_nx26 --operation mode is arithmetic G3_modgen_gt_453_nx26 = CARRY(G3_B_3 & (!G3_modgen_gt_453_nx24 # !G3_a_3) # !G3_B_3 & !G3_a_3 & !G3_modgen_gt_453_nx24); --G4_B_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_4 --operation mode is arithmetic G4_B_4_carry_eqn = G4_B_nx25; G4_B_4_lut_out = G4_B_4 $ (!G4_B_4_carry_eqn); G4_B_4 = DFFEAS(G4_B_4_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_B_nx35 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_nx35 --operation mode is arithmetic G4_B_nx35 = CARRY(!G4_B_nx25 & (G4_B_4 $ G4_NOT_UDn)); --Z1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_1 --operation mode is normal Z1_data_out_1_lut_out = Z1_data_out_0; Z1_data_out_1 = DFFEAS(Z1_data_out_1_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_1 --operation mode is normal Z2_data_out_1_lut_out = Z2_data_out_0; Z2_data_out_1 = DFFEAS(Z2_data_out_1_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_request_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_2 --operation mode is normal V1_request_2 = V1_select_rq & (Z2_data_out_2) # !V1_select_rq & Z1_data_out_2; --G4_nx573 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx573 --operation mode is normal G4_nx573 = V1_request_3 # V1_request_4 # V1_request_5; --G4_a_4 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|a_4 --operation mode is normal G4_a_4_lut_out = V1_request_3; G4_a_4 = DFFEAS(G4_a_4_lut_out, S1__clk1, T1_chipRST_n, , G4_nx12, , , G4_NOT_nx14, ); --G4_modgen_gt_453_nx26 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_453_nx26 --operation mode is arithmetic G4_modgen_gt_453_nx26 = CARRY(G4_B_3 & (!G4_modgen_gt_453_nx24 # !G4_a_3) # !G4_B_3 & !G4_a_3 & !G4_modgen_gt_453_nx24); --L1_timer_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_6 --operation mode is normal L1_timer_6_lut_out = L1_nx815 # L1_nx1223 & L1_nx814 # !L1_nx637; L1_timer_6 = DFFEAS(L1_timer_6_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1369, , , , ); --L1_timer_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_5 --operation mode is normal L1_timer_5_lut_out = L1_nx815 # L1_nx1224 & L1_nx814 # !L1_nx637; L1_timer_5 = DFFEAS(L1_timer_5_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1369, , , , ); --L1_timer_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_4 --operation mode is normal L1_timer_4_lut_out = L1_nx815 # L1_nx1225 & L1_nx814 # !L1_nx637; L1_timer_4 = DFFEAS(L1_timer_4_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1369, , , , ); --L1_nx818 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx818 --operation mode is normal L1_nx818 = L1_timer_3 # L1_timer_2 # L1_timer_1 # L1_timer_0; --L1_sm_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|sm_3 --operation mode is normal L1_sm_3_lut_out = L1_sm_6 # L1_modgen_select_223_nx2 # L1_sm_3 & L1_nx817; L1_sm_3 = DFFEAS(L1_sm_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_nx1346 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx1346 --operation mode is normal L1_nx1346 = L1_sm_6 # !L1_nx637; --L1_NOT_nx1355 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx1355 --operation mode is normal L1_NOT_nx1355 = !L1_modgen_select_210_nx2 & L1_nx909 & (L1_b_3 # !L1_sm_2); --L1_nx5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx5 --operation mode is normal L1_nx5 = L1_sm_4 # L1_sm_2; --L1_sm_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|sm_1 --operation mode is normal L1_sm_1_lut_out = L1_send_cfr & !L1_nx637; L1_sm_1 = DFFEAS(L1_sm_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --L1_modgen_select_210_nx2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|modgen_select_210_nx2 --operation mode is normal L1_modgen_select_210_nx2 = L1_sm_4 & L1_counter_2 & L1_counter_1 & L1_counter_0; --R2_NOT_nx499 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|NOT_nx499 --operation mode is normal R2_NOT_nx499 = !R2_sm_4 & !R2_ADC_SCLK; --R2_datasr_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_11 --operation mode is normal R2_datasr_11_lut_out = L1_cfr_11 & (R2_nx94 # R2_datasr_10 & R2_ADC_SCLK) # !L1_cfr_11 & R2_datasr_10 & R2_ADC_SCLK; R2_datasr_11 = DFFEAS(R2_datasr_11_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --GB1_event is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|event --operation mode is normal GB1_event_lut_out = GB1_state_0 & GB1_state_1 & !GB1_nx148 & GB1_nx149; GB1_event = DFFEAS(GB1_event_lut_out, S1__clk0, VCC, , , , , , ); --BB1_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx27 --operation mode is normal BB1_nx27 = AB1_buffer_empty & FB1_data_out_1 & !FB1_data_out_0 & JB1_event_async; --BB1_nx28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx28 --operation mode is normal BB1_nx28 = !FB1_data_out_2 & FB1_data_out_1 & (!JB1_event_async # !AB1_buffer_empty); --JB1_event_async is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|event_async --operation mode is normal JB1_event_async = BB1_timer_enable & !JB1_state_2 & !JB1_state_0 & !JB1_state_1; --BB1_nx29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx29 --operation mode is normal BB1_nx29 = !FB1_data_out_1 & (FB1_data_out_0 & (FB1_data_out_2) # !FB1_data_out_0 & LB1_d_initiate_send); --BB1_nx30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx30 --operation mode is normal BB1_nx30 = !AB1_buffer_empty & !FB1_data_out_2 & FB1_data_out_1 & !FB1_data_out_0; --AB1_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|data_out --operation mode is normal AB1_data_out = AB1_NOT_ob_empty & AB1_ob_data_68 # !AB1_NOT_ob_empty & (AB1_ob_crc_15); --AB1_buffer_empty is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|buffer_empty --operation mode is normal AB1_buffer_empty = AB1_bitcounter_6 & (AB1_bitcounter_5 # !AB1_modgen_gt_555_nx60 & AB1_bitcounter_4); --BB1_nx26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx26 --operation mode is normal BB1_nx26 = !FB1_data_out_2 & !FB1_data_out_1 & FB1_data_out_0; --BB1_stuffing_start_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|stuffing_start_n --operation mode is normal BB1_stuffing_start_n = FB1_data_out_1 # FB1_data_out_2 & FB1_data_out_0; --HB1_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_2 --operation mode is normal HB1_state_2_carry_eqn = HB1_state_nx12; HB1_state_2_lut_out = HB1_state_2 $ (!HB1_state_2_carry_eqn); HB1_state_2 = DFFEAS(HB1_state_2_lut_out, S1__clk0, VCC, , BB1_stuffing_strobe_in, , , HB1_SCLEAR, ); --HB1_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_1 --operation mode is arithmetic HB1_state_1_carry_eqn = HB1_state_nx6; HB1_state_1_lut_out = HB1_state_1 $ (HB1_state_1_carry_eqn); HB1_state_1 = DFFEAS(HB1_state_1_lut_out, S1__clk0, VCC, , BB1_stuffing_strobe_in, , , HB1_SCLEAR, ); --HB1_state_nx12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_nx12 --operation mode is arithmetic HB1_state_nx12 = CARRY(!HB1_state_nx6 # !HB1_state_1); --HB1_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_0 --operation mode is arithmetic HB1_state_0_lut_out = !HB1_state_0; HB1_state_0 = DFFEAS(HB1_state_0_lut_out, S1__clk0, VCC, , BB1_stuffing_strobe_in, , , HB1_SCLEAR, ); --HB1_state_nx6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_nx6 --operation mode is arithmetic HB1_state_nx6 = CARRY(HB1_state_0); --GB2_event is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|event --operation mode is normal GB2_event_lut_out = GB2_state_0 & GB2_state_1 & !GB2_nx148 & GB2_nx149; GB2_event = DFFEAS(GB2_event_lut_out, S1__clk0, VCC, , , , , , ); --BB2_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx27 --operation mode is normal BB2_nx27 = AB2_buffer_empty & FB2_data_out_1 & !FB2_data_out_0 & JB2_event_async; --BB2_nx28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx28 --operation mode is normal BB2_nx28 = !FB2_data_out_2 & FB2_data_out_1 & (!JB2_event_async # !AB2_buffer_empty); --JB2_event_async is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|event_async --operation mode is normal JB2_event_async = BB2_timer_enable & !JB2_state_2 & !JB2_state_0 & !JB2_state_1; --BB2_nx29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx29 --operation mode is normal BB2_nx29 = !FB2_data_out_1 & (FB2_data_out_0 & (FB2_data_out_2) # !FB2_data_out_0 & LB2_d_initiate_send); --BB2_nx30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx30 --operation mode is normal BB2_nx30 = !AB2_buffer_empty & !FB2_data_out_2 & FB2_data_out_1 & !FB2_data_out_0; --AB2_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|data_out --operation mode is normal AB2_data_out = AB2_NOT_ob_empty & AB2_ob_data_68 # !AB2_NOT_ob_empty & (AB2_ob_crc_15); --AB2_buffer_empty is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|buffer_empty --operation mode is normal AB2_buffer_empty = AB2_bitcounter_6 & (AB2_bitcounter_5 # !AB2_modgen_gt_555_nx60 & AB2_bitcounter_4); --BB2_nx26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx26 --operation mode is normal BB2_nx26 = !FB2_data_out_2 & !FB2_data_out_1 & FB2_data_out_0; --BB2_stuffing_start_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|stuffing_start_n --operation mode is normal BB2_stuffing_start_n = FB2_data_out_1 # FB2_data_out_2 & FB2_data_out_0; --HB2_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_2 --operation mode is normal HB2_state_2_carry_eqn = HB2_state_nx12; HB2_state_2_lut_out = HB2_state_2 $ (!HB2_state_2_carry_eqn); HB2_state_2 = DFFEAS(HB2_state_2_lut_out, S1__clk0, VCC, , BB2_stuffing_strobe_in, , , HB2_SCLEAR, ); --HB2_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_1 --operation mode is arithmetic HB2_state_1_carry_eqn = HB2_state_nx6; HB2_state_1_lut_out = HB2_state_1 $ (HB2_state_1_carry_eqn); HB2_state_1 = DFFEAS(HB2_state_1_lut_out, S1__clk0, VCC, , BB2_stuffing_strobe_in, , , HB2_SCLEAR, ); --HB2_state_nx12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_nx12 --operation mode is arithmetic HB2_state_nx12 = CARRY(!HB2_state_nx6 # !HB2_state_1); --HB2_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_0 --operation mode is arithmetic HB2_state_0_lut_out = !HB2_state_0; HB2_state_0 = DFFEAS(HB2_state_0_lut_out, S1__clk0, VCC, , BB2_stuffing_strobe_in, , , HB2_SCLEAR, ); --HB2_state_nx6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_nx6 --operation mode is arithmetic HB2_state_nx6 = CARRY(HB2_state_0); --M1_PQ_12 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_12 --operation mode is normal M1_PQ_12_lut_out = V1_request_19; M1_PQ_12 = DFFEAS(M1_PQ_12_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_11, , , M1_SERREG_1); --K1_NOT_climits_a_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_11 --operation mode is normal K1_NOT_climits_a_11_lut_out = !V1_request_20; K1_NOT_climits_a_11 = DFFEAS(K1_NOT_climits_a_11_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_11 --operation mode is normal K1_adc_last_4_11_lut_out = R1_RDATA_11; K1_adc_last_4_11 = DFFEAS(K1_adc_last_4_11_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx50 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx50 --operation mode is arithmetic K1_modgen_gt_268_nx50 = CARRY(K1_NOT_climits_a_10 & (K1_adc_last_4_10 # !K1_modgen_gt_268_nx48) # !K1_NOT_climits_a_10 & K1_adc_last_4_10 & !K1_modgen_gt_268_nx48); --K1_NOT_climits_d_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_11 --operation mode is normal K1_NOT_climits_d_11_lut_out = !V1_request_20; K1_NOT_climits_d_11 = DFFEAS(K1_NOT_climits_d_11_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_11 --operation mode is normal K1_adc_last_6_11_lut_out = R1_RDATA_11; K1_adc_last_6_11 = DFFEAS(K1_adc_last_6_11_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx50 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx50 --operation mode is arithmetic K1_modgen_gt_270_nx50 = CARRY(K1_NOT_climits_d_10 & (K1_adc_last_6_10 # !K1_modgen_gt_270_nx48) # !K1_NOT_climits_d_10 & K1_adc_last_6_10 & !K1_modgen_gt_270_nx48); --K1_NOT_climits_a_23 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_23 --operation mode is normal K1_NOT_climits_a_23_lut_out = K1_NOT_climits_a_23; K1_NOT_climits_a_23 = DFFEAS(K1_NOT_climits_a_23_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L521, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_11 --operation mode is normal K1_adc_last_5_11_lut_out = R1_RDATA_11; K1_adc_last_5_11 = DFFEAS(K1_adc_last_5_11_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx50 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx50 --operation mode is arithmetic K1_modgen_gt_269_nx50 = CARRY(K1_NOT_climits_a_22 & (K1_adc_last_5_10 # !K1_modgen_gt_269_nx48) # !K1_NOT_climits_a_22 & K1_adc_last_5_10 & !K1_modgen_gt_269_nx48); --K1_NOT_climits_d_23 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_23 --operation mode is normal K1_NOT_climits_d_23_lut_out = K1_NOT_climits_d_23; K1_NOT_climits_d_23 = DFFEAS(K1_NOT_climits_d_23_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L521, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_11 --operation mode is normal K1_adc_last_7_11_lut_out = R1_RDATA_11; K1_adc_last_7_11 = DFFEAS(K1_adc_last_7_11_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx50 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx50 --operation mode is arithmetic K1_modgen_gt_271_nx50 = CARRY(K1_NOT_climits_d_22 & (K1_adc_last_7_10 # !K1_modgen_gt_271_nx48) # !K1_NOT_climits_d_22 & K1_adc_last_7_10 & !K1_modgen_gt_271_nx48); --E1_NOT_rst_start is ni2io_wt:wt_ni|NOT_rst_start --operation mode is normal E1_NOT_rst_start_lut_out = T1_rd_wr_oase # !V1_request_48 # !V1_request_47 # !H1_ce_wtnip4; E1_NOT_rst_start = DFFEAS(E1_NOT_rst_start_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --E1_cnt_rst_6 is ni2io_wt:wt_ni|cnt_rst_6 --operation mode is arithmetic E1_cnt_rst_6_carry_eqn = E1_cnt_rst_nx41; E1_cnt_rst_6_lut_out = E1_cnt_rst_6 $ (!E1_cnt_rst_6_carry_eqn); E1_cnt_rst_6 = DFFEAS(E1_cnt_rst_6_lut_out, S1__clk1, T1_chipRST_n, , , , , !E1_NOT_rst_start, ); --E1_cnt_rst_nx46 is ni2io_wt:wt_ni|cnt_rst_nx46 --operation mode is arithmetic E1_cnt_rst_nx46 = CARRY(E1_cnt_rst_6 & (!E1_cnt_rst_nx41)); --V1_request_23 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_23 --operation mode is normal V1_request_23 = V1_select_rq & (Z2_data_out_23) # !V1_select_rq & Z1_data_out_23; --E1_nx398 is ni2io_wt:wt_ni|nx398 --operation mode is normal E1_nx398 = !V1_request_47 & !V1_request_48; --E1_nx396 is ni2io_wt:wt_ni|nx396 --operation mode is normal E1_nx396 = H1_ce_wtnip4 & !T1_rd_wr_oase; --V1_request_22 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_22 --operation mode is normal V1_request_22 = V1_select_rq & (Z2_data_out_22) # !V1_select_rq & Z1_data_out_22; --F1_nx788 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx788 --operation mode is normal F1_nx788 = F1_sm_top_5 # F1_sm_top_3; --F1_nx790 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx790 --operation mode is normal F1_nx790 = !F1_clkdivs # !F1_sm_sr_5; --F1_b_0_dup_234 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|b_0_dup_234 --operation mode is arithmetic F1_b_0_dup_234_carry_eqn = F1_result_dec_339_nx14; F1_b_0_dup_234 = F1_byte_counter_1 $ (!F1_b_0_dup_234_carry_eqn); --F1_result_dec_339_nx18 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|result_dec_339_nx18 --operation mode is arithmetic F1_result_dec_339_nx18 = CARRY(!F1_byte_counter_1 & (!F1_result_dec_339_nx14)); --F1_sm_top_5 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_top_5 --operation mode is normal F1_sm_top_5_lut_out = F1_sm_top_5 & (F1_nx790 # F1_sm_top_4 & !F1_nx800) # !F1_sm_top_5 & F1_sm_top_4 & (!F1_nx800); F1_sm_top_5 = DFFEAS(F1_sm_top_5_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --F1_sm_top_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|sm_top_3 --operation mode is normal F1_sm_top_3_lut_out = F1_sm_top_3 & (F1_nx790 # F1_sm_top_2 & !F1_nx800) # !F1_sm_top_3 & F1_sm_top_2 & (!F1_nx800); F1_sm_top_3 = DFFEAS(F1_sm_top_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --F1_iword2send_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|iword2send_2 --operation mode is normal F1_iword2send_2_lut_out = F1_iword2send_2; F1_iword2send_2 = DFFEAS(F1_iword2send_2_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_13, , , F1_a_3); --F1_iword2send_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|iword2send_1 --operation mode is normal F1_iword2send_1_lut_out = F1_iword2send_1; F1_iword2send_1 = DFFEAS(F1_iword2send_1_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_14, , , F1_a_3); --F1_iword2send_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|iword2send_0 --operation mode is normal F1_iword2send_0_lut_out = F1_iword2send_0; F1_iword2send_0 = DFFEAS(F1_iword2send_0_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_15, , , F1_a_3); --F1_nx803 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx803 --operation mode is normal F1_nx803 = F1_sm_top_1 & !F1_iword2send_3; --F1_nx850 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx850 --operation mode is normal F1_nx850 = !F1_sm_top_5 & !F1_sm_top_3 & (F1_sm_sr_5 # !F1_sm_top_1); --F1_iword2send_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|iword2send_3 --operation mode is normal F1_iword2send_3_lut_out = F1_iword2send_3; F1_iword2send_3 = DFFEAS(F1_iword2send_3_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_12, , , F1_a_3); --F1_nx789 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx789 --operation mode is normal F1_nx789 = F1_iword2send_0 # !F1_iword2send_1; --T1_nx413 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx413 --operation mode is normal T1_nx413 = !X1_data_out_1 & T1_long_transaction & !T1_nx402 & T1_nx408; --T1_nx439 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx439 --operation mode is normal T1_nx439 = !T1_nx399 & T1_nx404 & (H1_bus_ack # !V1_request_valid); --T1_nx399 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx399 --operation mode is normal T1_nx399 = X1_data_out_2 # X1_data_out_1; --T1_nx400 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx400 --operation mode is normal T1_nx400 = V1_request_50 # !V1_request_52 & !V1_request_51; --T1_nx438 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx438 --operation mode is normal T1_nx438 = V1_request_valid & !X1_data_out_2 & !X1_data_out_1 & !X1_data_out_0; --T1_nx405 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx405 --operation mode is normal T1_nx405 = !V1_request_49 & V1_request_valid & !X1_data_out_3 & !X1_data_out_0; --T1_a_2_dup_231 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|a_2_dup_231 --operation mode is normal T1_a_2_dup_231 = T1_long_transaction & (T1_waitcount_5 # T1_waitcount_4 # T1_nx411); --T1_nx401 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx401 --operation mode is normal T1_nx401 = V1_request_valid & !X1_data_out_3; --T1_ix34_ix32_nx8 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|ix34_ix32_nx8 --operation mode is normal T1_ix34_ix32_nx8 = !X1_data_out_0 # !X1_data_out_1; --T1_nx416 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx416 --operation mode is normal T1_nx416 = V1_request_51 & !V1_request_50 & V1_request_valid & X1_data_out_2; --T1_nx418 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx418 --operation mode is normal T1_nx418 = T1_nx408 # !X1_data_out_1 & !T1_nx400 & T1_nx405; --T1_nx436 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx436 --operation mode is normal T1_nx436 = V1_request_valid & H1_bus_ack & X1_data_out_0 & !T1_nx399; --H1_bus_dout_0 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_0 --operation mode is normal H1_bus_dout_0 = H1_nx212 # L1_RDATA_0 & H1_ce_sc_adc # !H1_nx660; --T1_nx408 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx408 --operation mode is normal T1_nx408 = !X1_data_out_3 & X1_data_out_2 & X1_data_out_0; --T1_nx406 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx406 --operation mode is normal T1_nx406 = V1_request_51 # !V1_request_52 & V1_request_50; --T1_nx432 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx432 --operation mode is normal T1_nx432 = V1_request_52 & !V1_request_50; --T1_nx433 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx433 --operation mode is normal T1_nx433 = V1_request_valid & X1_data_out_3 & X1_data_out_1 & X1_data_out_0; --T1_nx434 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx434 --operation mode is normal T1_nx434 = !X1_data_out_2 & T1_nx405; --T1_nx423 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx423 --operation mode is normal T1_nx423 = !T1_nx399 & T1_nx401 & (X1_data_out_0 # !T1_nx400); --T1_nx428 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx428 --operation mode is normal T1_nx428 = V1_request_valid & !X1_data_out_3 & (V1_request_52 $ V1_request_51); --Y1_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|next_state_3 --operation mode is normal Y1_next_state_3 = !Y1_nx83 & Y1_nx89 & Y1_nx109 & Y1_nx110; --Y1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|next_state_2 --operation mode is normal Y1_next_state_2 = Y1_nx92 # Y1_nx93 # Y1_nx107 # Y1_nx108; --Y1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|next_state_0 --operation mode is normal Y1_next_state_0 = Y1_nx99 # Y1_nx100 # Y1_nx104 # Y1_nx105; --CB1_strobe_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|strobe_out --operation mode is normal CB1_strobe_out_lut_out = Y1_s_to_ds & Y1_buffer_flush_n & CB1_nx10; CB1_strobe_out = DFFEAS(CB1_strobe_out_lut_out, S1__clk0, VCC, , , , , , ); --Z1_bitcounter_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_5 --operation mode is arithmetic Z1_bitcounter_5_carry_eqn = Z1_bitcounter_nx33; Z1_bitcounter_5_lut_out = Z1_bitcounter_5 $ (Z1_bitcounter_5_carry_eqn); Z1_bitcounter_5 = DFFEAS(Z1_bitcounter_5_lut_out, S1__clk0, VCC, , , , , !Y1_buffer_flush_n, ); --Z1_bitcounter_nx37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx37 --operation mode is arithmetic Z1_bitcounter_nx37 = CARRY(!Z1_bitcounter_nx33 # !Z1_bitcounter_5); --Z1_bitcounter_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_3 --operation mode is arithmetic Z1_bitcounter_3_carry_eqn = Z1_bitcounter_nx21; Z1_bitcounter_3_lut_out = Z1_bitcounter_3 $ (Z1_bitcounter_3_carry_eqn); Z1_bitcounter_3 = DFFEAS(Z1_bitcounter_3_lut_out, S1__clk0, VCC, , , , , !Y1_buffer_flush_n, ); --Z1_bitcounter_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx27 --operation mode is arithmetic Z1_bitcounter_nx27 = CARRY(!Z1_bitcounter_nx21 # !Z1_bitcounter_3); --Z1_bitcounter_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_4 --operation mode is arithmetic Z1_bitcounter_4_carry_eqn = Z1_bitcounter_nx27; Z1_bitcounter_4_lut_out = Z1_bitcounter_4 $ (!Z1_bitcounter_4_carry_eqn); Z1_bitcounter_4 = DFFEAS(Z1_bitcounter_4_lut_out, S1__clk0, VCC, , , , , !Y1_buffer_flush_n, ); --Z1_bitcounter_nx33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx33 --operation mode is arithmetic Z1_bitcounter_nx33 = CARRY(Z1_bitcounter_4 & (!Z1_bitcounter_nx27)); --Z1_bitcounter_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_6 --operation mode is normal Z1_bitcounter_6_carry_eqn = Z1_bitcounter_nx37; Z1_bitcounter_6_lut_out = Z1_bitcounter_6 $ (!Z1_bitcounter_6_carry_eqn); Z1_bitcounter_6 = DFFEAS(Z1_bitcounter_6_lut_out, S1__clk0, VCC, , , , , !Y1_buffer_flush_n, ); --Z1_bitcounter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_1 --operation mode is arithmetic Z1_bitcounter_1_carry_eqn = Z1_bitcounter_nx9; Z1_bitcounter_1_lut_out = Z1_bitcounter_1 $ (Z1_bitcounter_1_carry_eqn); Z1_bitcounter_1 = DFFEAS(Z1_bitcounter_1_lut_out, S1__clk0, VCC, , , , , !Y1_buffer_flush_n, ); --Z1_bitcounter_nx15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx15 --operation mode is arithmetic Z1_bitcounter_nx15 = CARRY(!Z1_bitcounter_nx9 # !Z1_bitcounter_1); --Z1_bitcounter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_0 --operation mode is arithmetic Z1_bitcounter_0_lut_out = Z1_bitcounter_0 $ CB1_strobe_out; Z1_bitcounter_0 = DFFEAS(Z1_bitcounter_0_lut_out, S1__clk0, VCC, , , , , !Y1_buffer_flush_n, ); --Z1_bitcounter_nx9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx9 --operation mode is arithmetic Z1_bitcounter_nx9 = CARRY(Z1_bitcounter_0 & CB1_strobe_out); --Z1_bitcounter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_2 --operation mode is arithmetic Z1_bitcounter_2_carry_eqn = Z1_bitcounter_nx15; Z1_bitcounter_2_lut_out = Z1_bitcounter_2 $ (!Z1_bitcounter_2_carry_eqn); Z1_bitcounter_2 = DFFEAS(Z1_bitcounter_2_lut_out, S1__clk0, VCC, , , , , !Y1_buffer_flush_n, ); --Z1_bitcounter_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx21 --operation mode is arithmetic Z1_bitcounter_nx21 = CARRY(Z1_bitcounter_2 & (!Z1_bitcounter_nx15)); --Y2_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|next_state_3 --operation mode is normal Y2_next_state_3 = !Y2_nx83 & Y2_nx89 & Y2_nx109 & Y2_nx110; --Y2_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|next_state_2 --operation mode is normal Y2_next_state_2 = Y2_nx92 # Y2_nx93 # Y2_nx107 # Y2_nx108; --Y2_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|next_state_0 --operation mode is normal Y2_next_state_0 = Y2_nx99 # Y2_nx100 # Y2_nx104 # Y2_nx105; --CB2_strobe_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|strobe_out --operation mode is normal CB2_strobe_out_lut_out = Y2_s_to_ds & Y2_buffer_flush_n & CB2_nx10; CB2_strobe_out = DFFEAS(CB2_strobe_out_lut_out, S1__clk0, VCC, , , , , , ); --Z2_bitcounter_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_5 --operation mode is arithmetic Z2_bitcounter_5_carry_eqn = Z2_bitcounter_nx33; Z2_bitcounter_5_lut_out = Z2_bitcounter_5 $ (Z2_bitcounter_5_carry_eqn); Z2_bitcounter_5 = DFFEAS(Z2_bitcounter_5_lut_out, S1__clk0, VCC, , , , , !Y2_buffer_flush_n, ); --Z2_bitcounter_nx37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx37 --operation mode is arithmetic Z2_bitcounter_nx37 = CARRY(!Z2_bitcounter_nx33 # !Z2_bitcounter_5); --Z2_bitcounter_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_3 --operation mode is arithmetic Z2_bitcounter_3_carry_eqn = Z2_bitcounter_nx21; Z2_bitcounter_3_lut_out = Z2_bitcounter_3 $ (Z2_bitcounter_3_carry_eqn); Z2_bitcounter_3 = DFFEAS(Z2_bitcounter_3_lut_out, S1__clk0, VCC, , , , , !Y2_buffer_flush_n, ); --Z2_bitcounter_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx27 --operation mode is arithmetic Z2_bitcounter_nx27 = CARRY(!Z2_bitcounter_nx21 # !Z2_bitcounter_3); --Z2_bitcounter_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_4 --operation mode is arithmetic Z2_bitcounter_4_carry_eqn = Z2_bitcounter_nx27; Z2_bitcounter_4_lut_out = Z2_bitcounter_4 $ (!Z2_bitcounter_4_carry_eqn); Z2_bitcounter_4 = DFFEAS(Z2_bitcounter_4_lut_out, S1__clk0, VCC, , , , , !Y2_buffer_flush_n, ); --Z2_bitcounter_nx33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx33 --operation mode is arithmetic Z2_bitcounter_nx33 = CARRY(Z2_bitcounter_4 & (!Z2_bitcounter_nx27)); --Z2_bitcounter_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_6 --operation mode is normal Z2_bitcounter_6_carry_eqn = Z2_bitcounter_nx37; Z2_bitcounter_6_lut_out = Z2_bitcounter_6 $ (!Z2_bitcounter_6_carry_eqn); Z2_bitcounter_6 = DFFEAS(Z2_bitcounter_6_lut_out, S1__clk0, VCC, , , , , !Y2_buffer_flush_n, ); --Z2_bitcounter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_1 --operation mode is arithmetic Z2_bitcounter_1_carry_eqn = Z2_bitcounter_nx9; Z2_bitcounter_1_lut_out = Z2_bitcounter_1 $ (Z2_bitcounter_1_carry_eqn); Z2_bitcounter_1 = DFFEAS(Z2_bitcounter_1_lut_out, S1__clk0, VCC, , , , , !Y2_buffer_flush_n, ); --Z2_bitcounter_nx15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx15 --operation mode is arithmetic Z2_bitcounter_nx15 = CARRY(!Z2_bitcounter_nx9 # !Z2_bitcounter_1); --Z2_bitcounter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_0 --operation mode is arithmetic Z2_bitcounter_0_lut_out = Z2_bitcounter_0 $ CB2_strobe_out; Z2_bitcounter_0 = DFFEAS(Z2_bitcounter_0_lut_out, S1__clk0, VCC, , , , , !Y2_buffer_flush_n, ); --Z2_bitcounter_nx9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx9 --operation mode is arithmetic Z2_bitcounter_nx9 = CARRY(Z2_bitcounter_0 & CB2_strobe_out); --Z2_bitcounter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_2 --operation mode is arithmetic Z2_bitcounter_2_carry_eqn = Z2_bitcounter_nx15; Z2_bitcounter_2_lut_out = Z2_bitcounter_2 $ (!Z2_bitcounter_2_carry_eqn); Z2_bitcounter_2 = DFFEAS(Z2_bitcounter_2_lut_out, S1__clk0, VCC, , , , , !Y2_buffer_flush_n, ); --Z2_bitcounter_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx21 --operation mode is arithmetic Z2_bitcounter_nx21 = CARRY(Z2_bitcounter_2 & (!Z2_bitcounter_nx15)); --V1_nx227 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx227 --operation mode is normal V1_nx227 = KB1_data_out_1 & !KB1_data_out_2 & KB1_data_out_0 # !KB1_data_out_1 & LB1_request_valid & (KB1_data_out_0 # !KB1_data_out_2); --LB2_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|next_state_3 --operation mode is normal LB2_next_state_3 = LB2_nx155 # !BB2_freeze_buffer & DB4_data_out_2 & LB2_nx182; --LB2_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|next_state_2 --operation mode is normal LB2_next_state_2 = LB2_nx156 # LB2_nx160 # LB2_nx178 # LB2_nx179; --LB2_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|next_state_1 --operation mode is normal LB2_next_state_1 = LB2_nx157 # LB2_nx145 & (U1_buf1_err # LB2_nx150); --LB2_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|next_state_0 --operation mode is normal LB2_next_state_0 = LB2_nx163 # LB2_nx170 # LB2_nx164 & LB2_nx165; --DB3_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1|data_out_3 --operation mode is normal DB3_data_out_3_lut_out = LB1_next_state_3; DB3_data_out_3 = DFFEAS(DB3_data_out_3_lut_out, S1__clk0, VCC, , , , , , ); --DB3_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1|data_out_2 --operation mode is normal DB3_data_out_2_lut_out = LB1_next_state_2; DB3_data_out_2 = DFFEAS(DB3_data_out_2_lut_out, S1__clk0, VCC, , , , , , ); --DB3_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1|data_out_1 --operation mode is normal DB3_data_out_1_lut_out = LB1_next_state_1; DB3_data_out_1 = DFFEAS(DB3_data_out_1_lut_out, S1__clk0, VCC, , , , , , ); --DB3_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1|data_out_0 --operation mode is normal DB3_data_out_0_lut_out = LB1_next_state_0; DB3_data_out_0 = DFFEAS(DB3_data_out_0_lut_out, S1__clk0, VCC, , , , , , ); --Z1_data_out_44 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_44 --operation mode is normal Z1_data_out_44_lut_out = Z1_data_out_43; Z1_data_out_44 = DFFEAS(Z1_data_out_44_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_44 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_44 --operation mode is normal Z2_data_out_44_lut_out = Z2_data_out_43; Z2_data_out_44 = DFFEAS(Z2_data_out_44_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --F1_nx786 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx786 --operation mode is normal F1_nx786 = !F1_iword2send_7 # !F1_sm_top_1; --F1_b_1_dup_404 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|b_1_dup_404 --operation mode is normal F1_b_1_dup_404_carry_eqn = F1_result_dec_382_nx18; F1_b_1_dup_404 = F1_bit_counter_2 $ (F1_b_1_dup_404_carry_eqn); --F1_b_1_dup_411 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|b_1_dup_411 --operation mode is arithmetic F1_b_1_dup_411_carry_eqn = F1_result_dec_382_nx14; F1_b_1_dup_411 = F1_bit_counter_1 $ (!F1_b_1_dup_411_carry_eqn); --F1_result_dec_382_nx18 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|result_dec_382_nx18 --operation mode is arithmetic F1_result_dec_382_nx18 = CARRY(!F1_bit_counter_1 & (!F1_result_dec_382_nx14)); --F1_b_1_dup_418 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|b_1_dup_418 --operation mode is normal F1_b_1_dup_418 = !F1_bit_counter_0; --F1_bytes2send_30 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_30 --operation mode is normal F1_bytes2send_30_lut_out = F1_bytes2send_30; F1_bytes2send_30 = DFFEAS(F1_bytes2send_30_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_1, , , F1_a_1); --F1_byte_send_5 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_send_5 --operation mode is normal F1_byte_send_5_lut_out = F1_nx761 # F1_nx762 # F1_nx763 # F1_nx764; F1_byte_send_5 = DFFEAS(F1_byte_send_5_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2817, , , , ); --F1_bytes2send_46 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_46 --operation mode is normal F1_bytes2send_46_lut_out = F1_bytes2send_46; F1_bytes2send_46 = DFFEAS(F1_bytes2send_46_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_17, , , F1_a_3); --F1_bytes2send_22 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_22 --operation mode is normal F1_bytes2send_22_lut_out = F1_bytes2send_22; F1_bytes2send_22 = DFFEAS(F1_bytes2send_22_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_9, , , F1_a_1); --F1_bytes2send_38 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_38 --operation mode is normal F1_bytes2send_38_lut_out = V1_request_25; F1_bytes2send_38 = DFFEAS(F1_bytes2send_38_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx479, , , , ); --F1_iword2send_6 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|iword2send_6 --operation mode is normal F1_iword2send_6_lut_out = F1_iword2send_6; F1_iword2send_6 = DFFEAS(F1_iword2send_6_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_9, , , F1_a_3); --F1_bytes2send_14 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_14 --operation mode is normal F1_bytes2send_14_lut_out = F1_bytes2send_14; F1_bytes2send_14 = DFFEAS(F1_bytes2send_14_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_17, , , F1_a_1); --F1_bytes2send_6 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_6 --operation mode is normal F1_bytes2send_6_lut_out = V1_request_25; F1_bytes2send_6 = DFFEAS(F1_bytes2send_6_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx543, , , , ); --K1_nx1223 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx1223 --operation mode is normal K1_nx1223_carry_eqn = K1_timer_dec_202_nx42; K1_nx1223 = K1_timer_6 $ (K1_nx1223_carry_eqn); --K1_nx897 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx897 --operation mode is normal K1_nx897 = K1_sm_2 # K1_sm_5 & !K1_b_3; --K1_nx898 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx898 --operation mode is normal K1_nx898 = K1_b_3 & (K1_sm_2 # K1_sm_5 & K1_ix38_ix21_nx8); --K1_NOT_nx1369 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx1369 --operation mode is normal K1_NOT_nx1369 = K1_nx989 # K1_nx692 & (K1_sm_5 # K1_sm_2); --K1_nx1224 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx1224 --operation mode is arithmetic K1_nx1224_carry_eqn = K1_timer_dec_202_nx38; K1_nx1224 = K1_timer_5 $ (!K1_nx1224_carry_eqn); --K1_timer_dec_202_nx42 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_dec_202_nx42 --operation mode is arithmetic K1_timer_dec_202_nx42 = CARRY(!K1_timer_5 & (!K1_timer_dec_202_nx38)); --K1_nx1225 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx1225 --operation mode is arithmetic K1_nx1225_carry_eqn = K1_timer_dec_202_nx34; K1_nx1225 = K1_timer_4 $ (K1_nx1225_carry_eqn); --K1_timer_dec_202_nx38 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_dec_202_nx38 --operation mode is arithmetic K1_timer_dec_202_nx38 = CARRY(K1_timer_4 # !K1_timer_dec_202_nx34); --K1_timer_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_3 --operation mode is normal K1_timer_3_lut_out = K1_nx898 # K1_nx1226 & K1_nx897 # !K1_nx692; K1_timer_3 = DFFEAS(K1_timer_3_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1369, , , , ); --K1_timer_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_2 --operation mode is normal K1_timer_2_lut_out = K1_nx898 # K1_nx1227 & K1_nx897 # !K1_nx692; K1_timer_2 = DFFEAS(K1_timer_2_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1369, , , , ); --K1_timer_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_1 --operation mode is normal K1_timer_1_lut_out = K1_nx898 # K1_nx1228 & K1_nx897 # !K1_nx692; K1_timer_1 = DFFEAS(K1_timer_1_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1369, , , , ); --K1_timer_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_0 --operation mode is normal K1_timer_0_lut_out = K1_nx898 # K1_nx1229 & K1_nx897 # !K1_nx692; K1_timer_0 = DFFEAS(K1_timer_0_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx1369, , , , ); --K1_nx900 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx900 --operation mode is normal K1_nx900 = K1_ce_adc # !R1_RDY; --K1_nx992 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx992 --operation mode is normal K1_nx992 = K1_nx902 & (K1_nx692 # !K1_send_cfr & K1_start_cyc); --Z1_data_out_19 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_19 --operation mode is normal Z1_data_out_19_lut_out = Z1_data_out_18; Z1_data_out_19 = DFFEAS(Z1_data_out_19_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_19 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_19 --operation mode is normal Z2_data_out_19_lut_out = Z2_data_out_18; Z2_data_out_19 = DFFEAS(Z2_data_out_19_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --K1_cfr_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_11 --operation mode is normal K1_cfr_11_lut_out = V1_request_20; K1_cfr_11 = DFFEAS(K1_cfr_11_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_10 --operation mode is normal R1_datasr_10_lut_out = K1_cfr_10 & (R1_nx94 # R1_datasr_9 & R1_ADC_SCLK) # !K1_cfr_10 & R1_datasr_9 & R1_ADC_SCLK; R1_datasr_10 = DFFEAS(R1_datasr_10_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --R1_nx94 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|nx94 --operation mode is normal R1_nx94 = K1_cmd_adc_1 & !K1_cmd_adc_2 & (!R1_nx60); --Z1_data_out_32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_32 --operation mode is normal Z1_data_out_32_lut_out = Z1_data_out_31; Z1_data_out_32 = DFFEAS(Z1_data_out_32_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_32 --operation mode is normal Z2_data_out_32_lut_out = Z2_data_out_31; Z2_data_out_32 = DFFEAS(Z2_data_out_32_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_36 --operation mode is normal Z1_data_out_36_lut_out = Z1_data_out_35; Z1_data_out_36 = DFFEAS(Z1_data_out_36_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_36 --operation mode is normal Z2_data_out_36_lut_out = Z2_data_out_35; Z2_data_out_36 = DFFEAS(Z2_data_out_36_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_data_out_35 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_35 --operation mode is normal Z1_data_out_35_lut_out = Z1_data_out_34; Z1_data_out_35 = DFFEAS(Z1_data_out_35_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_35 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_35 --operation mode is normal Z2_data_out_35_lut_out = Z2_data_out_34; Z2_data_out_35 = DFFEAS(Z2_data_out_35_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_nx228 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx228 --operation mode is normal V1_nx228 = !KB1_data_out_0 & LB2_request_valid & (KB1_data_out_2 # KB1_data_out_1); --V1_nx230 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx230 --operation mode is normal V1_nx230 = !KB1_data_out_1 # !KB1_data_out_2; --V1_nx222 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx222 --operation mode is normal V1_nx222 = KB1_data_out_0 & !BB1_freeze_buffer & !BB2_freeze_buffer # !KB1_data_out_0 & (T1_bridge_alter); --V1_nx223 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx223 --operation mode is normal V1_nx223 = KB1_data_out_1 & !KB1_data_out_0 & (LB2_request_valid) # !KB1_data_out_1 & (LB1_request_valid # !KB1_data_out_0); --V1_nx224 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx224 --operation mode is normal V1_nx224 = KB1_data_out_1 & LB2_request_valid & (!V1_nx231) # !KB1_data_out_1 & (V1_nx225); --V1_nx226 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx226 --operation mode is normal V1_nx226 = KB1_data_out_1 & (BB1_freeze_buffer # BB2_freeze_buffer) # !KB1_data_out_1 & (T1_bridge_alter); --H1_ix0_nx24 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ix0_nx24 --operation mode is normal H1_ix0_nx24_regcasc_in = H1_ix0_nx22; H1_ix0_nx24 = DFFEAS(H1_ix0_nx24_regcasc_in, S1__clk1, VCC, , , , , , ); --T1_nx1105 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx1105 --operation mode is normal T1_nx1105 = !X1_data_out_3 & (X1_data_out_2 & (!X1_data_out_0) # !X1_data_out_2 & !X1_data_out_1); --Z1_data_out_21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_21 --operation mode is normal Z1_data_out_21_lut_out = Z1_data_out_20; Z1_data_out_21 = DFFEAS(Z1_data_out_21_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_21 --operation mode is normal Z2_data_out_21_lut_out = Z2_data_out_20; Z2_data_out_21 = DFFEAS(Z2_data_out_21_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G1_modgen_gt_455_nx26 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_455_nx26 --operation mode is arithmetic G1_modgen_gt_455_nx26 = CARRY(G1_a_3 & (!G1_modgen_gt_455_nx24 # !G1_B_3) # !G1_a_3 & !G1_B_3 & !G1_modgen_gt_455_nx24); --Z1_data_out_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_13 --operation mode is normal Z1_data_out_13_lut_out = Z1_data_out_12; Z1_data_out_13 = DFFEAS(Z1_data_out_13_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_13 --operation mode is normal Z2_data_out_13_lut_out = Z2_data_out_12; Z2_data_out_13 = DFFEAS(Z2_data_out_13_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G2_modgen_gt_455_nx26 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_455_nx26 --operation mode is arithmetic G2_modgen_gt_455_nx26 = CARRY(G2_a_3 & (!G2_modgen_gt_455_nx24 # !G2_B_3) # !G2_a_3 & !G2_B_3 & !G2_modgen_gt_455_nx24); --Z1_data_out_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_5 --operation mode is normal Z1_data_out_5_lut_out = Z1_data_out_4; Z1_data_out_5 = DFFEAS(Z1_data_out_5_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_5 --operation mode is normal Z2_data_out_5_lut_out = Z2_data_out_4; Z2_data_out_5 = DFFEAS(Z2_data_out_5_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G3_modgen_gt_455_nx26 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_455_nx26 --operation mode is arithmetic G3_modgen_gt_455_nx26 = CARRY(G3_a_3 & (!G3_modgen_gt_455_nx24 # !G3_B_3) # !G3_a_3 & !G3_B_3 & !G3_modgen_gt_455_nx24); --W1_SAMPLES0_1 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|SAMPLES0_1 --operation mode is normal W1_SAMPLES0_1_lut_out = W1_SAMPLES0_0; W1_SAMPLES0_1 = DFFEAS(W1_SAMPLES0_1_lut_out, S1__clk0, VCC, , , , , , ); --W1_SAMPLES0_0 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|SAMPLES0_0 --operation mode is normal W1_SAMPLES0_0_lut_out = SER0_IN; W1_SAMPLES0_0 = DFFEAS(W1_SAMPLES0_0_lut_out, S1__clk0, VCC, , , , , , ); --W1_nx181 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|nx181 --operation mode is normal W1_nx181 = W1_SAMPLES0_1 $ !W1_SAMPLES0_0; --Y1_s_to_ds is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|s_to_ds --operation mode is normal Y1_s_to_ds = !DB1_data_out_1 & (DB1_data_out_3 & !DB1_data_out_2 & !DB1_data_out_0 # !DB1_data_out_3 & DB1_data_out_2 & DB1_data_out_0); --W1_SAMPLES1_1 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|SAMPLES1_1 --operation mode is normal W1_SAMPLES1_1_lut_out = W1_SAMPLES1_0; W1_SAMPLES1_1 = DFFEAS(W1_SAMPLES1_1_lut_out, S1__clk0, VCC, , , , , , ); --W1_SAMPLES1_0 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|SAMPLES1_0 --operation mode is normal W1_SAMPLES1_0_lut_out = SER1_IN; W1_SAMPLES1_0 = DFFEAS(W1_SAMPLES1_0_lut_out, S1__clk0, VCC, , , , , , ); --W1_nx183 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|nx183 --operation mode is normal W1_nx183 = W1_SAMPLES1_1 $ !W1_SAMPLES1_0; --Y2_s_to_ds is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|s_to_ds --operation mode is normal Y2_s_to_ds = !DB2_data_out_1 & (DB2_data_out_3 & !DB2_data_out_2 & !DB2_data_out_0 # !DB2_data_out_3 & DB2_data_out_2 & DB2_data_out_0); --G4_modgen_gt_455_nx26 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_455_nx26 --operation mode is arithmetic G4_modgen_gt_455_nx26 = CARRY(G4_a_3 & (!G4_modgen_gt_455_nx24 # !G4_B_3) # !G4_a_3 & !G4_B_3 & !G4_modgen_gt_455_nx24); --G1_B_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_3 --operation mode is arithmetic G1_B_3_carry_eqn = G1_B_nx19; G1_B_3_lut_out = G1_B_3 $ (G1_B_3_carry_eqn); G1_B_3 = DFFEAS(G1_B_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_B_nx25 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_nx25 --operation mode is arithmetic G1_B_nx25 = CARRY(G1_B_3 $ !G1_NOT_UDn # !G1_B_nx19); --G1_a_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|a_3 --operation mode is normal G1_a_3_lut_out = V1_request_28; G1_a_3 = DFFEAS(G1_a_3_lut_out, S1__clk1, T1_chipRST_n, , G1_nx12, , , G1_NOT_nx14, ); --G1_modgen_gt_453_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_453_nx24 --operation mode is arithmetic G1_modgen_gt_453_nx24 = CARRY(G1_B_2 & G1_a_2 & !G1_modgen_gt_453_nx22 # !G1_B_2 & (G1_a_2 # !G1_modgen_gt_453_nx22)); --G2_B_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_3 --operation mode is arithmetic G2_B_3_carry_eqn = G2_B_nx19; G2_B_3_lut_out = G2_B_3 $ (G2_B_3_carry_eqn); G2_B_3 = DFFEAS(G2_B_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_B_nx25 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_nx25 --operation mode is arithmetic G2_B_nx25 = CARRY(G2_B_3 $ !G2_NOT_UDn # !G2_B_nx19); --Z1_data_out_18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_18 --operation mode is normal Z1_data_out_18_lut_out = Z1_data_out_17; Z1_data_out_18 = DFFEAS(Z1_data_out_18_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_18 --operation mode is normal Z2_data_out_18_lut_out = Z2_data_out_17; Z2_data_out_18 = DFFEAS(Z2_data_out_18_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_request_20 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_20 --operation mode is normal V1_request_20 = V1_select_rq & (Z2_data_out_20) # !V1_select_rq & Z1_data_out_20; --V1_request_21 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_21 --operation mode is normal V1_request_21 = V1_select_rq & (Z2_data_out_21) # !V1_select_rq & Z1_data_out_21; --G2_a_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|a_3 --operation mode is normal G2_a_3_lut_out = V1_request_20; G2_a_3 = DFFEAS(G2_a_3_lut_out, S1__clk1, T1_chipRST_n, , G2_nx12, , , G2_NOT_nx14, ); --G2_modgen_gt_453_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_453_nx24 --operation mode is arithmetic G2_modgen_gt_453_nx24 = CARRY(G2_B_2 & G2_a_2 & !G2_modgen_gt_453_nx22 # !G2_B_2 & (G2_a_2 # !G2_modgen_gt_453_nx22)); --G3_B_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_3 --operation mode is arithmetic G3_B_3_carry_eqn = G3_B_nx19; G3_B_3_lut_out = G3_B_3 $ (G3_B_3_carry_eqn); G3_B_3 = DFFEAS(G3_B_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_B_nx25 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_nx25 --operation mode is arithmetic G3_B_nx25 = CARRY(G3_B_3 $ !G3_NOT_UDn # !G3_B_nx19); --Z1_data_out_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_10 --operation mode is normal Z1_data_out_10_lut_out = Z1_data_out_9; Z1_data_out_10 = DFFEAS(Z1_data_out_10_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_10 --operation mode is normal Z2_data_out_10_lut_out = Z2_data_out_9; Z2_data_out_10 = DFFEAS(Z2_data_out_10_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_request_11 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_11 --operation mode is normal V1_request_11 = V1_select_rq & (Z2_data_out_11) # !V1_select_rq & Z1_data_out_11; --V1_request_12 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_12 --operation mode is normal V1_request_12 = V1_select_rq & (Z2_data_out_12) # !V1_select_rq & Z1_data_out_12; --V1_request_13 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_13 --operation mode is normal V1_request_13 = V1_select_rq & (Z2_data_out_13) # !V1_select_rq & Z1_data_out_13; --G3_a_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|a_3 --operation mode is normal G3_a_3_lut_out = V1_request_12; G3_a_3 = DFFEAS(G3_a_3_lut_out, S1__clk1, T1_chipRST_n, , G3_nx12, , , G3_NOT_nx14, ); --G3_modgen_gt_453_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_453_nx24 --operation mode is arithmetic G3_modgen_gt_453_nx24 = CARRY(G3_B_2 & G3_a_2 & !G3_modgen_gt_453_nx22 # !G3_B_2 & (G3_a_2 # !G3_modgen_gt_453_nx22)); --G4_B_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_3 --operation mode is arithmetic G4_B_3_carry_eqn = G4_B_nx19; G4_B_3_lut_out = G4_B_3 $ (G4_B_3_carry_eqn); G4_B_3 = DFFEAS(G4_B_3_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_B_nx25 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_nx25 --operation mode is arithmetic G4_B_nx25 = CARRY(G4_B_3 $ !G4_NOT_UDn # !G4_B_nx19); --Z1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_2 --operation mode is normal Z1_data_out_2_lut_out = Z1_data_out_1; Z1_data_out_2 = DFFEAS(Z1_data_out_2_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_2 --operation mode is normal Z2_data_out_2_lut_out = Z2_data_out_1; Z2_data_out_2 = DFFEAS(Z2_data_out_2_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --V1_request_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_3 --operation mode is normal V1_request_3 = V1_select_rq & (Z2_data_out_3) # !V1_select_rq & Z1_data_out_3; --V1_request_4 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_4 --operation mode is normal V1_request_4 = V1_select_rq & (Z2_data_out_4) # !V1_select_rq & Z1_data_out_4; --V1_request_5 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_5 --operation mode is normal V1_request_5 = V1_select_rq & (Z2_data_out_5) # !V1_select_rq & Z1_data_out_5; --G4_a_3 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|a_3 --operation mode is normal G4_a_3_lut_out = V1_request_4; G4_a_3 = DFFEAS(G4_a_3_lut_out, S1__clk1, T1_chipRST_n, , G4_nx12, , , G4_NOT_nx14, ); --G4_modgen_gt_453_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_453_nx24 --operation mode is arithmetic G4_modgen_gt_453_nx24 = CARRY(G4_B_2 & G4_a_2 & !G4_modgen_gt_453_nx22 # !G4_B_2 & (G4_a_2 # !G4_modgen_gt_453_nx22)); --L1_nx1223 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx1223 --operation mode is normal L1_nx1223_carry_eqn = L1_timer_dec_202_nx42; L1_nx1223 = L1_timer_6 $ (L1_nx1223_carry_eqn); --L1_nx814 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx814 --operation mode is normal L1_nx814 = L1_sm_2 # L1_sm_5 & !L1_b_3; --L1_nx815 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx815 --operation mode is normal L1_nx815 = L1_b_3 & (L1_sm_2 # L1_sm_5 & L1_ix38_ix21_nx8); --L1_NOT_nx1369 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx1369 --operation mode is normal L1_NOT_nx1369 = L1_nx906 # L1_nx637 & (L1_sm_5 # L1_sm_2); --L1_nx1224 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx1224 --operation mode is arithmetic L1_nx1224_carry_eqn = L1_timer_dec_202_nx38; L1_nx1224 = L1_timer_5 $ (!L1_nx1224_carry_eqn); --L1_timer_dec_202_nx42 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_dec_202_nx42 --operation mode is arithmetic L1_timer_dec_202_nx42 = CARRY(!L1_timer_5 & (!L1_timer_dec_202_nx38)); --L1_nx1225 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx1225 --operation mode is arithmetic L1_nx1225_carry_eqn = L1_timer_dec_202_nx34; L1_nx1225 = L1_timer_4 $ (L1_nx1225_carry_eqn); --L1_timer_dec_202_nx38 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_dec_202_nx38 --operation mode is arithmetic L1_timer_dec_202_nx38 = CARRY(L1_timer_4 # !L1_timer_dec_202_nx34); --L1_timer_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_3 --operation mode is normal L1_timer_3_lut_out = L1_nx815 # L1_nx1226 & L1_nx814 # !L1_nx637; L1_timer_3 = DFFEAS(L1_timer_3_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1369, , , , ); --L1_timer_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_2 --operation mode is normal L1_timer_2_lut_out = L1_nx815 # L1_nx1227 & L1_nx814 # !L1_nx637; L1_timer_2 = DFFEAS(L1_timer_2_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1369, , , , ); --L1_timer_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_1 --operation mode is normal L1_timer_1_lut_out = L1_nx815 # L1_nx1228 & L1_nx814 # !L1_nx637; L1_timer_1 = DFFEAS(L1_timer_1_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1369, , , , ); --L1_timer_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_0 --operation mode is normal L1_timer_0_lut_out = L1_nx815 # L1_nx1229 & L1_nx814 # !L1_nx637; L1_timer_0 = DFFEAS(L1_timer_0_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx1369, , , , ); --L1_nx817 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx817 --operation mode is normal L1_nx817 = L1_ce_adc # !R2_RDY; --L1_nx909 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx909 --operation mode is normal L1_nx909 = L1_nx819 & (L1_nx637 # !L1_send_cfr & L1_start_cyc); --L1_cfr_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_11 --operation mode is normal L1_cfr_11_lut_out = V1_request_20; L1_cfr_11 = DFFEAS(L1_cfr_11_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_10 --operation mode is normal R2_datasr_10_lut_out = L1_cfr_10 & (R2_nx94 # R2_datasr_9 & R2_ADC_SCLK) # !L1_cfr_10 & R2_datasr_9 & R2_ADC_SCLK; R2_datasr_10 = DFFEAS(R2_datasr_10_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --R2_nx94 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|nx94 --operation mode is normal R2_nx94 = L1_cmd_adc_1 & !L1_cmd_adc_2 & (!R2_nx60); --GB1_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_0 --operation mode is normal GB1_state_0_lut_out = GB1_b_0_dup_123 # !BB1_sleep_reset_n; GB1_state_0 = DFFEAS(GB1_state_0_lut_out, S1__clk0, VCC, , , , , , ); --GB1_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_1 --operation mode is normal GB1_state_1_lut_out = GB1_b_0_dup_119 # !BB1_sleep_reset_n; GB1_state_1 = DFFEAS(GB1_state_1_lut_out, S1__clk0, VCC, , , , , , ); --GB1_nx148 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx148 --operation mode is normal GB1_nx148 = !GB1_state_5 # !GB1_state_4 # !GB1_state_3 # !GB1_state_2; --GB1_nx149 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx149 --operation mode is normal GB1_nx149 = BB1_sleep_reset_n; --BB1_timer_enable is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|timer_enable --operation mode is normal BB1_timer_enable = !FB1_data_out_2 & (FB1_data_out_1 # FB1_data_out_0); --JB1_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_2 --operation mode is normal JB1_state_2_lut_out = BB1_timer_enable & BB1_freeze_buffer & JB1_b_1; JB1_state_2 = DFFEAS(JB1_state_2_lut_out, S1__clk0, VCC, , JB1_nx116, , , , ); --JB1_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_0 --operation mode is normal JB1_state_0_lut_out = BB1_timer_enable & BB1_freeze_buffer & JB1_b_0; JB1_state_0 = DFFEAS(JB1_state_0_lut_out, S1__clk0, VCC, , JB1_nx116, , , , ); --JB1_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_1 --operation mode is normal JB1_state_1_lut_out = BB1_timer_enable & BB1_freeze_buffer & JB1_b_1_dup_60; JB1_state_1 = DFFEAS(JB1_state_1_lut_out, S1__clk0, VCC, , JB1_nx116, , , , ); --LB1_d_initiate_send is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_initiate_send --operation mode is normal LB1_d_initiate_send = !DB3_data_out_1 & !DB3_data_out_0 & (DB3_data_out_3 $ DB3_data_out_2); --AB1_ob_data_68 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_68 --operation mode is normal AB1_ob_data_68_lut_out = AB1_ob_data_67; AB1_ob_data_68 = DFFEAS(AB1_ob_data_68_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_68, , , AB1_a_2); --AB1_ob_crc_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_15 --operation mode is normal AB1_ob_crc_15_lut_out = AB1_ob_crc_14 $ (AB1_ob_crc_15 & (AB1_NOT_ob_empty)); AB1_ob_crc_15 = DFFEAS(AB1_ob_crc_15_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_68, , , AB1_a_2); --AB1_NOT_ob_empty is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|NOT_ob_empty --operation mode is normal AB1_NOT_ob_empty = !AB1_bitcounter_5 & AB1_modgen_gt_555_nx60 & !AB1_bitcounter_4 # !AB1_bitcounter_6; --AB1_bitcounter_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_5 --operation mode is arithmetic AB1_bitcounter_5_carry_eqn = AB1_bitcounter_nx33; AB1_bitcounter_5_lut_out = AB1_bitcounter_5 $ (AB1_bitcounter_5_carry_eqn); AB1_bitcounter_5 = DFFEAS(AB1_bitcounter_5_lut_out, S1__clk0, VCC, , , , , !BB1_freeze_buffer, ); --AB1_bitcounter_nx37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx37 --operation mode is arithmetic AB1_bitcounter_nx37 = CARRY(!AB1_bitcounter_nx33 # !AB1_bitcounter_5); --AB1_modgen_gt_555_nx60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|modgen_gt_555_nx60 --operation mode is normal AB1_modgen_gt_555_nx60 = !AB1_bitcounter_3 & (!AB1_bitcounter_1 & !AB1_bitcounter_0 # !AB1_bitcounter_2); --AB1_bitcounter_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_4 --operation mode is arithmetic AB1_bitcounter_4_carry_eqn = AB1_bitcounter_nx27; AB1_bitcounter_4_lut_out = AB1_bitcounter_4 $ (!AB1_bitcounter_4_carry_eqn); AB1_bitcounter_4 = DFFEAS(AB1_bitcounter_4_lut_out, S1__clk0, VCC, , , , , !BB1_freeze_buffer, ); --AB1_bitcounter_nx33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx33 --operation mode is arithmetic AB1_bitcounter_nx33 = CARRY(AB1_bitcounter_4 & (!AB1_bitcounter_nx27)); --AB1_bitcounter_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_6 --operation mode is normal AB1_bitcounter_6_carry_eqn = AB1_bitcounter_nx37; AB1_bitcounter_6_lut_out = AB1_bitcounter_6 $ (!AB1_bitcounter_6_carry_eqn); AB1_bitcounter_6 = DFFEAS(AB1_bitcounter_6_lut_out, S1__clk0, VCC, , , , , !BB1_freeze_buffer, ); --HB1_SCLEAR is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|SCLEAR --operation mode is normal HB1_SCLEAR = HB1_nx63 # BB1_stuffing_data_in $ HB1_data; --GB2_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_0 --operation mode is normal GB2_state_0_lut_out = GB2_b_0_dup_123 # !BB2_sleep_reset_n; GB2_state_0 = DFFEAS(GB2_state_0_lut_out, S1__clk0, VCC, , , , , , ); --GB2_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_1 --operation mode is normal GB2_state_1_lut_out = GB2_b_0_dup_119 # !BB2_sleep_reset_n; GB2_state_1 = DFFEAS(GB2_state_1_lut_out, S1__clk0, VCC, , , , , , ); --GB2_nx148 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx148 --operation mode is normal GB2_nx148 = !GB2_state_5 # !GB2_state_4 # !GB2_state_3 # !GB2_state_2; --GB2_nx149 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx149 --operation mode is normal GB2_nx149 = BB2_sleep_reset_n; --BB2_timer_enable is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|timer_enable --operation mode is normal BB2_timer_enable = !FB2_data_out_2 & (FB2_data_out_1 # FB2_data_out_0); --JB2_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_2 --operation mode is normal JB2_state_2_lut_out = BB2_timer_enable & BB2_freeze_buffer & JB2_b_1; JB2_state_2 = DFFEAS(JB2_state_2_lut_out, S1__clk0, VCC, , JB2_nx116, , , , ); --JB2_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_0 --operation mode is normal JB2_state_0_lut_out = BB2_timer_enable & BB2_freeze_buffer & JB2_b_0; JB2_state_0 = DFFEAS(JB2_state_0_lut_out, S1__clk0, VCC, , JB2_nx116, , , , ); --JB2_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_1 --operation mode is normal JB2_state_1_lut_out = BB2_timer_enable & BB2_freeze_buffer & JB2_b_1_dup_60; JB2_state_1 = DFFEAS(JB2_state_1_lut_out, S1__clk0, VCC, , JB2_nx116, , , , ); --LB2_d_initiate_send is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_initiate_send --operation mode is normal LB2_d_initiate_send = !DB4_data_out_1 & !DB4_data_out_0 & (DB4_data_out_3 $ DB4_data_out_2); --AB2_ob_data_68 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_68 --operation mode is normal AB2_ob_data_68_lut_out = AB2_ob_data_67; AB2_ob_data_68 = DFFEAS(AB2_ob_data_68_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_68, , , AB2_a_2); --AB2_ob_crc_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_15 --operation mode is normal AB2_ob_crc_15_lut_out = AB2_ob_crc_14 $ (AB2_ob_crc_15 & (AB2_NOT_ob_empty)); AB2_ob_crc_15 = DFFEAS(AB2_ob_crc_15_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_68, , , AB2_a_2); --AB2_NOT_ob_empty is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|NOT_ob_empty --operation mode is normal AB2_NOT_ob_empty = !AB2_bitcounter_5 & AB2_modgen_gt_555_nx60 & !AB2_bitcounter_4 # !AB2_bitcounter_6; --AB2_bitcounter_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_5 --operation mode is arithmetic AB2_bitcounter_5_carry_eqn = AB2_bitcounter_nx33; AB2_bitcounter_5_lut_out = AB2_bitcounter_5 $ (AB2_bitcounter_5_carry_eqn); AB2_bitcounter_5 = DFFEAS(AB2_bitcounter_5_lut_out, S1__clk0, VCC, , , , , !BB2_freeze_buffer, ); --AB2_bitcounter_nx37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx37 --operation mode is arithmetic AB2_bitcounter_nx37 = CARRY(!AB2_bitcounter_nx33 # !AB2_bitcounter_5); --AB2_modgen_gt_555_nx60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|modgen_gt_555_nx60 --operation mode is normal AB2_modgen_gt_555_nx60 = !AB2_bitcounter_3 & (!AB2_bitcounter_1 & !AB2_bitcounter_0 # !AB2_bitcounter_2); --AB2_bitcounter_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_4 --operation mode is arithmetic AB2_bitcounter_4_carry_eqn = AB2_bitcounter_nx27; AB2_bitcounter_4_lut_out = AB2_bitcounter_4 $ (!AB2_bitcounter_4_carry_eqn); AB2_bitcounter_4 = DFFEAS(AB2_bitcounter_4_lut_out, S1__clk0, VCC, , , , , !BB2_freeze_buffer, ); --AB2_bitcounter_nx33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx33 --operation mode is arithmetic AB2_bitcounter_nx33 = CARRY(AB2_bitcounter_4 & (!AB2_bitcounter_nx27)); --AB2_bitcounter_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_6 --operation mode is normal AB2_bitcounter_6_carry_eqn = AB2_bitcounter_nx37; AB2_bitcounter_6_lut_out = AB2_bitcounter_6 $ (!AB2_bitcounter_6_carry_eqn); AB2_bitcounter_6 = DFFEAS(AB2_bitcounter_6_lut_out, S1__clk0, VCC, , , , , !BB2_freeze_buffer, ); --HB2_SCLEAR is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|SCLEAR --operation mode is normal HB2_SCLEAR = HB2_nx63 # BB2_stuffing_data_in $ HB2_data; --M1_PQ_11 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_11 --operation mode is normal M1_PQ_11_lut_out = V1_request_20; M1_PQ_11 = DFFEAS(M1_PQ_11_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_10, , , M1_SERREG_1); --K1_NOT_nx510 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx510 --operation mode is normal K1_NOT_nx510 = H1_ce_psply_adc & !T1_rd_wr_oase & !V1_request_48 & !K1_nx993; --R1_RDATA_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_11 --operation mode is normal R1_RDATA_11_lut_out = R1_RDATA_10; R1_RDATA_11 = DFFEAS(R1_RDATA_11_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_NOT_nx2285 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx2285 --operation mode is normal K1_NOT_nx2285 = K1_sm_4 & K1_counter_2 & !K1_counter_1 & !K1_counter_0; --K1_NOT_climits_a_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_10 --operation mode is normal K1_NOT_climits_a_10_lut_out = !V1_request_21; K1_NOT_climits_a_10 = DFFEAS(K1_NOT_climits_a_10_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_10 --operation mode is normal K1_adc_last_4_10_lut_out = R1_RDATA_10; K1_adc_last_4_10 = DFFEAS(K1_adc_last_4_10_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx48 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx48 --operation mode is arithmetic K1_modgen_gt_268_nx48 = CARRY(K1_NOT_climits_a_9 & !K1_adc_last_4_9 & !K1_modgen_gt_268_nx46 # !K1_NOT_climits_a_9 & (!K1_modgen_gt_268_nx46 # !K1_adc_last_4_9)); --K1_NOT_nx462 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx462 --operation mode is normal K1_NOT_nx462 = H1_ce_psply_adc & !T1_rd_wr_oase & V1_request_48 & !K1_nx993; --K1_NOT_nx2333 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx2333 --operation mode is normal K1_NOT_nx2333 = K1_sm_4 & K1_counter_2 & K1_counter_1 & !K1_counter_0; --K1_NOT_climits_d_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_10 --operation mode is normal K1_NOT_climits_d_10_lut_out = !V1_request_21; K1_NOT_climits_d_10 = DFFEAS(K1_NOT_climits_d_10_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_10 --operation mode is normal K1_adc_last_6_10_lut_out = R1_RDATA_10; K1_adc_last_6_10 = DFFEAS(K1_adc_last_6_10_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx48 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx48 --operation mode is arithmetic K1_modgen_gt_270_nx48 = CARRY(K1_NOT_climits_d_9 & !K1_adc_last_6_9 & !K1_modgen_gt_270_nx46 # !K1_NOT_climits_d_9 & (!K1_modgen_gt_270_nx46 # !K1_adc_last_6_9)); --K1_NOT_ix37_ix9_nx8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_ix37_ix9_nx8 --operation mode is normal K1_NOT_ix37_ix9_nx8 = V1_request_46 & V1_request_47 & !V1_request_48; --K1_nx10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx10 --operation mode is normal K1_nx10 = H1_ce_psply_adc & !T1_rd_wr_oase; --K1_NOT_nx2309 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx2309 --operation mode is normal K1_NOT_nx2309 = K1_sm_4 & K1_counter_2 & !K1_counter_1 & K1_counter_0; --K1_NOT_climits_a_22 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_22 --operation mode is normal K1_NOT_climits_a_22_lut_out = K1_NOT_climits_a_22; K1_NOT_climits_a_22 = DFFEAS(K1_NOT_climits_a_22_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L721, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_10 --operation mode is normal K1_adc_last_5_10_lut_out = R1_RDATA_10; K1_adc_last_5_10 = DFFEAS(K1_adc_last_5_10_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx48 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx48 --operation mode is arithmetic K1_modgen_gt_269_nx48 = CARRY(K1_NOT_climits_a_21 & !K1_adc_last_5_9 & !K1_modgen_gt_269_nx46 # !K1_NOT_climits_a_21 & (!K1_modgen_gt_269_nx46 # !K1_adc_last_5_9)); --K1_NOT_ix37_ix7_nx8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_ix37_ix7_nx8 --operation mode is normal K1_NOT_ix37_ix7_nx8 = V1_request_46 & V1_request_47 & V1_request_48; --K1_NOT_climits_d_22 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_22 --operation mode is normal K1_NOT_climits_d_22_lut_out = K1_NOT_climits_d_22; K1_NOT_climits_d_22 = DFFEAS(K1_NOT_climits_d_22_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L721, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_10 --operation mode is normal K1_adc_last_7_10_lut_out = R1_RDATA_10; K1_adc_last_7_10 = DFFEAS(K1_adc_last_7_10_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx48 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx48 --operation mode is arithmetic K1_modgen_gt_271_nx48 = CARRY(K1_NOT_climits_d_21 & !K1_adc_last_7_9 & !K1_modgen_gt_271_nx46 # !K1_NOT_climits_d_21 & (!K1_modgen_gt_271_nx46 # !K1_adc_last_7_9)); --H1_ce_wtnip4 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ce_wtnip4 --operation mode is normal H1_ce_wtnip4_lut_out = !V1_request_33 & V1_request_34 & V1_request_35 & !V1_request_36; H1_ce_wtnip4 = DFFEAS(H1_ce_wtnip4_lut_out, S1__clk1, VCC, , , , , !T1_bus_req, ); --E1_cnt_rst_5 is ni2io_wt:wt_ni|cnt_rst_5 --operation mode is arithmetic E1_cnt_rst_5_carry_eqn = E1_cnt_rst_nx34; E1_cnt_rst_5_lut_out = E1_cnt_rst_5 $ (E1_cnt_rst_5_carry_eqn); E1_cnt_rst_5 = DFFEAS(E1_cnt_rst_5_lut_out, S1__clk1, T1_chipRST_n, , , , , !E1_NOT_rst_start, ); --E1_cnt_rst_nx41 is ni2io_wt:wt_ni|cnt_rst_nx41 --operation mode is arithmetic E1_cnt_rst_nx41 = CARRY(!E1_cnt_rst_nx34 # !E1_cnt_rst_5); --F1_result_dec_339_nx14 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|result_dec_339_nx14 --operation mode is arithmetic F1_result_dec_339_nx14 = CARRY(F1_byte_counter_0); --V1_request_14 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_14 --operation mode is normal V1_request_14 = V1_select_rq & (Z2_data_out_14) # !V1_select_rq & Z1_data_out_14; --T1_long_transaction is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|long_transaction --operation mode is normal T1_long_transaction_lut_out = V1_request_31; T1_long_transaction = DFFEAS(T1_long_transaction_lut_out, S1__clk0, VCC, , T1_nx241, , , , ); --T1_nx402 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx402 --operation mode is normal T1_nx402 = T1_waitcount_5 # T1_waitcount_4 # T1_nx411; --T1_nx404 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx404 --operation mode is normal T1_nx404 = !X1_data_out_3 & X1_data_out_0; --T1_waitcount_5 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_5 --operation mode is normal T1_waitcount_5_carry_eqn = T1_waitcount_nx37; T1_waitcount_5_lut_out = T1_waitcount_5 $ (!T1_waitcount_5_carry_eqn); T1_waitcount_5 = DFFEAS(T1_waitcount_5_lut_out, S1__clk0, VCC, , , ~GND, , , T1_nx383); --T1_waitcount_4 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_4 --operation mode is arithmetic T1_waitcount_4_carry_eqn = T1_waitcount_nx33; T1_waitcount_4_lut_out = T1_waitcount_4 $ (T1_waitcount_4_carry_eqn); T1_waitcount_4 = DFFEAS(T1_waitcount_4_lut_out, S1__clk0, VCC, , , ~GND, , , T1_nx383); --T1_waitcount_nx37 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx37 --operation mode is arithmetic T1_waitcount_nx37 = CARRY(T1_waitcount_4 # !T1_waitcount_nx33); --T1_nx411 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx411 --operation mode is normal T1_nx411 = T1_waitcount_3 # T1_waitcount_2 # T1_waitcount_1 # T1_waitcount_0; --H1_nx212 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx212 --operation mode is normal H1_nx212 = K1_RDATA_0 & (H1_ce_psply_adc # J1_RDATA_0 & H1_ce_pasa_adc) # !K1_RDATA_0 & J1_RDATA_0 & (H1_ce_pasa_adc); --L1_RDATA_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_0 --operation mode is normal L1_RDATA_0 = L1_nx901 # L1_nx902 # L1_nx903 # L1_nx904; --H1_nx660 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx660 --operation mode is normal H1_nx660 = E1_rdata_0 & !H1_sel_0 & (!H1_ce_dds # !F1_RDATA_0) # !E1_rdata_0 & (!H1_ce_dds # !F1_RDATA_0); --Y1_nx83 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx83 --operation mode is normal Y1_nx83 = Y1_sync_counter_0 # W1_d0_to_dll $ !Y1_d_buff; --Y1_nx89 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx89 --operation mode is normal Y1_nx89 = !DB1_data_out_3 & DB1_data_out_1 & !EB1_event_async; --Y1_nx109 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx109 --operation mode is normal Y1_nx109 = !DB1_data_out_2 & DB1_data_out_0; --Y1_nx110 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx110 --operation mode is normal Y1_nx110 = !Z1_buffer_full & !CB1_stuff_err & !Y1_sync_counter_2 & !Y1_sync_counter_1; --Y1_nx92 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx92 --operation mode is normal Y1_nx92 = DB1_data_out_0 & !Y1_nx81 & !Y1_nx83 & Y1_nx85; --Y1_nx93 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx93 --operation mode is normal Y1_nx93 = EB1_event_async & Y1_nx84 & (!DB1_data_out_0 # !DB1_data_out_2); --Y1_nx107 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx107 --operation mode is normal Y1_nx107 = Z1_buffer_full & (Y1_nx85 # !Y1_time_in_twofwd_n) # !Z1_buffer_full & CB1_stuff_err & (Y1_nx85 # !Y1_time_in_twofwd_n); --Y1_nx108 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx108 --operation mode is normal Y1_nx108 = Y1_nx91 # DB1_data_out_0 & Y1_nx80 & Y1_nx89; --Y1_nx99 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx99 --operation mode is normal Y1_nx99 = DB1_data_out_1 & (Y1_nx90 # EB1_event_async & Y1_nx88); --Y1_nx100 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx100 --operation mode is normal Y1_nx100 = !Y1_nx80 & Y1_nx86 & (Y1_nx81 # Y1_nx83); --Y1_nx104 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx104 --operation mode is normal Y1_nx104 = DB1_data_out_3 & (DB1_data_out_2 # DB1_data_out_0) # !DB1_data_out_3 & !DB1_data_out_2 & !DB1_data_out_1 & !DB1_data_out_0; --Y1_nx105 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx105 --operation mode is normal Y1_nx105 = Y1_nx98 # !DB1_data_out_1 & !DB1_data_out_0 & !Y1_nx80; --CB1_nx10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|nx10 --operation mode is normal CB1_nx10 = !CB1_counter_0 # !CB1_counter_1 # !CB1_counter_2; --Y2_nx83 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx83 --operation mode is normal Y2_nx83 = Y2_sync_counter_0 # W1_d1_to_dll $ !Y2_d_buff; --Y2_nx89 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx89 --operation mode is normal Y2_nx89 = !DB2_data_out_3 & DB2_data_out_1 & !EB2_event_async; --Y2_nx109 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx109 --operation mode is normal Y2_nx109 = !DB2_data_out_2 & DB2_data_out_0; --Y2_nx110 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx110 --operation mode is normal Y2_nx110 = !Z2_buffer_full & !CB2_stuff_err & !Y2_sync_counter_2 & !Y2_sync_counter_1; --Y2_nx92 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx92 --operation mode is normal Y2_nx92 = DB2_data_out_0 & !Y2_nx81 & !Y2_nx83 & Y2_nx85; --Y2_nx93 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx93 --operation mode is normal Y2_nx93 = EB2_event_async & Y2_nx84 & (!DB2_data_out_0 # !DB2_data_out_2); --Y2_nx107 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx107 --operation mode is normal Y2_nx107 = Z2_buffer_full & (Y2_nx85 # !Y2_time_in_twofwd_n) # !Z2_buffer_full & CB2_stuff_err & (Y2_nx85 # !Y2_time_in_twofwd_n); --Y2_nx108 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx108 --operation mode is normal Y2_nx108 = Y2_nx91 # DB2_data_out_0 & Y2_nx80 & Y2_nx89; --Y2_nx99 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx99 --operation mode is normal Y2_nx99 = DB2_data_out_1 & (Y2_nx90 # EB2_event_async & Y2_nx88); --Y2_nx100 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx100 --operation mode is normal Y2_nx100 = !Y2_nx80 & Y2_nx86 & (Y2_nx81 # Y2_nx83); --Y2_nx104 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx104 --operation mode is normal Y2_nx104 = DB2_data_out_3 & (DB2_data_out_2 # DB2_data_out_0) # !DB2_data_out_3 & !DB2_data_out_2 & !DB2_data_out_1 & !DB2_data_out_0; --Y2_nx105 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx105 --operation mode is normal Y2_nx105 = Y2_nx98 # !DB2_data_out_1 & !DB2_data_out_0 & !Y2_nx80; --CB2_nx10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|nx10 --operation mode is normal CB2_nx10 = !CB2_counter_0 # !CB2_counter_1 # !CB2_counter_2; --BB2_freeze_buffer is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|freeze_buffer --operation mode is normal BB2_freeze_buffer = FB2_data_out_1 # FB2_data_out_0; --LB2_nx155 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx155 --operation mode is normal LB2_nx155 = !DB4_data_out_2 & LB2_nx153 & (BB2_freeze_buffer # !DB4_data_out_0); --LB2_nx182 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx182 --operation mode is normal LB2_nx182 = !DB4_data_out_3 & DB4_data_out_1 & DB4_data_out_0; --LB2_nx156 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx156 --operation mode is normal LB2_nx156 = U1_buf1_err & !DB4_data_out_2 & DB4_data_out_0 & LB2_nx144; --LB2_nx160 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx160 --operation mode is normal LB2_nx160 = !Z2_data_valid & Z2_buffer_half & DB4_data_out_2 & LB2_nx144; --LB2_nx178 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx178 --operation mode is normal LB2_nx178 = !DB4_data_out_3 & DB4_data_out_1 & (LB2_nx180 # LB2_nx181); --LB2_nx179 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx179 --operation mode is normal LB2_nx179 = !DB4_data_out_3 & DB4_data_out_2 & (BB2_freeze_buffer # !DB4_data_out_0); --U1_buf1_err is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|buf1_err --operation mode is normal U1_buf1_err = Z2_buffer_full & !Z2_data_valid; --LB2_nx145 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx145 --operation mode is normal LB2_nx145 = !DB4_data_out_3 & !DB4_data_out_2 & !DB4_data_out_1 & DB4_data_out_0; --LB2_nx150 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx150 --operation mode is normal LB2_nx150 = LB2_forward_buffer_60 # LB2_forward_buffer_59; --LB2_nx157 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx157 --operation mode is normal LB2_nx157 = LB2_nx158 # LB2_nx159 # LB2_nx160 # LB2_nx161; --LB2_nx163 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx163 --operation mode is normal LB2_nx163 = LB2_nx172 # LB2_nx144 & LB2_nx146 & LB2_nx173; --LB2_nx164 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx164 --operation mode is normal LB2_nx164 = LB2_nx175 # LB2_nx147 & (LB2_nx168 # LB2_nx169); --LB2_nx165 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx165 --operation mode is normal LB2_nx165 = LB2_forward_buffer_58 # LB2_forward_buffer_57 # LB2_nx150 # LB2_nx171; --LB2_nx170 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx170 --operation mode is normal LB2_nx170 = BB2_freeze_buffer & (DB4_data_out_2 & (LB2_nx154) # !DB4_data_out_2 & LB2_nx153); --LB1_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|next_state_3 --operation mode is normal LB1_next_state_3 = LB1_nx155 # !BB1_freeze_buffer & DB3_data_out_2 & LB1_nx182; --LB1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|next_state_2 --operation mode is normal LB1_next_state_2 = LB1_nx156 # LB1_nx160 # LB1_nx178 # LB1_nx179; --LB1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|next_state_1 --operation mode is normal LB1_next_state_1 = LB1_nx157 # LB1_nx145 & (U1_buf0_err # LB1_nx150); --LB1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|next_state_0 --operation mode is normal LB1_next_state_0 = LB1_nx163 # LB1_nx170 # LB1_nx164 & LB1_nx165; --Z1_data_out_43 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_43 --operation mode is normal Z1_data_out_43_lut_out = Z1_data_out_42; Z1_data_out_43 = DFFEAS(Z1_data_out_43_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_43 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_43 --operation mode is normal Z2_data_out_43_lut_out = Z2_data_out_42; Z2_data_out_43 = DFFEAS(Z2_data_out_43_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --F1_result_dec_382_nx14 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|result_dec_382_nx14 --operation mode is arithmetic F1_result_dec_382_nx14 = CARRY(F1_bit_counter_0); --F1_nx761 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx761 --operation mode is normal F1_nx761 = F1_sm_sr_4 & (F1_byte_send_4 # F1_bytes2send_29 & F1_nx798) # !F1_sm_sr_4 & F1_bytes2send_29 & (F1_nx798); --F1_nx762 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx762 --operation mode is normal F1_nx762 = F1_bytes2send_45 & (F1_nx794 # F1_bytes2send_21 & F1_nx799) # !F1_bytes2send_45 & F1_bytes2send_21 & (F1_nx799); --F1_nx763 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx763 --operation mode is normal F1_nx763 = F1_bytes2send_37 & (F1_nx796 # F1_iword2send_5 & F1_nx793) # !F1_bytes2send_37 & F1_iword2send_5 & F1_nx793; --F1_nx764 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx764 --operation mode is normal F1_nx764 = F1_bytes2send_13 & (F1_nx795 # F1_bytes2send_5 & F1_nx797) # !F1_bytes2send_13 & F1_bytes2send_5 & (F1_nx797); --K1_nx989 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx989 --operation mode is normal K1_nx989 = !K1_send_cfr & K1_start_cyc & !K1_nx692; --K1_nx1226 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx1226 --operation mode is arithmetic K1_nx1226_carry_eqn = K1_timer_dec_202_nx30; K1_nx1226 = K1_timer_3 $ (!K1_nx1226_carry_eqn); --K1_timer_dec_202_nx34 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_dec_202_nx34 --operation mode is arithmetic K1_timer_dec_202_nx34 = CARRY(!K1_timer_3 & (!K1_timer_dec_202_nx30)); --K1_nx1227 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx1227 --operation mode is arithmetic K1_nx1227_carry_eqn = K1_timer_dec_202_nx26; K1_nx1227 = K1_timer_2 $ (K1_nx1227_carry_eqn); --K1_timer_dec_202_nx30 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_dec_202_nx30 --operation mode is arithmetic K1_timer_dec_202_nx30 = CARRY(K1_timer_2 # !K1_timer_dec_202_nx26); --K1_nx1228 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx1228 --operation mode is arithmetic K1_nx1228_carry_eqn = K1_timer_dec_202_nx22; K1_nx1228 = K1_timer_1 $ (!K1_nx1228_carry_eqn); --K1_timer_dec_202_nx26 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_dec_202_nx26 --operation mode is arithmetic K1_timer_dec_202_nx26 = CARRY(!K1_timer_1 & (!K1_timer_dec_202_nx22)); --K1_nx1229 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx1229 --operation mode is normal K1_nx1229 = !K1_timer_0; --K1_nx902 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx902 --operation mode is normal K1_nx902 = !K1_sm_7 & !K1_sm_5 & !K1_sm_3 & !K1_sm_1; --K1_cfr_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_10 --operation mode is normal K1_cfr_10_lut_out = V1_request_21; K1_cfr_10 = DFFEAS(K1_cfr_10_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_9 --operation mode is normal R1_datasr_9_lut_out = K1_cfr_9 & (R1_nx94 # R1_datasr_8 & R1_ADC_SCLK) # !K1_cfr_9 & R1_datasr_8 & R1_ADC_SCLK; R1_datasr_9 = DFFEAS(R1_datasr_9_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --BB1_freeze_buffer is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|freeze_buffer --operation mode is normal BB1_freeze_buffer = FB1_data_out_1 # FB1_data_out_0; --V1_nx225 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx225 --operation mode is normal V1_nx225 = KB1_data_out_2 & (V1_nx232) # !KB1_data_out_2 & !LB1_request_valid & LB2_request_valid; --V1_nx231 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx231 --operation mode is normal V1_nx231 = T1_bridge_alter & !KB1_data_out_2; --H1_ix0_nx22 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ix0_nx22 --operation mode is normal H1_ix0_nx22_regcasc_in = H1_ix0_nx20; H1_ix0_nx22 = DFFEAS(H1_ix0_nx22_regcasc_in, S1__clk1, VCC, , , , , , ); --Z1_data_out_20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_20 --operation mode is normal Z1_data_out_20_lut_out = Z1_data_out_19; Z1_data_out_20 = DFFEAS(Z1_data_out_20_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_20 --operation mode is normal Z2_data_out_20_lut_out = Z2_data_out_19; Z2_data_out_20 = DFFEAS(Z2_data_out_20_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G1_modgen_gt_455_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_455_nx24 --operation mode is arithmetic G1_modgen_gt_455_nx24 = CARRY(G1_a_2 & G1_B_2 & !G1_modgen_gt_455_nx22 # !G1_a_2 & (G1_B_2 # !G1_modgen_gt_455_nx22)); --Z1_data_out_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_12 --operation mode is normal Z1_data_out_12_lut_out = Z1_data_out_11; Z1_data_out_12 = DFFEAS(Z1_data_out_12_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_12 --operation mode is normal Z2_data_out_12_lut_out = Z2_data_out_11; Z2_data_out_12 = DFFEAS(Z2_data_out_12_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G2_modgen_gt_455_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_455_nx24 --operation mode is arithmetic G2_modgen_gt_455_nx24 = CARRY(G2_a_2 & G2_B_2 & !G2_modgen_gt_455_nx22 # !G2_a_2 & (G2_B_2 # !G2_modgen_gt_455_nx22)); --Z1_data_out_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_4 --operation mode is normal Z1_data_out_4_lut_out = Z1_data_out_3; Z1_data_out_4 = DFFEAS(Z1_data_out_4_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_4 --operation mode is normal Z2_data_out_4_lut_out = Z2_data_out_3; Z2_data_out_4 = DFFEAS(Z2_data_out_4_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G3_modgen_gt_455_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_455_nx24 --operation mode is arithmetic G3_modgen_gt_455_nx24 = CARRY(G3_a_2 & G3_B_2 & !G3_modgen_gt_455_nx22 # !G3_a_2 & (G3_B_2 # !G3_modgen_gt_455_nx22)); --DB1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1|data_out_1 --operation mode is normal DB1_data_out_1_lut_out = Y1_next_state_1; DB1_data_out_1 = DFFEAS(DB1_data_out_1_lut_out, S1__clk0, VCC, , , , , , ); --DB2_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1|data_out_1 --operation mode is normal DB2_data_out_1_lut_out = Y2_next_state_1; DB2_data_out_1 = DFFEAS(DB2_data_out_1_lut_out, S1__clk0, VCC, , , , , , ); --G4_modgen_gt_455_nx24 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_455_nx24 --operation mode is arithmetic G4_modgen_gt_455_nx24 = CARRY(G4_a_2 & G4_B_2 & !G4_modgen_gt_455_nx22 # !G4_a_2 & (G4_B_2 # !G4_modgen_gt_455_nx22)); --G1_B_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_2 --operation mode is arithmetic G1_B_2_carry_eqn = G1_B_nx13; G1_B_2_lut_out = G1_B_2 $ (!G1_B_2_carry_eqn); G1_B_2 = DFFEAS(G1_B_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_B_nx19 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_nx19 --operation mode is arithmetic G1_B_nx19 = CARRY(!G1_B_nx13 & (G1_B_2 $ G1_NOT_UDn)); --G1_a_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|a_2 --operation mode is normal G1_a_2_lut_out = V1_request_29; G1_a_2 = DFFEAS(G1_a_2_lut_out, S1__clk1, T1_chipRST_n, , G1_nx12, , , G1_NOT_nx14, ); --G1_modgen_gt_453_nx22 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_453_nx22 --operation mode is arithmetic G1_modgen_gt_453_nx22 = CARRY(G1_B_1 & (G1_nx584 # !G1_modgen_gt_453_nx20) # !G1_B_1 & G1_nx584 & !G1_modgen_gt_453_nx20); --G2_B_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_2 --operation mode is arithmetic G2_B_2_carry_eqn = G2_B_nx13; G2_B_2_lut_out = G2_B_2 $ (!G2_B_2_carry_eqn); G2_B_2 = DFFEAS(G2_B_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_B_nx19 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_nx19 --operation mode is arithmetic G2_B_nx19 = CARRY(!G2_B_nx13 & (G2_B_2 $ G2_NOT_UDn)); --G2_a_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|a_2 --operation mode is normal G2_a_2_lut_out = V1_request_21; G2_a_2 = DFFEAS(G2_a_2_lut_out, S1__clk1, T1_chipRST_n, , G2_nx12, , , G2_NOT_nx14, ); --G2_modgen_gt_453_nx22 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_453_nx22 --operation mode is arithmetic G2_modgen_gt_453_nx22 = CARRY(G2_B_1 & (G2_nx584 # !G2_modgen_gt_453_nx20) # !G2_B_1 & G2_nx584 & !G2_modgen_gt_453_nx20); --G3_B_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_2 --operation mode is arithmetic G3_B_2_carry_eqn = G3_B_nx13; G3_B_2_lut_out = G3_B_2 $ (!G3_B_2_carry_eqn); G3_B_2 = DFFEAS(G3_B_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_B_nx19 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_nx19 --operation mode is arithmetic G3_B_nx19 = CARRY(!G3_B_nx13 & (G3_B_2 $ G3_NOT_UDn)); --Z1_data_out_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_11 --operation mode is normal Z1_data_out_11_lut_out = Z1_data_out_10; Z1_data_out_11 = DFFEAS(Z1_data_out_11_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_11 --operation mode is normal Z2_data_out_11_lut_out = Z2_data_out_10; Z2_data_out_11 = DFFEAS(Z2_data_out_11_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G3_a_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|a_2 --operation mode is normal G3_a_2_lut_out = V1_request_13; G3_a_2 = DFFEAS(G3_a_2_lut_out, S1__clk1, T1_chipRST_n, , G3_nx12, , , G3_NOT_nx14, ); --G3_modgen_gt_453_nx22 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_453_nx22 --operation mode is arithmetic G3_modgen_gt_453_nx22 = CARRY(G3_B_1 & (G3_nx584 # !G3_modgen_gt_453_nx20) # !G3_B_1 & G3_nx584 & !G3_modgen_gt_453_nx20); --G4_B_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_2 --operation mode is arithmetic G4_B_2_carry_eqn = G4_B_nx13; G4_B_2_lut_out = G4_B_2 $ (!G4_B_2_carry_eqn); G4_B_2 = DFFEAS(G4_B_2_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_B_nx19 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_nx19 --operation mode is arithmetic G4_B_nx19 = CARRY(!G4_B_nx13 & (G4_B_2 $ G4_NOT_UDn)); --Z1_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_3 --operation mode is normal Z1_data_out_3_lut_out = Z1_data_out_2; Z1_data_out_3 = DFFEAS(Z1_data_out_3_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z2_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_3 --operation mode is normal Z2_data_out_3_lut_out = Z2_data_out_2; Z2_data_out_3 = DFFEAS(Z2_data_out_3_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --G4_a_2 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|a_2 --operation mode is normal G4_a_2_lut_out = V1_request_5; G4_a_2 = DFFEAS(G4_a_2_lut_out, S1__clk1, T1_chipRST_n, , G4_nx12, , , G4_NOT_nx14, ); --G4_modgen_gt_453_nx22 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_453_nx22 --operation mode is arithmetic G4_modgen_gt_453_nx22 = CARRY(G4_B_1 & (G4_nx584 # !G4_modgen_gt_453_nx20) # !G4_B_1 & G4_nx584 & !G4_modgen_gt_453_nx20); --L1_nx906 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx906 --operation mode is normal L1_nx906 = !L1_send_cfr & L1_start_cyc & !L1_nx637; --L1_nx1226 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx1226 --operation mode is arithmetic L1_nx1226_carry_eqn = L1_timer_dec_202_nx30; L1_nx1226 = L1_timer_3 $ (!L1_nx1226_carry_eqn); --L1_timer_dec_202_nx34 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_dec_202_nx34 --operation mode is arithmetic L1_timer_dec_202_nx34 = CARRY(!L1_timer_3 & (!L1_timer_dec_202_nx30)); --L1_nx1227 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx1227 --operation mode is arithmetic L1_nx1227_carry_eqn = L1_timer_dec_202_nx26; L1_nx1227 = L1_timer_2 $ (L1_nx1227_carry_eqn); --L1_timer_dec_202_nx30 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_dec_202_nx30 --operation mode is arithmetic L1_timer_dec_202_nx30 = CARRY(L1_timer_2 # !L1_timer_dec_202_nx26); --L1_nx1228 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx1228 --operation mode is arithmetic L1_nx1228_carry_eqn = L1_timer_dec_202_nx22; L1_nx1228 = L1_timer_1 $ (!L1_nx1228_carry_eqn); --L1_timer_dec_202_nx26 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_dec_202_nx26 --operation mode is arithmetic L1_timer_dec_202_nx26 = CARRY(!L1_timer_1 & (!L1_timer_dec_202_nx22)); --L1_nx1229 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx1229 --operation mode is normal L1_nx1229 = !L1_timer_0; --L1_nx819 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx819 --operation mode is normal L1_nx819 = !L1_sm_7 & !L1_sm_5 & !L1_sm_3 & !L1_sm_1; --L1_cfr_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_10 --operation mode is normal L1_cfr_10_lut_out = V1_request_21; L1_cfr_10 = DFFEAS(L1_cfr_10_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_9 --operation mode is normal R2_datasr_9_lut_out = L1_cfr_9 & (R2_nx94 # R2_datasr_8 & R2_ADC_SCLK) # !L1_cfr_9 & R2_datasr_8 & R2_ADC_SCLK; R2_datasr_9 = DFFEAS(R2_datasr_9_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --BB1_sleep_reset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|sleep_reset_n --operation mode is normal BB1_sleep_reset_n = FB1_data_out_2 & !FB1_data_out_1; --GB1_b_0_dup_123 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_123 --operation mode is normal GB1_b_0_dup_123 = !GB1_state_0 & GB1_nx21; --GB1_b_0_dup_119 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_119 --operation mode is arithmetic GB1_b_0_dup_119_carry_eqn = GB1_state_inc_736_nx20; GB1_b_0_dup_119 = GB1_nx21 & (GB1_state_1 $ GB1_b_0_dup_119_carry_eqn); --GB1_state_inc_736_nx24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx24 --operation mode is arithmetic GB1_state_inc_736_nx24 = CARRY(!GB1_state_inc_736_nx20 # !GB1_state_1); --GB1_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_2 --operation mode is normal GB1_state_2_lut_out = GB1_b_0_dup_115 # !BB1_sleep_reset_n; GB1_state_2 = DFFEAS(GB1_state_2_lut_out, S1__clk0, VCC, , , , , , ); --GB1_state_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_3 --operation mode is normal GB1_state_3_lut_out = GB1_b_0_dup_111 # !BB1_sleep_reset_n; GB1_state_3 = DFFEAS(GB1_state_3_lut_out, S1__clk0, VCC, , , , , , ); --GB1_state_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_4 --operation mode is normal GB1_state_4_lut_out = GB1_b_0_dup_107 # !BB1_sleep_reset_n; GB1_state_4 = DFFEAS(GB1_state_4_lut_out, S1__clk0, VCC, , , , , , ); --GB1_state_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_5 --operation mode is normal GB1_state_5_lut_out = GB1_b_0 # !BB1_sleep_reset_n; GB1_state_5 = DFFEAS(GB1_state_5_lut_out, S1__clk0, VCC, , , , , , ); --JB1_b_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|b_1 --operation mode is normal JB1_b_1_carry_eqn = JB1_state_inc_722_nx18; JB1_b_1 = JB1_nx18 & (JB1_state_2 $ !JB1_b_1_carry_eqn); --JB1_nx116 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|nx116 --operation mode is normal JB1_nx116 = BB1_timer_enable # !BB1_freeze_buffer; --JB1_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|b_0 --operation mode is normal JB1_b_0 = !JB1_state_0 & JB1_nx18; --JB1_b_1_dup_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|b_1_dup_60 --operation mode is arithmetic JB1_b_1_dup_60_carry_eqn = JB1_state_inc_722_nx14; JB1_b_1_dup_60 = JB1_nx18 & (JB1_state_1 $ JB1_b_1_dup_60_carry_eqn); --JB1_state_inc_722_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_inc_722_nx18 --operation mode is arithmetic JB1_state_inc_722_nx18 = CARRY(!JB1_state_inc_722_nx14 # !JB1_state_1); --AB1_ob_data_67 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_67 --operation mode is normal AB1_ob_data_67_lut_out = AB1_ob_data_66; AB1_ob_data_67 = DFFEAS(AB1_ob_data_67_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_67, , , AB1_a_2); --LB1_d_to_dll_68 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_68 --operation mode is normal LB1_d_to_dll_68 = Z1_data_out_68 & (LB1_nx148 # LB1_forward_buffer_60 & LB1_nx151) # !Z1_data_out_68 & LB1_forward_buffer_60 & (LB1_nx151); --AB1_a_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|a_2 --operation mode is normal AB1_a_2 = !BB1_freeze_buffer & LB1_d_we; --AB1_NOT_nx714 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|NOT_nx714 --operation mode is normal AB1_NOT_nx714 = BB1_freeze_buffer & BB1_request_data & (AB1_nx119) # !BB1_freeze_buffer & (LB1_d_we); --AB1_ob_crc_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_14 --operation mode is normal AB1_ob_crc_14_lut_out = AB1_ob_crc_13; AB1_ob_crc_14 = DFFEAS(AB1_ob_crc_14_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_67, , , AB1_a_2); --AB1_bitcounter_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_3 --operation mode is arithmetic AB1_bitcounter_3_carry_eqn = AB1_bitcounter_nx21; AB1_bitcounter_3_lut_out = AB1_bitcounter_3 $ (AB1_bitcounter_3_carry_eqn); AB1_bitcounter_3 = DFFEAS(AB1_bitcounter_3_lut_out, S1__clk0, VCC, , , , , !BB1_freeze_buffer, ); --AB1_bitcounter_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx27 --operation mode is arithmetic AB1_bitcounter_nx27 = CARRY(!AB1_bitcounter_nx21 # !AB1_bitcounter_3); --AB1_bitcounter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_1 --operation mode is arithmetic AB1_bitcounter_1_carry_eqn = AB1_bitcounter_nx9; AB1_bitcounter_1_lut_out = AB1_bitcounter_1 $ (AB1_bitcounter_1_carry_eqn); AB1_bitcounter_1 = DFFEAS(AB1_bitcounter_1_lut_out, S1__clk0, VCC, , , , , !BB1_freeze_buffer, ); --AB1_bitcounter_nx15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx15 --operation mode is arithmetic AB1_bitcounter_nx15 = CARRY(!AB1_bitcounter_nx9 # !AB1_bitcounter_1); --AB1_bitcounter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_0 --operation mode is arithmetic AB1_bitcounter_0_lut_out = AB1_bitcounter_0 $ AB1_nx1398; AB1_bitcounter_0 = DFFEAS(AB1_bitcounter_0_lut_out, S1__clk0, VCC, , , , , !BB1_freeze_buffer, ); --AB1_bitcounter_nx9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx9 --operation mode is arithmetic AB1_bitcounter_nx9 = CARRY(AB1_bitcounter_0 & AB1_nx1398); --AB1_bitcounter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_2 --operation mode is arithmetic AB1_bitcounter_2_carry_eqn = AB1_bitcounter_nx15; AB1_bitcounter_2_lut_out = AB1_bitcounter_2 $ (!AB1_bitcounter_2_carry_eqn); AB1_bitcounter_2 = DFFEAS(AB1_bitcounter_2_lut_out, S1__clk0, VCC, , , , , !BB1_freeze_buffer, ); --AB1_bitcounter_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx21 --operation mode is arithmetic AB1_bitcounter_nx21 = CARRY(AB1_bitcounter_2 & (!AB1_bitcounter_nx15)); --HB1_nx63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|nx63 --operation mode is normal HB1_nx63 = HB1_state_2 & HB1_state_1 & HB1_state_0 # !BB1_stuffing_start_n; --BB2_sleep_reset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|sleep_reset_n --operation mode is normal BB2_sleep_reset_n = FB2_data_out_2 & !FB2_data_out_1; --GB2_b_0_dup_123 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_123 --operation mode is normal GB2_b_0_dup_123 = !GB2_state_0 & GB2_nx21; --GB2_b_0_dup_119 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_119 --operation mode is arithmetic GB2_b_0_dup_119_carry_eqn = GB2_state_inc_736_nx20; GB2_b_0_dup_119 = GB2_nx21 & (GB2_state_1 $ GB2_b_0_dup_119_carry_eqn); --GB2_state_inc_736_nx24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx24 --operation mode is arithmetic GB2_state_inc_736_nx24 = CARRY(!GB2_state_inc_736_nx20 # !GB2_state_1); --GB2_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_2 --operation mode is normal GB2_state_2_lut_out = GB2_b_0_dup_115 # !BB2_sleep_reset_n; GB2_state_2 = DFFEAS(GB2_state_2_lut_out, S1__clk0, VCC, , , , , , ); --GB2_state_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_3 --operation mode is normal GB2_state_3_lut_out = GB2_b_0_dup_111 # !BB2_sleep_reset_n; GB2_state_3 = DFFEAS(GB2_state_3_lut_out, S1__clk0, VCC, , , , , , ); --GB2_state_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_4 --operation mode is normal GB2_state_4_lut_out = GB2_b_0_dup_107 # !BB2_sleep_reset_n; GB2_state_4 = DFFEAS(GB2_state_4_lut_out, S1__clk0, VCC, , , , , , ); --GB2_state_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_5 --operation mode is normal GB2_state_5_lut_out = GB2_b_0 # !BB2_sleep_reset_n; GB2_state_5 = DFFEAS(GB2_state_5_lut_out, S1__clk0, VCC, , , , , , ); --JB2_b_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|b_1 --operation mode is normal JB2_b_1_carry_eqn = JB2_state_inc_722_nx18; JB2_b_1 = JB2_nx18 & (JB2_state_2 $ !JB2_b_1_carry_eqn); --JB2_nx116 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|nx116 --operation mode is normal JB2_nx116 = BB2_timer_enable # !BB2_freeze_buffer; --JB2_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|b_0 --operation mode is normal JB2_b_0 = !JB2_state_0 & JB2_nx18; --JB2_b_1_dup_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|b_1_dup_60 --operation mode is arithmetic JB2_b_1_dup_60_carry_eqn = JB2_state_inc_722_nx14; JB2_b_1_dup_60 = JB2_nx18 & (JB2_state_1 $ JB2_b_1_dup_60_carry_eqn); --JB2_state_inc_722_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_inc_722_nx18 --operation mode is arithmetic JB2_state_inc_722_nx18 = CARRY(!JB2_state_inc_722_nx14 # !JB2_state_1); --AB2_ob_data_67 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_67 --operation mode is normal AB2_ob_data_67_lut_out = AB2_ob_data_66; AB2_ob_data_67 = DFFEAS(AB2_ob_data_67_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_67, , , AB2_a_2); --LB2_d_to_dll_68 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_68 --operation mode is normal LB2_d_to_dll_68 = Z2_data_out_68 & (LB2_nx148 # LB2_forward_buffer_60 & LB2_nx151) # !Z2_data_out_68 & LB2_forward_buffer_60 & (LB2_nx151); --AB2_a_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|a_2 --operation mode is normal AB2_a_2 = !BB2_freeze_buffer & LB2_d_we; --AB2_NOT_nx714 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|NOT_nx714 --operation mode is normal AB2_NOT_nx714 = BB2_freeze_buffer & BB2_request_data & (AB2_nx119) # !BB2_freeze_buffer & (LB2_d_we); --AB2_ob_crc_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_14 --operation mode is normal AB2_ob_crc_14_lut_out = AB2_ob_crc_13; AB2_ob_crc_14 = DFFEAS(AB2_ob_crc_14_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_67, , , AB2_a_2); --AB2_bitcounter_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_3 --operation mode is arithmetic AB2_bitcounter_3_carry_eqn = AB2_bitcounter_nx21; AB2_bitcounter_3_lut_out = AB2_bitcounter_3 $ (AB2_bitcounter_3_carry_eqn); AB2_bitcounter_3 = DFFEAS(AB2_bitcounter_3_lut_out, S1__clk0, VCC, , , , , !BB2_freeze_buffer, ); --AB2_bitcounter_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx27 --operation mode is arithmetic AB2_bitcounter_nx27 = CARRY(!AB2_bitcounter_nx21 # !AB2_bitcounter_3); --AB2_bitcounter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_1 --operation mode is arithmetic AB2_bitcounter_1_carry_eqn = AB2_bitcounter_nx9; AB2_bitcounter_1_lut_out = AB2_bitcounter_1 $ (AB2_bitcounter_1_carry_eqn); AB2_bitcounter_1 = DFFEAS(AB2_bitcounter_1_lut_out, S1__clk0, VCC, , , , , !BB2_freeze_buffer, ); --AB2_bitcounter_nx15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx15 --operation mode is arithmetic AB2_bitcounter_nx15 = CARRY(!AB2_bitcounter_nx9 # !AB2_bitcounter_1); --AB2_bitcounter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_0 --operation mode is arithmetic AB2_bitcounter_0_lut_out = AB2_bitcounter_0 $ AB2_nx1398; AB2_bitcounter_0 = DFFEAS(AB2_bitcounter_0_lut_out, S1__clk0, VCC, , , , , !BB2_freeze_buffer, ); --AB2_bitcounter_nx9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx9 --operation mode is arithmetic AB2_bitcounter_nx9 = CARRY(AB2_bitcounter_0 & AB2_nx1398); --AB2_bitcounter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_2 --operation mode is arithmetic AB2_bitcounter_2_carry_eqn = AB2_bitcounter_nx15; AB2_bitcounter_2_lut_out = AB2_bitcounter_2 $ (!AB2_bitcounter_2_carry_eqn); AB2_bitcounter_2 = DFFEAS(AB2_bitcounter_2_lut_out, S1__clk0, VCC, , , , , !BB2_freeze_buffer, ); --AB2_bitcounter_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx21 --operation mode is arithmetic AB2_bitcounter_nx21 = CARRY(AB2_bitcounter_2 & (!AB2_bitcounter_nx15)); --HB2_nx63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|nx63 --operation mode is normal HB2_nx63 = HB2_state_2 & HB2_state_1 & HB2_state_0 # !BB2_stuffing_start_n; --M1_PQ_10 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_10 --operation mode is normal M1_PQ_10_lut_out = V1_request_21; M1_PQ_10 = DFFEAS(M1_PQ_10_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_9, , , M1_SERREG_1); --K1_nx993 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx993 --operation mode is normal K1_nx993 = !V1_request_47 # !V1_request_46; --R1_RDATA_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_10 --operation mode is normal R1_RDATA_10_lut_out = R1_RDATA_9; R1_RDATA_10 = DFFEAS(R1_RDATA_10_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --R1_NOT_nx295 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|NOT_nx295 --operation mode is normal R1_NOT_nx295 = R1_ADC_SCLK & (R1_counter_3 # R1_counter_2 # !R1_fifo_rd); --K1_NOT_climits_a_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_9 --operation mode is normal K1_NOT_climits_a_9_lut_out = !V1_request_22; K1_NOT_climits_a_9 = DFFEAS(K1_NOT_climits_a_9_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_9 --operation mode is normal K1_adc_last_4_9_lut_out = R1_RDATA_9; K1_adc_last_4_9 = DFFEAS(K1_adc_last_4_9_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx46 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx46 --operation mode is arithmetic K1_modgen_gt_268_nx46 = CARRY(K1_NOT_climits_a_8 & (K1_adc_last_4_8 # !K1_modgen_gt_268_nx44) # !K1_NOT_climits_a_8 & K1_adc_last_4_8 & !K1_modgen_gt_268_nx44); --K1_NOT_climits_d_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_9 --operation mode is normal K1_NOT_climits_d_9_lut_out = !V1_request_22; K1_NOT_climits_d_9 = DFFEAS(K1_NOT_climits_d_9_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_9 --operation mode is normal K1_adc_last_6_9_lut_out = R1_RDATA_9; K1_adc_last_6_9 = DFFEAS(K1_adc_last_6_9_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx46 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx46 --operation mode is arithmetic K1_modgen_gt_270_nx46 = CARRY(K1_NOT_climits_d_8 & (K1_adc_last_6_8 # !K1_modgen_gt_270_nx44) # !K1_NOT_climits_d_8 & K1_adc_last_6_8 & !K1_modgen_gt_270_nx44); --K1_NOT_climits_a_21 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_21 --operation mode is normal K1_NOT_climits_a_21_lut_out = K1_NOT_climits_a_21; K1_NOT_climits_a_21 = DFFEAS(K1_NOT_climits_a_21_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L921, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_9 --operation mode is normal K1_adc_last_5_9_lut_out = R1_RDATA_9; K1_adc_last_5_9 = DFFEAS(K1_adc_last_5_9_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx46 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx46 --operation mode is arithmetic K1_modgen_gt_269_nx46 = CARRY(K1_NOT_climits_a_20 & (K1_adc_last_5_8 # !K1_modgen_gt_269_nx44) # !K1_NOT_climits_a_20 & K1_adc_last_5_8 & !K1_modgen_gt_269_nx44); --K1_NOT_climits_d_21 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_21 --operation mode is normal K1_NOT_climits_d_21_lut_out = K1_NOT_climits_d_21; K1_NOT_climits_d_21 = DFFEAS(K1_NOT_climits_d_21_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L921, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_9 --operation mode is normal K1_adc_last_7_9_lut_out = R1_RDATA_9; K1_adc_last_7_9 = DFFEAS(K1_adc_last_7_9_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx46 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx46 --operation mode is arithmetic K1_modgen_gt_271_nx46 = CARRY(K1_NOT_climits_d_20 & (K1_adc_last_7_8 # !K1_modgen_gt_271_nx44) # !K1_NOT_climits_d_20 & K1_adc_last_7_8 & !K1_modgen_gt_271_nx44); --E1_cnt_rst_4 is ni2io_wt:wt_ni|cnt_rst_4 --operation mode is arithmetic E1_cnt_rst_4_carry_eqn = E1_cnt_rst_nx28; E1_cnt_rst_4_lut_out = E1_cnt_rst_4 $ (!E1_cnt_rst_4_carry_eqn); E1_cnt_rst_4 = DFFEAS(E1_cnt_rst_4_lut_out, S1__clk1, T1_chipRST_n, , , , , !E1_NOT_rst_start, ); --E1_cnt_rst_nx34 is ni2io_wt:wt_ni|cnt_rst_nx34 --operation mode is arithmetic E1_cnt_rst_nx34 = CARRY(E1_cnt_rst_4 & (!E1_cnt_rst_nx28)); --T1_nx241 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx241 --operation mode is normal T1_nx241 = X1_data_out_3 & !X1_data_out_2 & !X1_data_out_1 & X1_data_out_0; --T1_nx383 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx383 --operation mode is normal T1_nx383 = T1_long_transaction & T1_nx407; --T1_waitcount_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_3 --operation mode is arithmetic T1_waitcount_3_carry_eqn = T1_waitcount_nx28; T1_waitcount_3_lut_out = T1_waitcount_3 $ (!T1_waitcount_3_carry_eqn); T1_waitcount_3 = DFFEAS(T1_waitcount_3_lut_out, S1__clk0, VCC, , , VCC, , , T1_nx383); --T1_waitcount_nx33 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx33 --operation mode is arithmetic T1_waitcount_nx33 = CARRY(!T1_waitcount_3 & (!T1_waitcount_nx28)); --T1_waitcount_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_2 --operation mode is arithmetic T1_waitcount_2_carry_eqn = T1_waitcount_nx21; T1_waitcount_2_lut_out = T1_waitcount_2 $ (T1_waitcount_2_carry_eqn); T1_waitcount_2 = DFFEAS(T1_waitcount_2_lut_out, S1__clk0, VCC, , , ~GND, , , T1_nx383); --T1_waitcount_nx28 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx28 --operation mode is arithmetic T1_waitcount_nx28 = CARRY(T1_waitcount_2 # !T1_waitcount_nx21); --T1_waitcount_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_1 --operation mode is arithmetic T1_waitcount_1_carry_eqn = T1_waitcount_nx15; T1_waitcount_1_lut_out = T1_waitcount_1 $ (!T1_waitcount_1_carry_eqn); T1_waitcount_1 = DFFEAS(T1_waitcount_1_lut_out, S1__clk0, VCC, , , ~GND, , , T1_nx383); --T1_waitcount_nx21 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx21 --operation mode is arithmetic T1_waitcount_nx21 = CARRY(!T1_waitcount_1 & (!T1_waitcount_nx15)); --T1_waitcount_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_0 --operation mode is arithmetic T1_waitcount_0_lut_out = T1_waitcount_0 $ T1_nx403; T1_waitcount_0 = DFFEAS(T1_waitcount_0_lut_out, S1__clk0, VCC, , , ~GND, , , T1_nx383); --T1_waitcount_nx15 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx15 --operation mode is arithmetic T1_waitcount_nx15 = CARRY(T1_waitcount_0 # !T1_nx403); --K1_RDATA_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_0 --operation mode is normal K1_RDATA_0 = K1_nx984 # K1_nx985 # K1_nx986 # K1_nx987; --J1_RDATA_0 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_0 --operation mode is normal J1_RDATA_0 = V1_request_38 & (J1_PAADC_MuxA_0) # !V1_request_38 & Q1_q_b[0]; --L1_nx901 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx901 --operation mode is normal L1_nx901 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_0) # !V1_request_48 & L1_adc_last_0_0); --L1_nx902 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx902 --operation mode is normal L1_nx902 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_0) # !V1_request_48 & L1_adc_last_4_0); --L1_nx903 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx903 --operation mode is normal L1_nx903 = V1_request_46 & !V1_request_47 & L1_cfr_0; --L1_nx904 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx904 --operation mode is normal L1_nx904 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_0 # !V1_request_48 & (!L1_NOT_climits_a_0)); --E1_rdata_0 is ni2io_wt:wt_ni|rdata_0 --operation mode is normal E1_rdata_0 = V1_request_37 & UB1_q_b[0] # !V1_request_37 & (E1_nx369 & E1_nx370); --H1_sel_0 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|sel_0 --operation mode is normal H1_sel_0_lut_out = H1_nx214 & (V1_request_35 & !V1_request_36 # !V1_request_35 & V1_request_36 & H1_nx213); H1_sel_0 = DFFEAS(H1_sel_0_lut_out, S1__clk1, VCC, , , , , , ); --F1_RDATA_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_0 --operation mode is normal F1_RDATA_0 = F1_nx835 # F1_nx836 # V1_request_46 & F1_config_0; --Y1_d_buff is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|d_buff --operation mode is normal Y1_d_buff_lut_out = W1_d0_to_dll; Y1_d_buff = DFFEAS(Y1_d_buff_lut_out, S1__clk0, VCC, , , , , , ); --Y1_sync_counter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|sync_counter_0 --operation mode is normal Y1_sync_counter_0_lut_out = DB1_data_out_3 & !DB1_data_out_2 & !DB1_data_out_0 # !DB1_data_out_3 & DB1_data_out_2 & (Y1_nx142 # !DB1_data_out_0); Y1_sync_counter_0 = DFFEAS(Y1_sync_counter_0_lut_out, S1__clk0, VCC, , Y1_NOT_nx210, , , , ); --EB1_event_async is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|event_async --operation mode is normal EB1_event_async = Y1_time_in_enable & !EB1_state_2 & !EB1_state_0 & EB1_state_1; --Z1_buffer_full is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|buffer_full --operation mode is normal Z1_buffer_full = Z1_bitcounter_6 & (Z1_bitcounter_5 # Z1_bitcounter_4 & Z1_nx280); --CB1_stuff_err is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|stuff_err --operation mode is normal CB1_stuff_err_lut_out = !CB1_nx10 & CB1_nx233 & (W1_d0_to_dll $ !CB1_data_out); CB1_stuff_err = DFFEAS(CB1_stuff_err_lut_out, S1__clk0, VCC, , , , , , ); --Y1_sync_counter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|sync_counter_2 --operation mode is normal Y1_sync_counter_2_lut_out = DB1_data_out_3 & !DB1_data_out_2 & !DB1_data_out_0 # !DB1_data_out_3 & DB1_data_out_2 & (Y1_nx140 # !DB1_data_out_0); Y1_sync_counter_2 = DFFEAS(Y1_sync_counter_2_lut_out, S1__clk0, VCC, , Y1_NOT_nx210, , , , ); --Y1_sync_counter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|sync_counter_1 --operation mode is normal Y1_sync_counter_1_lut_out = DB1_data_out_3 & !DB1_data_out_2 & !DB1_data_out_0 # !DB1_data_out_3 & DB1_data_out_2 & (Y1_nx141 # !DB1_data_out_0); Y1_sync_counter_1 = DFFEAS(Y1_sync_counter_1_lut_out, S1__clk0, VCC, , Y1_NOT_nx210, , , , ); --Y1_nx81 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx81 --operation mode is normal Y1_nx81 = Y1_sync_counter_2 # Y1_sync_counter_1; --Y1_nx85 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx85 --operation mode is normal Y1_nx85 = !DB1_data_out_3 & DB1_data_out_2 & !DB1_data_out_1; --Y1_nx84 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx84 --operation mode is normal Y1_nx84 = !DB1_data_out_3 & DB1_data_out_1; --Y1_time_in_twofwd_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|time_in_twofwd_n --operation mode is normal Y1_time_in_twofwd_n = DB1_data_out_2 # DB1_data_out_1 # DB1_data_out_0 # !DB1_data_out_3; --Y1_nx80 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx80 --operation mode is normal Y1_nx80 = Z1_buffer_full # CB1_stuff_err; --Y1_nx91 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx91 --operation mode is normal Y1_nx91 = !DB1_data_out_3 & DB1_data_out_2 & DB1_data_out_1 & !EB1_event_async; --Y1_nx88 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx88 --operation mode is normal Y1_nx88 = !Z1_buffer_full & !CB1_stuff_err # !DB1_data_out_0; --Y1_nx90 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx90 --operation mode is normal Y1_nx90 = DB1_data_out_3 # DB1_data_out_2; --Y1_nx86 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx86 --operation mode is normal Y1_nx86 = DB1_data_out_2 # DB1_data_out_1 & DB1_data_out_0; --Y1_nx98 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx98 --operation mode is normal Y1_nx98 = !W1_d0_to_dll & !DB1_data_out_2 & !DB1_data_out_1 & DB1_data_out_0; --CB1_counter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_2 --operation mode is normal CB1_counter_2_carry_eqn = CB1_counter_nx12; CB1_counter_2_lut_out = CB1_counter_2 $ (!CB1_counter_2_carry_eqn); CB1_counter_2 = DFFEAS(CB1_counter_2_lut_out, S1__clk0, VCC, , CB1_nx90, , , CB1_SCLEAR, ); --CB1_counter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_1 --operation mode is arithmetic CB1_counter_1_carry_eqn = CB1_counter_nx6; CB1_counter_1_lut_out = CB1_counter_1 $ (CB1_counter_1_carry_eqn); CB1_counter_1 = DFFEAS(CB1_counter_1_lut_out, S1__clk0, VCC, , CB1_nx90, , , CB1_SCLEAR, ); --CB1_counter_nx12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_nx12 --operation mode is arithmetic CB1_counter_nx12 = CARRY(!CB1_counter_nx6 # !CB1_counter_1); --CB1_counter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_0 --operation mode is arithmetic CB1_counter_0_lut_out = !CB1_counter_0; CB1_counter_0 = DFFEAS(CB1_counter_0_lut_out, S1__clk0, VCC, , CB1_nx90, , , CB1_SCLEAR, ); --CB1_counter_nx6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_nx6 --operation mode is arithmetic CB1_counter_nx6 = CARRY(CB1_counter_0); --Y2_d_buff is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|d_buff --operation mode is normal Y2_d_buff_lut_out = W1_d1_to_dll; Y2_d_buff = DFFEAS(Y2_d_buff_lut_out, S1__clk0, VCC, , , , , , ); --Y2_sync_counter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|sync_counter_0 --operation mode is normal Y2_sync_counter_0_lut_out = DB2_data_out_3 & !DB2_data_out_2 & !DB2_data_out_0 # !DB2_data_out_3 & DB2_data_out_2 & (Y2_nx142 # !DB2_data_out_0); Y2_sync_counter_0 = DFFEAS(Y2_sync_counter_0_lut_out, S1__clk0, VCC, , Y2_NOT_nx210, , , , ); --EB2_event_async is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|event_async --operation mode is normal EB2_event_async = Y2_time_in_enable & !EB2_state_2 & !EB2_state_0 & EB2_state_1; --Z2_buffer_full is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|buffer_full --operation mode is normal Z2_buffer_full = Z2_bitcounter_6 & (Z2_bitcounter_5 # Z2_bitcounter_4 & Z2_nx280); --CB2_stuff_err is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|stuff_err --operation mode is normal CB2_stuff_err_lut_out = !CB2_nx10 & CB2_nx233 & (W1_d1_to_dll $ !CB2_data_out); CB2_stuff_err = DFFEAS(CB2_stuff_err_lut_out, S1__clk0, VCC, , , , , , ); --Y2_sync_counter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|sync_counter_2 --operation mode is normal Y2_sync_counter_2_lut_out = DB2_data_out_3 & !DB2_data_out_2 & !DB2_data_out_0 # !DB2_data_out_3 & DB2_data_out_2 & (Y2_nx140 # !DB2_data_out_0); Y2_sync_counter_2 = DFFEAS(Y2_sync_counter_2_lut_out, S1__clk0, VCC, , Y2_NOT_nx210, , , , ); --Y2_sync_counter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|sync_counter_1 --operation mode is normal Y2_sync_counter_1_lut_out = DB2_data_out_3 & !DB2_data_out_2 & !DB2_data_out_0 # !DB2_data_out_3 & DB2_data_out_2 & (Y2_nx141 # !DB2_data_out_0); Y2_sync_counter_1 = DFFEAS(Y2_sync_counter_1_lut_out, S1__clk0, VCC, , Y2_NOT_nx210, , , , ); --Y2_nx81 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx81 --operation mode is normal Y2_nx81 = Y2_sync_counter_2 # Y2_sync_counter_1; --Y2_nx85 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx85 --operation mode is normal Y2_nx85 = !DB2_data_out_3 & DB2_data_out_2 & !DB2_data_out_1; --Y2_nx84 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx84 --operation mode is normal Y2_nx84 = !DB2_data_out_3 & DB2_data_out_1; --Y2_time_in_twofwd_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|time_in_twofwd_n --operation mode is normal Y2_time_in_twofwd_n = DB2_data_out_2 # DB2_data_out_1 # DB2_data_out_0 # !DB2_data_out_3; --Y2_nx80 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx80 --operation mode is normal Y2_nx80 = Z2_buffer_full # CB2_stuff_err; --Y2_nx91 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx91 --operation mode is normal Y2_nx91 = !DB2_data_out_3 & DB2_data_out_2 & DB2_data_out_1 & !EB2_event_async; --Y2_nx88 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx88 --operation mode is normal Y2_nx88 = !Z2_buffer_full & !CB2_stuff_err # !DB2_data_out_0; --Y2_nx90 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx90 --operation mode is normal Y2_nx90 = DB2_data_out_3 # DB2_data_out_2; --Y2_nx86 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx86 --operation mode is normal Y2_nx86 = DB2_data_out_2 # DB2_data_out_1 & DB2_data_out_0; --Y2_nx98 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx98 --operation mode is normal Y2_nx98 = !W1_d1_to_dll & !DB2_data_out_2 & !DB2_data_out_1 & DB2_data_out_0; --CB2_counter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_2 --operation mode is normal CB2_counter_2_carry_eqn = CB2_counter_nx12; CB2_counter_2_lut_out = CB2_counter_2 $ (!CB2_counter_2_carry_eqn); CB2_counter_2 = DFFEAS(CB2_counter_2_lut_out, S1__clk0, VCC, , CB2_nx90, , , CB2_SCLEAR, ); --CB2_counter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_1 --operation mode is arithmetic CB2_counter_1_carry_eqn = CB2_counter_nx6; CB2_counter_1_lut_out = CB2_counter_1 $ (CB2_counter_1_carry_eqn); CB2_counter_1 = DFFEAS(CB2_counter_1_lut_out, S1__clk0, VCC, , CB2_nx90, , , CB2_SCLEAR, ); --CB2_counter_nx12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_nx12 --operation mode is arithmetic CB2_counter_nx12 = CARRY(!CB2_counter_nx6 # !CB2_counter_1); --CB2_counter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_0 --operation mode is arithmetic CB2_counter_0_lut_out = !CB2_counter_0; CB2_counter_0 = DFFEAS(CB2_counter_0_lut_out, S1__clk0, VCC, , CB2_nx90, , , CB2_SCLEAR, ); --CB2_counter_nx6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_nx6 --operation mode is arithmetic CB2_counter_nx6 = CARRY(CB2_counter_0); --LB2_nx153 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx153 --operation mode is normal LB2_nx153 = DB4_data_out_3 & !DB4_data_out_1; --LB2_nx144 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx144 --operation mode is normal LB2_nx144 = !DB4_data_out_3 & !DB4_data_out_1; --Z2_data_valid is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_valid --operation mode is normal Z2_data_valid = Z2_buffer_full & Z2_nx278 & Z2_nx282 & Z2_nx283; --Z2_buffer_half is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|buffer_half --operation mode is normal Z2_buffer_half = Z2_bitcounter_6 & (Z2_bitcounter_5 # Z2_bitcounter_4 & Z2_nx281); --LB2_nx180 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx180 --operation mode is normal LB2_nx180 = !DB4_data_out_0 & (!BB2_freeze_buffer & V1_reply1_valid # !Z2_data_valid); --LB2_nx181 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx181 --operation mode is normal LB2_nx181 = !DB4_data_out_2 & DB4_data_out_0 & (!BB2_freeze_buffer # !Z2_data_valid); --LB2_forward_buffer_60 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_60 --operation mode is normal LB2_forward_buffer_60 = !Z2_data_out_60; --LB2_forward_buffer_59 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_59 --operation mode is arithmetic LB2_forward_buffer_59_carry_eqn = LB2_result_inc_871_nx24; LB2_forward_buffer_59 = Z2_data_out_59 $ (LB2_forward_buffer_59_carry_eqn); --LB2_result_inc_871_nx28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_871_nx28 --operation mode is arithmetic LB2_result_inc_871_nx28 = CARRY(!LB2_result_inc_871_nx24 # !Z2_data_out_59); --LB2_nx158 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx158 --operation mode is normal LB2_nx158 = LB2_nx149 & (BB2_freeze_buffer # !Z2_data_valid & !DB4_data_out_2); --LB2_nx159 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx159 --operation mode is normal LB2_nx159 = !DB4_data_out_0 & LB2_nx149 & (DB4_data_out_2 # !V1_reply1_valid); --LB2_nx161 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx161 --operation mode is normal LB2_nx161 = LB2_nx145 & (LB2_forward_buffer_54 # LB2_forward_buffer_53 # LB2_nx177); --LB2_nx146 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx146 --operation mode is normal LB2_nx146 = !DB4_data_out_2 & !DB4_data_out_0; --LB2_nx172 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx172 --operation mode is normal LB2_nx172 = LB2_nx149 & (LB2_nx174 # !V1_wait_for_bridge & !LB2_nx152); --LB2_nx173 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx173 --operation mode is normal LB2_nx173 = !V1_wait_for_bridge & LB2_b_dirty & (Z2_data_valid # U1_buf1_err); --LB2_nx147 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx147 --operation mode is normal LB2_nx147 = !U1_buf1_err & LB2_modgen_eq_783_nx24 & LB2_nx143 & LB2_nx144; --LB2_nx168 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx168 --operation mode is normal LB2_nx168 = Z2_data_out_64 & (Z2_data_out_63 $ LB2_forward_buffer_55 # !LB2_forward_buffer_56) # !Z2_data_out_64 & (LB2_forward_buffer_56 # Z2_data_out_63 $ LB2_forward_buffer_55); --LB2_nx169 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx169 --operation mode is normal LB2_nx169 = Z2_data_out_68 & (Z2_data_out_67 $ LB2_forward_buffer_59 # !LB2_forward_buffer_60) # !Z2_data_out_68 & (LB2_forward_buffer_60 # Z2_data_out_67 $ LB2_forward_buffer_59); --LB2_nx175 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx175 --operation mode is normal LB2_nx175 = LB2_nx176 # LB2_nx147 & (LB2_modgen_eq_784_nx0 # LB2_nx167); --LB2_forward_buffer_58 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_58 --operation mode is arithmetic LB2_forward_buffer_58_carry_eqn = LB2_result_inc_871_nx28; LB2_forward_buffer_58 = Z2_data_out_58 $ (!LB2_forward_buffer_58_carry_eqn); --LB2_result_inc_871_nx32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_871_nx32 --operation mode is arithmetic LB2_result_inc_871_nx32 = CARRY(Z2_data_out_58 & (!LB2_result_inc_871_nx28)); --LB2_forward_buffer_57 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_57 --operation mode is arithmetic LB2_forward_buffer_57_carry_eqn = LB2_result_inc_871_nx32; LB2_forward_buffer_57 = Z2_data_out_57 $ (LB2_forward_buffer_57_carry_eqn); --LB2_result_inc_871_nx36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_871_nx36 --operation mode is arithmetic LB2_result_inc_871_nx36 = CARRY(!LB2_result_inc_871_nx32 # !Z2_data_out_57); --LB2_nx171 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx171 --operation mode is normal LB2_nx171 = LB2_forward_buffer_56 # LB2_forward_buffer_55 # LB2_forward_buffer_54 # LB2_forward_buffer_53; --LB2_nx154 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx154 --operation mode is normal LB2_nx154 = LB2_nx182 # LB2_nx144 & (Z2_data_valid # !Z2_buffer_half); --LB1_nx155 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx155 --operation mode is normal LB1_nx155 = !DB3_data_out_2 & LB1_nx153 & (BB1_freeze_buffer # !DB3_data_out_0); --LB1_nx182 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx182 --operation mode is normal LB1_nx182 = !DB3_data_out_3 & DB3_data_out_1 & DB3_data_out_0; --LB1_nx156 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx156 --operation mode is normal LB1_nx156 = U1_buf0_err & !DB3_data_out_2 & DB3_data_out_0 & LB1_nx144; --LB1_nx160 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx160 --operation mode is normal LB1_nx160 = !Z1_data_valid & Z1_buffer_half & DB3_data_out_2 & LB1_nx144; --LB1_nx178 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx178 --operation mode is normal LB1_nx178 = !DB3_data_out_3 & DB3_data_out_1 & (LB1_nx180 # LB1_nx181); --LB1_nx179 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx179 --operation mode is normal LB1_nx179 = !DB3_data_out_3 & DB3_data_out_2 & (BB1_freeze_buffer # !DB3_data_out_0); --U1_buf0_err is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|buf0_err --operation mode is normal U1_buf0_err = Z1_buffer_full & !Z1_data_valid; --LB1_nx145 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx145 --operation mode is normal LB1_nx145 = !DB3_data_out_3 & !DB3_data_out_2 & !DB3_data_out_1 & DB3_data_out_0; --LB1_nx150 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx150 --operation mode is normal LB1_nx150 = LB1_forward_buffer_60 # LB1_forward_buffer_59; --LB1_nx157 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx157 --operation mode is normal LB1_nx157 = LB1_nx158 # LB1_nx159 # LB1_nx160 # LB1_nx161; --LB1_nx163 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx163 --operation mode is normal LB1_nx163 = LB1_nx172 # LB1_nx144 & LB1_nx146 & LB1_nx173; --LB1_nx164 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx164 --operation mode is normal LB1_nx164 = LB1_nx175 # LB1_nx147 & (LB1_nx168 # LB1_nx169); --LB1_nx165 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx165 --operation mode is normal LB1_nx165 = LB1_forward_buffer_58 # LB1_forward_buffer_57 # LB1_nx150 # LB1_nx171; --LB1_nx170 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx170 --operation mode is normal LB1_nx170 = BB1_freeze_buffer & (DB3_data_out_2 & (LB1_nx154) # !DB3_data_out_2 & LB1_nx153); --F1_bytes2send_29 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_29 --operation mode is normal F1_bytes2send_29_lut_out = F1_bytes2send_29; F1_bytes2send_29 = DFFEAS(F1_bytes2send_29_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_2, , , F1_a_1); --F1_byte_send_4 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_send_4 --operation mode is normal F1_byte_send_4_lut_out = F1_nx765 # F1_nx766 # F1_nx767 # F1_nx768; F1_byte_send_4 = DFFEAS(F1_byte_send_4_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2817, , , , ); --F1_bytes2send_45 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_45 --operation mode is normal F1_bytes2send_45_lut_out = F1_bytes2send_45; F1_bytes2send_45 = DFFEAS(F1_bytes2send_45_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_18, , , F1_a_3); --F1_bytes2send_21 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_21 --operation mode is normal F1_bytes2send_21_lut_out = F1_bytes2send_21; F1_bytes2send_21 = DFFEAS(F1_bytes2send_21_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_10, , , F1_a_1); --F1_bytes2send_37 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_37 --operation mode is normal F1_bytes2send_37_lut_out = V1_request_26; F1_bytes2send_37 = DFFEAS(F1_bytes2send_37_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx479, , , , ); --F1_iword2send_5 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|iword2send_5 --operation mode is normal F1_iword2send_5_lut_out = F1_iword2send_5; F1_iword2send_5 = DFFEAS(F1_iword2send_5_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_10, , , F1_a_3); --F1_bytes2send_13 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_13 --operation mode is normal F1_bytes2send_13_lut_out = F1_bytes2send_13; F1_bytes2send_13 = DFFEAS(F1_bytes2send_13_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_18, , , F1_a_1); --F1_bytes2send_5 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_5 --operation mode is normal F1_bytes2send_5_lut_out = V1_request_26; F1_bytes2send_5 = DFFEAS(F1_bytes2send_5_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx543, , , , ); --K1_timer_dec_202_nx22 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|timer_dec_202_nx22 --operation mode is arithmetic K1_timer_dec_202_nx22 = CARRY(K1_timer_0); --K1_cfr_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_9 --operation mode is normal K1_cfr_9_lut_out = V1_request_22; K1_cfr_9 = DFFEAS(K1_cfr_9_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_8 --operation mode is normal R1_datasr_8_lut_out = K1_cfr_8 & (R1_nx94 # R1_datasr_7 & R1_ADC_SCLK) # !K1_cfr_8 & R1_datasr_7 & R1_ADC_SCLK; R1_datasr_8 = DFFEAS(R1_datasr_8_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --V1_nx232 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx232 --operation mode is normal V1_nx232 = !BB1_freeze_buffer & !BB2_freeze_buffer; --H1_ix0_nx20 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|ix0_nx20 --operation mode is normal H1_ix0_nx20_lut_out = T1_bus_req; H1_ix0_nx20 = DFFEAS(H1_ix0_nx20_lut_out, S1__clk1, VCC, , , , , , ); --G1_modgen_gt_455_nx22 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_455_nx22 --operation mode is arithmetic G1_modgen_gt_455_nx22 = CARRY(G1_nx584 & !G1_B_1 & !G1_modgen_gt_455_nx20 # !G1_nx584 & (!G1_modgen_gt_455_nx20 # !G1_B_1)); --G2_modgen_gt_455_nx22 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_455_nx22 --operation mode is arithmetic G2_modgen_gt_455_nx22 = CARRY(G2_nx584 & !G2_B_1 & !G2_modgen_gt_455_nx20 # !G2_nx584 & (!G2_modgen_gt_455_nx20 # !G2_B_1)); --G3_modgen_gt_455_nx22 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_455_nx22 --operation mode is arithmetic G3_modgen_gt_455_nx22 = CARRY(G3_nx584 & !G3_B_1 & !G3_modgen_gt_455_nx20 # !G3_nx584 & (!G3_modgen_gt_455_nx20 # !G3_B_1)); --Y1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|next_state_1 --operation mode is normal Y1_next_state_1 = Y1_nx94 # Y1_nx95 # Y1_nx97 # Y1_nx106; --Y2_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|next_state_1 --operation mode is normal Y2_next_state_1 = Y2_nx94 # Y2_nx95 # Y2_nx97 # Y2_nx106; --G4_modgen_gt_455_nx22 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_455_nx22 --operation mode is arithmetic G4_modgen_gt_455_nx22 = CARRY(G4_nx584 & !G4_B_1 & !G4_modgen_gt_455_nx20 # !G4_nx584 & (!G4_modgen_gt_455_nx20 # !G4_B_1)); --G1_B_1 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_1 --operation mode is arithmetic G1_B_1_carry_eqn = G1_B_nx7; G1_B_1_lut_out = G1_B_1 $ (G1_B_1_carry_eqn); G1_B_1 = DFFEAS(G1_B_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_B_nx13 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_nx13 --operation mode is arithmetic G1_B_nx13 = CARRY(G1_B_1 $ !G1_NOT_UDn # !G1_B_nx7); --G1_nx584 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx584 --operation mode is normal G1_nx584_lut_out = !V1_request_30; G1_nx584 = DFFEAS(G1_nx584_lut_out, S1__clk1, T1_chipRST_n, , G1_nx12, , , G1_NOT_nx14, ); --G1_modgen_gt_453_nx20 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_453_nx20 --operation mode is arithmetic G1_modgen_gt_453_nx20 = CARRY(!G1_nx589 & !G1_B_0); --G2_B_1 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_1 --operation mode is arithmetic G2_B_1_carry_eqn = G2_B_nx7; G2_B_1_lut_out = G2_B_1 $ (G2_B_1_carry_eqn); G2_B_1 = DFFEAS(G2_B_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_B_nx13 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_nx13 --operation mode is arithmetic G2_B_nx13 = CARRY(G2_B_1 $ !G2_NOT_UDn # !G2_B_nx7); --G2_nx584 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx584 --operation mode is normal G2_nx584_lut_out = !V1_request_22; G2_nx584 = DFFEAS(G2_nx584_lut_out, S1__clk1, T1_chipRST_n, , G2_nx12, , , G2_NOT_nx14, ); --G2_modgen_gt_453_nx20 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_453_nx20 --operation mode is arithmetic G2_modgen_gt_453_nx20 = CARRY(!G2_nx589 & !G2_B_0); --G3_B_1 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_1 --operation mode is arithmetic G3_B_1_carry_eqn = G3_B_nx7; G3_B_1_lut_out = G3_B_1 $ (G3_B_1_carry_eqn); G3_B_1 = DFFEAS(G3_B_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_B_nx13 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_nx13 --operation mode is arithmetic G3_B_nx13 = CARRY(G3_B_1 $ !G3_NOT_UDn # !G3_B_nx7); --G3_nx584 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx584 --operation mode is normal G3_nx584_lut_out = !V1_request_14; G3_nx584 = DFFEAS(G3_nx584_lut_out, S1__clk1, T1_chipRST_n, , G3_nx12, , , G3_NOT_nx14, ); --G3_modgen_gt_453_nx20 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_453_nx20 --operation mode is arithmetic G3_modgen_gt_453_nx20 = CARRY(!G3_nx589 & !G3_B_0); --G4_B_1 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_1 --operation mode is arithmetic G4_B_1_carry_eqn = G4_B_nx7; G4_B_1_lut_out = G4_B_1 $ (G4_B_1_carry_eqn); G4_B_1 = DFFEAS(G4_B_1_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_B_nx13 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_nx13 --operation mode is arithmetic G4_B_nx13 = CARRY(G4_B_1 $ !G4_NOT_UDn # !G4_B_nx7); --G4_nx584 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx584 --operation mode is normal G4_nx584_lut_out = !V1_request_6; G4_nx584 = DFFEAS(G4_nx584_lut_out, S1__clk1, T1_chipRST_n, , G4_nx12, , , G4_NOT_nx14, ); --G4_modgen_gt_453_nx20 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_453_nx20 --operation mode is arithmetic G4_modgen_gt_453_nx20 = CARRY(!G4_nx589 & !G4_B_0); --L1_timer_dec_202_nx22 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|timer_dec_202_nx22 --operation mode is arithmetic L1_timer_dec_202_nx22 = CARRY(L1_timer_0); --L1_cfr_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_9 --operation mode is normal L1_cfr_9_lut_out = V1_request_22; L1_cfr_9 = DFFEAS(L1_cfr_9_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_8 --operation mode is normal R2_datasr_8_lut_out = L1_cfr_8 & (R2_nx94 # R2_datasr_7 & R2_ADC_SCLK) # !L1_cfr_8 & R2_datasr_7 & R2_ADC_SCLK; R2_datasr_8 = DFFEAS(R2_datasr_8_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --GB1_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx21 --operation mode is normal GB1_nx21 = GB1_nx148 # !GB1_state_1 # !GB1_state_0; --GB1_state_inc_736_nx20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx20 --operation mode is arithmetic GB1_state_inc_736_nx20 = CARRY(GB1_state_0); --GB1_b_0_dup_115 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_115 --operation mode is arithmetic GB1_b_0_dup_115_carry_eqn = GB1_state_inc_736_nx24; GB1_b_0_dup_115 = GB1_nx21 & (GB1_state_2 $ !GB1_b_0_dup_115_carry_eqn); --GB1_state_inc_736_nx28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx28 --operation mode is arithmetic GB1_state_inc_736_nx28 = CARRY(GB1_state_2 & (!GB1_state_inc_736_nx24)); --GB1_b_0_dup_111 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_111 --operation mode is arithmetic GB1_b_0_dup_111_carry_eqn = GB1_state_inc_736_nx28; GB1_b_0_dup_111 = GB1_nx21 & (GB1_state_3 $ GB1_b_0_dup_111_carry_eqn); --GB1_state_inc_736_nx32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx32 --operation mode is arithmetic GB1_state_inc_736_nx32 = CARRY(!GB1_state_inc_736_nx28 # !GB1_state_3); --GB1_b_0_dup_107 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_107 --operation mode is arithmetic GB1_b_0_dup_107_carry_eqn = GB1_state_inc_736_nx32; GB1_b_0_dup_107 = GB1_nx21 & (GB1_state_4 $ !GB1_b_0_dup_107_carry_eqn); --GB1_state_inc_736_nx36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx36 --operation mode is arithmetic GB1_state_inc_736_nx36 = CARRY(GB1_state_4 & (!GB1_state_inc_736_nx32)); --GB1_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0 --operation mode is normal GB1_b_0_carry_eqn = GB1_state_inc_736_nx36; GB1_b_0 = GB1_nx21 & (GB1_state_5 $ GB1_b_0_carry_eqn); --JB1_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|nx18 --operation mode is normal JB1_nx18 = JB1_state_0 # JB1_state_1 # !JB1_state_2; --JB1_state_inc_722_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_inc_722_nx14 --operation mode is arithmetic JB1_state_inc_722_nx14 = CARRY(JB1_state_0); --AB1_ob_data_66 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_66 --operation mode is normal AB1_ob_data_66_lut_out = AB1_ob_data_65; AB1_ob_data_66 = DFFEAS(AB1_ob_data_66_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_66, , , AB1_a_2); --LB1_d_to_dll_67 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_67 --operation mode is normal LB1_d_to_dll_67 = Z1_data_out_67 & (LB1_nx148 # LB1_forward_buffer_59 & LB1_nx151) # !Z1_data_out_67 & LB1_forward_buffer_59 & (LB1_nx151); --Z1_data_out_68 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_68 --operation mode is normal Z1_data_out_68_lut_out = Z1_data_out_67; Z1_data_out_68 = DFFEAS(Z1_data_out_68_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --LB1_forward_buffer_60 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_60 --operation mode is normal LB1_forward_buffer_60 = !Z1_data_out_60; --LB1_nx148 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx148 --operation mode is normal LB1_nx148 = !DB3_data_out_2 & (DB3_data_out_0 # !V1_altered_frame0); --LB1_nx151 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx151 --operation mode is normal LB1_nx151 = V1_altered_frame0 & !DB3_data_out_2 & !DB3_data_out_0; --LB1_d_we is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_we --operation mode is normal LB1_d_we = !DB3_data_out_3 & DB3_data_out_1 & (DB3_data_out_0 # !DB3_data_out_2); --BB1_request_data is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|request_data --operation mode is normal BB1_request_data = !FB1_data_out_2 & FB1_data_out_1 & FB1_data_out_0 & !HB1_stuff_bit_inserted; --AB1_nx119 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|nx119 --operation mode is normal AB1_nx119 = AB1_nx120 # !AB1_bitcounter_5 & !AB1_bitcounter_3 & AB1_nx121; --AB1_ob_crc_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_13 --operation mode is normal AB1_ob_crc_13_lut_out = AB1_ob_crc_12; AB1_ob_crc_13 = DFFEAS(AB1_ob_crc_13_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_66, , , AB1_a_2); --AB1_nx1398 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|nx1398 --operation mode is normal AB1_nx1398 = BB1_request_data & !AB1_buffer_empty; --GB2_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx21 --operation mode is normal GB2_nx21 = GB2_nx148 # !GB2_state_1 # !GB2_state_0; --GB2_state_inc_736_nx20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx20 --operation mode is arithmetic GB2_state_inc_736_nx20 = CARRY(GB2_state_0); --GB2_b_0_dup_115 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_115 --operation mode is arithmetic GB2_b_0_dup_115_carry_eqn = GB2_state_inc_736_nx24; GB2_b_0_dup_115 = GB2_nx21 & (GB2_state_2 $ !GB2_b_0_dup_115_carry_eqn); --GB2_state_inc_736_nx28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx28 --operation mode is arithmetic GB2_state_inc_736_nx28 = CARRY(GB2_state_2 & (!GB2_state_inc_736_nx24)); --GB2_b_0_dup_111 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_111 --operation mode is arithmetic GB2_b_0_dup_111_carry_eqn = GB2_state_inc_736_nx28; GB2_b_0_dup_111 = GB2_nx21 & (GB2_state_3 $ GB2_b_0_dup_111_carry_eqn); --GB2_state_inc_736_nx32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx32 --operation mode is arithmetic GB2_state_inc_736_nx32 = CARRY(!GB2_state_inc_736_nx28 # !GB2_state_3); --GB2_b_0_dup_107 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_107 --operation mode is arithmetic GB2_b_0_dup_107_carry_eqn = GB2_state_inc_736_nx32; GB2_b_0_dup_107 = GB2_nx21 & (GB2_state_4 $ !GB2_b_0_dup_107_carry_eqn); --GB2_state_inc_736_nx36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_736_nx36 --operation mode is arithmetic GB2_state_inc_736_nx36 = CARRY(GB2_state_4 & (!GB2_state_inc_736_nx32)); --GB2_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0 --operation mode is normal GB2_b_0_carry_eqn = GB2_state_inc_736_nx36; GB2_b_0 = GB2_nx21 & (GB2_state_5 $ GB2_b_0_carry_eqn); --JB2_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|nx18 --operation mode is normal JB2_nx18 = JB2_state_0 # JB2_state_1 # !JB2_state_2; --JB2_state_inc_722_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_inc_722_nx14 --operation mode is arithmetic JB2_state_inc_722_nx14 = CARRY(JB2_state_0); --AB2_ob_data_66 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_66 --operation mode is normal AB2_ob_data_66_lut_out = AB2_ob_data_65; AB2_ob_data_66 = DFFEAS(AB2_ob_data_66_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_66, , , AB2_a_2); --LB2_d_to_dll_67 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_67 --operation mode is normal LB2_d_to_dll_67 = Z2_data_out_67 & (LB2_nx148 # LB2_forward_buffer_59 & LB2_nx151) # !Z2_data_out_67 & LB2_forward_buffer_59 & (LB2_nx151); --Z2_data_out_68 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_68 --operation mode is normal Z2_data_out_68_lut_out = Z2_data_out_67; Z2_data_out_68 = DFFEAS(Z2_data_out_68_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --LB2_nx148 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx148 --operation mode is normal LB2_nx148 = !DB4_data_out_2 & (DB4_data_out_0 # !V1_altered_frame1); --LB2_nx151 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx151 --operation mode is normal LB2_nx151 = V1_altered_frame1 & !DB4_data_out_2 & !DB4_data_out_0; --LB2_d_we is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_we --operation mode is normal LB2_d_we = !DB4_data_out_3 & DB4_data_out_1 & (DB4_data_out_0 # !DB4_data_out_2); --BB2_request_data is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|request_data --operation mode is normal BB2_request_data = !FB2_data_out_2 & FB2_data_out_1 & FB2_data_out_0 & !HB2_stuff_bit_inserted; --AB2_nx119 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|nx119 --operation mode is normal AB2_nx119 = AB2_nx120 # !AB2_bitcounter_5 & !AB2_bitcounter_3 & AB2_nx121; --AB2_ob_crc_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_13 --operation mode is normal AB2_ob_crc_13_lut_out = AB2_ob_crc_12; AB2_ob_crc_13 = DFFEAS(AB2_ob_crc_13_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_66, , , AB2_a_2); --AB2_nx1398 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|nx1398 --operation mode is normal AB2_nx1398 = BB2_request_data & !AB2_buffer_empty; --M1_PQ_9 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_9 --operation mode is normal M1_PQ_9_lut_out = V1_request_22; M1_PQ_9 = DFFEAS(M1_PQ_9_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_8, , , M1_SERREG_1); --R1_RDATA_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_9 --operation mode is normal R1_RDATA_9_lut_out = R1_RDATA_8; R1_RDATA_9 = DFFEAS(R1_RDATA_9_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --R1_fifo_rd is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|fifo_rd --operation mode is normal R1_fifo_rd_lut_out = K1_cmd_adc_1 & K1_cmd_adc_2; R1_fifo_rd = DFFEAS(R1_fifo_rd_lut_out, S1__clk1, VCC, , R1_modgen_select_195_nx4, , , , ); --K1_NOT_climits_a_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_8 --operation mode is normal K1_NOT_climits_a_8_lut_out = !V1_request_23; K1_NOT_climits_a_8 = DFFEAS(K1_NOT_climits_a_8_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_8 --operation mode is normal K1_adc_last_4_8_lut_out = R1_RDATA_8; K1_adc_last_4_8 = DFFEAS(K1_adc_last_4_8_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx44 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx44 --operation mode is arithmetic K1_modgen_gt_268_nx44 = CARRY(K1_NOT_climits_a_7 & !K1_adc_last_4_7 & !K1_modgen_gt_268_nx42 # !K1_NOT_climits_a_7 & (!K1_modgen_gt_268_nx42 # !K1_adc_last_4_7)); --K1_NOT_climits_d_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_8 --operation mode is normal K1_NOT_climits_d_8_lut_out = !V1_request_23; K1_NOT_climits_d_8 = DFFEAS(K1_NOT_climits_d_8_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_8 --operation mode is normal K1_adc_last_6_8_lut_out = R1_RDATA_8; K1_adc_last_6_8 = DFFEAS(K1_adc_last_6_8_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx44 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx44 --operation mode is arithmetic K1_modgen_gt_270_nx44 = CARRY(K1_NOT_climits_d_7 & !K1_adc_last_6_7 & !K1_modgen_gt_270_nx42 # !K1_NOT_climits_d_7 & (!K1_modgen_gt_270_nx42 # !K1_adc_last_6_7)); --K1_NOT_climits_a_20 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_20 --operation mode is normal K1_NOT_climits_a_20_lut_out = K1_NOT_climits_a_20; K1_NOT_climits_a_20 = DFFEAS(K1_NOT_climits_a_20_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L131, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_8 --operation mode is normal K1_adc_last_5_8_lut_out = R1_RDATA_8; K1_adc_last_5_8 = DFFEAS(K1_adc_last_5_8_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx44 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx44 --operation mode is arithmetic K1_modgen_gt_269_nx44 = CARRY(K1_NOT_climits_a_19 & !K1_adc_last_5_7 & !K1_modgen_gt_269_nx42 # !K1_NOT_climits_a_19 & (!K1_modgen_gt_269_nx42 # !K1_adc_last_5_7)); --K1_NOT_climits_d_20 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_20 --operation mode is normal K1_NOT_climits_d_20_lut_out = K1_NOT_climits_d_20; K1_NOT_climits_d_20 = DFFEAS(K1_NOT_climits_d_20_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L131, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_8 --operation mode is normal K1_adc_last_7_8_lut_out = R1_RDATA_8; K1_adc_last_7_8 = DFFEAS(K1_adc_last_7_8_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx44 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx44 --operation mode is arithmetic K1_modgen_gt_271_nx44 = CARRY(K1_NOT_climits_d_19 & !K1_adc_last_7_7 & !K1_modgen_gt_271_nx42 # !K1_NOT_climits_d_19 & (!K1_modgen_gt_271_nx42 # !K1_adc_last_7_7)); --E1_cnt_rst_3 is ni2io_wt:wt_ni|cnt_rst_3 --operation mode is arithmetic E1_cnt_rst_3_carry_eqn = E1_cnt_rst_nx22; E1_cnt_rst_3_lut_out = E1_cnt_rst_3 $ (E1_cnt_rst_3_carry_eqn); E1_cnt_rst_3 = DFFEAS(E1_cnt_rst_3_lut_out, S1__clk1, T1_chipRST_n, , , , , !E1_NOT_rst_start, ); --E1_cnt_rst_nx28 is ni2io_wt:wt_ni|cnt_rst_nx28 --operation mode is arithmetic E1_cnt_rst_nx28 = CARRY(!E1_cnt_rst_nx22 # !E1_cnt_rst_3); --T1_nx403 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx403 --operation mode is normal T1_nx403 = T1_nx425 & (T1_waitcount_5 # T1_waitcount_4 # T1_nx411); --K1_nx984 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx984 --operation mode is normal K1_nx984 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_0) # !V1_request_48 & K1_adc_last_0_0); --K1_nx985 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx985 --operation mode is normal K1_nx985 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_0) # !V1_request_48 & K1_adc_last_4_0); --K1_nx986 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx986 --operation mode is normal K1_nx986 = V1_request_46 & !V1_request_47 & K1_cfr_0; --K1_nx987 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx987 --operation mode is normal K1_nx987 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_0 # !V1_request_48 & (!K1_NOT_climits_a_0)); --Q1_q_b[0] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[0] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[0]_PORT_A_data_in = J1_wdata_ram_0; Q1_q_b[0]_PORT_A_data_in_reg = DFFE(Q1_q_b[0]_PORT_A_data_in, Q1_q_b[0]_clock_0, , , Q1_q_b[0]_clock_enable_0); Q1_q_b[0]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[0]_PORT_A_address_reg = DFFE(Q1_q_b[0]_PORT_A_address, Q1_q_b[0]_clock_0, , , Q1_q_b[0]_clock_enable_0); Q1_q_b[0]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[0]_PORT_B_address_reg = DFFE(Q1_q_b[0]_PORT_B_address, Q1_q_b[0]_clock_1, , , ); Q1_q_b[0]_PORT_A_write_enable = VCC; Q1_q_b[0]_PORT_A_write_enable_reg = DFFE(Q1_q_b[0]_PORT_A_write_enable, Q1_q_b[0]_clock_0, , , Q1_q_b[0]_clock_enable_0); Q1_q_b[0]_PORT_B_read_enable = VCC; Q1_q_b[0]_PORT_B_read_enable_reg = DFFE(Q1_q_b[0]_PORT_B_read_enable, Q1_q_b[0]_clock_1, , , ); Q1_q_b[0]_clock_0 = S1__clk1; Q1_q_b[0]_clock_1 = S1__clk1; Q1_q_b[0]_clock_enable_0 = J1_sm; Q1_q_b[0]_PORT_B_data_out = MEMORY(Q1_q_b[0]_PORT_A_data_in_reg, , Q1_q_b[0]_PORT_A_address_reg, Q1_q_b[0]_PORT_B_address_reg, Q1_q_b[0]_PORT_A_write_enable_reg, Q1_q_b[0]_PORT_B_read_enable_reg, , , Q1_q_b[0]_clock_0, Q1_q_b[0]_clock_1, Q1_q_b[0]_clock_enable_0, , , ); Q1_q_b[0]_PORT_B_data_out_reg = DFFE(Q1_q_b[0]_PORT_B_data_out, Q1_q_b[0]_clock_1, , , ); Q1_q_b[0] = Q1_q_b[0]_PORT_B_data_out_reg[0]; --Q1_q_b[16] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[16] Q1_q_b[0]_PORT_A_data_in = J1_wdata_ram_0; Q1_q_b[0]_PORT_A_data_in_reg = DFFE(Q1_q_b[0]_PORT_A_data_in, Q1_q_b[0]_clock_0, , , Q1_q_b[0]_clock_enable_0); Q1_q_b[0]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[0]_PORT_A_address_reg = DFFE(Q1_q_b[0]_PORT_A_address, Q1_q_b[0]_clock_0, , , Q1_q_b[0]_clock_enable_0); Q1_q_b[0]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[0]_PORT_B_address_reg = DFFE(Q1_q_b[0]_PORT_B_address, Q1_q_b[0]_clock_1, , , ); Q1_q_b[0]_PORT_A_write_enable = VCC; Q1_q_b[0]_PORT_A_write_enable_reg = DFFE(Q1_q_b[0]_PORT_A_write_enable, Q1_q_b[0]_clock_0, , , Q1_q_b[0]_clock_enable_0); Q1_q_b[0]_PORT_B_read_enable = VCC; Q1_q_b[0]_PORT_B_read_enable_reg = DFFE(Q1_q_b[0]_PORT_B_read_enable, Q1_q_b[0]_clock_1, , , ); Q1_q_b[0]_clock_0 = S1__clk1; Q1_q_b[0]_clock_1 = S1__clk1; Q1_q_b[0]_clock_enable_0 = J1_sm; Q1_q_b[0]_PORT_B_data_out = MEMORY(Q1_q_b[0]_PORT_A_data_in_reg, , Q1_q_b[0]_PORT_A_address_reg, Q1_q_b[0]_PORT_B_address_reg, Q1_q_b[0]_PORT_A_write_enable_reg, Q1_q_b[0]_PORT_B_read_enable_reg, , , Q1_q_b[0]_clock_0, Q1_q_b[0]_clock_1, Q1_q_b[0]_clock_enable_0, , , ); Q1_q_b[0]_PORT_B_data_out_reg = DFFE(Q1_q_b[0]_PORT_B_data_out, Q1_q_b[0]_clock_1, , , ); Q1_q_b[16] = Q1_q_b[0]_PORT_B_data_out_reg[1]; --L1_adc_last_0_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_0 --operation mode is normal L1_adc_last_0_0_lut_out = R2_RDATA_0; L1_adc_last_0_0 = DFFEAS(L1_adc_last_0_0_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_0 --operation mode is normal L1_adc_last_2_0_lut_out = R2_RDATA_0; L1_adc_last_2_0 = DFFEAS(L1_adc_last_2_0_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_nx908 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx908 --operation mode is normal L1_nx908 = V1_request_46 # V1_request_47; --L1_adc_last_4_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_0 --operation mode is normal L1_adc_last_4_0_lut_out = R2_RDATA_0; L1_adc_last_4_0 = DFFEAS(L1_adc_last_4_0_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_0 --operation mode is normal L1_adc_last_6_0_lut_out = R2_RDATA_0; L1_adc_last_6_0 = DFFEAS(L1_adc_last_6_0_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_nx907 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx907 --operation mode is normal L1_nx907 = V1_request_46 # !V1_request_47; --L1_cfr_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_0 --operation mode is normal L1_cfr_0_lut_out = V1_request_31; L1_cfr_0 = DFFEAS(L1_cfr_0_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --L1_NOT_climits_d_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_0 --operation mode is normal L1_NOT_climits_d_0_lut_out = !V1_request_31; L1_NOT_climits_d_0 = DFFEAS(L1_NOT_climits_d_0_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_0 --operation mode is normal L1_NOT_climits_a_0_lut_out = !V1_request_31; L1_NOT_climits_a_0 = DFFEAS(L1_NOT_climits_a_0_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --L1_nx910 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx910 --operation mode is normal L1_nx910 = !V1_request_47 # !V1_request_46; --UB1_q_b[0] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[0] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB1_q_b[0]_PORT_A_data_in = RB1_dout_0; UB1_q_b[0]_PORT_A_data_in_reg = DFFE(UB1_q_b[0]_PORT_A_data_in, UB1_q_b[0]_clock_0, UB1_q_b[0]_clear_0, , UB1_q_b[0]_clock_enable_0); UB1_q_b[0]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[0]_PORT_A_address_reg = DFFE(UB1_q_b[0]_PORT_A_address, UB1_q_b[0]_clock_0, UB1_q_b[0]_clear_0, , UB1_q_b[0]_clock_enable_0); UB1_q_b[0]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[0]_PORT_B_address_reg = DFFE(UB1_q_b[0]_PORT_B_address, UB1_q_b[0]_clock_1, , , ); UB1_q_b[0]_PORT_A_write_enable = VCC; UB1_q_b[0]_PORT_A_write_enable_reg = DFFE(UB1_q_b[0]_PORT_A_write_enable, UB1_q_b[0]_clock_0, UB1_q_b[0]_clear_0, , UB1_q_b[0]_clock_enable_0); UB1_q_b[0]_PORT_B_read_enable = VCC; UB1_q_b[0]_PORT_B_read_enable_reg = DFFE(UB1_q_b[0]_PORT_B_read_enable, UB1_q_b[0]_clock_1, , , ); UB1_q_b[0]_clock_0 = !WT_STR; UB1_q_b[0]_clock_1 = S1__clk1; UB1_q_b[0]_clock_enable_0 = PB1_we_p; UB1_q_b[0]_clear_0 = !E1_NOT_clear; UB1_q_b[0]_PORT_B_data_out = MEMORY(UB1_q_b[0]_PORT_A_data_in_reg, , UB1_q_b[0]_PORT_A_address_reg, UB1_q_b[0]_PORT_B_address_reg, UB1_q_b[0]_PORT_A_write_enable_reg, UB1_q_b[0]_PORT_B_read_enable_reg, , , UB1_q_b[0]_clock_0, UB1_q_b[0]_clock_1, UB1_q_b[0]_clock_enable_0, , UB1_q_b[0]_clear_0, ); UB1_q_b[0]_PORT_B_data_out_reg = DFFE(UB1_q_b[0]_PORT_B_data_out, UB1_q_b[0]_clock_1, , , ); UB1_q_b[0] = UB1_q_b[0]_PORT_B_data_out_reg[0]; --UB1_q_b[8] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[8] UB1_q_b[0]_PORT_A_data_in = RB1_dout_0; UB1_q_b[0]_PORT_A_data_in_reg = DFFE(UB1_q_b[0]_PORT_A_data_in, UB1_q_b[0]_clock_0, UB1_q_b[0]_clear_0, , UB1_q_b[0]_clock_enable_0); UB1_q_b[0]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[0]_PORT_A_address_reg = DFFE(UB1_q_b[0]_PORT_A_address, UB1_q_b[0]_clock_0, UB1_q_b[0]_clear_0, , UB1_q_b[0]_clock_enable_0); UB1_q_b[0]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[0]_PORT_B_address_reg = DFFE(UB1_q_b[0]_PORT_B_address, UB1_q_b[0]_clock_1, , , ); UB1_q_b[0]_PORT_A_write_enable = VCC; UB1_q_b[0]_PORT_A_write_enable_reg = DFFE(UB1_q_b[0]_PORT_A_write_enable, UB1_q_b[0]_clock_0, UB1_q_b[0]_clear_0, , UB1_q_b[0]_clock_enable_0); UB1_q_b[0]_PORT_B_read_enable = VCC; UB1_q_b[0]_PORT_B_read_enable_reg = DFFE(UB1_q_b[0]_PORT_B_read_enable, UB1_q_b[0]_clock_1, , , ); UB1_q_b[0]_clock_0 = !WT_STR; UB1_q_b[0]_clock_1 = S1__clk1; UB1_q_b[0]_clock_enable_0 = PB1_we_p; UB1_q_b[0]_clear_0 = !E1_NOT_clear; UB1_q_b[0]_PORT_B_data_out = MEMORY(UB1_q_b[0]_PORT_A_data_in_reg, , UB1_q_b[0]_PORT_A_address_reg, UB1_q_b[0]_PORT_B_address_reg, UB1_q_b[0]_PORT_A_write_enable_reg, UB1_q_b[0]_PORT_B_read_enable_reg, , , UB1_q_b[0]_clock_0, UB1_q_b[0]_clock_1, UB1_q_b[0]_clock_enable_0, , UB1_q_b[0]_clear_0, ); UB1_q_b[0]_PORT_B_data_out_reg = DFFE(UB1_q_b[0]_PORT_B_data_out, UB1_q_b[0]_clock_1, , , ); UB1_q_b[8] = UB1_q_b[0]_PORT_B_data_out_reg[1]; --E1_nx369 is ni2io_wt:wt_ni|nx369 --operation mode is normal E1_nx369 = V1_request_47 # V1_request_48 & (E1_or_mask_0) # !V1_request_48 & E1_sel_s_0; --E1_nx370 is ni2io_wt:wt_ni|nx370 --operation mode is normal E1_nx370 = V1_request_48 & (SB1_Q_0) # !V1_request_48 & SB2_Q_0 # !V1_request_47; --H1_nx213 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx213 --operation mode is normal H1_nx213 = !V1_request_37 & V1_request_38 & !V1_request_39 & V1_request_40; --H1_nx214 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx214 --operation mode is normal H1_nx214 = !V1_request_33 & V1_request_34 & T1_bus_req; --F1_nx835 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx835 --operation mode is normal F1_nx835 = F1_bytes2send_32 & (F1_a_3 # F1_bytes_rcvd_32 & F1_nx787) # !F1_bytes2send_32 & F1_bytes_rcvd_32 & (F1_nx787); --F1_nx836 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx836 --operation mode is normal F1_nx836 = F1_bytes2send_0 & (F1_a_1 # F1_bytes_rcvd_0 & F1_nx785) # !F1_bytes2send_0 & F1_bytes_rcvd_0 & (F1_nx785); --Y1_nx142 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx142 --operation mode is normal Y1_nx142 = !Y1_sync_counter_0; --Y1_NOT_nx210 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|NOT_nx210 --operation mode is normal Y1_NOT_nx210 = Y1_nx87 # Y1_nx101 # Y1_nx85 & Y1_nx103; --Y1_time_in_enable is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|time_in_enable --operation mode is normal Y1_time_in_enable = DB1_data_out_3 & !DB1_data_out_2 & !DB1_data_out_1 & !DB1_data_out_0 # !DB1_data_out_3 & (DB1_data_out_1 # DB1_data_out_2 & DB1_data_out_0); --EB1_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_2 --operation mode is normal EB1_state_2_lut_out = !EB1_nx92 & (EB1_nx94 # EB1_b_1 & EB1_nx93); EB1_state_2 = DFFEAS(EB1_state_2_lut_out, S1__clk0, VCC, , EB1_nx116, , , , ); --EB1_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_0 --operation mode is normal EB1_state_0_lut_out = Y1_time_in_reset_n & (EB1_nx95 # !Y1_time_in_twofwd_n & EB1_nx96); EB1_state_0 = DFFEAS(EB1_state_0_lut_out, S1__clk0, VCC, , EB1_nx116, , , , ); --EB1_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_1 --operation mode is normal EB1_state_1_lut_out = EB1_nx92 # EB1_nx97 # EB1_b_1_dup_64 & EB1_nx93; EB1_state_1 = DFFEAS(EB1_state_1_lut_out, S1__clk0, VCC, , EB1_nx116, , , , ); --Z1_nx280 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx280 --operation mode is normal Z1_nx280 = Z1_bitcounter_3 # Z1_bitcounter_2 & (Z1_bitcounter_1 # Z1_bitcounter_0); --CB1_nx233 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|nx233 --operation mode is normal CB1_nx233 = Y1_s_to_ds & Y1_buffer_flush_n; --Y1_nx140 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx140 --operation mode is normal Y1_nx140_carry_eqn = Y1_result_dec_689_nx18; Y1_nx140 = Y1_sync_counter_2 $ (Y1_nx140_carry_eqn); --Y1_nx141 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx141 --operation mode is arithmetic Y1_nx141_carry_eqn = Y1_result_dec_689_nx14; Y1_nx141 = Y1_sync_counter_1 $ (!Y1_nx141_carry_eqn); --Y1_result_dec_689_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|result_dec_689_nx18 --operation mode is arithmetic Y1_result_dec_689_nx18 = CARRY(!Y1_sync_counter_1 & (!Y1_result_dec_689_nx14)); --CB1_SCLEAR is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|SCLEAR --operation mode is normal CB1_SCLEAR = W1_d0_to_dll $ CB1_data_out # !CB1_nx10 # !Y1_buffer_flush_n; --Y2_nx142 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx142 --operation mode is normal Y2_nx142 = !Y2_sync_counter_0; --Y2_NOT_nx210 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|NOT_nx210 --operation mode is normal Y2_NOT_nx210 = Y2_nx87 # Y2_nx101 # Y2_nx85 & Y2_nx103; --Y2_time_in_enable is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|time_in_enable --operation mode is normal Y2_time_in_enable = DB2_data_out_3 & !DB2_data_out_2 & !DB2_data_out_1 & !DB2_data_out_0 # !DB2_data_out_3 & (DB2_data_out_1 # DB2_data_out_2 & DB2_data_out_0); --EB2_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_2 --operation mode is normal EB2_state_2_lut_out = !EB2_nx92 & (EB2_nx94 # EB2_b_1 & EB2_nx93); EB2_state_2 = DFFEAS(EB2_state_2_lut_out, S1__clk0, VCC, , EB2_nx116, , , , ); --EB2_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_0 --operation mode is normal EB2_state_0_lut_out = Y2_time_in_reset_n & (EB2_nx95 # !Y2_time_in_twofwd_n & EB2_nx96); EB2_state_0 = DFFEAS(EB2_state_0_lut_out, S1__clk0, VCC, , EB2_nx116, , , , ); --EB2_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_1 --operation mode is normal EB2_state_1_lut_out = EB2_nx92 # EB2_nx97 # EB2_b_1_dup_64 & EB2_nx93; EB2_state_1 = DFFEAS(EB2_state_1_lut_out, S1__clk0, VCC, , EB2_nx116, , , , ); --Z2_nx280 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx280 --operation mode is normal Z2_nx280 = Z2_bitcounter_3 # Z2_bitcounter_2 & (Z2_bitcounter_1 # Z2_bitcounter_0); --CB2_nx233 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|nx233 --operation mode is normal CB2_nx233 = Y2_s_to_ds & Y2_buffer_flush_n; --Y2_nx140 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx140 --operation mode is normal Y2_nx140_carry_eqn = Y2_result_dec_689_nx18; Y2_nx140 = Y2_sync_counter_2 $ (Y2_nx140_carry_eqn); --Y2_nx141 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx141 --operation mode is arithmetic Y2_nx141_carry_eqn = Y2_result_dec_689_nx14; Y2_nx141 = Y2_sync_counter_1 $ (!Y2_nx141_carry_eqn); --Y2_result_dec_689_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|result_dec_689_nx18 --operation mode is arithmetic Y2_result_dec_689_nx18 = CARRY(!Y2_sync_counter_1 & (!Y2_result_dec_689_nx14)); --CB2_SCLEAR is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|SCLEAR --operation mode is normal CB2_SCLEAR = W1_d1_to_dll $ CB2_data_out # !CB2_nx10 # !Y2_buffer_flush_n; --Z2_nx278 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx278 --operation mode is normal Z2_nx278 = !Z2_b_crc_11 & !Z2_b_crc_10 & !Z2_b_crc_9 & !Z2_b_crc_8; --Z2_nx282 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx282 --operation mode is normal Z2_nx282 = !Z2_b_crc_15 & !Z2_b_crc_14 & !Z2_b_crc_13 & !Z2_b_crc_12; --Z2_nx283 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx283 --operation mode is normal Z2_nx283 = !Z2_b_crc_1 & !Z2_b_crc_0 & Z2_nx279 & Z2_nx284; --Z2_nx281 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx281 --operation mode is normal Z2_nx281 = Z2_bitcounter_3 # Z2_bitcounter_1 # Z2_bitcounter_0 # Z2_bitcounter_2; --V1_reply1_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|reply1_valid --operation mode is normal V1_reply1_valid = T1_reply_valid & !KB1_data_out_0 & V1_nx221; --Z2_data_out_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_60 --operation mode is normal Z2_data_out_60_lut_out = Z2_data_out_59; Z2_data_out_60 = DFFEAS(Z2_data_out_60_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z2_data_out_59 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_59 --operation mode is normal Z2_data_out_59_lut_out = Z2_data_out_58; Z2_data_out_59 = DFFEAS(Z2_data_out_59_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --LB2_result_inc_871_nx24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_871_nx24 --operation mode is arithmetic LB2_result_inc_871_nx24 = CARRY(Z2_data_out_60); --LB2_nx149 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx149 --operation mode is normal LB2_nx149 = !DB4_data_out_3 & DB4_data_out_1; --LB2_forward_buffer_54 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_54 --operation mode is arithmetic LB2_forward_buffer_54_carry_eqn = LB2_result_inc_871_nx44; LB2_forward_buffer_54 = Z2_data_out_54 $ (!LB2_forward_buffer_54_carry_eqn); --LB2_result_inc_871_nx48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_871_nx48 --operation mode is arithmetic LB2_result_inc_871_nx48 = CARRY(Z2_data_out_54 & (!LB2_result_inc_871_nx44)); --LB2_forward_buffer_53 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_53 --operation mode is normal LB2_forward_buffer_53_carry_eqn = LB2_result_inc_871_nx48; LB2_forward_buffer_53 = Z2_data_out_53 $ (LB2_forward_buffer_53_carry_eqn); --LB2_nx177 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx177 --operation mode is normal LB2_nx177 = LB2_forward_buffer_58 # LB2_forward_buffer_57 # LB2_forward_buffer_56 # LB2_forward_buffer_55; --V1_wait_for_bridge is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|wait_for_bridge --operation mode is normal V1_wait_for_bridge = KB1_data_out_2 $ (KB1_data_out_1 & KB1_data_out_0); --LB2_nx152 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx152 --operation mode is normal LB2_nx152 = DB4_data_out_0 # !DB4_data_out_2; --LB2_nx174 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx174 --operation mode is normal LB2_nx174 = Z2_data_valid & BB2_freeze_buffer & !DB4_data_out_2 & DB4_data_out_0; --LB2_b_dirty is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|b_dirty --operation mode is normal LB2_b_dirty_lut_out = !Z2_data_valid & !U1_buf1_err & !LB2_b_dirty; LB2_b_dirty = DFFEAS(LB2_b_dirty_lut_out, S1__clk0, VCC, , LB2_nx354, , , , ); --LB2_modgen_eq_783_nx24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|modgen_eq_783_nx24 --operation mode is normal LB2_modgen_eq_783_nx24 = LB2_nx162 # !Z2_data_out_66 # !Z2_data_out_67 # !Z2_data_out_68; --LB2_nx143 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx143 --operation mode is normal LB2_nx143 = !DB4_data_out_2 & DB4_data_out_0; --Z2_data_out_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_64 --operation mode is normal Z2_data_out_64_lut_out = Z2_data_out_63; Z2_data_out_64 = DFFEAS(Z2_data_out_64_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z2_data_out_63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_63 --operation mode is normal Z2_data_out_63_lut_out = Z2_data_out_62; Z2_data_out_63 = DFFEAS(Z2_data_out_63_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --LB2_forward_buffer_56 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_56 --operation mode is arithmetic LB2_forward_buffer_56_carry_eqn = LB2_result_inc_871_nx36; LB2_forward_buffer_56 = Z2_data_out_56 $ (!LB2_forward_buffer_56_carry_eqn); --LB2_result_inc_871_nx40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_871_nx40 --operation mode is arithmetic LB2_result_inc_871_nx40 = CARRY(Z2_data_out_56 & (!LB2_result_inc_871_nx36)); --LB2_forward_buffer_55 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_55 --operation mode is arithmetic LB2_forward_buffer_55_carry_eqn = LB2_result_inc_871_nx40; LB2_forward_buffer_55 = Z2_data_out_55 $ (LB2_forward_buffer_55_carry_eqn); --LB2_result_inc_871_nx44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_871_nx44 --operation mode is arithmetic LB2_result_inc_871_nx44 = CARRY(!LB2_result_inc_871_nx40 # !Z2_data_out_55); --Z2_data_out_67 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_67 --operation mode is normal Z2_data_out_67_lut_out = Z2_data_out_66; Z2_data_out_67 = DFFEAS(Z2_data_out_67_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --LB2_modgen_eq_784_nx0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|modgen_eq_784_nx0 --operation mode is normal LB2_modgen_eq_784_nx0 = Z2_data_out_62 $ LB2_forward_buffer_54; --LB2_nx167 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx167 --operation mode is normal LB2_nx167 = Z2_data_out_66 & (Z2_data_out_65 $ LB2_forward_buffer_57 # !LB2_forward_buffer_58) # !Z2_data_out_66 & (LB2_forward_buffer_58 # Z2_data_out_65 $ LB2_forward_buffer_57); --LB2_nx176 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx176 --operation mode is normal LB2_nx176 = !Z2_data_out_61 & !U1_buf1_err & LB2_nx145; --Z2_data_out_58 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_58 --operation mode is normal Z2_data_out_58_lut_out = Z2_data_out_57; Z2_data_out_58 = DFFEAS(Z2_data_out_58_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z2_data_out_57 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_57 --operation mode is normal Z2_data_out_57_lut_out = Z2_data_out_56; Z2_data_out_57 = DFFEAS(Z2_data_out_57_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --LB1_nx153 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx153 --operation mode is normal LB1_nx153 = DB3_data_out_3 & !DB3_data_out_1; --LB1_nx144 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx144 --operation mode is normal LB1_nx144 = !DB3_data_out_3 & !DB3_data_out_1; --Z1_data_valid is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_valid --operation mode is normal Z1_data_valid = Z1_buffer_full & Z1_nx278 & Z1_nx282 & Z1_nx283; --Z1_buffer_half is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|buffer_half --operation mode is normal Z1_buffer_half = Z1_bitcounter_6 & (Z1_bitcounter_5 # Z1_bitcounter_4 & Z1_nx281); --LB1_nx180 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx180 --operation mode is normal LB1_nx180 = !DB3_data_out_0 & (!BB1_freeze_buffer & V1_reply0_valid # !Z1_data_valid); --LB1_nx181 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx181 --operation mode is normal LB1_nx181 = !DB3_data_out_2 & DB3_data_out_0 & (!BB1_freeze_buffer # !Z1_data_valid); --LB1_forward_buffer_59 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_59 --operation mode is arithmetic LB1_forward_buffer_59_carry_eqn = LB1_result_inc_871_nx24; LB1_forward_buffer_59 = Z1_data_out_59 $ (LB1_forward_buffer_59_carry_eqn); --LB1_result_inc_871_nx28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_871_nx28 --operation mode is arithmetic LB1_result_inc_871_nx28 = CARRY(!LB1_result_inc_871_nx24 # !Z1_data_out_59); --LB1_nx158 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx158 --operation mode is normal LB1_nx158 = LB1_nx149 & (BB1_freeze_buffer # !Z1_data_valid & !DB3_data_out_2); --LB1_nx159 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx159 --operation mode is normal LB1_nx159 = !DB3_data_out_0 & LB1_nx149 & (DB3_data_out_2 # !V1_reply0_valid); --LB1_nx161 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx161 --operation mode is normal LB1_nx161 = LB1_nx145 & (LB1_forward_buffer_54 # LB1_forward_buffer_53 # LB1_nx177); --LB1_nx146 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx146 --operation mode is normal LB1_nx146 = !DB3_data_out_2 & !DB3_data_out_0; --LB1_nx172 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx172 --operation mode is normal LB1_nx172 = LB1_nx149 & (LB1_nx174 # !V1_wait_for_bridge & !LB1_nx152); --LB1_nx173 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx173 --operation mode is normal LB1_nx173 = !V1_wait_for_bridge & LB1_b_dirty & (Z1_data_valid # U1_buf0_err); --LB1_nx147 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx147 --operation mode is normal LB1_nx147 = !U1_buf0_err & LB1_modgen_eq_783_nx24 & LB1_nx143 & LB1_nx144; --LB1_nx168 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx168 --operation mode is normal LB1_nx168 = Z1_data_out_64 & (Z1_data_out_63 $ LB1_forward_buffer_55 # !LB1_forward_buffer_56) # !Z1_data_out_64 & (LB1_forward_buffer_56 # Z1_data_out_63 $ LB1_forward_buffer_55); --LB1_nx169 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx169 --operation mode is normal LB1_nx169 = Z1_data_out_68 & (Z1_data_out_67 $ LB1_forward_buffer_59 # !LB1_forward_buffer_60) # !Z1_data_out_68 & (LB1_forward_buffer_60 # Z1_data_out_67 $ LB1_forward_buffer_59); --LB1_nx175 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx175 --operation mode is normal LB1_nx175 = LB1_nx176 # LB1_nx147 & (LB1_modgen_eq_784_nx0 # LB1_nx167); --LB1_forward_buffer_58 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_58 --operation mode is arithmetic LB1_forward_buffer_58_carry_eqn = LB1_result_inc_871_nx28; LB1_forward_buffer_58 = Z1_data_out_58 $ (!LB1_forward_buffer_58_carry_eqn); --LB1_result_inc_871_nx32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_871_nx32 --operation mode is arithmetic LB1_result_inc_871_nx32 = CARRY(Z1_data_out_58 & (!LB1_result_inc_871_nx28)); --LB1_forward_buffer_57 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_57 --operation mode is arithmetic LB1_forward_buffer_57_carry_eqn = LB1_result_inc_871_nx32; LB1_forward_buffer_57 = Z1_data_out_57 $ (LB1_forward_buffer_57_carry_eqn); --LB1_result_inc_871_nx36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_871_nx36 --operation mode is arithmetic LB1_result_inc_871_nx36 = CARRY(!LB1_result_inc_871_nx32 # !Z1_data_out_57); --LB1_nx171 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx171 --operation mode is normal LB1_nx171 = LB1_forward_buffer_56 # LB1_forward_buffer_55 # LB1_forward_buffer_54 # LB1_forward_buffer_53; --LB1_nx154 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx154 --operation mode is normal LB1_nx154 = LB1_nx182 # LB1_nx144 & (Z1_data_valid # !Z1_buffer_half); --F1_nx765 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx765 --operation mode is normal F1_nx765 = F1_sm_sr_4 & (F1_byte_send_3 # F1_bytes2send_28 & F1_nx798) # !F1_sm_sr_4 & F1_bytes2send_28 & (F1_nx798); --F1_nx766 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx766 --operation mode is normal F1_nx766 = F1_bytes2send_44 & (F1_nx794 # F1_bytes2send_20 & F1_nx799) # !F1_bytes2send_44 & F1_bytes2send_20 & (F1_nx799); --F1_nx767 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx767 --operation mode is normal F1_nx767 = F1_bytes2send_36 & (F1_nx796 # F1_iword2send_4 & F1_nx793) # !F1_bytes2send_36 & F1_iword2send_4 & F1_nx793; --F1_nx768 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx768 --operation mode is normal F1_nx768 = F1_bytes2send_12 & (F1_nx795 # F1_bytes2send_4 & F1_nx797) # !F1_bytes2send_12 & F1_bytes2send_4 & (F1_nx797); --K1_cfr_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_8 --operation mode is normal K1_cfr_8_lut_out = V1_request_23; K1_cfr_8 = DFFEAS(K1_cfr_8_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_7 --operation mode is normal R1_datasr_7_lut_out = K1_cfr_7 & (R1_nx94 # R1_datasr_6 & R1_ADC_SCLK) # !K1_cfr_7 & R1_datasr_6 & R1_ADC_SCLK; R1_datasr_7 = DFFEAS(R1_datasr_7_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --G1_modgen_gt_455_nx20 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|modgen_gt_455_nx20 --operation mode is arithmetic G1_modgen_gt_455_nx20 = CARRY(G1_B_0 & G1_nx589); --G2_modgen_gt_455_nx20 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|modgen_gt_455_nx20 --operation mode is arithmetic G2_modgen_gt_455_nx20 = CARRY(G2_B_0 & G2_nx589); --G3_modgen_gt_455_nx20 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|modgen_gt_455_nx20 --operation mode is arithmetic G3_modgen_gt_455_nx20 = CARRY(G3_B_0 & G3_nx589); --Y1_nx94 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx94 --operation mode is normal Y1_nx94 = W1_d0_to_dll & !DB1_data_out_1 & DB1_data_out_0 & !Y1_nx90; --Y1_nx95 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx95 --operation mode is normal Y1_nx95 = !DB1_data_out_2 & Y1_nx84 & !Y1_nx88 # !Y1_time_in_twofwd_n; --Y1_nx97 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx97 --operation mode is normal Y1_nx97 = Y1_nx81 & (Y1_nx85 # Y1_nx89) # !Y1_nx81 & Y1_nx80 & Y1_nx85; --Y1_nx106 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx106 --operation mode is normal Y1_nx106 = Y1_nx91 # Y1_nx96 # !DB1_data_out_0 & Y1_nx82; --Y2_nx94 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx94 --operation mode is normal Y2_nx94 = W1_d1_to_dll & !DB2_data_out_1 & DB2_data_out_0 & !Y2_nx90; --Y2_nx95 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx95 --operation mode is normal Y2_nx95 = !DB2_data_out_2 & Y2_nx84 & !Y2_nx88 # !Y2_time_in_twofwd_n; --Y2_nx97 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx97 --operation mode is normal Y2_nx97 = Y2_nx81 & (Y2_nx85 # Y2_nx89) # !Y2_nx81 & Y2_nx80 & Y2_nx85; --Y2_nx106 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx106 --operation mode is normal Y2_nx106 = Y2_nx91 # Y2_nx96 # !DB2_data_out_0 & Y2_nx82; --G4_modgen_gt_455_nx20 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|modgen_gt_455_nx20 --operation mode is arithmetic G4_modgen_gt_455_nx20 = CARRY(G4_B_0 & G4_nx589); --G1_B_0 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_0 --operation mode is arithmetic G1_B_0_carry_eqn = G1_B_nx56; G1_B_0_lut_out = G1_NOT_nx144 $ (G1_B_0_carry_eqn); G1_B_0 = DFFEAS(G1_B_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G1_B_nx7 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_nx7 --operation mode is arithmetic G1_B_nx7 = CARRY(G1_NOT_nx144 & (G1_NOT_UDn $ G1_B_nx56)); --G1_nx589 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|nx589 --operation mode is normal G1_nx589_lut_out = !V1_request_31; G1_nx589 = DFFEAS(G1_nx589_lut_out, S1__clk1, T1_chipRST_n, , G1_nx12, , , G1_NOT_nx14, ); --G2_B_0 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_0 --operation mode is arithmetic G2_B_0_carry_eqn = G2_B_nx56; G2_B_0_lut_out = G2_NOT_nx144 $ (G2_B_0_carry_eqn); G2_B_0 = DFFEAS(G2_B_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G2_B_nx7 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_nx7 --operation mode is arithmetic G2_B_nx7 = CARRY(G2_NOT_nx144 & (G2_NOT_UDn $ G2_B_nx56)); --G2_nx589 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|nx589 --operation mode is normal G2_nx589_lut_out = !V1_request_23; G2_nx589 = DFFEAS(G2_nx589_lut_out, S1__clk1, T1_chipRST_n, , G2_nx12, , , G2_NOT_nx14, ); --G3_B_0 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_0 --operation mode is arithmetic G3_B_0_carry_eqn = G3_B_nx56; G3_B_0_lut_out = G3_NOT_nx144 $ (G3_B_0_carry_eqn); G3_B_0 = DFFEAS(G3_B_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G3_B_nx7 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_nx7 --operation mode is arithmetic G3_B_nx7 = CARRY(G3_NOT_nx144 & (G3_NOT_UDn $ G3_B_nx56)); --G3_nx589 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|nx589 --operation mode is normal G3_nx589_lut_out = !V1_request_15; G3_nx589 = DFFEAS(G3_nx589_lut_out, S1__clk1, T1_chipRST_n, , G3_nx12, , , G3_NOT_nx14, ); --G4_B_0 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_0 --operation mode is arithmetic G4_B_0_carry_eqn = G4_B_nx56; G4_B_0_lut_out = G4_NOT_nx144 $ (G4_B_0_carry_eqn); G4_B_0 = DFFEAS(G4_B_0_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --G4_B_nx7 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_nx7 --operation mode is arithmetic G4_B_nx7 = CARRY(G4_NOT_nx144 & (G4_NOT_UDn $ G4_B_nx56)); --V1_request_6 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_6 --operation mode is normal V1_request_6 = V1_select_rq & (Z2_data_out_6) # !V1_select_rq & Z1_data_out_6; --G4_nx589 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|nx589 --operation mode is normal G4_nx589_lut_out = !V1_request_7; G4_nx589 = DFFEAS(G4_nx589_lut_out, S1__clk1, T1_chipRST_n, , G4_nx12, , , G4_NOT_nx14, ); --L1_cfr_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_8 --operation mode is normal L1_cfr_8_lut_out = V1_request_23; L1_cfr_8 = DFFEAS(L1_cfr_8_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_7 --operation mode is normal R2_datasr_7_lut_out = L1_cfr_7 & (R2_nx94 # R2_datasr_6 & R2_ADC_SCLK) # !L1_cfr_7 & R2_datasr_6 & R2_ADC_SCLK; R2_datasr_7 = DFFEAS(R2_datasr_7_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --AB1_ob_data_65 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_65 --operation mode is normal AB1_ob_data_65_lut_out = AB1_ob_data_64; AB1_ob_data_65 = DFFEAS(AB1_ob_data_65_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_65, , , AB1_a_2); --LB1_d_to_dll_66 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_66 --operation mode is normal LB1_d_to_dll_66 = Z1_data_out_66 & (LB1_nx148 # LB1_forward_buffer_58 & LB1_nx151) # !Z1_data_out_66 & LB1_forward_buffer_58 & (LB1_nx151); --Z1_data_out_67 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_67 --operation mode is normal Z1_data_out_67_lut_out = Z1_data_out_66; Z1_data_out_67 = DFFEAS(Z1_data_out_67_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z1_data_out_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_60 --operation mode is normal Z1_data_out_60_lut_out = Z1_data_out_59; Z1_data_out_60 = DFFEAS(Z1_data_out_60_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --V1_altered_frame0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|altered_frame0 --operation mode is normal V1_altered_frame0 = T1_altered_frame & KB1_data_out_0 & (!KB1_data_out_1 # !KB1_data_out_2); --AB1_nx120 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|nx120 --operation mode is normal AB1_nx120 = !AB1_bitcounter_5 & !AB1_bitcounter_4 # !AB1_bitcounter_6; --AB1_nx121 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|nx121 --operation mode is normal AB1_nx121 = !AB1_bitcounter_1 & !AB1_bitcounter_0 # !AB1_bitcounter_2; --AB1_ob_crc_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_12 --operation mode is normal AB1_ob_crc_12_lut_out = AB1_ob_crc_11; AB1_ob_crc_12 = DFFEAS(AB1_ob_crc_12_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_65, , , AB1_a_2); --AB2_ob_data_65 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_65 --operation mode is normal AB2_ob_data_65_lut_out = AB2_ob_data_64; AB2_ob_data_65 = DFFEAS(AB2_ob_data_65_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_65, , , AB2_a_2); --LB2_d_to_dll_66 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_66 --operation mode is normal LB2_d_to_dll_66 = Z2_data_out_66 & (LB2_nx148 # LB2_forward_buffer_58 & LB2_nx151) # !Z2_data_out_66 & LB2_forward_buffer_58 & (LB2_nx151); --V1_altered_frame1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|altered_frame1 --operation mode is normal V1_altered_frame1 = T1_altered_frame & !KB1_data_out_0 & (KB1_data_out_2 # KB1_data_out_1); --AB2_nx120 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|nx120 --operation mode is normal AB2_nx120 = !AB2_bitcounter_5 & !AB2_bitcounter_4 # !AB2_bitcounter_6; --AB2_nx121 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|nx121 --operation mode is normal AB2_nx121 = !AB2_bitcounter_1 & !AB2_bitcounter_0 # !AB2_bitcounter_2; --AB2_ob_crc_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_12 --operation mode is normal AB2_ob_crc_12_lut_out = AB2_ob_crc_11; AB2_ob_crc_12 = DFFEAS(AB2_ob_crc_12_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_65, , , AB2_a_2); --M1_PQ_8 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_8 --operation mode is normal M1_PQ_8_lut_out = V1_request_23; M1_PQ_8 = DFFEAS(M1_PQ_8_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_7, , , M1_SERREG_1); --R1_RDATA_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_8 --operation mode is normal R1_RDATA_8_lut_out = R1_RDATA_7; R1_RDATA_8 = DFFEAS(R1_RDATA_8_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_NOT_climits_a_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_7 --operation mode is normal K1_NOT_climits_a_7_lut_out = !V1_request_24; K1_NOT_climits_a_7 = DFFEAS(K1_NOT_climits_a_7_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_7 --operation mode is normal K1_adc_last_4_7_lut_out = R1_RDATA_7; K1_adc_last_4_7 = DFFEAS(K1_adc_last_4_7_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx42 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx42 --operation mode is arithmetic K1_modgen_gt_268_nx42 = CARRY(K1_NOT_climits_a_6 & (K1_adc_last_4_6 # !K1_modgen_gt_268_nx40) # !K1_NOT_climits_a_6 & K1_adc_last_4_6 & !K1_modgen_gt_268_nx40); --K1_NOT_climits_d_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_7 --operation mode is normal K1_NOT_climits_d_7_lut_out = !V1_request_24; K1_NOT_climits_d_7 = DFFEAS(K1_NOT_climits_d_7_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_7 --operation mode is normal K1_adc_last_6_7_lut_out = R1_RDATA_7; K1_adc_last_6_7 = DFFEAS(K1_adc_last_6_7_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx42 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx42 --operation mode is arithmetic K1_modgen_gt_270_nx42 = CARRY(K1_NOT_climits_d_6 & (K1_adc_last_6_6 # !K1_modgen_gt_270_nx40) # !K1_NOT_climits_d_6 & K1_adc_last_6_6 & !K1_modgen_gt_270_nx40); --K1_NOT_climits_a_19 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_19 --operation mode is normal K1_NOT_climits_a_19_lut_out = K1_NOT_climits_a_19; K1_NOT_climits_a_19 = DFFEAS(K1_NOT_climits_a_19_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L331, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_7 --operation mode is normal K1_adc_last_5_7_lut_out = R1_RDATA_7; K1_adc_last_5_7 = DFFEAS(K1_adc_last_5_7_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx42 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx42 --operation mode is arithmetic K1_modgen_gt_269_nx42 = CARRY(K1_NOT_climits_a_18 & (K1_adc_last_5_6 # !K1_modgen_gt_269_nx40) # !K1_NOT_climits_a_18 & K1_adc_last_5_6 & !K1_modgen_gt_269_nx40); --K1_NOT_climits_d_19 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_19 --operation mode is normal K1_NOT_climits_d_19_lut_out = K1_NOT_climits_d_19; K1_NOT_climits_d_19 = DFFEAS(K1_NOT_climits_d_19_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L331, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_7 --operation mode is normal K1_adc_last_7_7_lut_out = R1_RDATA_7; K1_adc_last_7_7 = DFFEAS(K1_adc_last_7_7_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx42 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx42 --operation mode is arithmetic K1_modgen_gt_271_nx42 = CARRY(K1_NOT_climits_d_18 & (K1_adc_last_7_6 # !K1_modgen_gt_271_nx40) # !K1_NOT_climits_d_18 & K1_adc_last_7_6 & !K1_modgen_gt_271_nx40); --E1_cnt_rst_2 is ni2io_wt:wt_ni|cnt_rst_2 --operation mode is arithmetic E1_cnt_rst_2_carry_eqn = E1_cnt_rst_nx16; E1_cnt_rst_2_lut_out = E1_cnt_rst_2 $ (!E1_cnt_rst_2_carry_eqn); E1_cnt_rst_2 = DFFEAS(E1_cnt_rst_2_lut_out, S1__clk1, T1_chipRST_n, , , , , !E1_NOT_rst_start, ); --E1_cnt_rst_nx22 is ni2io_wt:wt_ni|cnt_rst_nx22 --operation mode is arithmetic E1_cnt_rst_nx22 = CARRY(E1_cnt_rst_2 & (!E1_cnt_rst_nx16)); --T1_nx425 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx425 --operation mode is normal T1_nx425 = !X1_data_out_3 & X1_data_out_0 & (X1_data_out_2 # X1_data_out_1); --K1_adc_last_0_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_0 --operation mode is normal K1_adc_last_0_0_lut_out = R1_RDATA_0; K1_adc_last_0_0 = DFFEAS(K1_adc_last_0_0_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_0 --operation mode is normal K1_adc_last_2_0_lut_out = R1_RDATA_0; K1_adc_last_2_0 = DFFEAS(K1_adc_last_2_0_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --K1_nx991 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx991 --operation mode is normal K1_nx991 = V1_request_46 # V1_request_47; --K1_adc_last_4_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_0 --operation mode is normal K1_adc_last_4_0_lut_out = R1_RDATA_0; K1_adc_last_4_0 = DFFEAS(K1_adc_last_4_0_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_adc_last_6_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_0 --operation mode is normal K1_adc_last_6_0_lut_out = R1_RDATA_0; K1_adc_last_6_0 = DFFEAS(K1_adc_last_6_0_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_nx990 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx990 --operation mode is normal K1_nx990 = V1_request_46 # !V1_request_47; --K1_cfr_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_0 --operation mode is normal K1_cfr_0_lut_out = V1_request_31; K1_cfr_0 = DFFEAS(K1_cfr_0_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --K1_NOT_climits_d_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_0 --operation mode is normal K1_NOT_climits_d_0_lut_out = !V1_request_31; K1_NOT_climits_d_0 = DFFEAS(K1_NOT_climits_d_0_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_NOT_climits_a_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_0 --operation mode is normal K1_NOT_climits_a_0_lut_out = !V1_request_31; K1_NOT_climits_a_0 = DFFEAS(K1_NOT_climits_a_0_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --J1_wdata_ram_0 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_0 --operation mode is normal J1_wdata_ram_0_lut_out = PAADC_D[0]; J1_wdata_ram_0 = DFFEAS(J1_wdata_ram_0_lut_out, S1__clk1, VCC, , , , , , ); --V1_request_45 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_45 --operation mode is normal V1_request_45 = V1_select_rq & (Z2_data_out_45) # !V1_select_rq & Z1_data_out_45; --V1_request_44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_44 --operation mode is normal V1_request_44 = V1_select_rq & (Z2_data_out_44) # !V1_select_rq & Z1_data_out_44; --V1_request_43 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_43 --operation mode is normal V1_request_43 = V1_select_rq & (Z2_data_out_43) # !V1_select_rq & Z1_data_out_43; --R2_RDATA_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_0 --operation mode is normal R2_RDATA_0_lut_out = SC_ADC_SDO; R2_RDATA_0 = DFFEAS(R2_RDATA_0_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --L1_NOT_nx2189 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx2189 --operation mode is normal L1_NOT_nx2189 = L1_sm_4 & !L1_counter_2 & !L1_counter_1 & !L1_counter_0; --L1_NOT_nx2237 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx2237 --operation mode is normal L1_NOT_nx2237 = L1_sm_4 & !L1_counter_2 & L1_counter_1 & !L1_counter_0; --L1_NOT_nx2285 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx2285 --operation mode is normal L1_NOT_nx2285 = L1_sm_4 & L1_counter_2 & !L1_counter_1 & !L1_counter_0; --L1_NOT_nx2333 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx2333 --operation mode is normal L1_NOT_nx2333 = L1_sm_4 & L1_counter_2 & L1_counter_1 & !L1_counter_0; --L1_NOT_nx462 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx462 --operation mode is normal L1_NOT_nx462 = H1_ce_sc_adc & !T1_rd_wr_oase & V1_request_48 & !L1_nx910; --L1_NOT_nx510 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx510 --operation mode is normal L1_NOT_nx510 = H1_ce_sc_adc & !T1_rd_wr_oase & !V1_request_48 & !L1_nx910; --PB1_we_p is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|we_p --operation mode is normal PB1_we_p_lut_out = !PB1_NOT_we_p_r & (PB1_nx48 # PB1_nx49 # PB1_nx50); PB1_we_p = DFFEAS(PB1_we_p_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --E1_NOT_clear is ni2io_wt:wt_ni|NOT_clear --operation mode is normal E1_NOT_clear_lut_out = T1_rd_wr_oase # V1_request_48 # !V1_request_47 # !H1_ce_wtnip4; E1_NOT_clear = DFFEAS(E1_NOT_clear_lut_out, S1__clk1, T1_chipRST_n, , , , , , ); --RB1_dout_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|dout_0 --operation mode is normal RB1_dout_0 = RB1_modgen_gt_34_nx56 & (RB1_q1pass_0) # !RB1_modgen_gt_34_nx56 & RB1_q1pass_1; --SB2_Q_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_0 --operation mode is arithmetic SB2_Q_0_lut_out = SB2_Q_0 $ PB1_we_p; SB2_Q_0 = DFFEAS(SB2_Q_0_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx10 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx10 --operation mode is arithmetic SB2_Q_nx10 = CARRY(SB2_Q_0 & PB1_we_p); --SB2_Q_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_1 --operation mode is arithmetic SB2_Q_1_carry_eqn = SB2_Q_nx10; SB2_Q_1_lut_out = SB2_Q_1 $ (SB2_Q_1_carry_eqn); SB2_Q_1 = DFFEAS(SB2_Q_1_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx16 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx16 --operation mode is arithmetic SB2_Q_nx16 = CARRY(!SB2_Q_nx10 # !SB2_Q_1); --SB2_Q_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_2 --operation mode is arithmetic SB2_Q_2_carry_eqn = SB2_Q_nx16; SB2_Q_2_lut_out = SB2_Q_2 $ (!SB2_Q_2_carry_eqn); SB2_Q_2 = DFFEAS(SB2_Q_2_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx22 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx22 --operation mode is arithmetic SB2_Q_nx22 = CARRY(SB2_Q_2 & (!SB2_Q_nx16)); --SB2_Q_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_3 --operation mode is arithmetic SB2_Q_3_carry_eqn = SB2_Q_nx22; SB2_Q_3_lut_out = SB2_Q_3 $ (SB2_Q_3_carry_eqn); SB2_Q_3 = DFFEAS(SB2_Q_3_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx28 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx28 --operation mode is arithmetic SB2_Q_nx28 = CARRY(!SB2_Q_nx22 # !SB2_Q_3); --SB2_Q_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_4 --operation mode is arithmetic SB2_Q_4_carry_eqn = SB2_Q_nx28; SB2_Q_4_lut_out = SB2_Q_4 $ (!SB2_Q_4_carry_eqn); SB2_Q_4 = DFFEAS(SB2_Q_4_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx34 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx34 --operation mode is arithmetic SB2_Q_nx34 = CARRY(SB2_Q_4 & (!SB2_Q_nx28)); --SB2_Q_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_5 --operation mode is arithmetic SB2_Q_5_carry_eqn = SB2_Q_nx34; SB2_Q_5_lut_out = SB2_Q_5 $ (SB2_Q_5_carry_eqn); SB2_Q_5 = DFFEAS(SB2_Q_5_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx40 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx40 --operation mode is arithmetic SB2_Q_nx40 = CARRY(!SB2_Q_nx34 # !SB2_Q_5); --SB2_Q_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_6 --operation mode is arithmetic SB2_Q_6_carry_eqn = SB2_Q_nx40; SB2_Q_6_lut_out = SB2_Q_6 $ (!SB2_Q_6_carry_eqn); SB2_Q_6 = DFFEAS(SB2_Q_6_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx44 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx44 --operation mode is arithmetic SB2_Q_nx44 = CARRY(SB2_Q_6 & (!SB2_Q_nx40)); --SB2_Q_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_7 --operation mode is arithmetic SB2_Q_7_carry_eqn = SB2_Q_nx44; SB2_Q_7_lut_out = SB2_Q_7 $ (SB2_Q_7_carry_eqn); SB2_Q_7 = DFFEAS(SB2_Q_7_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx48 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx48 --operation mode is arithmetic SB2_Q_nx48 = CARRY(!SB2_Q_nx44 # !SB2_Q_7); --SB2_Q_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_8 --operation mode is arithmetic SB2_Q_8_carry_eqn = SB2_Q_nx48; SB2_Q_8_lut_out = SB2_Q_8 $ (!SB2_Q_8_carry_eqn); SB2_Q_8 = DFFEAS(SB2_Q_8_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx52 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx52 --operation mode is arithmetic SB2_Q_nx52 = CARRY(SB2_Q_8 & (!SB2_Q_nx48)); --SB2_Q_9 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_9 --operation mode is arithmetic SB2_Q_9_carry_eqn = SB2_Q_nx52; SB2_Q_9_lut_out = SB2_Q_9 $ (SB2_Q_9_carry_eqn); SB2_Q_9 = DFFEAS(SB2_Q_9_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx57 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx57 --operation mode is arithmetic SB2_Q_nx57 = CARRY(!SB2_Q_nx52 # !SB2_Q_9); --SB2_Q_10 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_10 --operation mode is arithmetic SB2_Q_10_carry_eqn = SB2_Q_nx57; SB2_Q_10_lut_out = SB2_Q_10 $ (!SB2_Q_10_carry_eqn); SB2_Q_10 = DFFEAS(SB2_Q_10_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB2_Q_nx61 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_nx61 --operation mode is arithmetic SB2_Q_nx61 = CARRY(SB2_Q_10 & (!SB2_Q_nx57)); --SB2_Q_11 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:wa_p|Q_11 --operation mode is normal SB2_Q_11_carry_eqn = SB2_Q_nx61; SB2_Q_11_lut_out = SB2_Q_11 $ (SB2_Q_11_carry_eqn); SB2_Q_11 = DFFEAS(SB2_Q_11_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --E1_sel_s_0 is ni2io_wt:wt_ni|sel_s_0 --operation mode is normal E1_sel_s_0_lut_out = E1_sel_s_0; E1_sel_s_0 = DFFEAS(E1_sel_s_0_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_31, , , E1_nx398); --E1_or_mask_0 is ni2io_wt:wt_ni|or_mask_0 --operation mode is normal E1_or_mask_0_lut_out = E1_or_mask_0; E1_or_mask_0 = DFFEAS(E1_or_mask_0_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_31, , , E1_nx399); --SB1_Q_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_0 --operation mode is arithmetic SB1_Q_0_lut_out = SB1_Q_0 $ PB1_par_en; SB1_Q_0 = DFFEAS(SB1_Q_0_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx10 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx10 --operation mode is arithmetic SB1_Q_nx10 = CARRY(SB1_Q_0 & PB1_par_en); --F1_bytes2send_32 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_32 --operation mode is normal F1_bytes2send_32_lut_out = V1_request_31; F1_bytes2send_32 = DFFEAS(F1_bytes2send_32_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx479, , , , ); --F1_bytes_rcvd_32 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_32 --operation mode is normal F1_bytes_rcvd_32_lut_out = F1_nx2247; F1_bytes_rcvd_32 = DFFEAS(F1_bytes_rcvd_32_lut_out, S1__clk1, VCC, , F1_NOT_nx2121, , , , ); --F1_nx787 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx787 --operation mode is normal F1_nx787 = !V1_request_46 & V1_request_47 & V1_request_48; --F1_bytes2send_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_0 --operation mode is normal F1_bytes2send_0_lut_out = V1_request_31; F1_bytes2send_0 = DFFEAS(F1_bytes2send_0_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx543, , , , ); --F1_bytes_rcvd_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_0 --operation mode is normal F1_bytes_rcvd_0_lut_out = F1_nx2247; F1_bytes_rcvd_0 = DFFEAS(F1_bytes_rcvd_0_lut_out, S1__clk1, VCC, , F1_NOT_nx2249, , , , ); --F1_nx785 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx785 --operation mode is normal F1_nx785 = !V1_request_46 & V1_request_47 & !V1_request_48; --Y1_nx87 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx87 --operation mode is normal Y1_nx87 = !DB1_data_out_2 & !DB1_data_out_1 & !DB1_data_out_0; --Y1_nx101 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx101 --operation mode is normal Y1_nx101 = !DB1_data_out_3 & !DB1_data_out_0 & (!DB1_data_out_1 # !DB1_data_out_2); --Y1_nx103 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx103 --operation mode is normal Y1_nx103 = Y1_sync_counter_2 # Y1_sync_counter_1 # Y1_sync_counter_0; --EB1_b_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|b_1 --operation mode is normal EB1_b_1_carry_eqn = EB1_state_inc_653_nx18; EB1_b_1 = EB1_nx18 & (EB1_state_2 $ !EB1_b_1_carry_eqn); --EB1_nx92 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx92 --operation mode is normal EB1_nx92 = !Y1_time_in_hotreset_n # !Y1_time_in_reset_n; --EB1_nx93 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx93 --operation mode is normal EB1_nx93 = Y1_time_in_enable & Y1_time_in_twofwd_n; --EB1_nx94 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx94 --operation mode is normal EB1_nx94 = !Y1_time_in_twofwd_n & !EB1_state_2 & !EB1_state_0 & EB1_state_1; --EB1_nx116 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx116 --operation mode is normal EB1_nx116 = Y1_time_in_enable # !Y1_time_in_twofwd_n # !Y1_time_in_hotreset_n # !Y1_time_in_reset_n; --Y1_time_in_reset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|time_in_reset_n --operation mode is normal Y1_time_in_reset_n = DB1_data_out_3 # DB1_data_out_2 # DB1_data_out_1 # DB1_data_out_0; --EB1_nx95 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx95 --operation mode is normal EB1_nx95 = Y1_time_in_enable & Y1_time_in_twofwd_n & EB1_b_0 # !Y1_time_in_hotreset_n; --EB1_nx96 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx96 --operation mode is normal EB1_nx96 = !EB1_state_1 & (EB1_state_2 $ EB1_state_0); --EB1_b_1_dup_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|b_1_dup_64 --operation mode is arithmetic EB1_b_1_dup_64_carry_eqn = EB1_state_inc_653_nx14; EB1_b_1_dup_64 = EB1_nx18 & (EB1_state_1 $ EB1_b_1_dup_64_carry_eqn); --EB1_state_inc_653_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_inc_653_nx18 --operation mode is arithmetic EB1_state_inc_653_nx18 = CARRY(!EB1_state_inc_653_nx14 # !EB1_state_1); --EB1_nx97 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx97 --operation mode is normal EB1_nx97 = !Y1_time_in_twofwd_n & !EB1_state_2 & !EB1_state_1; --Y1_result_dec_689_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|result_dec_689_nx14 --operation mode is arithmetic Y1_result_dec_689_nx14 = CARRY(Y1_sync_counter_0); --Y2_nx87 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx87 --operation mode is normal Y2_nx87 = !DB2_data_out_2 & !DB2_data_out_1 & !DB2_data_out_0; --Y2_nx101 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx101 --operation mode is normal Y2_nx101 = !DB2_data_out_3 & !DB2_data_out_0 & (!DB2_data_out_1 # !DB2_data_out_2); --Y2_nx103 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx103 --operation mode is normal Y2_nx103 = Y2_sync_counter_2 # Y2_sync_counter_1 # Y2_sync_counter_0; --EB2_b_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|b_1 --operation mode is normal EB2_b_1_carry_eqn = EB2_state_inc_653_nx18; EB2_b_1 = EB2_nx18 & (EB2_state_2 $ !EB2_b_1_carry_eqn); --EB2_nx92 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx92 --operation mode is normal EB2_nx92 = !Y2_time_in_hotreset_n # !Y2_time_in_reset_n; --EB2_nx93 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx93 --operation mode is normal EB2_nx93 = Y2_time_in_enable & Y2_time_in_twofwd_n; --EB2_nx94 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx94 --operation mode is normal EB2_nx94 = !Y2_time_in_twofwd_n & !EB2_state_2 & !EB2_state_0 & EB2_state_1; --EB2_nx116 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx116 --operation mode is normal EB2_nx116 = Y2_time_in_enable # !Y2_time_in_twofwd_n # !Y2_time_in_hotreset_n # !Y2_time_in_reset_n; --Y2_time_in_reset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|time_in_reset_n --operation mode is normal Y2_time_in_reset_n = DB2_data_out_3 # DB2_data_out_2 # DB2_data_out_1 # DB2_data_out_0; --EB2_nx95 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx95 --operation mode is normal EB2_nx95 = Y2_time_in_enable & Y2_time_in_twofwd_n & EB2_b_0 # !Y2_time_in_hotreset_n; --EB2_nx96 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx96 --operation mode is normal EB2_nx96 = !EB2_state_1 & (EB2_state_2 $ EB2_state_0); --EB2_b_1_dup_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|b_1_dup_64 --operation mode is arithmetic EB2_b_1_dup_64_carry_eqn = EB2_state_inc_653_nx14; EB2_b_1_dup_64 = EB2_nx18 & (EB2_state_1 $ EB2_b_1_dup_64_carry_eqn); --EB2_state_inc_653_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_inc_653_nx18 --operation mode is arithmetic EB2_state_inc_653_nx18 = CARRY(!EB2_state_inc_653_nx14 # !EB2_state_1); --EB2_nx97 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx97 --operation mode is normal EB2_nx97 = !Y2_time_in_twofwd_n & !EB2_state_2 & !EB2_state_1; --Y2_result_dec_689_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|result_dec_689_nx14 --operation mode is arithmetic Y2_result_dec_689_nx14 = CARRY(Y2_sync_counter_0); --Z2_b_crc_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_11 --operation mode is normal Z2_b_crc_11_lut_out = Y2_buffer_flush_n & Z2_b_crc_10; Z2_b_crc_11 = DFFEAS(Z2_b_crc_11_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_10 --operation mode is normal Z2_b_crc_10_lut_out = Y2_buffer_flush_n & Z2_b_crc_9; Z2_b_crc_10 = DFFEAS(Z2_b_crc_10_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_9 --operation mode is normal Z2_b_crc_9_lut_out = Y2_buffer_flush_n & Z2_b_crc_8; Z2_b_crc_9 = DFFEAS(Z2_b_crc_9_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_8 --operation mode is normal Z2_b_crc_8_lut_out = Y2_buffer_flush_n & Z2_b_crc_7; Z2_b_crc_8 = DFFEAS(Z2_b_crc_8_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_15 --operation mode is normal Z2_b_crc_15_lut_out = Z2_b_crc_15 $ Z2_b_crc_14; Z2_b_crc_15 = DFFEAS(Z2_b_crc_15_lut_out, S1__clk0, VCC, , Z2_nx1520, , , !Y2_buffer_flush_n, ); --Z2_b_crc_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_14 --operation mode is normal Z2_b_crc_14_lut_out = Y2_buffer_flush_n & Z2_b_crc_13; Z2_b_crc_14 = DFFEAS(Z2_b_crc_14_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_13 --operation mode is normal Z2_b_crc_13_lut_out = Y2_buffer_flush_n & Z2_b_crc_12; Z2_b_crc_13 = DFFEAS(Z2_b_crc_13_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_12 --operation mode is normal Z2_b_crc_12_lut_out = Y2_buffer_flush_n & Z2_b_crc_11; Z2_b_crc_12 = DFFEAS(Z2_b_crc_12_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_1 --operation mode is normal Z2_b_crc_1_lut_out = Y2_buffer_flush_n & Z2_b_crc_0; Z2_b_crc_1 = DFFEAS(Z2_b_crc_1_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_0 --operation mode is normal Z2_b_crc_0_lut_out = CB2_data_out $ Z2_b_crc_15; Z2_b_crc_0 = DFFEAS(Z2_b_crc_0_lut_out, S1__clk0, VCC, , Z2_nx1520, , , !Y2_buffer_flush_n, ); --Z2_nx279 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx279 --operation mode is normal Z2_nx279 = !Z2_b_crc_7 & !Z2_b_crc_6 & !Z2_b_crc_5 & !Z2_b_crc_4; --Z2_nx284 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx284 --operation mode is normal Z2_nx284 = !Z2_b_crc_3 & !Z2_b_crc_2; --T1_reply_valid is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_valid --operation mode is normal T1_reply_valid = !X1_data_out_0 & (X1_data_out_3 $ (X1_data_out_2 # X1_data_out_1)); --V1_nx221 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx221 --operation mode is normal V1_nx221 = KB1_data_out_2 & (KB1_data_out_1 & (V1_nx818) # !KB1_data_out_1 & !T1_bridge_alter) # !KB1_data_out_2 & !T1_bridge_alter & KB1_data_out_1; --Z2_data_out_54 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_54 --operation mode is normal Z2_data_out_54_lut_out = Z2_data_out_53; Z2_data_out_54 = DFFEAS(Z2_data_out_54_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z2_data_out_53 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_53 --operation mode is normal Z2_data_out_53_lut_out = Z2_data_out_52; Z2_data_out_53 = DFFEAS(Z2_data_out_53_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --LB2_nx354 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx354 --operation mode is normal LB2_nx354 = LB2_b_dirty & LB2_nx145 & (Z2_data_valid # U1_buf1_err) # !LB2_b_dirty & !Z2_data_valid & !U1_buf1_err; --Z2_data_out_66 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_66 --operation mode is normal Z2_data_out_66_lut_out = Z2_data_out_65; Z2_data_out_66 = DFFEAS(Z2_data_out_66_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --LB2_nx162 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx162 --operation mode is normal LB2_nx162 = !Z2_data_out_62 # !Z2_data_out_63 # !Z2_data_out_64 # !Z2_data_out_65; --Z2_data_out_62 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_62 --operation mode is normal Z2_data_out_62_lut_out = Z2_data_out_61; Z2_data_out_62 = DFFEAS(Z2_data_out_62_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z2_data_out_56 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_56 --operation mode is normal Z2_data_out_56_lut_out = Z2_data_out_55; Z2_data_out_56 = DFFEAS(Z2_data_out_56_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z2_data_out_55 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_55 --operation mode is normal Z2_data_out_55_lut_out = Z2_data_out_54; Z2_data_out_55 = DFFEAS(Z2_data_out_55_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z2_data_out_65 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_65 --operation mode is normal Z2_data_out_65_lut_out = Z2_data_out_64; Z2_data_out_65 = DFFEAS(Z2_data_out_65_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z2_data_out_61 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_61 --operation mode is normal Z2_data_out_61_lut_out = Z2_data_out_60; Z2_data_out_61 = DFFEAS(Z2_data_out_61_lut_out, S1__clk0, VCC, , Z2_NOT_nx676, , , !Y2_buffer_flush_n, ); --Z1_nx278 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx278 --operation mode is normal Z1_nx278 = !Z1_b_crc_11 & !Z1_b_crc_10 & !Z1_b_crc_9 & !Z1_b_crc_8; --Z1_nx282 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx282 --operation mode is normal Z1_nx282 = !Z1_b_crc_15 & !Z1_b_crc_14 & !Z1_b_crc_13 & !Z1_b_crc_12; --Z1_nx283 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx283 --operation mode is normal Z1_nx283 = !Z1_b_crc_1 & !Z1_b_crc_0 & Z1_nx279 & Z1_nx284; --Z1_nx281 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx281 --operation mode is normal Z1_nx281 = Z1_bitcounter_3 # Z1_bitcounter_1 # Z1_bitcounter_0 # Z1_bitcounter_2; --V1_reply0_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|reply0_valid --operation mode is normal V1_reply0_valid = T1_reply_valid & KB1_data_out_0 & (V1_nx234 # V1_nx235); --Z1_data_out_59 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_59 --operation mode is normal Z1_data_out_59_lut_out = Z1_data_out_58; Z1_data_out_59 = DFFEAS(Z1_data_out_59_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --LB1_result_inc_871_nx24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_871_nx24 --operation mode is arithmetic LB1_result_inc_871_nx24 = CARRY(Z1_data_out_60); --LB1_nx149 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx149 --operation mode is normal LB1_nx149 = !DB3_data_out_3 & DB3_data_out_1; --LB1_forward_buffer_54 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_54 --operation mode is arithmetic LB1_forward_buffer_54_carry_eqn = LB1_result_inc_871_nx44; LB1_forward_buffer_54 = Z1_data_out_54 $ (!LB1_forward_buffer_54_carry_eqn); --LB1_result_inc_871_nx48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_871_nx48 --operation mode is arithmetic LB1_result_inc_871_nx48 = CARRY(Z1_data_out_54 & (!LB1_result_inc_871_nx44)); --LB1_forward_buffer_53 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_53 --operation mode is normal LB1_forward_buffer_53_carry_eqn = LB1_result_inc_871_nx48; LB1_forward_buffer_53 = Z1_data_out_53 $ (LB1_forward_buffer_53_carry_eqn); --LB1_nx177 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx177 --operation mode is normal LB1_nx177 = LB1_forward_buffer_58 # LB1_forward_buffer_57 # LB1_forward_buffer_56 # LB1_forward_buffer_55; --LB1_nx152 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx152 --operation mode is normal LB1_nx152 = DB3_data_out_0 # !DB3_data_out_2; --LB1_nx174 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx174 --operation mode is normal LB1_nx174 = Z1_data_valid & BB1_freeze_buffer & !DB3_data_out_2 & DB3_data_out_0; --LB1_b_dirty is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|b_dirty --operation mode is normal LB1_b_dirty_lut_out = !Z1_data_valid & !U1_buf0_err & !LB1_b_dirty; LB1_b_dirty = DFFEAS(LB1_b_dirty_lut_out, S1__clk0, VCC, , LB1_nx354, , , , ); --LB1_modgen_eq_783_nx24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|modgen_eq_783_nx24 --operation mode is normal LB1_modgen_eq_783_nx24 = LB1_nx162 # !Z1_data_out_66 # !Z1_data_out_67 # !Z1_data_out_68; --LB1_nx143 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx143 --operation mode is normal LB1_nx143 = !DB3_data_out_2 & DB3_data_out_0; --Z1_data_out_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_64 --operation mode is normal Z1_data_out_64_lut_out = Z1_data_out_63; Z1_data_out_64 = DFFEAS(Z1_data_out_64_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z1_data_out_63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_63 --operation mode is normal Z1_data_out_63_lut_out = Z1_data_out_62; Z1_data_out_63 = DFFEAS(Z1_data_out_63_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --LB1_forward_buffer_56 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_56 --operation mode is arithmetic LB1_forward_buffer_56_carry_eqn = LB1_result_inc_871_nx36; LB1_forward_buffer_56 = Z1_data_out_56 $ (!LB1_forward_buffer_56_carry_eqn); --LB1_result_inc_871_nx40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_871_nx40 --operation mode is arithmetic LB1_result_inc_871_nx40 = CARRY(Z1_data_out_56 & (!LB1_result_inc_871_nx36)); --LB1_forward_buffer_55 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_55 --operation mode is arithmetic LB1_forward_buffer_55_carry_eqn = LB1_result_inc_871_nx40; LB1_forward_buffer_55 = Z1_data_out_55 $ (LB1_forward_buffer_55_carry_eqn); --LB1_result_inc_871_nx44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_871_nx44 --operation mode is arithmetic LB1_result_inc_871_nx44 = CARRY(!LB1_result_inc_871_nx40 # !Z1_data_out_55); --LB1_modgen_eq_784_nx0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|modgen_eq_784_nx0 --operation mode is normal LB1_modgen_eq_784_nx0 = Z1_data_out_62 $ LB1_forward_buffer_54; --LB1_nx167 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx167 --operation mode is normal LB1_nx167 = Z1_data_out_66 & (Z1_data_out_65 $ LB1_forward_buffer_57 # !LB1_forward_buffer_58) # !Z1_data_out_66 & (LB1_forward_buffer_58 # Z1_data_out_65 $ LB1_forward_buffer_57); --LB1_nx176 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx176 --operation mode is normal LB1_nx176 = !Z1_data_out_61 & !U1_buf0_err & LB1_nx145; --Z1_data_out_58 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_58 --operation mode is normal Z1_data_out_58_lut_out = Z1_data_out_57; Z1_data_out_58 = DFFEAS(Z1_data_out_58_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z1_data_out_57 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_57 --operation mode is normal Z1_data_out_57_lut_out = Z1_data_out_56; Z1_data_out_57 = DFFEAS(Z1_data_out_57_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --F1_bytes2send_28 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_28 --operation mode is normal F1_bytes2send_28_lut_out = F1_bytes2send_28; F1_bytes2send_28 = DFFEAS(F1_bytes2send_28_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_3, , , F1_a_1); --F1_byte_send_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_send_3 --operation mode is normal F1_byte_send_3_lut_out = F1_nx769 # F1_nx770 # F1_nx771 # F1_nx772; F1_byte_send_3 = DFFEAS(F1_byte_send_3_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2817, , , , ); --F1_bytes2send_44 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_44 --operation mode is normal F1_bytes2send_44_lut_out = F1_bytes2send_44; F1_bytes2send_44 = DFFEAS(F1_bytes2send_44_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_19, , , F1_a_3); --F1_bytes2send_20 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_20 --operation mode is normal F1_bytes2send_20_lut_out = F1_bytes2send_20; F1_bytes2send_20 = DFFEAS(F1_bytes2send_20_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_11, , , F1_a_1); --F1_bytes2send_36 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_36 --operation mode is normal F1_bytes2send_36_lut_out = V1_request_27; F1_bytes2send_36 = DFFEAS(F1_bytes2send_36_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx479, , , , ); --F1_iword2send_4 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|iword2send_4 --operation mode is normal F1_iword2send_4_lut_out = F1_iword2send_4; F1_iword2send_4 = DFFEAS(F1_iword2send_4_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_11, , , F1_a_3); --F1_bytes2send_12 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_12 --operation mode is normal F1_bytes2send_12_lut_out = F1_bytes2send_12; F1_bytes2send_12 = DFFEAS(F1_bytes2send_12_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_19, , , F1_a_1); --F1_bytes2send_4 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_4 --operation mode is normal F1_bytes2send_4_lut_out = V1_request_27; F1_bytes2send_4 = DFFEAS(F1_bytes2send_4_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx543, , , , ); --K1_cfr_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_7 --operation mode is normal K1_cfr_7_lut_out = V1_request_24; K1_cfr_7 = DFFEAS(K1_cfr_7_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_6 --operation mode is normal R1_datasr_6_lut_out = K1_cfr_6 & (R1_nx94 # R1_datasr_5 & R1_ADC_SCLK) # !K1_cfr_6 & R1_datasr_5 & R1_ADC_SCLK; R1_datasr_6 = DFFEAS(R1_datasr_6_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --Y1_nx82 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx82 --operation mode is normal Y1_nx82 = !DB1_data_out_3 & DB1_data_out_2; --Y1_nx96 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx96 --operation mode is normal Y1_nx96 = Y1_nx83 & (Y1_nx85 # Y1_nx89) # !Y1_nx83 & !DB1_data_out_0 & (Y1_nx89); --Y2_nx82 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx82 --operation mode is normal Y2_nx82 = !DB2_data_out_3 & DB2_data_out_2; --Y2_nx96 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx96 --operation mode is normal Y2_nx96 = Y2_nx83 & (Y2_nx85 # Y2_nx89) # !Y2_nx83 & !DB2_data_out_0 & (Y2_nx89); --G1_NOT_nx144 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|NOT_nx144 --operation mode is normal G1_NOT_nx144 = G1_cnt_6 & G1_nx544 & !G1_nx571 & G1_nx572; --G1_B_nx56 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_0_dgpot|B_nx56 --operation mode is arithmetic G1_B_nx56 = CARRY(G1_B_0); --G2_NOT_nx144 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|NOT_nx144 --operation mode is normal G2_NOT_nx144 = G2_cnt_6 & G2_nx544 & !G2_nx571 & G2_nx572; --G2_B_nx56 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_1_dgpot|B_nx56 --operation mode is arithmetic G2_B_nx56 = CARRY(G2_B_0); --G3_NOT_nx144 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|NOT_nx144 --operation mode is normal G3_NOT_nx144 = G3_cnt_6 & G3_nx544 & !G3_nx571 & G3_nx572; --G3_B_nx56 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_2_dgpot|B_nx56 --operation mode is arithmetic G3_B_nx56 = CARRY(G3_B_0); --G4_NOT_nx144 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|NOT_nx144 --operation mode is normal G4_NOT_nx144 = G4_cnt_6 & G4_nx544 & !G4_nx571 & G4_nx572; --G4_B_nx56 is ADC_DAC_1_notri:adcdac_notri|digpot4:dgi_3_dgpot|B_nx56 --operation mode is arithmetic G4_B_nx56 = CARRY(G4_B_0); --V1_request_7 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_7 --operation mode is normal V1_request_7 = V1_select_rq & (Z2_data_out_7) # !V1_select_rq & Z1_data_out_7; --L1_cfr_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_7 --operation mode is normal L1_cfr_7_lut_out = V1_request_24; L1_cfr_7 = DFFEAS(L1_cfr_7_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_6 --operation mode is normal R2_datasr_6_lut_out = L1_cfr_6 & (R2_nx94 # R2_datasr_5 & R2_ADC_SCLK) # !L1_cfr_6 & R2_datasr_5 & R2_ADC_SCLK; R2_datasr_6 = DFFEAS(R2_datasr_6_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --AB1_ob_data_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_64 --operation mode is normal AB1_ob_data_64_lut_out = AB1_ob_data_63; AB1_ob_data_64 = DFFEAS(AB1_ob_data_64_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_64, , , AB1_a_2); --LB1_d_to_dll_65 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_65 --operation mode is normal LB1_d_to_dll_65 = Z1_data_out_65 & (LB1_nx148 # LB1_forward_buffer_57 & LB1_nx151) # !Z1_data_out_65 & LB1_forward_buffer_57 & (LB1_nx151); --Z1_data_out_66 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_66 --operation mode is normal Z1_data_out_66_lut_out = Z1_data_out_65; Z1_data_out_66 = DFFEAS(Z1_data_out_66_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --T1_altered_frame is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|altered_frame --operation mode is normal T1_altered_frame = !X1_data_out_0 & (X1_data_out_3 & !X1_data_out_2 & !X1_data_out_1 # !X1_data_out_3 & (X1_data_out_2 $ X1_data_out_1)); --AB1_ob_crc_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_11 --operation mode is normal AB1_ob_crc_11_lut_out = AB1_ob_crc_10; AB1_ob_crc_11 = DFFEAS(AB1_ob_crc_11_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_64, , , AB1_a_2); --AB2_ob_data_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_64 --operation mode is normal AB2_ob_data_64_lut_out = AB2_ob_data_63; AB2_ob_data_64 = DFFEAS(AB2_ob_data_64_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_64, , , AB2_a_2); --LB2_d_to_dll_65 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_65 --operation mode is normal LB2_d_to_dll_65 = Z2_data_out_65 & (LB2_nx148 # LB2_forward_buffer_57 & LB2_nx151) # !Z2_data_out_65 & LB2_forward_buffer_57 & (LB2_nx151); --AB2_ob_crc_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_11 --operation mode is normal AB2_ob_crc_11_lut_out = AB2_ob_crc_10; AB2_ob_crc_11 = DFFEAS(AB2_ob_crc_11_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_64, , , AB2_a_2); --M1_PQ_7 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_7 --operation mode is normal M1_PQ_7_lut_out = V1_request_24; M1_PQ_7 = DFFEAS(M1_PQ_7_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_6, , , M1_SERREG_1); --R1_RDATA_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_7 --operation mode is normal R1_RDATA_7_lut_out = R1_RDATA_6; R1_RDATA_7 = DFFEAS(R1_RDATA_7_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_NOT_climits_a_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_6 --operation mode is normal K1_NOT_climits_a_6_lut_out = !V1_request_25; K1_NOT_climits_a_6 = DFFEAS(K1_NOT_climits_a_6_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_6 --operation mode is normal K1_adc_last_4_6_lut_out = R1_RDATA_6; K1_adc_last_4_6 = DFFEAS(K1_adc_last_4_6_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx40 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx40 --operation mode is arithmetic K1_modgen_gt_268_nx40 = CARRY(K1_NOT_climits_a_5 & !K1_adc_last_4_5 & !K1_modgen_gt_268_nx38 # !K1_NOT_climits_a_5 & (!K1_modgen_gt_268_nx38 # !K1_adc_last_4_5)); --K1_NOT_climits_d_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_6 --operation mode is normal K1_NOT_climits_d_6_lut_out = !V1_request_25; K1_NOT_climits_d_6 = DFFEAS(K1_NOT_climits_d_6_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_6 --operation mode is normal K1_adc_last_6_6_lut_out = R1_RDATA_6; K1_adc_last_6_6 = DFFEAS(K1_adc_last_6_6_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx40 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx40 --operation mode is arithmetic K1_modgen_gt_270_nx40 = CARRY(K1_NOT_climits_d_5 & !K1_adc_last_6_5 & !K1_modgen_gt_270_nx38 # !K1_NOT_climits_d_5 & (!K1_modgen_gt_270_nx38 # !K1_adc_last_6_5)); --K1_NOT_climits_a_18 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_18 --operation mode is normal K1_NOT_climits_a_18_lut_out = K1_NOT_climits_a_18; K1_NOT_climits_a_18 = DFFEAS(K1_NOT_climits_a_18_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L531, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_6 --operation mode is normal K1_adc_last_5_6_lut_out = R1_RDATA_6; K1_adc_last_5_6 = DFFEAS(K1_adc_last_5_6_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx40 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx40 --operation mode is arithmetic K1_modgen_gt_269_nx40 = CARRY(K1_NOT_climits_a_17 & !K1_adc_last_5_5 & !K1_modgen_gt_269_nx38 # !K1_NOT_climits_a_17 & (!K1_modgen_gt_269_nx38 # !K1_adc_last_5_5)); --K1_NOT_climits_d_18 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_18 --operation mode is normal K1_NOT_climits_d_18_lut_out = K1_NOT_climits_d_18; K1_NOT_climits_d_18 = DFFEAS(K1_NOT_climits_d_18_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L531, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_6 --operation mode is normal K1_adc_last_7_6_lut_out = R1_RDATA_6; K1_adc_last_7_6 = DFFEAS(K1_adc_last_7_6_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx40 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx40 --operation mode is arithmetic K1_modgen_gt_271_nx40 = CARRY(K1_NOT_climits_d_17 & !K1_adc_last_7_5 & !K1_modgen_gt_271_nx38 # !K1_NOT_climits_d_17 & (!K1_modgen_gt_271_nx38 # !K1_adc_last_7_5)); --E1_cnt_rst_1 is ni2io_wt:wt_ni|cnt_rst_1 --operation mode is arithmetic E1_cnt_rst_1_carry_eqn = E1_cnt_rst_nx10; E1_cnt_rst_1_lut_out = E1_cnt_rst_1 $ (E1_cnt_rst_1_carry_eqn); E1_cnt_rst_1 = DFFEAS(E1_cnt_rst_1_lut_out, S1__clk1, T1_chipRST_n, , , , , !E1_NOT_rst_start, ); --E1_cnt_rst_nx16 is ni2io_wt:wt_ni|cnt_rst_nx16 --operation mode is arithmetic E1_cnt_rst_nx16 = CARRY(!E1_cnt_rst_nx10 # !E1_cnt_rst_1); --R1_RDATA_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_0 --operation mode is normal R1_RDATA_0_lut_out = MSply_ADC_SDO; R1_RDATA_0 = DFFEAS(R1_RDATA_0_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_NOT_nx2189 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx2189 --operation mode is normal K1_NOT_nx2189 = K1_sm_4 & !K1_counter_2 & !K1_counter_1 & !K1_counter_0; --K1_NOT_nx2237 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx2237 --operation mode is normal K1_NOT_nx2237 = K1_sm_4 & !K1_counter_2 & K1_counter_1 & !K1_counter_0; --R2_NOT_nx295 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|NOT_nx295 --operation mode is normal R2_NOT_nx295 = R2_ADC_SCLK & (R2_counter_3 # R2_counter_2 # !R2_fifo_rd); --PB1_NOT_we_p_r is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|NOT_we_p_r --operation mode is normal PB1_NOT_we_p_r_lut_out = VCC; PB1_NOT_we_p_r = DFFEAS(PB1_NOT_we_p_r_lut_out, !WT_STR, E1_NOT_clear, , PB1_NOT_modgen_eq_10_nx44, , , , ); --PB1_nx48 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|nx48 --operation mode is normal PB1_nx48 = SB2_Q_11 # !SB2_Q_8 # !SB2_Q_9 # !SB2_Q_10; --PB1_nx49 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|nx49 --operation mode is normal PB1_nx49 = !SB2_Q_4 # !SB2_Q_5 # !SB2_Q_6 # !SB2_Q_7; --PB1_nx50 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|nx50 --operation mode is normal PB1_nx50 = !SB2_Q_0 # !SB2_Q_1 # !SB2_Q_2 # !SB2_Q_3; --RB1_q1pass_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|q1pass_1 --operation mode is normal RB1_q1pass_1 = E1_sel_s_1 & (PB1_data_1p_m_1) # !E1_sel_s_1 & (RB1_nx152 & (PB1_data_1p_m_1) # !RB1_nx152 & PB1_data_1p_m_2); --RB1_q1pass_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|q1pass_0 --operation mode is normal RB1_q1pass_0 = E1_NOT_sel_s_3 & (RB1_modgen_gt_19_nx42 & (PB1_data_1p_m_0) # !RB1_modgen_gt_19_nx42 & PB1_data_1p_m_1) # !E1_NOT_sel_s_3 & (PB1_data_1p_m_0); --RB1_modgen_gt_34_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|modgen_gt_34_nx56 --operation mode is normal RB1_modgen_gt_34_nx56 = E1_sel_p_2 # E1_sel_p_1 # !E1_NOT_sel_p_0 # !E1_NOT_sel_p_3; --E1_nx399 is ni2io_wt:wt_ni|nx399 --operation mode is normal E1_nx399 = !V1_request_47 & V1_request_48; --PB1_par_en is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|par_en --operation mode is normal PB1_par_en = PB1_we_p & PB1_nx152; --F1_nx2247 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2247 --operation mode is normal F1_nx2247 = F1_byte_recv_0 & (!F1_iword2send_7 # !F1_sm_top_1); --F1_bytes_rcvd_40 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_40 --operation mode is normal F1_bytes_rcvd_40 = DFFEAS(F1_nx2247, S1__clk1, VCC, , F1_NOT_nx2089, , , , ); --F1_NOT_nx2121 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx2121 --operation mode is normal F1_NOT_nx2121 = F1_nx801 # F1_byte_counter_2 & !F1_byte_counter_1 & F1_nx804; --F1_NOT_nx2249 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx2249 --operation mode is normal F1_NOT_nx2249 = F1_nx801 # !F1_byte_counter_2 & !F1_byte_counter_1 & F1_nx804; --EB1_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx18 --operation mode is normal EB1_nx18 = EB1_state_0 # EB1_state_1 # !EB1_state_2; --Y1_time_in_hotreset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|time_in_hotreset_n --operation mode is normal Y1_time_in_hotreset_n = DB1_data_out_3 # DB1_data_out_2 & (DB1_data_out_0 # !DB1_data_out_1) # !DB1_data_out_2 & (DB1_data_out_1 # !DB1_data_out_0); --EB1_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|b_0 --operation mode is normal EB1_b_0 = !EB1_state_0 & EB1_nx18; --EB1_state_inc_653_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_inc_653_nx14 --operation mode is arithmetic EB1_state_inc_653_nx14 = CARRY(EB1_state_0); --EB2_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx18 --operation mode is normal EB2_nx18 = EB2_state_0 # EB2_state_1 # !EB2_state_2; --Y2_time_in_hotreset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|time_in_hotreset_n --operation mode is normal Y2_time_in_hotreset_n = DB2_data_out_3 # DB2_data_out_2 & (DB2_data_out_0 # !DB2_data_out_1) # !DB2_data_out_2 & (DB2_data_out_1 # !DB2_data_out_0); --EB2_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|b_0 --operation mode is normal EB2_b_0 = !EB2_state_0 & EB2_nx18; --EB2_state_inc_653_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_inc_653_nx14 --operation mode is arithmetic EB2_state_inc_653_nx14 = CARRY(EB2_state_0); --Z2_nx1520 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx1520 --operation mode is normal Z2_nx1520 = CB2_strobe_out & !Z2_buffer_full # !Y2_buffer_flush_n; --Z2_b_crc_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_7 --operation mode is normal Z2_b_crc_7_lut_out = Y2_buffer_flush_n & Z2_b_crc_6; Z2_b_crc_7 = DFFEAS(Z2_b_crc_7_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_6 --operation mode is normal Z2_b_crc_6_lut_out = Y2_buffer_flush_n & Z2_b_crc_5; Z2_b_crc_6 = DFFEAS(Z2_b_crc_6_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_5 --operation mode is normal Z2_b_crc_5_lut_out = Y2_buffer_flush_n & Z2_b_crc_4; Z2_b_crc_5 = DFFEAS(Z2_b_crc_5_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_4 --operation mode is normal Z2_b_crc_4_lut_out = Y2_buffer_flush_n & Z2_b_crc_3; Z2_b_crc_4 = DFFEAS(Z2_b_crc_4_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_3 --operation mode is normal Z2_b_crc_3_lut_out = Y2_buffer_flush_n & Z2_b_crc_2; Z2_b_crc_3 = DFFEAS(Z2_b_crc_3_lut_out, S1__clk0, VCC, , Z2_nx1520, , , , ); --Z2_b_crc_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_2 --operation mode is normal Z2_b_crc_2_lut_out = Z2_b_crc_15 $ Z2_b_crc_1; Z2_b_crc_2 = DFFEAS(Z2_b_crc_2_lut_out, S1__clk0, VCC, , Z2_nx1520, , , !Y2_buffer_flush_n, ); --V1_nx818 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx818 --operation mode is normal V1_nx818 = V1_bridge_buffered $ !V1_bridge; --Z1_b_crc_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_11 --operation mode is normal Z1_b_crc_11_lut_out = Y1_buffer_flush_n & Z1_b_crc_10; Z1_b_crc_11 = DFFEAS(Z1_b_crc_11_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_10 --operation mode is normal Z1_b_crc_10_lut_out = Y1_buffer_flush_n & Z1_b_crc_9; Z1_b_crc_10 = DFFEAS(Z1_b_crc_10_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_9 --operation mode is normal Z1_b_crc_9_lut_out = Y1_buffer_flush_n & Z1_b_crc_8; Z1_b_crc_9 = DFFEAS(Z1_b_crc_9_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_8 --operation mode is normal Z1_b_crc_8_lut_out = Y1_buffer_flush_n & Z1_b_crc_7; Z1_b_crc_8 = DFFEAS(Z1_b_crc_8_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_15 --operation mode is normal Z1_b_crc_15_lut_out = Z1_b_crc_15 $ Z1_b_crc_14; Z1_b_crc_15 = DFFEAS(Z1_b_crc_15_lut_out, S1__clk0, VCC, , Z1_nx1520, , , !Y1_buffer_flush_n, ); --Z1_b_crc_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_14 --operation mode is normal Z1_b_crc_14_lut_out = Y1_buffer_flush_n & Z1_b_crc_13; Z1_b_crc_14 = DFFEAS(Z1_b_crc_14_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_13 --operation mode is normal Z1_b_crc_13_lut_out = Y1_buffer_flush_n & Z1_b_crc_12; Z1_b_crc_13 = DFFEAS(Z1_b_crc_13_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_12 --operation mode is normal Z1_b_crc_12_lut_out = Y1_buffer_flush_n & Z1_b_crc_11; Z1_b_crc_12 = DFFEAS(Z1_b_crc_12_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_1 --operation mode is normal Z1_b_crc_1_lut_out = Y1_buffer_flush_n & Z1_b_crc_0; Z1_b_crc_1 = DFFEAS(Z1_b_crc_1_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_0 --operation mode is normal Z1_b_crc_0_lut_out = CB1_data_out $ Z1_b_crc_15; Z1_b_crc_0 = DFFEAS(Z1_b_crc_0_lut_out, S1__clk0, VCC, , Z1_nx1520, , , !Y1_buffer_flush_n, ); --Z1_nx279 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx279 --operation mode is normal Z1_nx279 = !Z1_b_crc_7 & !Z1_b_crc_6 & !Z1_b_crc_5 & !Z1_b_crc_4; --Z1_nx284 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx284 --operation mode is normal Z1_nx284 = !Z1_b_crc_3 & !Z1_b_crc_2; --V1_nx234 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx234 --operation mode is normal V1_nx234 = KB1_data_out_2 & !KB1_data_out_1 & (V1_bridge_buffered $ !V1_bridge); --V1_nx235 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx235 --operation mode is normal V1_nx235 = !T1_bridge_alter & !KB1_data_out_2; --Z1_data_out_54 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_54 --operation mode is normal Z1_data_out_54_lut_out = Z1_data_out_53; Z1_data_out_54 = DFFEAS(Z1_data_out_54_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z1_data_out_53 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_53 --operation mode is normal Z1_data_out_53_lut_out = Z1_data_out_52; Z1_data_out_53 = DFFEAS(Z1_data_out_53_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --LB1_nx354 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx354 --operation mode is normal LB1_nx354 = LB1_b_dirty & LB1_nx145 & (Z1_data_valid # U1_buf0_err) # !LB1_b_dirty & !Z1_data_valid & !U1_buf0_err; --LB1_nx162 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx162 --operation mode is normal LB1_nx162 = !Z1_data_out_62 # !Z1_data_out_63 # !Z1_data_out_64 # !Z1_data_out_65; --Z1_data_out_62 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_62 --operation mode is normal Z1_data_out_62_lut_out = Z1_data_out_61; Z1_data_out_62 = DFFEAS(Z1_data_out_62_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z1_data_out_56 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_56 --operation mode is normal Z1_data_out_56_lut_out = Z1_data_out_55; Z1_data_out_56 = DFFEAS(Z1_data_out_56_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z1_data_out_55 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_55 --operation mode is normal Z1_data_out_55_lut_out = Z1_data_out_54; Z1_data_out_55 = DFFEAS(Z1_data_out_55_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z1_data_out_65 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_65 --operation mode is normal Z1_data_out_65_lut_out = Z1_data_out_64; Z1_data_out_65 = DFFEAS(Z1_data_out_65_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --Z1_data_out_61 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_61 --operation mode is normal Z1_data_out_61_lut_out = Z1_data_out_60; Z1_data_out_61 = DFFEAS(Z1_data_out_61_lut_out, S1__clk0, VCC, , Z1_NOT_nx676, , , !Y1_buffer_flush_n, ); --F1_nx769 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx769 --operation mode is normal F1_nx769 = F1_sm_sr_4 & (F1_byte_send_2 # F1_bytes2send_27 & F1_nx798) # !F1_sm_sr_4 & F1_bytes2send_27 & (F1_nx798); --F1_nx770 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx770 --operation mode is normal F1_nx770 = F1_bytes2send_43 & (F1_nx794 # F1_bytes2send_19 & F1_nx799) # !F1_bytes2send_43 & F1_bytes2send_19 & (F1_nx799); --F1_nx771 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx771 --operation mode is normal F1_nx771 = F1_bytes2send_35 & (F1_nx796 # F1_iword2send_3 & F1_nx793) # !F1_bytes2send_35 & F1_iword2send_3 & F1_nx793; --F1_nx772 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx772 --operation mode is normal F1_nx772 = F1_bytes2send_11 & (F1_nx795 # F1_bytes2send_3 & F1_nx797) # !F1_bytes2send_11 & F1_bytes2send_3 & (F1_nx797); --K1_cfr_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_6 --operation mode is normal K1_cfr_6_lut_out = V1_request_25; K1_cfr_6 = DFFEAS(K1_cfr_6_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_5 --operation mode is normal R1_datasr_5_lut_out = K1_cfr_5 & (R1_nx94 # R1_datasr_4 & R1_ADC_SCLK) # !K1_cfr_5 & R1_datasr_4 & R1_ADC_SCLK; R1_datasr_5 = DFFEAS(R1_datasr_5_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --L1_cfr_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_6 --operation mode is normal L1_cfr_6_lut_out = V1_request_25; L1_cfr_6 = DFFEAS(L1_cfr_6_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_5 --operation mode is normal R2_datasr_5_lut_out = L1_cfr_5 & (R2_nx94 # R2_datasr_4 & R2_ADC_SCLK) # !L1_cfr_5 & R2_datasr_4 & R2_ADC_SCLK; R2_datasr_5 = DFFEAS(R2_datasr_5_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --AB1_ob_data_63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_63 --operation mode is normal AB1_ob_data_63_lut_out = AB1_ob_data_62; AB1_ob_data_63 = DFFEAS(AB1_ob_data_63_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_63, , , AB1_a_2); --LB1_d_to_dll_64 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_64 --operation mode is normal LB1_d_to_dll_64 = Z1_data_out_64 & (LB1_nx148 # LB1_forward_buffer_56 & LB1_nx151) # !Z1_data_out_64 & LB1_forward_buffer_56 & (LB1_nx151); --AB1_ob_crc_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_10 --operation mode is normal AB1_ob_crc_10_lut_out = AB1_ob_crc_9; AB1_ob_crc_10 = DFFEAS(AB1_ob_crc_10_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_63, , , AB1_a_2); --AB2_ob_data_63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_63 --operation mode is normal AB2_ob_data_63_lut_out = AB2_ob_data_62; AB2_ob_data_63 = DFFEAS(AB2_ob_data_63_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_63, , , AB2_a_2); --LB2_d_to_dll_64 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_64 --operation mode is normal LB2_d_to_dll_64 = Z2_data_out_64 & (LB2_nx148 # LB2_forward_buffer_56 & LB2_nx151) # !Z2_data_out_64 & LB2_forward_buffer_56 & (LB2_nx151); --AB2_ob_crc_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_10 --operation mode is normal AB2_ob_crc_10_lut_out = AB2_ob_crc_9; AB2_ob_crc_10 = DFFEAS(AB2_ob_crc_10_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_63, , , AB2_a_2); --M1_PQ_6 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_6 --operation mode is normal M1_PQ_6_lut_out = V1_request_25; M1_PQ_6 = DFFEAS(M1_PQ_6_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_5, , , M1_SERREG_1); --R1_RDATA_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_6 --operation mode is normal R1_RDATA_6_lut_out = R1_RDATA_5; R1_RDATA_6 = DFFEAS(R1_RDATA_6_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_NOT_climits_a_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_5 --operation mode is normal K1_NOT_climits_a_5_lut_out = !V1_request_26; K1_NOT_climits_a_5 = DFFEAS(K1_NOT_climits_a_5_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_5 --operation mode is normal K1_adc_last_4_5_lut_out = R1_RDATA_5; K1_adc_last_4_5 = DFFEAS(K1_adc_last_4_5_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx38 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx38 --operation mode is arithmetic K1_modgen_gt_268_nx38 = CARRY(K1_NOT_climits_a_4 & (K1_adc_last_4_4 # !K1_modgen_gt_268_nx36) # !K1_NOT_climits_a_4 & K1_adc_last_4_4 & !K1_modgen_gt_268_nx36); --K1_NOT_climits_d_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_5 --operation mode is normal K1_NOT_climits_d_5_lut_out = !V1_request_26; K1_NOT_climits_d_5 = DFFEAS(K1_NOT_climits_d_5_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_5 --operation mode is normal K1_adc_last_6_5_lut_out = R1_RDATA_5; K1_adc_last_6_5 = DFFEAS(K1_adc_last_6_5_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx38 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx38 --operation mode is arithmetic K1_modgen_gt_270_nx38 = CARRY(K1_NOT_climits_d_4 & (K1_adc_last_6_4 # !K1_modgen_gt_270_nx36) # !K1_NOT_climits_d_4 & K1_adc_last_6_4 & !K1_modgen_gt_270_nx36); --K1_NOT_climits_a_17 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_17 --operation mode is normal K1_NOT_climits_a_17_lut_out = K1_NOT_climits_a_17; K1_NOT_climits_a_17 = DFFEAS(K1_NOT_climits_a_17_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L731, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_5 --operation mode is normal K1_adc_last_5_5_lut_out = R1_RDATA_5; K1_adc_last_5_5 = DFFEAS(K1_adc_last_5_5_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx38 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx38 --operation mode is arithmetic K1_modgen_gt_269_nx38 = CARRY(K1_NOT_climits_a_16 & (K1_adc_last_5_4 # !K1_modgen_gt_269_nx36) # !K1_NOT_climits_a_16 & K1_adc_last_5_4 & !K1_modgen_gt_269_nx36); --K1_NOT_climits_d_17 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_17 --operation mode is normal K1_NOT_climits_d_17_lut_out = K1_NOT_climits_d_17; K1_NOT_climits_d_17 = DFFEAS(K1_NOT_climits_d_17_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L731, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_5 --operation mode is normal K1_adc_last_7_5_lut_out = R1_RDATA_5; K1_adc_last_7_5 = DFFEAS(K1_adc_last_7_5_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx38 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx38 --operation mode is arithmetic K1_modgen_gt_271_nx38 = CARRY(K1_NOT_climits_d_16 & (K1_adc_last_7_4 # !K1_modgen_gt_271_nx36) # !K1_NOT_climits_d_16 & K1_adc_last_7_4 & !K1_modgen_gt_271_nx36); --E1_cnt_rst_0 is ni2io_wt:wt_ni|cnt_rst_0 --operation mode is arithmetic E1_cnt_rst_0_lut_out = E1_cnt_rst_0 $ E1_modgen_eq_84_nx32; E1_cnt_rst_0 = DFFEAS(E1_cnt_rst_0_lut_out, S1__clk1, T1_chipRST_n, , , , , !E1_NOT_rst_start, ); --E1_cnt_rst_nx10 is ni2io_wt:wt_ni|cnt_rst_nx10 --operation mode is arithmetic E1_cnt_rst_nx10 = CARRY(E1_cnt_rst_0 & E1_modgen_eq_84_nx32); --R2_fifo_rd is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|fifo_rd --operation mode is normal R2_fifo_rd_lut_out = L1_cmd_adc_1 & L1_cmd_adc_2; R2_fifo_rd = DFFEAS(R2_fifo_rd_lut_out, S1__clk1, VCC, , R2_modgen_select_195_nx4, , , , ); --PB1_NOT_modgen_eq_10_nx44 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|NOT_modgen_eq_10_nx44 --operation mode is normal PB1_NOT_modgen_eq_10_nx44 = !PB1_nx48 & !PB1_nx49 & !PB1_nx50; --PB1_data_1p_m_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_2 --operation mode is normal PB1_data_1p_m_2 = E1_or_mask_2 # !E1_NOT_and_mask_2 & (E1_NOT_xor_mask_2 $ !TB1_q_2); --PB1_data_1p_m_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_1 --operation mode is normal PB1_data_1p_m_1 = E1_or_mask_1 # !E1_NOT_and_mask_1 & (E1_NOT_xor_mask_1 $ !TB1_q_1); --E1_sel_s_1 is ni2io_wt:wt_ni|sel_s_1 --operation mode is normal E1_sel_s_1_lut_out = E1_sel_s_1; E1_sel_s_1 = DFFEAS(E1_sel_s_1_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_30, , , E1_nx398); --RB1_nx152 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx152 --operation mode is normal RB1_nx152 = E1_sel_s_2 # !E1_NOT_sel_s_3; --PB1_data_1p_m_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_0 --operation mode is normal PB1_data_1p_m_0 = E1_or_mask_0 # !E1_NOT_and_mask_0 & (E1_NOT_xor_mask_0 $ !TB1_q_0); --E1_NOT_sel_s_3 is ni2io_wt:wt_ni|NOT_sel_s_3 --operation mode is normal E1_NOT_sel_s_3_lut_out = E1_NOT_sel_s_3; E1_NOT_sel_s_3 = DFFEAS(E1_NOT_sel_s_3_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L261, , , E1_nx398); --RB1_modgen_gt_19_nx42 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|modgen_gt_19_nx42 --operation mode is normal RB1_modgen_gt_19_nx42 = E1_sel_s_2 # E1_sel_s_1 # E1_sel_s_0; --E1_NOT_sel_p_3 is ni2io_wt:wt_ni|NOT_sel_p_3 --operation mode is normal E1_NOT_sel_p_3_lut_out = E1_NOT_sel_p_3; E1_NOT_sel_p_3 = DFFEAS(E1_NOT_sel_p_3_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L651, , , E1_nx398); --E1_sel_p_2 is ni2io_wt:wt_ni|sel_p_2 --operation mode is normal E1_sel_p_2_lut_out = E1_sel_p_2; E1_sel_p_2 = DFFEAS(E1_sel_p_2_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_25, , , E1_nx398); --E1_sel_p_1 is ni2io_wt:wt_ni|sel_p_1 --operation mode is normal E1_sel_p_1_lut_out = E1_sel_p_1; E1_sel_p_1 = DFFEAS(E1_sel_p_1_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_26, , , E1_nx398); --E1_NOT_sel_p_0 is ni2io_wt:wt_ni|NOT_sel_p_0 --operation mode is normal E1_NOT_sel_p_0_lut_out = E1_NOT_sel_p_0; E1_NOT_sel_p_0 = DFFEAS(E1_NOT_sel_p_0_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L061, , , E1_nx398); --PB1_nx152 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|nx152 --operation mode is normal PB1_nx152 = PB1_modgen_xor_1035_nx14 $ PB1_modgen_xor_1035_nx18 $ RB1_dout_7 $ RB1_prty_bit; --F1_byte_recv_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_recv_0 --operation mode is normal F1_byte_recv_0_lut_out = F1_sm_sr_1 & DDS_SDO # !F1_sm_sr_1 & (F1_byte_recv_0); F1_byte_recv_0 = DFFEAS(F1_byte_recv_0_lut_out, S1__clk1, T1_chipRST_n, , F1_clkdivs, , , , ); --F1_NOT_nx2089 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx2089 --operation mode is normal F1_NOT_nx2089 = F1_nx801 # F1_byte_counter_2 & F1_byte_counter_1 & F1_nx802; --F1_nx801 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx801 --operation mode is normal F1_nx801 = F1_sm_top_1 & F1_iword2send_7 & (!F1_sm_sr_5 # !F1_sm_top_5); --F1_nx804 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx804 --operation mode is normal F1_nx804 = F1_sm_top_5 & F1_sm_sr_5 & F1_byte_counter_0; --Z1_nx1520 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx1520 --operation mode is normal Z1_nx1520 = CB1_strobe_out & !Z1_buffer_full # !Y1_buffer_flush_n; --Z1_b_crc_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_7 --operation mode is normal Z1_b_crc_7_lut_out = Y1_buffer_flush_n & Z1_b_crc_6; Z1_b_crc_7 = DFFEAS(Z1_b_crc_7_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_6 --operation mode is normal Z1_b_crc_6_lut_out = Y1_buffer_flush_n & Z1_b_crc_5; Z1_b_crc_6 = DFFEAS(Z1_b_crc_6_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_5 --operation mode is normal Z1_b_crc_5_lut_out = Y1_buffer_flush_n & Z1_b_crc_4; Z1_b_crc_5 = DFFEAS(Z1_b_crc_5_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_4 --operation mode is normal Z1_b_crc_4_lut_out = Y1_buffer_flush_n & Z1_b_crc_3; Z1_b_crc_4 = DFFEAS(Z1_b_crc_4_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_3 --operation mode is normal Z1_b_crc_3_lut_out = Y1_buffer_flush_n & Z1_b_crc_2; Z1_b_crc_3 = DFFEAS(Z1_b_crc_3_lut_out, S1__clk0, VCC, , Z1_nx1520, , , , ); --Z1_b_crc_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_2 --operation mode is normal Z1_b_crc_2_lut_out = Z1_b_crc_15 $ Z1_b_crc_1; Z1_b_crc_2 = DFFEAS(Z1_b_crc_2_lut_out, S1__clk0, VCC, , Z1_nx1520, , , !Y1_buffer_flush_n, ); --F1_bytes2send_27 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_27 --operation mode is normal F1_bytes2send_27_lut_out = F1_bytes2send_27; F1_bytes2send_27 = DFFEAS(F1_bytes2send_27_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_4, , , F1_a_1); --F1_byte_send_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_send_2 --operation mode is normal F1_byte_send_2_lut_out = F1_nx773 # F1_nx774 # F1_nx775 # F1_nx776; F1_byte_send_2 = DFFEAS(F1_byte_send_2_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2817, , , , ); --F1_bytes2send_43 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_43 --operation mode is normal F1_bytes2send_43_lut_out = F1_bytes2send_43; F1_bytes2send_43 = DFFEAS(F1_bytes2send_43_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_20, , , F1_a_3); --F1_bytes2send_19 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_19 --operation mode is normal F1_bytes2send_19_lut_out = F1_bytes2send_19; F1_bytes2send_19 = DFFEAS(F1_bytes2send_19_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_12, , , F1_a_1); --F1_bytes2send_35 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_35 --operation mode is normal F1_bytes2send_35_lut_out = V1_request_28; F1_bytes2send_35 = DFFEAS(F1_bytes2send_35_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx479, , , , ); --F1_bytes2send_11 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_11 --operation mode is normal F1_bytes2send_11_lut_out = F1_bytes2send_11; F1_bytes2send_11 = DFFEAS(F1_bytes2send_11_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_20, , , F1_a_1); --F1_bytes2send_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_3 --operation mode is normal F1_bytes2send_3_lut_out = V1_request_28; F1_bytes2send_3 = DFFEAS(F1_bytes2send_3_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx543, , , , ); --K1_cfr_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_5 --operation mode is normal K1_cfr_5_lut_out = V1_request_26; K1_cfr_5 = DFFEAS(K1_cfr_5_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_4 --operation mode is normal R1_datasr_4_lut_out = K1_cfr_4 & (R1_nx94 # R1_datasr_3 & R1_ADC_SCLK) # !K1_cfr_4 & R1_datasr_3 & R1_ADC_SCLK; R1_datasr_4 = DFFEAS(R1_datasr_4_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --L1_cfr_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_5 --operation mode is normal L1_cfr_5_lut_out = V1_request_26; L1_cfr_5 = DFFEAS(L1_cfr_5_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_4 --operation mode is normal R2_datasr_4_lut_out = L1_cfr_4 & (R2_nx94 # R2_datasr_3 & R2_ADC_SCLK) # !L1_cfr_4 & R2_datasr_3 & R2_ADC_SCLK; R2_datasr_4 = DFFEAS(R2_datasr_4_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --AB1_ob_data_62 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_62 --operation mode is normal AB1_ob_data_62_lut_out = AB1_ob_data_61; AB1_ob_data_62 = DFFEAS(AB1_ob_data_62_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_62, , , AB1_a_2); --LB1_d_to_dll_63 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_63 --operation mode is normal LB1_d_to_dll_63 = Z1_data_out_63 & (LB1_nx148 # LB1_forward_buffer_55 & LB1_nx151) # !Z1_data_out_63 & LB1_forward_buffer_55 & (LB1_nx151); --AB1_ob_crc_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_9 --operation mode is normal AB1_ob_crc_9_lut_out = AB1_ob_crc_8; AB1_ob_crc_9 = DFFEAS(AB1_ob_crc_9_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_62, , , AB1_a_2); --AB2_ob_data_62 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_62 --operation mode is normal AB2_ob_data_62_lut_out = AB2_ob_data_61; AB2_ob_data_62 = DFFEAS(AB2_ob_data_62_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_62, , , AB2_a_2); --LB2_d_to_dll_63 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_63 --operation mode is normal LB2_d_to_dll_63 = Z2_data_out_63 & (LB2_nx148 # LB2_forward_buffer_55 & LB2_nx151) # !Z2_data_out_63 & LB2_forward_buffer_55 & (LB2_nx151); --AB2_ob_crc_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_9 --operation mode is normal AB2_ob_crc_9_lut_out = AB2_ob_crc_8; AB2_ob_crc_9 = DFFEAS(AB2_ob_crc_9_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_62, , , AB2_a_2); --M1_PQ_5 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_5 --operation mode is normal M1_PQ_5_lut_out = V1_request_26; M1_PQ_5 = DFFEAS(M1_PQ_5_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_4, , , M1_SERREG_1); --R1_RDATA_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_5 --operation mode is normal R1_RDATA_5_lut_out = R1_RDATA_4; R1_RDATA_5 = DFFEAS(R1_RDATA_5_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_NOT_climits_a_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_4 --operation mode is normal K1_NOT_climits_a_4_lut_out = !V1_request_27; K1_NOT_climits_a_4 = DFFEAS(K1_NOT_climits_a_4_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_4 --operation mode is normal K1_adc_last_4_4_lut_out = R1_RDATA_4; K1_adc_last_4_4 = DFFEAS(K1_adc_last_4_4_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx36 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx36 --operation mode is arithmetic K1_modgen_gt_268_nx36 = CARRY(K1_NOT_climits_a_3 & !K1_adc_last_4_3 & !K1_modgen_gt_268_nx34 # !K1_NOT_climits_a_3 & (!K1_modgen_gt_268_nx34 # !K1_adc_last_4_3)); --K1_NOT_climits_d_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_4 --operation mode is normal K1_NOT_climits_d_4_lut_out = !V1_request_27; K1_NOT_climits_d_4 = DFFEAS(K1_NOT_climits_d_4_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_4 --operation mode is normal K1_adc_last_6_4_lut_out = R1_RDATA_4; K1_adc_last_6_4 = DFFEAS(K1_adc_last_6_4_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx36 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx36 --operation mode is arithmetic K1_modgen_gt_270_nx36 = CARRY(K1_NOT_climits_d_3 & !K1_adc_last_6_3 & !K1_modgen_gt_270_nx34 # !K1_NOT_climits_d_3 & (!K1_modgen_gt_270_nx34 # !K1_adc_last_6_3)); --K1_NOT_climits_a_16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_16 --operation mode is normal K1_NOT_climits_a_16_lut_out = K1_NOT_climits_a_16; K1_NOT_climits_a_16 = DFFEAS(K1_NOT_climits_a_16_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L931, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_4 --operation mode is normal K1_adc_last_5_4_lut_out = R1_RDATA_4; K1_adc_last_5_4 = DFFEAS(K1_adc_last_5_4_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx36 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx36 --operation mode is arithmetic K1_modgen_gt_269_nx36 = CARRY(K1_NOT_climits_a_15 & !K1_adc_last_5_3 & !K1_modgen_gt_269_nx34 # !K1_NOT_climits_a_15 & (!K1_modgen_gt_269_nx34 # !K1_adc_last_5_3)); --K1_NOT_climits_d_16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_16 --operation mode is normal K1_NOT_climits_d_16_lut_out = K1_NOT_climits_d_16; K1_NOT_climits_d_16 = DFFEAS(K1_NOT_climits_d_16_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L931, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_4 --operation mode is normal K1_adc_last_7_4_lut_out = R1_RDATA_4; K1_adc_last_7_4 = DFFEAS(K1_adc_last_7_4_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx36 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx36 --operation mode is arithmetic K1_modgen_gt_271_nx36 = CARRY(K1_NOT_climits_d_15 & !K1_adc_last_7_3 & !K1_modgen_gt_271_nx34 # !K1_NOT_climits_d_15 & (!K1_modgen_gt_271_nx34 # !K1_adc_last_7_3)); --E1_modgen_eq_84_nx32 is ni2io_wt:wt_ni|modgen_eq_84_nx32 --operation mode is normal E1_modgen_eq_84_nx32 = E1_nx313 # E1_nx314 # !E1_cnt_rst_8; --E1_or_mask_2 is ni2io_wt:wt_ni|or_mask_2 --operation mode is normal E1_or_mask_2_lut_out = E1_or_mask_2; E1_or_mask_2 = DFFEAS(E1_or_mask_2_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_29, , , E1_nx399); --E1_NOT_and_mask_2 is ni2io_wt:wt_ni|NOT_and_mask_2 --operation mode is normal E1_NOT_and_mask_2_lut_out = E1_NOT_and_mask_2; E1_NOT_and_mask_2 = DFFEAS(E1_NOT_and_mask_2_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L741, , , E1_nx399); --E1_NOT_xor_mask_2 is ni2io_wt:wt_ni|NOT_xor_mask_2 --operation mode is normal E1_NOT_xor_mask_2_lut_out = E1_NOT_xor_mask_2; E1_NOT_xor_mask_2 = DFFEAS(E1_NOT_xor_mask_2_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L721, , , E1_nx399); --TB1_q_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_2 --operation mode is normal TB1_q_2_lut_out = WT_P4D[2]; TB1_q_2 = DFFEAS(TB1_q_2_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --E1_or_mask_1 is ni2io_wt:wt_ni|or_mask_1 --operation mode is normal E1_or_mask_1_lut_out = E1_or_mask_1; E1_or_mask_1 = DFFEAS(E1_or_mask_1_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_30, , , E1_nx399); --E1_NOT_and_mask_1 is ni2io_wt:wt_ni|NOT_and_mask_1 --operation mode is normal E1_NOT_and_mask_1_lut_out = E1_NOT_and_mask_1; E1_NOT_and_mask_1 = DFFEAS(E1_NOT_and_mask_1_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L941, , , E1_nx399); --E1_NOT_xor_mask_1 is ni2io_wt:wt_ni|NOT_xor_mask_1 --operation mode is normal E1_NOT_xor_mask_1_lut_out = E1_NOT_xor_mask_1; E1_NOT_xor_mask_1 = DFFEAS(E1_NOT_xor_mask_1_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L921, , , E1_nx399); --TB1_q_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_1 --operation mode is normal TB1_q_1_lut_out = WT_P4D[1]; TB1_q_1 = DFFEAS(TB1_q_1_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --E1_sel_s_2 is ni2io_wt:wt_ni|sel_s_2 --operation mode is normal E1_sel_s_2_lut_out = E1_sel_s_2; E1_sel_s_2 = DFFEAS(E1_sel_s_2_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_29, , , E1_nx398); --E1_NOT_and_mask_0 is ni2io_wt:wt_ni|NOT_and_mask_0 --operation mode is normal E1_NOT_and_mask_0_lut_out = E1_NOT_and_mask_0; E1_NOT_and_mask_0 = DFFEAS(E1_NOT_and_mask_0_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L151, , , E1_nx399); --E1_NOT_xor_mask_0 is ni2io_wt:wt_ni|NOT_xor_mask_0 --operation mode is normal E1_NOT_xor_mask_0_lut_out = E1_NOT_xor_mask_0; E1_NOT_xor_mask_0 = DFFEAS(E1_NOT_xor_mask_0_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L131, , , E1_nx399); --TB1_q_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_0 --operation mode is normal TB1_q_0_lut_out = WT_P4D[0]; TB1_q_0 = DFFEAS(TB1_q_0_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --PB1_modgen_xor_1035_nx14 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|modgen_xor_1035_nx14 --operation mode is normal PB1_modgen_xor_1035_nx14 = RB1_dout_0 $ RB1_dout_1 $ RB1_dout_2 $ RB1_dout_3; --PB1_modgen_xor_1035_nx18 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|modgen_xor_1035_nx18 --operation mode is normal PB1_modgen_xor_1035_nx18 = RB1_dout_6 $ RB1_dout_5 $ RB1_dout_4; --RB1_dout_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|dout_7 --operation mode is normal RB1_dout_7 = E1_NOT_sel_p_3 & RB1_q1pass_8 # !E1_NOT_sel_p_3 & (RB1_q1pass_7); --RB1_prty_bit is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|prty_bit --operation mode is normal RB1_prty_bit = E1_NOT_sel_p_3 & (RB1_nx157 & RB1_nx158) # !E1_NOT_sel_p_3 & RB1_q1pass_8; --F1_nx802 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx802 --operation mode is normal F1_nx802 = F1_sm_top_5 & F1_sm_sr_5 & !F1_byte_counter_0; --F1_nx773 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx773 --operation mode is normal F1_nx773 = F1_sm_sr_4 & (F1_byte_send_1 # F1_bytes2send_26 & F1_nx798) # !F1_sm_sr_4 & F1_bytes2send_26 & (F1_nx798); --F1_nx774 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx774 --operation mode is normal F1_nx774 = F1_bytes2send_42 & (F1_nx794 # F1_bytes2send_18 & F1_nx799) # !F1_bytes2send_42 & F1_bytes2send_18 & (F1_nx799); --F1_nx775 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx775 --operation mode is normal F1_nx775 = F1_bytes2send_34 & (F1_nx796 # F1_iword2send_2 & F1_nx793) # !F1_bytes2send_34 & F1_iword2send_2 & F1_nx793; --F1_nx776 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx776 --operation mode is normal F1_nx776 = F1_bytes2send_10 & (F1_nx795 # F1_bytes2send_2 & F1_nx797) # !F1_bytes2send_10 & F1_bytes2send_2 & (F1_nx797); --K1_cfr_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_4 --operation mode is normal K1_cfr_4_lut_out = V1_request_27; K1_cfr_4 = DFFEAS(K1_cfr_4_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_3 --operation mode is normal R1_datasr_3_lut_out = K1_cfr_3 & (R1_nx94 # R1_datasr_2 & R1_ADC_SCLK) # !K1_cfr_3 & R1_datasr_2 & R1_ADC_SCLK; R1_datasr_3 = DFFEAS(R1_datasr_3_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --L1_cfr_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_4 --operation mode is normal L1_cfr_4_lut_out = V1_request_27; L1_cfr_4 = DFFEAS(L1_cfr_4_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_3 --operation mode is normal R2_datasr_3_lut_out = L1_cfr_3 & (R2_nx94 # R2_datasr_2 & R2_ADC_SCLK) # !L1_cfr_3 & R2_datasr_2 & R2_ADC_SCLK; R2_datasr_3 = DFFEAS(R2_datasr_3_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --AB1_ob_data_61 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_61 --operation mode is normal AB1_ob_data_61_lut_out = AB1_ob_data_60; AB1_ob_data_61 = DFFEAS(AB1_ob_data_61_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_61, , , AB1_a_2); --LB1_d_to_dll_62 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_62 --operation mode is normal LB1_d_to_dll_62 = Z1_data_out_62 & (LB1_nx148 # LB1_forward_buffer_54 & LB1_nx151) # !Z1_data_out_62 & LB1_forward_buffer_54 & (LB1_nx151); --AB1_ob_crc_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_8 --operation mode is normal AB1_ob_crc_8_lut_out = AB1_ob_crc_7; AB1_ob_crc_8 = DFFEAS(AB1_ob_crc_8_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_61, , , AB1_a_2); --AB2_ob_data_61 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_61 --operation mode is normal AB2_ob_data_61_lut_out = AB2_ob_data_60; AB2_ob_data_61 = DFFEAS(AB2_ob_data_61_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_61, , , AB2_a_2); --LB2_d_to_dll_62 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_62 --operation mode is normal LB2_d_to_dll_62 = Z2_data_out_62 & (LB2_nx148 # LB2_forward_buffer_54 & LB2_nx151) # !Z2_data_out_62 & LB2_forward_buffer_54 & (LB2_nx151); --AB2_ob_crc_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_8 --operation mode is normal AB2_ob_crc_8_lut_out = AB2_ob_crc_7; AB2_ob_crc_8 = DFFEAS(AB2_ob_crc_8_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_61, , , AB2_a_2); --M1_PQ_4 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_4 --operation mode is normal M1_PQ_4_lut_out = V1_request_27; M1_PQ_4 = DFFEAS(M1_PQ_4_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_3, , , M1_SERREG_1); --R1_RDATA_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_4 --operation mode is normal R1_RDATA_4_lut_out = R1_RDATA_3; R1_RDATA_4 = DFFEAS(R1_RDATA_4_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_NOT_climits_a_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_3 --operation mode is normal K1_NOT_climits_a_3_lut_out = !V1_request_28; K1_NOT_climits_a_3 = DFFEAS(K1_NOT_climits_a_3_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_3 --operation mode is normal K1_adc_last_4_3_lut_out = R1_RDATA_3; K1_adc_last_4_3 = DFFEAS(K1_adc_last_4_3_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx34 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx34 --operation mode is arithmetic K1_modgen_gt_268_nx34 = CARRY(K1_NOT_climits_a_2 & (K1_adc_last_4_2 # !K1_modgen_gt_268_nx32) # !K1_NOT_climits_a_2 & K1_adc_last_4_2 & !K1_modgen_gt_268_nx32); --K1_NOT_climits_d_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_3 --operation mode is normal K1_NOT_climits_d_3_lut_out = !V1_request_28; K1_NOT_climits_d_3 = DFFEAS(K1_NOT_climits_d_3_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_3 --operation mode is normal K1_adc_last_6_3_lut_out = R1_RDATA_3; K1_adc_last_6_3 = DFFEAS(K1_adc_last_6_3_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx34 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx34 --operation mode is arithmetic K1_modgen_gt_270_nx34 = CARRY(K1_NOT_climits_d_2 & (K1_adc_last_6_2 # !K1_modgen_gt_270_nx32) # !K1_NOT_climits_d_2 & K1_adc_last_6_2 & !K1_modgen_gt_270_nx32); --K1_NOT_climits_a_15 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_15 --operation mode is normal K1_NOT_climits_a_15_lut_out = K1_NOT_climits_a_15; K1_NOT_climits_a_15 = DFFEAS(K1_NOT_climits_a_15_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L141, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_3 --operation mode is normal K1_adc_last_5_3_lut_out = R1_RDATA_3; K1_adc_last_5_3 = DFFEAS(K1_adc_last_5_3_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx34 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx34 --operation mode is arithmetic K1_modgen_gt_269_nx34 = CARRY(K1_NOT_climits_a_14 & (K1_adc_last_5_2 # !K1_modgen_gt_269_nx32) # !K1_NOT_climits_a_14 & K1_adc_last_5_2 & !K1_modgen_gt_269_nx32); --K1_NOT_climits_d_15 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_15 --operation mode is normal K1_NOT_climits_d_15_lut_out = K1_NOT_climits_d_15; K1_NOT_climits_d_15 = DFFEAS(K1_NOT_climits_d_15_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L141, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_3 --operation mode is normal K1_adc_last_7_3_lut_out = R1_RDATA_3; K1_adc_last_7_3 = DFFEAS(K1_adc_last_7_3_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx34 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx34 --operation mode is arithmetic K1_modgen_gt_271_nx34 = CARRY(K1_NOT_climits_d_14 & (K1_adc_last_7_2 # !K1_modgen_gt_271_nx32) # !K1_NOT_climits_d_14 & K1_adc_last_7_2 & !K1_modgen_gt_271_nx32); --E1_cnt_rst_8 is ni2io_wt:wt_ni|cnt_rst_8 --operation mode is normal E1_cnt_rst_8_carry_eqn = E1_cnt_rst_nx50; E1_cnt_rst_8_lut_out = E1_cnt_rst_8 $ (!E1_cnt_rst_8_carry_eqn); E1_cnt_rst_8 = DFFEAS(E1_cnt_rst_8_lut_out, S1__clk1, T1_chipRST_n, , , , , !E1_NOT_rst_start, ); --E1_nx313 is ni2io_wt:wt_ni|nx313 --operation mode is normal E1_nx313 = !E1_cnt_rst_4 # !E1_cnt_rst_5 # !E1_cnt_rst_6 # !E1_cnt_rst_7; --E1_nx314 is ni2io_wt:wt_ni|nx314 --operation mode is normal E1_nx314 = !E1_cnt_rst_0 # !E1_cnt_rst_1 # !E1_cnt_rst_2 # !E1_cnt_rst_3; --RB1_dout_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|dout_1 --operation mode is normal RB1_dout_1 = E1_sel_p_1 & (RB1_q1pass_1) # !E1_sel_p_1 & (RB1_nx151 & (RB1_q1pass_1) # !RB1_nx151 & RB1_q1pass_2); --RB1_dout_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|dout_2 --operation mode is normal RB1_dout_2 = RB1_modgen_gt_30_nx56 & (RB1_q1pass_2) # !RB1_modgen_gt_30_nx56 & RB1_q1pass_3; --RB1_dout_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|dout_3 --operation mode is normal RB1_dout_3 = E1_NOT_sel_p_3 & (E1_sel_p_2 & (RB1_q1pass_3) # !E1_sel_p_2 & RB1_q1pass_4) # !E1_NOT_sel_p_3 & (RB1_q1pass_3); --RB1_dout_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|dout_6 --operation mode is normal RB1_dout_6 = RB1_modgen_gt_22_nx56 & (RB1_q1pass_6) # !RB1_modgen_gt_22_nx56 & RB1_q1pass_7; --RB1_dout_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|dout_5 --operation mode is normal RB1_dout_5 = E1_NOT_sel_p_3 & (RB1_nx153 & (RB1_q1pass_5) # !RB1_nx153 & RB1_q1pass_6) # !E1_NOT_sel_p_3 & (RB1_q1pass_5); --RB1_dout_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|dout_4 --operation mode is normal RB1_dout_4 = RB1_modgen_gt_26_nx56 & (RB1_q1pass_4) # !RB1_modgen_gt_26_nx56 & RB1_q1pass_5; --RB1_q1pass_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|q1pass_8 --operation mode is normal RB1_q1pass_8 = E1_NOT_sel_s_3 & PB1_data_1p_m_9 # !E1_NOT_sel_s_3 & (RB1_modgen_gt_19_nx42 & (PB1_data_1p_m_8) # !RB1_modgen_gt_19_nx42 & PB1_data_1p_m_9); --RB1_q1pass_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|q1pass_7 --operation mode is normal RB1_q1pass_7 = E1_NOT_sel_s_3 & PB1_data_1p_m_8 # !E1_NOT_sel_s_3 & (PB1_data_1p_m_7); --RB1_nx157 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx157 --operation mode is normal RB1_nx157 = E1_sel_p_2 # RB1_nx155 & (RB1_nx149 # !E1_sel_p_1); --RB1_nx158 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx158 --operation mode is normal RB1_nx158 = RB1_nx156 & (RB1_nx150 # !E1_sel_p_1) # !E1_sel_p_2; --F1_bytes2send_26 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_26 --operation mode is normal F1_bytes2send_26_lut_out = F1_bytes2send_26; F1_bytes2send_26 = DFFEAS(F1_bytes2send_26_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_5, , , F1_a_1); --F1_byte_send_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_send_1 --operation mode is normal F1_byte_send_1_lut_out = F1_nx777 # F1_nx778 # F1_nx779 # F1_nx780; F1_byte_send_1 = DFFEAS(F1_byte_send_1_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2817, , , , ); --F1_bytes2send_42 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_42 --operation mode is normal F1_bytes2send_42_lut_out = F1_bytes2send_42; F1_bytes2send_42 = DFFEAS(F1_bytes2send_42_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_21, , , F1_a_3); --F1_bytes2send_18 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_18 --operation mode is normal F1_bytes2send_18_lut_out = F1_bytes2send_18; F1_bytes2send_18 = DFFEAS(F1_bytes2send_18_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_13, , , F1_a_1); --F1_bytes2send_34 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_34 --operation mode is normal F1_bytes2send_34_lut_out = V1_request_29; F1_bytes2send_34 = DFFEAS(F1_bytes2send_34_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx479, , , , ); --F1_bytes2send_10 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_10 --operation mode is normal F1_bytes2send_10_lut_out = F1_bytes2send_10; F1_bytes2send_10 = DFFEAS(F1_bytes2send_10_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_21, , , F1_a_1); --F1_bytes2send_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_2 --operation mode is normal F1_bytes2send_2_lut_out = V1_request_29; F1_bytes2send_2 = DFFEAS(F1_bytes2send_2_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx543, , , , ); --K1_cfr_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_3 --operation mode is normal K1_cfr_3_lut_out = V1_request_28; K1_cfr_3 = DFFEAS(K1_cfr_3_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_2 --operation mode is normal R1_datasr_2_lut_out = K1_cfr_2 & (R1_nx94 # R1_datasr_1 & R1_ADC_SCLK) # !K1_cfr_2 & R1_datasr_1 & R1_ADC_SCLK; R1_datasr_2 = DFFEAS(R1_datasr_2_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --L1_cfr_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_3 --operation mode is normal L1_cfr_3_lut_out = V1_request_28; L1_cfr_3 = DFFEAS(L1_cfr_3_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_2 --operation mode is normal R2_datasr_2_lut_out = L1_cfr_2 & (R2_nx94 # R2_datasr_1 & R2_ADC_SCLK) # !L1_cfr_2 & R2_datasr_1 & R2_ADC_SCLK; R2_datasr_2 = DFFEAS(R2_datasr_2_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --AB1_ob_data_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_60 --operation mode is normal AB1_ob_data_60_lut_out = AB1_ob_data_59; AB1_ob_data_60 = DFFEAS(AB1_ob_data_60_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_60, , , AB1_a_2); --LB1_d_to_dll_61 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_61 --operation mode is normal LB1_d_to_dll_61 = LB1_nx166 # Z1_data_out_61 & !DB3_data_out_2 & DB3_data_out_0; --AB1_ob_crc_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_7 --operation mode is normal AB1_ob_crc_7_lut_out = AB1_ob_crc_6; AB1_ob_crc_7 = DFFEAS(AB1_ob_crc_7_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_60, , , AB1_a_2); --AB2_ob_data_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_60 --operation mode is normal AB2_ob_data_60_lut_out = AB2_ob_data_59; AB2_ob_data_60 = DFFEAS(AB2_ob_data_60_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_60, , , AB2_a_2); --LB2_d_to_dll_61 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_61 --operation mode is normal LB2_d_to_dll_61 = LB2_nx166 # Z2_data_out_61 & !DB4_data_out_2 & DB4_data_out_0; --AB2_ob_crc_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_7 --operation mode is normal AB2_ob_crc_7_lut_out = AB2_ob_crc_6; AB2_ob_crc_7 = DFFEAS(AB2_ob_crc_7_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_60, , , AB2_a_2); --M1_PQ_3 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_3 --operation mode is normal M1_PQ_3_lut_out = V1_request_28; M1_PQ_3 = DFFEAS(M1_PQ_3_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_2, , , M1_SERREG_1); --R1_RDATA_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_3 --operation mode is normal R1_RDATA_3_lut_out = R1_RDATA_2; R1_RDATA_3 = DFFEAS(R1_RDATA_3_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_NOT_climits_a_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_2 --operation mode is normal K1_NOT_climits_a_2_lut_out = !V1_request_29; K1_NOT_climits_a_2 = DFFEAS(K1_NOT_climits_a_2_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_2 --operation mode is normal K1_adc_last_4_2_lut_out = R1_RDATA_2; K1_adc_last_4_2 = DFFEAS(K1_adc_last_4_2_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx32 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx32 --operation mode is arithmetic K1_modgen_gt_268_nx32 = CARRY(K1_NOT_climits_a_1 & !K1_adc_last_4_1 & !K1_modgen_gt_268_nx30 # !K1_NOT_climits_a_1 & (!K1_modgen_gt_268_nx30 # !K1_adc_last_4_1)); --K1_NOT_climits_d_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_2 --operation mode is normal K1_NOT_climits_d_2_lut_out = !V1_request_29; K1_NOT_climits_d_2 = DFFEAS(K1_NOT_climits_d_2_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_2 --operation mode is normal K1_adc_last_6_2_lut_out = R1_RDATA_2; K1_adc_last_6_2 = DFFEAS(K1_adc_last_6_2_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx32 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx32 --operation mode is arithmetic K1_modgen_gt_270_nx32 = CARRY(K1_NOT_climits_d_1 & !K1_adc_last_6_1 & !K1_modgen_gt_270_nx30 # !K1_NOT_climits_d_1 & (!K1_modgen_gt_270_nx30 # !K1_adc_last_6_1)); --K1_NOT_climits_a_14 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_14 --operation mode is normal K1_NOT_climits_a_14_lut_out = K1_NOT_climits_a_14; K1_NOT_climits_a_14 = DFFEAS(K1_NOT_climits_a_14_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L341, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_2 --operation mode is normal K1_adc_last_5_2_lut_out = R1_RDATA_2; K1_adc_last_5_2 = DFFEAS(K1_adc_last_5_2_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx32 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx32 --operation mode is arithmetic K1_modgen_gt_269_nx32 = CARRY(K1_NOT_climits_a_13 & !K1_adc_last_5_1 & !K1_modgen_gt_269_nx30 # !K1_NOT_climits_a_13 & (!K1_modgen_gt_269_nx30 # !K1_adc_last_5_1)); --K1_NOT_climits_d_14 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_14 --operation mode is normal K1_NOT_climits_d_14_lut_out = K1_NOT_climits_d_14; K1_NOT_climits_d_14 = DFFEAS(K1_NOT_climits_d_14_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L341, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_2 --operation mode is normal K1_adc_last_7_2_lut_out = R1_RDATA_2; K1_adc_last_7_2 = DFFEAS(K1_adc_last_7_2_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx32 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx32 --operation mode is arithmetic K1_modgen_gt_271_nx32 = CARRY(K1_NOT_climits_d_13 & !K1_adc_last_7_1 & !K1_modgen_gt_271_nx30 # !K1_NOT_climits_d_13 & (!K1_modgen_gt_271_nx30 # !K1_adc_last_7_1)); --RB1_q1pass_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|q1pass_2 --operation mode is normal RB1_q1pass_2 = RB1_modgen_gt_17_nx56 & (PB1_data_1p_m_2) # !RB1_modgen_gt_17_nx56 & PB1_data_1p_m_3; --RB1_nx151 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx151 --operation mode is normal RB1_nx151 = E1_sel_p_2 # !E1_NOT_sel_p_3; --RB1_q1pass_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|q1pass_3 --operation mode is normal RB1_q1pass_3 = E1_NOT_sel_s_3 & (E1_sel_s_2 & (PB1_data_1p_m_3) # !E1_sel_s_2 & PB1_data_1p_m_4) # !E1_NOT_sel_s_3 & (PB1_data_1p_m_3); --RB1_modgen_gt_30_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|modgen_gt_30_nx56 --operation mode is normal RB1_modgen_gt_30_nx56 = E1_sel_p_2 # E1_sel_p_1 & !E1_NOT_sel_p_0 # !E1_NOT_sel_p_3; --RB1_q1pass_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|q1pass_4 --operation mode is normal RB1_q1pass_4 = RB1_modgen_gt_15_nx56 & (PB1_data_1p_m_4) # !RB1_modgen_gt_15_nx56 & PB1_data_1p_m_5; --RB1_q1pass_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|q1pass_6 --operation mode is normal RB1_q1pass_6 = RB1_modgen_gt_13_nx56 & (PB1_data_1p_m_6) # !RB1_modgen_gt_13_nx56 & PB1_data_1p_m_7; --RB1_modgen_gt_22_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|modgen_gt_22_nx56 --operation mode is normal RB1_modgen_gt_22_nx56 = E1_sel_p_2 & E1_sel_p_1 & !E1_NOT_sel_p_0 # !E1_NOT_sel_p_3; --RB1_q1pass_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|q1pass_5 --operation mode is normal RB1_q1pass_5 = E1_NOT_sel_s_3 & (RB1_nx154 & (PB1_data_1p_m_5) # !RB1_nx154 & PB1_data_1p_m_6) # !E1_NOT_sel_s_3 & (PB1_data_1p_m_5); --RB1_nx153 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx153 --operation mode is normal RB1_nx153 = E1_sel_p_2 & E1_sel_p_1; --RB1_modgen_gt_26_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|modgen_gt_26_nx56 --operation mode is normal RB1_modgen_gt_26_nx56 = E1_sel_p_2 & (E1_sel_p_1 # !E1_NOT_sel_p_0) # !E1_NOT_sel_p_3; --PB1_data_1p_m_9 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_9 --operation mode is normal PB1_data_1p_m_9 = E1_or_mask_9 # !E1_NOT_and_mask_9 & (E1_NOT_xor_mask_9 $ !TB1_q_9); --PB1_data_1p_m_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_8 --operation mode is normal PB1_data_1p_m_8 = E1_or_mask_8 # !E1_NOT_and_mask_8 & (E1_NOT_xor_mask_8 $ !TB1_q_8); --PB1_data_1p_m_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_7 --operation mode is normal PB1_data_1p_m_7 = E1_or_mask_7 # !E1_NOT_and_mask_7 & (E1_NOT_xor_mask_7 $ !TB1_q_7); --RB1_nx149 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx149 --operation mode is normal RB1_nx149 = E1_NOT_sel_p_0 & (RB1_q1pass_2) # !E1_NOT_sel_p_0 & RB1_q1pass_3; --RB1_nx155 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx155 --operation mode is normal RB1_nx155 = E1_sel_p_1 # E1_NOT_sel_p_0 & (RB1_q1pass_0) # !E1_NOT_sel_p_0 & RB1_q1pass_1; --RB1_nx150 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx150 --operation mode is normal RB1_nx150 = E1_NOT_sel_p_0 & (RB1_q1pass_6) # !E1_NOT_sel_p_0 & RB1_q1pass_7; --RB1_nx156 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx156 --operation mode is normal RB1_nx156 = E1_sel_p_1 # E1_NOT_sel_p_0 & (RB1_q1pass_4) # !E1_NOT_sel_p_0 & RB1_q1pass_5; --F1_nx777 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx777 --operation mode is normal F1_nx777 = F1_sm_sr_4 & (F1_byte_send_0 # F1_bytes2send_25 & F1_nx798) # !F1_sm_sr_4 & F1_bytes2send_25 & (F1_nx798); --F1_nx778 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx778 --operation mode is normal F1_nx778 = F1_bytes2send_41 & (F1_nx794 # F1_bytes2send_17 & F1_nx799) # !F1_bytes2send_41 & F1_bytes2send_17 & (F1_nx799); --F1_nx779 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx779 --operation mode is normal F1_nx779 = F1_bytes2send_33 & (F1_nx796 # F1_iword2send_1 & F1_nx793) # !F1_bytes2send_33 & F1_iword2send_1 & F1_nx793; --F1_nx780 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx780 --operation mode is normal F1_nx780 = F1_bytes2send_9 & (F1_nx795 # F1_bytes2send_1 & F1_nx797) # !F1_bytes2send_9 & F1_bytes2send_1 & (F1_nx797); --K1_cfr_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_2 --operation mode is normal K1_cfr_2_lut_out = V1_request_29; K1_cfr_2 = DFFEAS(K1_cfr_2_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_1 --operation mode is normal R1_datasr_1_lut_out = K1_cfr_1 & (R1_nx94 # R1_datasr_0 & R1_ADC_SCLK) # !K1_cfr_1 & R1_datasr_0 & R1_ADC_SCLK; R1_datasr_1 = DFFEAS(R1_datasr_1_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --L1_cfr_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_2 --operation mode is normal L1_cfr_2_lut_out = V1_request_29; L1_cfr_2 = DFFEAS(L1_cfr_2_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_1 --operation mode is normal R2_datasr_1_lut_out = L1_cfr_1 & (R2_nx94 # R2_datasr_0 & R2_ADC_SCLK) # !L1_cfr_1 & R2_datasr_0 & R2_ADC_SCLK; R2_datasr_1 = DFFEAS(R2_datasr_1_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --AB1_ob_data_59 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_59 --operation mode is normal AB1_ob_data_59_lut_out = AB1_ob_data_58; AB1_ob_data_59 = DFFEAS(AB1_ob_data_59_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_59, , , AB1_a_2); --LB1_d_to_dll_60 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_60 --operation mode is normal LB1_d_to_dll_60 = !DB3_data_out_2 & LB1_forward_buffer_60 & (DB3_data_out_0 # !V1_altered_frame0); --LB1_nx166 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx166 --operation mode is normal LB1_nx166 = !V1_altered_frame0 & LB1_nx146 & (LB1_modgen_eq_783_nx24 # !V1_bridge); --AB1_ob_crc_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_6 --operation mode is normal AB1_ob_crc_6_lut_out = AB1_ob_crc_5; AB1_ob_crc_6 = DFFEAS(AB1_ob_crc_6_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_59, , , AB1_a_2); --AB2_ob_data_59 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_59 --operation mode is normal AB2_ob_data_59_lut_out = AB2_ob_data_58; AB2_ob_data_59 = DFFEAS(AB2_ob_data_59_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_59, , , AB2_a_2); --LB2_d_to_dll_60 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_60 --operation mode is normal LB2_d_to_dll_60 = !DB4_data_out_2 & LB2_forward_buffer_60 & (DB4_data_out_0 # !V1_altered_frame1); --LB2_nx166 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx166 --operation mode is normal LB2_nx166 = !V1_altered_frame1 & LB2_nx146 & (LB2_modgen_eq_783_nx24 # !V1_bridge); --AB2_ob_crc_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_6 --operation mode is normal AB2_ob_crc_6_lut_out = AB2_ob_crc_5; AB2_ob_crc_6 = DFFEAS(AB2_ob_crc_6_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_59, , , AB2_a_2); --M1_PQ_2 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_2 --operation mode is normal M1_PQ_2_lut_out = V1_request_29; M1_PQ_2 = DFFEAS(M1_PQ_2_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_1, , , M1_SERREG_1); --R1_RDATA_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_2 --operation mode is normal R1_RDATA_2_lut_out = R1_RDATA_1; R1_RDATA_2 = DFFEAS(R1_RDATA_2_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_NOT_climits_a_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_1 --operation mode is normal K1_NOT_climits_a_1_lut_out = !V1_request_30; K1_NOT_climits_a_1 = DFFEAS(K1_NOT_climits_a_1_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_4_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_4_1 --operation mode is normal K1_adc_last_4_1_lut_out = R1_RDATA_1; K1_adc_last_4_1 = DFFEAS(K1_adc_last_4_1_lut_out, S1__clk1, VCC, , K1_NOT_nx2285, , , , ); --K1_modgen_gt_268_nx30 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_268_nx30 --operation mode is arithmetic K1_modgen_gt_268_nx30 = CARRY(K1_adc_last_4_0 & K1_NOT_climits_a_0); --K1_NOT_climits_d_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_1 --operation mode is normal K1_NOT_climits_d_1_lut_out = !V1_request_30; K1_NOT_climits_d_1 = DFFEAS(K1_NOT_climits_d_1_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --K1_adc_last_6_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_6_1 --operation mode is normal K1_adc_last_6_1_lut_out = R1_RDATA_1; K1_adc_last_6_1 = DFFEAS(K1_adc_last_6_1_lut_out, S1__clk1, VCC, , K1_NOT_nx2333, , , , ); --K1_modgen_gt_270_nx30 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_270_nx30 --operation mode is arithmetic K1_modgen_gt_270_nx30 = CARRY(K1_adc_last_6_0 & K1_NOT_climits_d_0); --K1_NOT_climits_a_13 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_13 --operation mode is normal K1_NOT_climits_a_13_lut_out = K1_NOT_climits_a_13; K1_NOT_climits_a_13 = DFFEAS(K1_NOT_climits_a_13_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L541, , , K1_NOT_ix37_ix9_nx8); --K1_adc_last_5_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_1 --operation mode is normal K1_adc_last_5_1_lut_out = R1_RDATA_1; K1_adc_last_5_1 = DFFEAS(K1_adc_last_5_1_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_modgen_gt_269_nx30 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_269_nx30 --operation mode is arithmetic K1_modgen_gt_269_nx30 = CARRY(K1_adc_last_5_0 & K1_NOT_climits_a_12); --K1_NOT_climits_d_13 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_13 --operation mode is normal K1_NOT_climits_d_13_lut_out = K1_NOT_climits_d_13; K1_NOT_climits_d_13 = DFFEAS(K1_NOT_climits_d_13_lut_out, S1__clk1, T1_chipRST_n, , K1_nx10, V1L541, , , K1_NOT_ix37_ix7_nx8); --K1_adc_last_7_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_1 --operation mode is normal K1_adc_last_7_1_lut_out = R1_RDATA_1; K1_adc_last_7_1 = DFFEAS(K1_adc_last_7_1_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_modgen_gt_271_nx30 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|modgen_gt_271_nx30 --operation mode is arithmetic K1_modgen_gt_271_nx30 = CARRY(K1_adc_last_7_0 & K1_NOT_climits_d_12); --PB1_data_1p_m_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_3 --operation mode is normal PB1_data_1p_m_3 = E1_or_mask_3 # !E1_NOT_and_mask_3 & (E1_NOT_xor_mask_3 $ !TB1_q_3); --RB1_modgen_gt_17_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|modgen_gt_17_nx56 --operation mode is normal RB1_modgen_gt_17_nx56 = E1_sel_s_2 # E1_sel_s_1 & E1_sel_s_0 # !E1_NOT_sel_s_3; --PB1_data_1p_m_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_4 --operation mode is normal PB1_data_1p_m_4 = E1_or_mask_4 # !E1_NOT_and_mask_4 & (E1_NOT_xor_mask_4 $ !TB1_q_4); --PB1_data_1p_m_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_5 --operation mode is normal PB1_data_1p_m_5 = E1_or_mask_5 # !E1_NOT_and_mask_5 & (E1_NOT_xor_mask_5 $ !TB1_q_5); --RB1_modgen_gt_15_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|modgen_gt_15_nx56 --operation mode is normal RB1_modgen_gt_15_nx56 = E1_sel_s_2 & (E1_sel_s_1 # E1_sel_s_0) # !E1_NOT_sel_s_3; --PB1_data_1p_m_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|data_1p_m_6 --operation mode is normal PB1_data_1p_m_6 = E1_or_mask_6 # !E1_NOT_and_mask_6 & (E1_NOT_xor_mask_6 $ !TB1_q_6); --RB1_modgen_gt_13_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|modgen_gt_13_nx56 --operation mode is normal RB1_modgen_gt_13_nx56 = E1_sel_s_2 & E1_sel_s_1 & E1_sel_s_0 # !E1_NOT_sel_s_3; --RB1_nx154 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_exclude_in_10_4:ex_p|nx154 --operation mode is normal RB1_nx154 = E1_sel_s_2 & E1_sel_s_1; --E1_or_mask_9 is ni2io_wt:wt_ni|or_mask_9 --operation mode is normal E1_or_mask_9_lut_out = E1_or_mask_9; E1_or_mask_9 = DFFEAS(E1_or_mask_9_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_22, , , E1_nx399); --E1_NOT_and_mask_9 is ni2io_wt:wt_ni|NOT_and_mask_9 --operation mode is normal E1_NOT_and_mask_9_lut_out = E1_NOT_and_mask_9; E1_NOT_and_mask_9 = DFFEAS(E1_NOT_and_mask_9_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L331, , , E1_nx399); --E1_NOT_xor_mask_9 is ni2io_wt:wt_ni|NOT_xor_mask_9 --operation mode is normal E1_NOT_xor_mask_9_lut_out = E1_NOT_xor_mask_9; E1_NOT_xor_mask_9 = DFFEAS(E1_NOT_xor_mask_9_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L311, , , E1_nx399); --TB1_q_9 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_9 --operation mode is normal TB1_q_9_lut_out = WT_P4D[9]; TB1_q_9 = DFFEAS(TB1_q_9_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --E1_or_mask_8 is ni2io_wt:wt_ni|or_mask_8 --operation mode is normal E1_or_mask_8_lut_out = E1_or_mask_8; E1_or_mask_8 = DFFEAS(E1_or_mask_8_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_23, , , E1_nx399); --E1_NOT_and_mask_8 is ni2io_wt:wt_ni|NOT_and_mask_8 --operation mode is normal E1_NOT_and_mask_8_lut_out = E1_NOT_and_mask_8; E1_NOT_and_mask_8 = DFFEAS(E1_NOT_and_mask_8_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L531, , , E1_nx399); --E1_NOT_xor_mask_8 is ni2io_wt:wt_ni|NOT_xor_mask_8 --operation mode is normal E1_NOT_xor_mask_8_lut_out = E1_NOT_xor_mask_8; E1_NOT_xor_mask_8 = DFFEAS(E1_NOT_xor_mask_8_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L511, , , E1_nx399); --TB1_q_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_8 --operation mode is normal TB1_q_8_lut_out = WT_P4D[8]; TB1_q_8 = DFFEAS(TB1_q_8_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --E1_or_mask_7 is ni2io_wt:wt_ni|or_mask_7 --operation mode is normal E1_or_mask_7_lut_out = E1_or_mask_7; E1_or_mask_7 = DFFEAS(E1_or_mask_7_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_24, , , E1_nx399); --E1_NOT_and_mask_7 is ni2io_wt:wt_ni|NOT_and_mask_7 --operation mode is normal E1_NOT_and_mask_7_lut_out = E1_NOT_and_mask_7; E1_NOT_and_mask_7 = DFFEAS(E1_NOT_and_mask_7_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L731, , , E1_nx399); --E1_NOT_xor_mask_7 is ni2io_wt:wt_ni|NOT_xor_mask_7 --operation mode is normal E1_NOT_xor_mask_7_lut_out = E1_NOT_xor_mask_7; E1_NOT_xor_mask_7 = DFFEAS(E1_NOT_xor_mask_7_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L711, , , E1_nx399); --TB1_q_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_7 --operation mode is normal TB1_q_7_lut_out = WT_P4D[7]; TB1_q_7 = DFFEAS(TB1_q_7_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --F1_bytes2send_25 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_25 --operation mode is normal F1_bytes2send_25_lut_out = F1_bytes2send_25; F1_bytes2send_25 = DFFEAS(F1_bytes2send_25_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_6, , , F1_a_1); --F1_byte_send_0 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_send_0 --operation mode is normal F1_byte_send_0_lut_out = F1_nx781 # F1_nx782 # F1_nx783 # F1_nx844; F1_byte_send_0 = DFFEAS(F1_byte_send_0_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2817, , , , ); --F1_bytes2send_41 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_41 --operation mode is normal F1_bytes2send_41_lut_out = F1_bytes2send_41; F1_bytes2send_41 = DFFEAS(F1_bytes2send_41_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_22, , , F1_a_3); --F1_bytes2send_17 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_17 --operation mode is normal F1_bytes2send_17_lut_out = F1_bytes2send_17; F1_bytes2send_17 = DFFEAS(F1_bytes2send_17_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_14, , , F1_a_1); --F1_bytes2send_33 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_33 --operation mode is normal F1_bytes2send_33_lut_out = V1_request_30; F1_bytes2send_33 = DFFEAS(F1_bytes2send_33_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx479, , , , ); --F1_bytes2send_9 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_9 --operation mode is normal F1_bytes2send_9_lut_out = F1_bytes2send_9; F1_bytes2send_9 = DFFEAS(F1_bytes2send_9_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_22, , , F1_a_1); --F1_bytes2send_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_1 --operation mode is normal F1_bytes2send_1_lut_out = V1_request_30; F1_bytes2send_1 = DFFEAS(F1_bytes2send_1_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx543, , , , ); --K1_cfr_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|cfr_1 --operation mode is normal K1_cfr_1_lut_out = V1_request_30; K1_cfr_1 = DFFEAS(K1_cfr_1_lut_out, S1__clk1, T1_chipRST_n, , K1_nx538, , , , ); --R1_datasr_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|datasr_0 --operation mode is normal R1_datasr_0_lut_out = K1_cfr_0 & R1_nx94; R1_datasr_0 = DFFEAS(R1_datasr_0_lut_out, S1__clk1, VCC, , R1_NOT_nx214, , , , ); --L1_cfr_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|cfr_1 --operation mode is normal L1_cfr_1_lut_out = V1_request_30; L1_cfr_1 = DFFEAS(L1_cfr_1_lut_out, S1__clk1, T1_chipRST_n, , L1_nx538, , , , ); --R2_datasr_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_0 --operation mode is normal R2_datasr_0_lut_out = L1_cfr_0 & R2_nx94; R2_datasr_0 = DFFEAS(R2_datasr_0_lut_out, S1__clk1, VCC, , R2_NOT_nx214, , , , ); --AB1_ob_data_58 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_58 --operation mode is normal AB1_ob_data_58_lut_out = AB1_ob_data_57; AB1_ob_data_58 = DFFEAS(AB1_ob_data_58_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_58, , , AB1_a_2); --LB1_d_to_dll_59 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_59 --operation mode is normal LB1_d_to_dll_59 = !DB3_data_out_2 & LB1_forward_buffer_59 & (DB3_data_out_0 # !V1_altered_frame0); --AB1_ob_crc_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_5 --operation mode is normal AB1_ob_crc_5_lut_out = AB1_ob_crc_4; AB1_ob_crc_5 = DFFEAS(AB1_ob_crc_5_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_58, , , AB1_a_2); --AB2_ob_data_58 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_58 --operation mode is normal AB2_ob_data_58_lut_out = AB2_ob_data_57; AB2_ob_data_58 = DFFEAS(AB2_ob_data_58_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_58, , , AB2_a_2); --LB2_d_to_dll_59 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_59 --operation mode is normal LB2_d_to_dll_59 = !DB4_data_out_2 & LB2_forward_buffer_59 & (DB4_data_out_0 # !V1_altered_frame1); --AB2_ob_crc_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_5 --operation mode is normal AB2_ob_crc_5_lut_out = AB2_ob_crc_4; AB2_ob_crc_5 = DFFEAS(AB2_ob_crc_5_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_58, , , AB2_a_2); --M1_PQ_1 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_1 --operation mode is normal M1_PQ_1_lut_out = V1_request_30; M1_PQ_1 = DFFEAS(M1_PQ_1_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_dup0_0, , , M1_SERREG_1); --R1_RDATA_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|TLV2548:adc|RDATA_1 --operation mode is normal R1_RDATA_1_lut_out = R1_RDATA_0; R1_RDATA_1 = DFFEAS(R1_RDATA_1_lut_out, S1__clk1, VCC, , R1_NOT_nx295, , , , ); --K1_adc_last_5_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_5_0 --operation mode is normal K1_adc_last_5_0_lut_out = R1_RDATA_0; K1_adc_last_5_0 = DFFEAS(K1_adc_last_5_0_lut_out, S1__clk1, VCC, , K1_NOT_nx2309, , , , ); --K1_NOT_climits_a_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_a_12 --operation mode is normal K1_NOT_climits_a_12_lut_out = !V1_request_19; K1_NOT_climits_a_12 = DFFEAS(K1_NOT_climits_a_12_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx510, , , , ); --K1_adc_last_7_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_7_0 --operation mode is normal K1_adc_last_7_0_lut_out = R1_RDATA_0; K1_adc_last_7_0 = DFFEAS(K1_adc_last_7_0_lut_out, S1__clk1, VCC, , K1_modgen_select_210_nx2, , , , ); --K1_NOT_climits_d_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_climits_d_12 --operation mode is normal K1_NOT_climits_d_12_lut_out = !V1_request_19; K1_NOT_climits_d_12 = DFFEAS(K1_NOT_climits_d_12_lut_out, S1__clk1, T1_chipRST_n, , K1_NOT_nx462, , , , ); --E1_or_mask_3 is ni2io_wt:wt_ni|or_mask_3 --operation mode is normal E1_or_mask_3_lut_out = E1_or_mask_3; E1_or_mask_3 = DFFEAS(E1_or_mask_3_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_28, , , E1_nx399); --E1_NOT_and_mask_3 is ni2io_wt:wt_ni|NOT_and_mask_3 --operation mode is normal E1_NOT_and_mask_3_lut_out = E1_NOT_and_mask_3; E1_NOT_and_mask_3 = DFFEAS(E1_NOT_and_mask_3_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L541, , , E1_nx399); --E1_NOT_xor_mask_3 is ni2io_wt:wt_ni|NOT_xor_mask_3 --operation mode is normal E1_NOT_xor_mask_3_lut_out = E1_NOT_xor_mask_3; E1_NOT_xor_mask_3 = DFFEAS(E1_NOT_xor_mask_3_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L521, , , E1_nx399); --TB1_q_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_3 --operation mode is normal TB1_q_3_lut_out = WT_P4D[3]; TB1_q_3 = DFFEAS(TB1_q_3_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --E1_or_mask_4 is ni2io_wt:wt_ni|or_mask_4 --operation mode is normal E1_or_mask_4_lut_out = E1_or_mask_4; E1_or_mask_4 = DFFEAS(E1_or_mask_4_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_27, , , E1_nx399); --E1_NOT_and_mask_4 is ni2io_wt:wt_ni|NOT_and_mask_4 --operation mode is normal E1_NOT_and_mask_4_lut_out = E1_NOT_and_mask_4; E1_NOT_and_mask_4 = DFFEAS(E1_NOT_and_mask_4_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L341, , , E1_nx399); --E1_NOT_xor_mask_4 is ni2io_wt:wt_ni|NOT_xor_mask_4 --operation mode is normal E1_NOT_xor_mask_4_lut_out = E1_NOT_xor_mask_4; E1_NOT_xor_mask_4 = DFFEAS(E1_NOT_xor_mask_4_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L321, , , E1_nx399); --TB1_q_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_4 --operation mode is normal TB1_q_4_lut_out = WT_P4D[4]; TB1_q_4 = DFFEAS(TB1_q_4_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --E1_or_mask_5 is ni2io_wt:wt_ni|or_mask_5 --operation mode is normal E1_or_mask_5_lut_out = E1_or_mask_5; E1_or_mask_5 = DFFEAS(E1_or_mask_5_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_26, , , E1_nx399); --E1_NOT_and_mask_5 is ni2io_wt:wt_ni|NOT_and_mask_5 --operation mode is normal E1_NOT_and_mask_5_lut_out = E1_NOT_and_mask_5; E1_NOT_and_mask_5 = DFFEAS(E1_NOT_and_mask_5_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L141, , , E1_nx399); --E1_NOT_xor_mask_5 is ni2io_wt:wt_ni|NOT_xor_mask_5 --operation mode is normal E1_NOT_xor_mask_5_lut_out = E1_NOT_xor_mask_5; E1_NOT_xor_mask_5 = DFFEAS(E1_NOT_xor_mask_5_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L121, , , E1_nx399); --TB1_q_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_5 --operation mode is normal TB1_q_5_lut_out = WT_P4D[5]; TB1_q_5 = DFFEAS(TB1_q_5_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --E1_or_mask_6 is ni2io_wt:wt_ni|or_mask_6 --operation mode is normal E1_or_mask_6_lut_out = E1_or_mask_6; E1_or_mask_6 = DFFEAS(E1_or_mask_6_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1_request_25, , , E1_nx399); --E1_NOT_and_mask_6 is ni2io_wt:wt_ni|NOT_and_mask_6 --operation mode is normal E1_NOT_and_mask_6_lut_out = E1_NOT_and_mask_6; E1_NOT_and_mask_6 = DFFEAS(E1_NOT_and_mask_6_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L931, , , E1_nx399); --E1_NOT_xor_mask_6 is ni2io_wt:wt_ni|NOT_xor_mask_6 --operation mode is normal E1_NOT_xor_mask_6_lut_out = E1_NOT_xor_mask_6; E1_NOT_xor_mask_6 = DFFEAS(E1_NOT_xor_mask_6_lut_out, S1__clk1, T1_chipRST_n, , E1_nx396, V1L911, , , E1_nx399); --TB1_q_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|reg_clr_10:rg1p|q_6 --operation mode is normal TB1_q_6_lut_out = WT_P4D[6]; TB1_q_6 = DFFEAS(TB1_q_6_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --F1_nx781 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx781 --operation mode is normal F1_nx781 = F1_bytes2send_40 & (F1_nx794 # F1_bytes2send_16 & F1_nx799) # !F1_bytes2send_40 & F1_bytes2send_16 & (F1_nx799); --F1_nx782 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx782 --operation mode is normal F1_nx782 = F1_bytes2send_32 & (F1_nx796 # F1_iword2send_0 & F1_nx793) # !F1_bytes2send_32 & F1_iword2send_0 & F1_nx793; --F1_nx783 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx783 --operation mode is normal F1_nx783 = F1_bytes2send_8 & (F1_nx795 # F1_bytes2send_0 & F1_nx797) # !F1_bytes2send_8 & F1_bytes2send_0 & (F1_nx797); --F1_nx844 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx844 --operation mode is normal F1_nx844 = F1_bytes2send_24 & F1_nx798; --AB1_ob_data_57 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_57 --operation mode is normal AB1_ob_data_57_lut_out = AB1_ob_data_56; AB1_ob_data_57 = DFFEAS(AB1_ob_data_57_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_57, , , AB1_a_2); --LB1_d_to_dll_58 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_58 --operation mode is normal LB1_d_to_dll_58 = !DB3_data_out_2 & LB1_forward_buffer_58 & (DB3_data_out_0 # !V1_altered_frame0); --AB1_ob_crc_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_4 --operation mode is normal AB1_ob_crc_4_lut_out = AB1_ob_crc_3; AB1_ob_crc_4 = DFFEAS(AB1_ob_crc_4_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_57, , , AB1_a_2); --AB2_ob_data_57 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_57 --operation mode is normal AB2_ob_data_57_lut_out = AB2_ob_data_56; AB2_ob_data_57 = DFFEAS(AB2_ob_data_57_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_57, , , AB2_a_2); --LB2_d_to_dll_58 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_58 --operation mode is normal LB2_d_to_dll_58 = !DB4_data_out_2 & LB2_forward_buffer_58 & (DB4_data_out_0 # !V1_altered_frame1); --AB2_ob_crc_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_4 --operation mode is normal AB2_ob_crc_4_lut_out = AB2_ob_crc_3; AB2_ob_crc_4 = DFFEAS(AB2_ob_crc_4_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_57, , , AB2_a_2); --M1_PQ_dup0_0 is ADC_DAC_1_notri:adcdac_notri|TLV5630_16:slow_dac2|PQ_dup0_0 --operation mode is normal M1_PQ_dup0_0_lut_out = V1_request_31; M1_PQ_dup0_0 = DFFEAS(M1_PQ_dup0_0_lut_out, S1__clk1, VCC, , M1_NOT_nx150, M1_PQ_15, , , M1_SERREG_1); --F1_bytes2send_40 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_40 --operation mode is normal F1_bytes2send_40_lut_out = F1_bytes2send_40; F1_bytes2send_40 = DFFEAS(F1_bytes2send_40_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_23, , , F1_a_3); --F1_bytes2send_16 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_16 --operation mode is normal F1_bytes2send_16_lut_out = F1_bytes2send_16; F1_bytes2send_16 = DFFEAS(F1_bytes2send_16_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_15, , , F1_a_1); --F1_bytes2send_8 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_8 --operation mode is normal F1_bytes2send_8_lut_out = F1_bytes2send_8; F1_bytes2send_8 = DFFEAS(F1_bytes2send_8_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_23, , , F1_a_1); --F1_bytes2send_24 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes2send_24 --operation mode is normal F1_bytes2send_24_lut_out = F1_bytes2send_24; F1_bytes2send_24 = DFFEAS(F1_bytes2send_24_lut_out, S1__clk1, T1_chipRST_n, , F1_nx8, V1_request_7, , , F1_a_1); --AB1_ob_data_56 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_56 --operation mode is normal AB1_ob_data_56_lut_out = AB1_ob_data_55; AB1_ob_data_56 = DFFEAS(AB1_ob_data_56_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_56, , , AB1_a_2); --LB1_d_to_dll_57 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_57 --operation mode is normal LB1_d_to_dll_57 = !DB3_data_out_2 & LB1_forward_buffer_57 & (DB3_data_out_0 # !V1_altered_frame0); --AB1_ob_crc_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_3 --operation mode is normal AB1_ob_crc_3_lut_out = AB1_ob_crc_2; AB1_ob_crc_3 = DFFEAS(AB1_ob_crc_3_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_56, , , AB1_a_2); --AB2_ob_data_56 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_56 --operation mode is normal AB2_ob_data_56_lut_out = AB2_ob_data_55; AB2_ob_data_56 = DFFEAS(AB2_ob_data_56_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_56, , , AB2_a_2); --LB2_d_to_dll_57 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_57 --operation mode is normal LB2_d_to_dll_57 = !DB4_data_out_2 & LB2_forward_buffer_57 & (DB4_data_out_0 # !V1_altered_frame1); --AB2_ob_crc_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_3 --operation mode is normal AB2_ob_crc_3_lut_out = AB2_ob_crc_2; AB2_ob_crc_3 = DFFEAS(AB2_ob_crc_3_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_56, , , AB2_a_2); --AB1_ob_data_55 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_55 --operation mode is normal AB1_ob_data_55_lut_out = AB1_ob_data_54; AB1_ob_data_55 = DFFEAS(AB1_ob_data_55_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_55, , , AB1_a_2); --LB1_d_to_dll_56 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_56 --operation mode is normal LB1_d_to_dll_56 = !DB3_data_out_2 & LB1_forward_buffer_56 & (DB3_data_out_0 # !V1_altered_frame0); --AB1_ob_crc_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_2 --operation mode is normal AB1_ob_crc_2_lut_out = AB1_ob_crc_1 $ (AB1_ob_crc_15 & (AB1_NOT_ob_empty)); AB1_ob_crc_2 = DFFEAS(AB1_ob_crc_2_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_55, , , AB1_a_2); --AB2_ob_data_55 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_55 --operation mode is normal AB2_ob_data_55_lut_out = AB2_ob_data_54; AB2_ob_data_55 = DFFEAS(AB2_ob_data_55_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_55, , , AB2_a_2); --LB2_d_to_dll_56 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_56 --operation mode is normal LB2_d_to_dll_56 = !DB4_data_out_2 & LB2_forward_buffer_56 & (DB4_data_out_0 # !V1_altered_frame1); --AB2_ob_crc_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_2 --operation mode is normal AB2_ob_crc_2_lut_out = AB2_ob_crc_1 $ (AB2_ob_crc_15 & (AB2_NOT_ob_empty)); AB2_ob_crc_2 = DFFEAS(AB2_ob_crc_2_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_55, , , AB2_a_2); --AB1_ob_data_54 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_54 --operation mode is normal AB1_ob_data_54_lut_out = AB1_ob_data_53; AB1_ob_data_54 = DFFEAS(AB1_ob_data_54_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_54, , , AB1_a_2); --LB1_d_to_dll_55 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_55 --operation mode is normal LB1_d_to_dll_55 = !DB3_data_out_2 & LB1_forward_buffer_55 & (DB3_data_out_0 # !V1_altered_frame0); --AB1_ob_crc_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_1 --operation mode is normal AB1_ob_crc_1_lut_out = AB1_ob_crc_0; AB1_ob_crc_1 = DFFEAS(AB1_ob_crc_1_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_54, , , AB1_a_2); --AB2_ob_data_54 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_54 --operation mode is normal AB2_ob_data_54_lut_out = AB2_ob_data_53; AB2_ob_data_54 = DFFEAS(AB2_ob_data_54_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_54, , , AB2_a_2); --LB2_d_to_dll_55 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_55 --operation mode is normal LB2_d_to_dll_55 = !DB4_data_out_2 & LB2_forward_buffer_55 & (DB4_data_out_0 # !V1_altered_frame1); --AB2_ob_crc_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_1 --operation mode is normal AB2_ob_crc_1_lut_out = AB2_ob_crc_0; AB2_ob_crc_1 = DFFEAS(AB2_ob_crc_1_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_54, , , AB2_a_2); --AB1_ob_data_53 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_53 --operation mode is normal AB1_ob_data_53_lut_out = AB1_ob_data_52; AB1_ob_data_53 = DFFEAS(AB1_ob_data_53_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_53, , , AB1_a_2); --LB1_d_to_dll_54 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_54 --operation mode is normal LB1_d_to_dll_54 = !DB3_data_out_2 & LB1_forward_buffer_54 & (DB3_data_out_0 # !V1_altered_frame0); --AB1_ob_crc_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_0 --operation mode is normal AB1_ob_crc_0_lut_out = AB1_ob_data_52 $ (AB1_ob_crc_15 & (AB1_NOT_ob_empty)); AB1_ob_crc_0 = DFFEAS(AB1_ob_crc_0_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_53, , , AB1_a_2); --AB2_ob_data_53 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_53 --operation mode is normal AB2_ob_data_53_lut_out = AB2_ob_data_52; AB2_ob_data_53 = DFFEAS(AB2_ob_data_53_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_53, , , AB2_a_2); --LB2_d_to_dll_54 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_54 --operation mode is normal LB2_d_to_dll_54 = !DB4_data_out_2 & LB2_forward_buffer_54 & (DB4_data_out_0 # !V1_altered_frame1); --AB2_ob_crc_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_0 --operation mode is normal AB2_ob_crc_0_lut_out = AB2_ob_data_52 $ (AB2_ob_crc_15 & (AB2_NOT_ob_empty)); AB2_ob_crc_0 = DFFEAS(AB2_ob_crc_0_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_53, , , AB2_a_2); --AB1_ob_data_52 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_52 --operation mode is normal AB1_ob_data_52_lut_out = AB1_ob_data_51; AB1_ob_data_52 = DFFEAS(AB1_ob_data_52_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_52, , , AB1_a_2); --LB1_d_to_dll_53 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_53 --operation mode is normal LB1_d_to_dll_53 = !DB3_data_out_2 & LB1_forward_buffer_53 & (DB3_data_out_0 # !V1_altered_frame0); --AB2_ob_data_52 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_52 --operation mode is normal AB2_ob_data_52_lut_out = AB2_ob_data_51; AB2_ob_data_52 = DFFEAS(AB2_ob_data_52_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_52, , , AB2_a_2); --LB2_d_to_dll_53 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_53 --operation mode is normal LB2_d_to_dll_53 = !DB4_data_out_2 & LB2_forward_buffer_53 & (DB4_data_out_0 # !V1_altered_frame1); --AB1_ob_data_51 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_51 --operation mode is normal AB1_ob_data_51_lut_out = AB1_ob_data_50; AB1_ob_data_51 = DFFEAS(AB1_ob_data_51_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_51, , , AB1_a_2); --LB1_d_to_dll_52 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_52 --operation mode is normal LB1_d_to_dll_52 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_52 # !DB3_data_out_0 & (T1_reply_52)); --AB2_ob_data_51 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_51 --operation mode is normal AB2_ob_data_51_lut_out = AB2_ob_data_50; AB2_ob_data_51 = DFFEAS(AB2_ob_data_51_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_51, , , AB2_a_2); --LB2_d_to_dll_52 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_52 --operation mode is normal LB2_d_to_dll_52 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_52 # !DB4_data_out_0 & (T1_reply_52)); --AB1_ob_data_50 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_50 --operation mode is normal AB1_ob_data_50_lut_out = AB1_ob_data_49; AB1_ob_data_50 = DFFEAS(AB1_ob_data_50_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_50, , , AB1_a_2); --LB1_d_to_dll_51 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_51 --operation mode is normal LB1_d_to_dll_51 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_51 # !DB3_data_out_0 & (T1_reply_51)); --T1_reply_52 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_52 --operation mode is normal T1_reply_52 = V1_request_52 # !X1_data_out_1 & !X1_data_out_0 & !T1_ix34_ix22_nx10; --AB2_ob_data_50 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_50 --operation mode is normal AB2_ob_data_50_lut_out = AB2_ob_data_49; AB2_ob_data_50 = DFFEAS(AB2_ob_data_50_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_50, , , AB2_a_2); --LB2_d_to_dll_51 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_51 --operation mode is normal LB2_d_to_dll_51 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_51 # !DB4_data_out_0 & (T1_reply_51)); --AB1_ob_data_49 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_49 --operation mode is normal AB1_ob_data_49_lut_out = AB1_ob_data_48; AB1_ob_data_49 = DFFEAS(AB1_ob_data_49_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_49, , , AB1_a_2); --LB1_d_to_dll_50 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_50 --operation mode is normal LB1_d_to_dll_50 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_50 # !DB3_data_out_0 & (T1_reply_50)); --T1_reply_51 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_51 --operation mode is normal T1_reply_51 = V1_request_51 # !X1_data_out_1 & !X1_data_out_0 & !T1_ix34_ix22_nx10; --T1_ix34_ix22_nx10 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|ix34_ix22_nx10 --operation mode is normal T1_ix34_ix22_nx10 = X1_data_out_2 # !X1_data_out_3; --AB2_ob_data_49 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_49 --operation mode is normal AB2_ob_data_49_lut_out = AB2_ob_data_48; AB2_ob_data_49 = DFFEAS(AB2_ob_data_49_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_49, , , AB2_a_2); --LB2_d_to_dll_50 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_50 --operation mode is normal LB2_d_to_dll_50 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_50 # !DB4_data_out_0 & (T1_reply_50)); --AB1_ob_data_48 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_48 --operation mode is normal AB1_ob_data_48_lut_out = AB1_ob_data_47; AB1_ob_data_48 = DFFEAS(AB1_ob_data_48_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_48, , , AB1_a_2); --LB1_d_to_dll_49 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_49 --operation mode is normal LB1_d_to_dll_49 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_49 # !DB3_data_out_0 & (T1_reply_49)); --T1_reply_50 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_50 --operation mode is normal T1_reply_50 = V1_request_50 # !X1_data_out_1 & !X1_data_out_0 & !T1_ix34_ix22_nx10; --AB2_ob_data_48 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_48 --operation mode is normal AB2_ob_data_48_lut_out = AB2_ob_data_47; AB2_ob_data_48 = DFFEAS(AB2_ob_data_48_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_48, , , AB2_a_2); --LB2_d_to_dll_49 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_49 --operation mode is normal LB2_d_to_dll_49 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_49 # !DB4_data_out_0 & (T1_reply_49)); --AB1_ob_data_47 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_47 --operation mode is normal AB1_ob_data_47_lut_out = AB1_ob_data_46; AB1_ob_data_47 = DFFEAS(AB1_ob_data_47_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_47, , , AB1_a_2); --LB1_d_to_dll_48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_48 --operation mode is normal LB1_d_to_dll_48 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_48 # !DB3_data_out_0 & (T1_reply_48)); --T1_reply_49 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_49 --operation mode is normal T1_reply_49 = V1_request_49 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_47 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_47 --operation mode is normal AB2_ob_data_47_lut_out = AB2_ob_data_46; AB2_ob_data_47 = DFFEAS(AB2_ob_data_47_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_47, , , AB2_a_2); --LB2_d_to_dll_48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_48 --operation mode is normal LB2_d_to_dll_48 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_48 # !DB4_data_out_0 & (T1_reply_48)); --AB1_ob_data_46 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_46 --operation mode is normal AB1_ob_data_46_lut_out = AB1_ob_data_45; AB1_ob_data_46 = DFFEAS(AB1_ob_data_46_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_46, , , AB1_a_2); --LB1_d_to_dll_47 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_47 --operation mode is normal LB1_d_to_dll_47 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_47 # !DB3_data_out_0 & (T1_reply_47)); --T1_reply_48 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_48 --operation mode is normal T1_reply_48 = V1_request_48 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_46 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_46 --operation mode is normal AB2_ob_data_46_lut_out = AB2_ob_data_45; AB2_ob_data_46 = DFFEAS(AB2_ob_data_46_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_46, , , AB2_a_2); --LB2_d_to_dll_47 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_47 --operation mode is normal LB2_d_to_dll_47 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_47 # !DB4_data_out_0 & (T1_reply_47)); --AB1_ob_data_45 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_45 --operation mode is normal AB1_ob_data_45_lut_out = AB1_ob_data_44; AB1_ob_data_45 = DFFEAS(AB1_ob_data_45_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_45, , , AB1_a_2); --LB1_d_to_dll_46 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_46 --operation mode is normal LB1_d_to_dll_46 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_46 # !DB3_data_out_0 & (T1_reply_46)); --T1_reply_47 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_47 --operation mode is normal T1_reply_47 = V1_request_47 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_45 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_45 --operation mode is normal AB2_ob_data_45_lut_out = AB2_ob_data_44; AB2_ob_data_45 = DFFEAS(AB2_ob_data_45_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_45, , , AB2_a_2); --LB2_d_to_dll_46 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_46 --operation mode is normal LB2_d_to_dll_46 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_46 # !DB4_data_out_0 & (T1_reply_46)); --AB1_ob_data_44 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_44 --operation mode is normal AB1_ob_data_44_lut_out = AB1_ob_data_43; AB1_ob_data_44 = DFFEAS(AB1_ob_data_44_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_44, , , AB1_a_2); --LB1_d_to_dll_45 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_45 --operation mode is normal LB1_d_to_dll_45 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_45 # !DB3_data_out_0 & (T1_reply_45)); --T1_reply_46 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_46 --operation mode is normal T1_reply_46 = V1_request_46 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_44 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_44 --operation mode is normal AB2_ob_data_44_lut_out = AB2_ob_data_43; AB2_ob_data_44 = DFFEAS(AB2_ob_data_44_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_44, , , AB2_a_2); --LB2_d_to_dll_45 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_45 --operation mode is normal LB2_d_to_dll_45 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_45 # !DB4_data_out_0 & (T1_reply_45)); --AB1_ob_data_43 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_43 --operation mode is normal AB1_ob_data_43_lut_out = AB1_ob_data_42; AB1_ob_data_43 = DFFEAS(AB1_ob_data_43_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_43, , , AB1_a_2); --LB1_d_to_dll_44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_44 --operation mode is normal LB1_d_to_dll_44 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_44 # !DB3_data_out_0 & (T1_reply_44)); --T1_reply_45 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_45 --operation mode is normal T1_reply_45 = V1_request_45 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_43 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_43 --operation mode is normal AB2_ob_data_43_lut_out = AB2_ob_data_42; AB2_ob_data_43 = DFFEAS(AB2_ob_data_43_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_43, , , AB2_a_2); --LB2_d_to_dll_44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_44 --operation mode is normal LB2_d_to_dll_44 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_44 # !DB4_data_out_0 & (T1_reply_44)); --AB1_ob_data_42 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_42 --operation mode is normal AB1_ob_data_42_lut_out = AB1_ob_data_41; AB1_ob_data_42 = DFFEAS(AB1_ob_data_42_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_42, , , AB1_a_2); --LB1_d_to_dll_43 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_43 --operation mode is normal LB1_d_to_dll_43 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_43 # !DB3_data_out_0 & (T1_reply_43)); --T1_reply_44 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_44 --operation mode is normal T1_reply_44 = V1_request_44 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_42 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_42 --operation mode is normal AB2_ob_data_42_lut_out = AB2_ob_data_41; AB2_ob_data_42 = DFFEAS(AB2_ob_data_42_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_42, , , AB2_a_2); --LB2_d_to_dll_43 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_43 --operation mode is normal LB2_d_to_dll_43 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_43 # !DB4_data_out_0 & (T1_reply_43)); --AB1_ob_data_41 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_41 --operation mode is normal AB1_ob_data_41_lut_out = AB1_ob_data_40; AB1_ob_data_41 = DFFEAS(AB1_ob_data_41_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_41, , , AB1_a_2); --LB1_d_to_dll_42 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_42 --operation mode is normal LB1_d_to_dll_42 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_42 # !DB3_data_out_0 & (T1_reply_42)); --T1_reply_43 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_43 --operation mode is normal T1_reply_43 = V1_request_43 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_41 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_41 --operation mode is normal AB2_ob_data_41_lut_out = AB2_ob_data_40; AB2_ob_data_41 = DFFEAS(AB2_ob_data_41_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_41, , , AB2_a_2); --LB2_d_to_dll_42 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_42 --operation mode is normal LB2_d_to_dll_42 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_42 # !DB4_data_out_0 & (T1_reply_42)); --AB1_ob_data_40 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_40 --operation mode is normal AB1_ob_data_40_lut_out = AB1_ob_data_39; AB1_ob_data_40 = DFFEAS(AB1_ob_data_40_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_40, , , AB1_a_2); --LB1_d_to_dll_41 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_41 --operation mode is normal LB1_d_to_dll_41 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_41 # !DB3_data_out_0 & (T1_reply_41)); --T1_reply_42 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_42 --operation mode is normal T1_reply_42 = V1_request_42 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_40 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_40 --operation mode is normal AB2_ob_data_40_lut_out = AB2_ob_data_39; AB2_ob_data_40 = DFFEAS(AB2_ob_data_40_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_40, , , AB2_a_2); --LB2_d_to_dll_41 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_41 --operation mode is normal LB2_d_to_dll_41 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_41 # !DB4_data_out_0 & (T1_reply_41)); --AB1_ob_data_39 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_39 --operation mode is normal AB1_ob_data_39_lut_out = AB1_ob_data_38; AB1_ob_data_39 = DFFEAS(AB1_ob_data_39_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_39, , , AB1_a_2); --LB1_d_to_dll_40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_40 --operation mode is normal LB1_d_to_dll_40 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_40 # !DB3_data_out_0 & (T1_reply_40)); --T1_reply_41 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_41 --operation mode is normal T1_reply_41 = V1_request_41 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_39 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_39 --operation mode is normal AB2_ob_data_39_lut_out = AB2_ob_data_38; AB2_ob_data_39 = DFFEAS(AB2_ob_data_39_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_39, , , AB2_a_2); --LB2_d_to_dll_40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_40 --operation mode is normal LB2_d_to_dll_40 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_40 # !DB4_data_out_0 & (T1_reply_40)); --AB1_ob_data_38 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_38 --operation mode is normal AB1_ob_data_38_lut_out = AB1_ob_data_37; AB1_ob_data_38 = DFFEAS(AB1_ob_data_38_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_38, , , AB1_a_2); --LB1_d_to_dll_39 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_39 --operation mode is normal LB1_d_to_dll_39 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_39 # !DB3_data_out_0 & (T1_reply_39)); --T1_reply_40 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_40 --operation mode is normal T1_reply_40 = V1_request_40 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_38 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_38 --operation mode is normal AB2_ob_data_38_lut_out = AB2_ob_data_37; AB2_ob_data_38 = DFFEAS(AB2_ob_data_38_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_38, , , AB2_a_2); --LB2_d_to_dll_39 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_39 --operation mode is normal LB2_d_to_dll_39 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_39 # !DB4_data_out_0 & (T1_reply_39)); --AB1_ob_data_37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_37 --operation mode is normal AB1_ob_data_37_lut_out = AB1_ob_data_36; AB1_ob_data_37 = DFFEAS(AB1_ob_data_37_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_37, , , AB1_a_2); --LB1_d_to_dll_38 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_38 --operation mode is normal LB1_d_to_dll_38 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_38 # !DB3_data_out_0 & (T1_reply_38)); --T1_reply_39 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_39 --operation mode is normal T1_reply_39 = V1_request_39 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_37 --operation mode is normal AB2_ob_data_37_lut_out = AB2_ob_data_36; AB2_ob_data_37 = DFFEAS(AB2_ob_data_37_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_37, , , AB2_a_2); --LB2_d_to_dll_38 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_38 --operation mode is normal LB2_d_to_dll_38 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_38 # !DB4_data_out_0 & (T1_reply_38)); --AB1_ob_data_36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_36 --operation mode is normal AB1_ob_data_36_lut_out = AB1_ob_data_35; AB1_ob_data_36 = DFFEAS(AB1_ob_data_36_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_36, , , AB1_a_2); --LB1_d_to_dll_37 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_37 --operation mode is normal LB1_d_to_dll_37 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_37 # !DB3_data_out_0 & (T1_reply_37)); --T1_reply_38 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_38 --operation mode is normal T1_reply_38 = V1_request_38 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_36 --operation mode is normal AB2_ob_data_36_lut_out = AB2_ob_data_35; AB2_ob_data_36 = DFFEAS(AB2_ob_data_36_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_36, , , AB2_a_2); --LB2_d_to_dll_37 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_37 --operation mode is normal LB2_d_to_dll_37 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_37 # !DB4_data_out_0 & (T1_reply_37)); --AB1_ob_data_35 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_35 --operation mode is normal AB1_ob_data_35_lut_out = AB1_ob_data_34; AB1_ob_data_35 = DFFEAS(AB1_ob_data_35_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_35, , , AB1_a_2); --LB1_d_to_dll_36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_36 --operation mode is normal LB1_d_to_dll_36 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_36 # !DB3_data_out_0 & (T1_reply_36)); --T1_reply_37 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_37 --operation mode is normal T1_reply_37 = V1_request_37 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_35 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_35 --operation mode is normal AB2_ob_data_35_lut_out = AB2_ob_data_34; AB2_ob_data_35 = DFFEAS(AB2_ob_data_35_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_35, , , AB2_a_2); --LB2_d_to_dll_36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_36 --operation mode is normal LB2_d_to_dll_36 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_36 # !DB4_data_out_0 & (T1_reply_36)); --AB1_ob_data_34 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_34 --operation mode is normal AB1_ob_data_34_lut_out = AB1_ob_data_33; AB1_ob_data_34 = DFFEAS(AB1_ob_data_34_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_34, , , AB1_a_2); --LB1_d_to_dll_35 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_35 --operation mode is normal LB1_d_to_dll_35 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_35 # !DB3_data_out_0 & (T1_reply_35)); --T1_reply_36 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_36 --operation mode is normal T1_reply_36 = V1_request_36 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_34 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_34 --operation mode is normal AB2_ob_data_34_lut_out = AB2_ob_data_33; AB2_ob_data_34 = DFFEAS(AB2_ob_data_34_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_34, , , AB2_a_2); --LB2_d_to_dll_35 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_35 --operation mode is normal LB2_d_to_dll_35 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_35 # !DB4_data_out_0 & (T1_reply_35)); --AB1_ob_data_33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_33 --operation mode is normal AB1_ob_data_33_lut_out = AB1_ob_data_32; AB1_ob_data_33 = DFFEAS(AB1_ob_data_33_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_33, , , AB1_a_2); --LB1_d_to_dll_34 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_34 --operation mode is normal LB1_d_to_dll_34 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_34 # !DB3_data_out_0 & (T1_reply_34)); --T1_reply_35 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_35 --operation mode is normal T1_reply_35 = V1_request_35 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_33 --operation mode is normal AB2_ob_data_33_lut_out = AB2_ob_data_32; AB2_ob_data_33 = DFFEAS(AB2_ob_data_33_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_33, , , AB2_a_2); --LB2_d_to_dll_34 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_34 --operation mode is normal LB2_d_to_dll_34 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_34 # !DB4_data_out_0 & (T1_reply_34)); --AB1_ob_data_32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_32 --operation mode is normal AB1_ob_data_32_lut_out = AB1_ob_data_31; AB1_ob_data_32 = DFFEAS(AB1_ob_data_32_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_32, , , AB1_a_2); --LB1_d_to_dll_33 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_33 --operation mode is normal LB1_d_to_dll_33 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_33 # !DB3_data_out_0 & (T1_reply_33)); --T1_reply_34 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_34 --operation mode is normal T1_reply_34 = V1_request_34 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_32 --operation mode is normal AB2_ob_data_32_lut_out = AB2_ob_data_31; AB2_ob_data_32 = DFFEAS(AB2_ob_data_32_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_32, , , AB2_a_2); --LB2_d_to_dll_33 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_33 --operation mode is normal LB2_d_to_dll_33 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_33 # !DB4_data_out_0 & (T1_reply_33)); --AB1_ob_data_31 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_31 --operation mode is normal AB1_ob_data_31_lut_out = AB1_ob_data_30; AB1_ob_data_31 = DFFEAS(AB1_ob_data_31_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_31, , , AB1_a_2); --LB1_d_to_dll_32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_32 --operation mode is normal LB1_d_to_dll_32 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_32 # !DB3_data_out_0 & (T1_reply_32)); --T1_reply_33 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_33 --operation mode is normal T1_reply_33 = V1_request_33 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_31 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_31 --operation mode is normal AB2_ob_data_31_lut_out = AB2_ob_data_30; AB2_ob_data_31 = DFFEAS(AB2_ob_data_31_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_31, , , AB2_a_2); --LB2_d_to_dll_32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_32 --operation mode is normal LB2_d_to_dll_32 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_32 # !DB4_data_out_0 & (T1_reply_32)); --AB1_ob_data_30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_30 --operation mode is normal AB1_ob_data_30_lut_out = AB1_ob_data_29; AB1_ob_data_30 = DFFEAS(AB1_ob_data_30_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_30, , , AB1_a_2); --LB1_d_to_dll_31 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_31 --operation mode is normal LB1_d_to_dll_31 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_31 # !DB3_data_out_0 & (T1_reply_31)); --T1_reply_32 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_32 --operation mode is normal T1_reply_32 = V1_request_32 & (X1_data_out_1 # X1_data_out_0 # T1_ix34_ix22_nx10); --AB2_ob_data_30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_30 --operation mode is normal AB2_ob_data_30_lut_out = AB2_ob_data_29; AB2_ob_data_30 = DFFEAS(AB2_ob_data_30_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_30, , , AB2_a_2); --LB2_d_to_dll_31 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_31 --operation mode is normal LB2_d_to_dll_31 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_31 # !DB4_data_out_0 & (T1_reply_31)); --AB1_ob_data_29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_29 --operation mode is normal AB1_ob_data_29_lut_out = AB1_ob_data_28; AB1_ob_data_29 = DFFEAS(AB1_ob_data_29_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_29, , , AB1_a_2); --LB1_d_to_dll_30 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_30 --operation mode is normal LB1_d_to_dll_30 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_30 # !DB3_data_out_0 & (T1_reply_30)); --T1_reply_31 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_31 --operation mode is normal T1_reply_31 = V1_request_31 & (T1_a_0_dup_53 # T1_read_data_0 & !T1_ix34_ix30_nx12) # !V1_request_31 & T1_read_data_0 & (!T1_ix34_ix30_nx12); --V1_request_32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_32 --operation mode is normal V1_request_32 = V1_select_rq & (Z2_data_out_32) # !V1_select_rq & Z1_data_out_32; --AB2_ob_data_29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_29 --operation mode is normal AB2_ob_data_29_lut_out = AB2_ob_data_28; AB2_ob_data_29 = DFFEAS(AB2_ob_data_29_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_29, , , AB2_a_2); --LB2_d_to_dll_30 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_30 --operation mode is normal LB2_d_to_dll_30 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_30 # !DB4_data_out_0 & (T1_reply_30)); --AB1_ob_data_28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_28 --operation mode is normal AB1_ob_data_28_lut_out = AB1_ob_data_27; AB1_ob_data_28 = DFFEAS(AB1_ob_data_28_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_28, , , AB1_a_2); --LB1_d_to_dll_29 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_29 --operation mode is normal LB1_d_to_dll_29 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_29 # !DB3_data_out_0 & (T1_reply_29)); --T1_reply_30 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_30 --operation mode is normal T1_reply_30 = V1_request_30 & (T1_a_0_dup_53 # T1_read_data_1 & !T1_ix34_ix30_nx12) # !V1_request_30 & T1_read_data_1 & (!T1_ix34_ix30_nx12); --T1_read_data_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_0 --operation mode is normal T1_read_data_0_lut_out = H1_bus_dout_0; T1_read_data_0 = DFFEAS(T1_read_data_0_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --T1_a_0_dup_53 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|a_0_dup_53 --operation mode is normal T1_a_0_dup_53 = !X1_data_out_3 & X1_data_out_1 & !X1_data_out_0; --T1_ix34_ix30_nx12 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|ix34_ix30_nx12 --operation mode is normal T1_ix34_ix30_nx12 = X1_data_out_3 # X1_data_out_1 # X1_data_out_0 # !X1_data_out_2; --AB2_ob_data_28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_28 --operation mode is normal AB2_ob_data_28_lut_out = AB2_ob_data_27; AB2_ob_data_28 = DFFEAS(AB2_ob_data_28_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_28, , , AB2_a_2); --LB2_d_to_dll_29 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_29 --operation mode is normal LB2_d_to_dll_29 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_29 # !DB4_data_out_0 & (T1_reply_29)); --AB1_ob_data_27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_27 --operation mode is normal AB1_ob_data_27_lut_out = AB1_ob_data_26; AB1_ob_data_27 = DFFEAS(AB1_ob_data_27_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_27, , , AB1_a_2); --LB1_d_to_dll_28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_28 --operation mode is normal LB1_d_to_dll_28 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_28 # !DB3_data_out_0 & (T1_reply_28)); --T1_reply_29 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_29 --operation mode is normal T1_reply_29 = V1_request_29 & (T1_a_0_dup_53 # T1_read_data_2 & !T1_ix34_ix30_nx12) # !V1_request_29 & T1_read_data_2 & (!T1_ix34_ix30_nx12); --T1_read_data_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_1 --operation mode is normal T1_read_data_1_lut_out = H1_bus_dout_1; T1_read_data_1 = DFFEAS(T1_read_data_1_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --T1_nx397 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx397 --operation mode is normal T1_nx397 = !X1_data_out_3 & X1_data_out_1 & X1_data_out_0; --AB2_ob_data_27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_27 --operation mode is normal AB2_ob_data_27_lut_out = AB2_ob_data_26; AB2_ob_data_27 = DFFEAS(AB2_ob_data_27_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_27, , , AB2_a_2); --LB2_d_to_dll_28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_28 --operation mode is normal LB2_d_to_dll_28 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_28 # !DB4_data_out_0 & (T1_reply_28)); --AB1_ob_data_26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_26 --operation mode is normal AB1_ob_data_26_lut_out = AB1_ob_data_25; AB1_ob_data_26 = DFFEAS(AB1_ob_data_26_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_26, , , AB1_a_2); --LB1_d_to_dll_27 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_27 --operation mode is normal LB1_d_to_dll_27 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_27 # !DB3_data_out_0 & (T1_reply_27)); --T1_reply_28 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_28 --operation mode is normal T1_reply_28 = V1_request_28 & (T1_a_0_dup_53 # T1_read_data_3 & !T1_ix34_ix30_nx12) # !V1_request_28 & T1_read_data_3 & (!T1_ix34_ix30_nx12); --T1_read_data_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_2 --operation mode is normal T1_read_data_2_lut_out = H1_bus_dout_2; T1_read_data_2 = DFFEAS(T1_read_data_2_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_1 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_1 --operation mode is normal H1_bus_dout_1 = H1_nx209 # H1_nx210 # E1_rdata_1 & H1_sel_0; --AB2_ob_data_26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_26 --operation mode is normal AB2_ob_data_26_lut_out = AB2_ob_data_25; AB2_ob_data_26 = DFFEAS(AB2_ob_data_26_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_26, , , AB2_a_2); --LB2_d_to_dll_27 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_27 --operation mode is normal LB2_d_to_dll_27 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_27 # !DB4_data_out_0 & (T1_reply_27)); --AB1_ob_data_25 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_25 --operation mode is normal AB1_ob_data_25_lut_out = AB1_ob_data_24; AB1_ob_data_25 = DFFEAS(AB1_ob_data_25_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_25, , , AB1_a_2); --LB1_d_to_dll_26 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_26 --operation mode is normal LB1_d_to_dll_26 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_26 # !DB3_data_out_0 & (T1_reply_26)); --T1_reply_27 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_27 --operation mode is normal T1_reply_27 = V1_request_27 & (T1_a_0_dup_53 # T1_read_data_4 & !T1_ix34_ix30_nx12) # !V1_request_27 & T1_read_data_4 & (!T1_ix34_ix30_nx12); --T1_read_data_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_3 --operation mode is normal T1_read_data_3_lut_out = H1_bus_dout_3; T1_read_data_3 = DFFEAS(T1_read_data_3_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_2 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_2 --operation mode is normal H1_bus_dout_2 = H1_nx207 # H1_nx208 # E1_rdata_2 & H1_sel_0; --E1_rdata_1 is ni2io_wt:wt_ni|rdata_1 --operation mode is normal E1_rdata_1 = V1_request_37 & UB1_q_b[1] # !V1_request_37 & (E1_nx367 & E1_nx368); --H1_nx209 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx209 --operation mode is normal H1_nx209 = L1_RDATA_1 & (H1_ce_sc_adc # F1_RDATA_1 & H1_ce_dds) # !L1_RDATA_1 & F1_RDATA_1 & H1_ce_dds; --H1_nx210 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx210 --operation mode is normal H1_nx210 = K1_RDATA_1 & (H1_ce_psply_adc # J1_RDATA_1 & H1_ce_pasa_adc) # !K1_RDATA_1 & J1_RDATA_1 & (H1_ce_pasa_adc); --AB2_ob_data_25 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_25 --operation mode is normal AB2_ob_data_25_lut_out = AB2_ob_data_24; AB2_ob_data_25 = DFFEAS(AB2_ob_data_25_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_25, , , AB2_a_2); --LB2_d_to_dll_26 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_26 --operation mode is normal LB2_d_to_dll_26 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_26 # !DB4_data_out_0 & (T1_reply_26)); --AB1_ob_data_24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_24 --operation mode is normal AB1_ob_data_24_lut_out = AB1_ob_data_23; AB1_ob_data_24 = DFFEAS(AB1_ob_data_24_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_24, , , AB1_a_2); --LB1_d_to_dll_25 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_25 --operation mode is normal LB1_d_to_dll_25 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_25 # !DB3_data_out_0 & (T1_reply_25)); --T1_reply_26 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_26 --operation mode is normal T1_reply_26 = V1_request_26 & (T1_a_0_dup_53 # T1_read_data_5 & !T1_ix34_ix30_nx12) # !V1_request_26 & T1_read_data_5 & (!T1_ix34_ix30_nx12); --T1_read_data_4 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_4 --operation mode is normal T1_read_data_4_lut_out = H1_bus_dout_4; T1_read_data_4 = DFFEAS(T1_read_data_4_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_3 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_3 --operation mode is normal H1_bus_dout_3 = H1_nx205 # H1_nx206 # E1_rdata_3 & H1_sel_0; --E1_rdata_2 is ni2io_wt:wt_ni|rdata_2 --operation mode is normal E1_rdata_2 = V1_request_37 & UB1_q_b[2] # !V1_request_37 & (E1_nx365 & E1_nx366); --H1_nx207 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx207 --operation mode is normal H1_nx207 = L1_RDATA_2 & (H1_ce_sc_adc # F1_RDATA_2 & H1_ce_dds) # !L1_RDATA_2 & F1_RDATA_2 & H1_ce_dds; --H1_nx208 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx208 --operation mode is normal H1_nx208 = K1_RDATA_2 & (H1_ce_psply_adc # J1_RDATA_2 & H1_ce_pasa_adc) # !K1_RDATA_2 & J1_RDATA_2 & (H1_ce_pasa_adc); --UB1_q_b[1] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[1] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB1_q_b[1]_PORT_A_data_in = RB1_dout_1; UB1_q_b[1]_PORT_A_data_in_reg = DFFE(UB1_q_b[1]_PORT_A_data_in, UB1_q_b[1]_clock_0, UB1_q_b[1]_clear_0, , UB1_q_b[1]_clock_enable_0); UB1_q_b[1]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[1]_PORT_A_address_reg = DFFE(UB1_q_b[1]_PORT_A_address, UB1_q_b[1]_clock_0, UB1_q_b[1]_clear_0, , UB1_q_b[1]_clock_enable_0); UB1_q_b[1]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[1]_PORT_B_address_reg = DFFE(UB1_q_b[1]_PORT_B_address, UB1_q_b[1]_clock_1, , , ); UB1_q_b[1]_PORT_A_write_enable = VCC; UB1_q_b[1]_PORT_A_write_enable_reg = DFFE(UB1_q_b[1]_PORT_A_write_enable, UB1_q_b[1]_clock_0, UB1_q_b[1]_clear_0, , UB1_q_b[1]_clock_enable_0); UB1_q_b[1]_PORT_B_read_enable = VCC; UB1_q_b[1]_PORT_B_read_enable_reg = DFFE(UB1_q_b[1]_PORT_B_read_enable, UB1_q_b[1]_clock_1, , , ); UB1_q_b[1]_clock_0 = !WT_STR; UB1_q_b[1]_clock_1 = S1__clk1; UB1_q_b[1]_clock_enable_0 = PB1_we_p; UB1_q_b[1]_clear_0 = !E1_NOT_clear; UB1_q_b[1]_PORT_B_data_out = MEMORY(UB1_q_b[1]_PORT_A_data_in_reg, , UB1_q_b[1]_PORT_A_address_reg, UB1_q_b[1]_PORT_B_address_reg, UB1_q_b[1]_PORT_A_write_enable_reg, UB1_q_b[1]_PORT_B_read_enable_reg, , , UB1_q_b[1]_clock_0, UB1_q_b[1]_clock_1, UB1_q_b[1]_clock_enable_0, , UB1_q_b[1]_clear_0, ); UB1_q_b[1]_PORT_B_data_out_reg = DFFE(UB1_q_b[1]_PORT_B_data_out, UB1_q_b[1]_clock_1, , , ); UB1_q_b[1] = UB1_q_b[1]_PORT_B_data_out_reg[0]; --UB1_q_b[9] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[9] UB1_q_b[1]_PORT_A_data_in = RB1_dout_1; UB1_q_b[1]_PORT_A_data_in_reg = DFFE(UB1_q_b[1]_PORT_A_data_in, UB1_q_b[1]_clock_0, UB1_q_b[1]_clear_0, , UB1_q_b[1]_clock_enable_0); UB1_q_b[1]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[1]_PORT_A_address_reg = DFFE(UB1_q_b[1]_PORT_A_address, UB1_q_b[1]_clock_0, UB1_q_b[1]_clear_0, , UB1_q_b[1]_clock_enable_0); UB1_q_b[1]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[1]_PORT_B_address_reg = DFFE(UB1_q_b[1]_PORT_B_address, UB1_q_b[1]_clock_1, , , ); UB1_q_b[1]_PORT_A_write_enable = VCC; UB1_q_b[1]_PORT_A_write_enable_reg = DFFE(UB1_q_b[1]_PORT_A_write_enable, UB1_q_b[1]_clock_0, UB1_q_b[1]_clear_0, , UB1_q_b[1]_clock_enable_0); UB1_q_b[1]_PORT_B_read_enable = VCC; UB1_q_b[1]_PORT_B_read_enable_reg = DFFE(UB1_q_b[1]_PORT_B_read_enable, UB1_q_b[1]_clock_1, , , ); UB1_q_b[1]_clock_0 = !WT_STR; UB1_q_b[1]_clock_1 = S1__clk1; UB1_q_b[1]_clock_enable_0 = PB1_we_p; UB1_q_b[1]_clear_0 = !E1_NOT_clear; UB1_q_b[1]_PORT_B_data_out = MEMORY(UB1_q_b[1]_PORT_A_data_in_reg, , UB1_q_b[1]_PORT_A_address_reg, UB1_q_b[1]_PORT_B_address_reg, UB1_q_b[1]_PORT_A_write_enable_reg, UB1_q_b[1]_PORT_B_read_enable_reg, , , UB1_q_b[1]_clock_0, UB1_q_b[1]_clock_1, UB1_q_b[1]_clock_enable_0, , UB1_q_b[1]_clear_0, ); UB1_q_b[1]_PORT_B_data_out_reg = DFFE(UB1_q_b[1]_PORT_B_data_out, UB1_q_b[1]_clock_1, , , ); UB1_q_b[9] = UB1_q_b[1]_PORT_B_data_out_reg[1]; --E1_nx367 is ni2io_wt:wt_ni|nx367 --operation mode is normal E1_nx367 = V1_request_47 # V1_request_48 & (E1_or_mask_1) # !V1_request_48 & E1_sel_s_1; --E1_nx368 is ni2io_wt:wt_ni|nx368 --operation mode is normal E1_nx368 = V1_request_48 & (SB1_Q_1) # !V1_request_48 & SB2_Q_1 # !V1_request_47; --L1_RDATA_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_1 --operation mode is normal L1_RDATA_1 = L1_nx897 # L1_nx898 # L1_nx899 # L1_nx900; --F1_RDATA_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_1 --operation mode is normal F1_RDATA_1 = F1_nx833 # F1_nx834 # V1_request_46 & F1_config_1; --K1_RDATA_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_1 --operation mode is normal K1_RDATA_1 = K1_nx980 # K1_nx981 # K1_nx982 # K1_nx983; --J1_RDATA_1 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_1 --operation mode is normal J1_RDATA_1 = V1_request_38 & (J1_PAADC_MuxA_1) # !V1_request_38 & Q1_q_b[1]; --AB2_ob_data_24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_24 --operation mode is normal AB2_ob_data_24_lut_out = AB2_ob_data_23; AB2_ob_data_24 = DFFEAS(AB2_ob_data_24_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_24, , , AB2_a_2); --LB2_d_to_dll_25 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_25 --operation mode is normal LB2_d_to_dll_25 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_25 # !DB4_data_out_0 & (T1_reply_25)); --AB1_ob_data_23 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_23 --operation mode is normal AB1_ob_data_23_lut_out = AB1_ob_data_22; AB1_ob_data_23 = DFFEAS(AB1_ob_data_23_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_23, , , AB1_a_2); --LB1_d_to_dll_24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_24 --operation mode is normal LB1_d_to_dll_24 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_24 # !DB3_data_out_0 & (T1_reply_24)); --T1_reply_25 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_25 --operation mode is normal T1_reply_25 = V1_request_25 & (T1_a_0_dup_53 # T1_read_data_6 & !T1_ix34_ix30_nx12) # !V1_request_25 & T1_read_data_6 & (!T1_ix34_ix30_nx12); --T1_read_data_5 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_5 --operation mode is normal T1_read_data_5_lut_out = H1_bus_dout_5; T1_read_data_5 = DFFEAS(T1_read_data_5_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_4 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_4 --operation mode is normal H1_bus_dout_4 = H1_nx203 # H1_nx204 # E1_rdata_4 & H1_sel_0; --E1_rdata_3 is ni2io_wt:wt_ni|rdata_3 --operation mode is normal E1_rdata_3 = V1_request_37 & UB1_q_b[3] # !V1_request_37 & (E1_nx363 & E1_nx364); --H1_nx205 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx205 --operation mode is normal H1_nx205 = L1_RDATA_3 & (H1_ce_sc_adc # F1_RDATA_3 & H1_ce_dds) # !L1_RDATA_3 & F1_RDATA_3 & H1_ce_dds; --H1_nx206 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx206 --operation mode is normal H1_nx206 = K1_RDATA_3 & (H1_ce_psply_adc # J1_RDATA_3 & H1_ce_pasa_adc) # !K1_RDATA_3 & J1_RDATA_3 & (H1_ce_pasa_adc); --UB1_q_b[2] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[2] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB1_q_b[2]_PORT_A_data_in = RB1_dout_2; UB1_q_b[2]_PORT_A_data_in_reg = DFFE(UB1_q_b[2]_PORT_A_data_in, UB1_q_b[2]_clock_0, UB1_q_b[2]_clear_0, , UB1_q_b[2]_clock_enable_0); UB1_q_b[2]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[2]_PORT_A_address_reg = DFFE(UB1_q_b[2]_PORT_A_address, UB1_q_b[2]_clock_0, UB1_q_b[2]_clear_0, , UB1_q_b[2]_clock_enable_0); UB1_q_b[2]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[2]_PORT_B_address_reg = DFFE(UB1_q_b[2]_PORT_B_address, UB1_q_b[2]_clock_1, , , ); UB1_q_b[2]_PORT_A_write_enable = VCC; UB1_q_b[2]_PORT_A_write_enable_reg = DFFE(UB1_q_b[2]_PORT_A_write_enable, UB1_q_b[2]_clock_0, UB1_q_b[2]_clear_0, , UB1_q_b[2]_clock_enable_0); UB1_q_b[2]_PORT_B_read_enable = VCC; UB1_q_b[2]_PORT_B_read_enable_reg = DFFE(UB1_q_b[2]_PORT_B_read_enable, UB1_q_b[2]_clock_1, , , ); UB1_q_b[2]_clock_0 = !WT_STR; UB1_q_b[2]_clock_1 = S1__clk1; UB1_q_b[2]_clock_enable_0 = PB1_we_p; UB1_q_b[2]_clear_0 = !E1_NOT_clear; UB1_q_b[2]_PORT_B_data_out = MEMORY(UB1_q_b[2]_PORT_A_data_in_reg, , UB1_q_b[2]_PORT_A_address_reg, UB1_q_b[2]_PORT_B_address_reg, UB1_q_b[2]_PORT_A_write_enable_reg, UB1_q_b[2]_PORT_B_read_enable_reg, , , UB1_q_b[2]_clock_0, UB1_q_b[2]_clock_1, UB1_q_b[2]_clock_enable_0, , UB1_q_b[2]_clear_0, ); UB1_q_b[2]_PORT_B_data_out_reg = DFFE(UB1_q_b[2]_PORT_B_data_out, UB1_q_b[2]_clock_1, , , ); UB1_q_b[2] = UB1_q_b[2]_PORT_B_data_out_reg[0]; --UB1_q_b[10] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[10] UB1_q_b[2]_PORT_A_data_in = RB1_dout_2; UB1_q_b[2]_PORT_A_data_in_reg = DFFE(UB1_q_b[2]_PORT_A_data_in, UB1_q_b[2]_clock_0, UB1_q_b[2]_clear_0, , UB1_q_b[2]_clock_enable_0); UB1_q_b[2]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[2]_PORT_A_address_reg = DFFE(UB1_q_b[2]_PORT_A_address, UB1_q_b[2]_clock_0, UB1_q_b[2]_clear_0, , UB1_q_b[2]_clock_enable_0); UB1_q_b[2]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[2]_PORT_B_address_reg = DFFE(UB1_q_b[2]_PORT_B_address, UB1_q_b[2]_clock_1, , , ); UB1_q_b[2]_PORT_A_write_enable = VCC; UB1_q_b[2]_PORT_A_write_enable_reg = DFFE(UB1_q_b[2]_PORT_A_write_enable, UB1_q_b[2]_clock_0, UB1_q_b[2]_clear_0, , UB1_q_b[2]_clock_enable_0); UB1_q_b[2]_PORT_B_read_enable = VCC; UB1_q_b[2]_PORT_B_read_enable_reg = DFFE(UB1_q_b[2]_PORT_B_read_enable, UB1_q_b[2]_clock_1, , , ); UB1_q_b[2]_clock_0 = !WT_STR; UB1_q_b[2]_clock_1 = S1__clk1; UB1_q_b[2]_clock_enable_0 = PB1_we_p; UB1_q_b[2]_clear_0 = !E1_NOT_clear; UB1_q_b[2]_PORT_B_data_out = MEMORY(UB1_q_b[2]_PORT_A_data_in_reg, , UB1_q_b[2]_PORT_A_address_reg, UB1_q_b[2]_PORT_B_address_reg, UB1_q_b[2]_PORT_A_write_enable_reg, UB1_q_b[2]_PORT_B_read_enable_reg, , , UB1_q_b[2]_clock_0, UB1_q_b[2]_clock_1, UB1_q_b[2]_clock_enable_0, , UB1_q_b[2]_clear_0, ); UB1_q_b[2]_PORT_B_data_out_reg = DFFE(UB1_q_b[2]_PORT_B_data_out, UB1_q_b[2]_clock_1, , , ); UB1_q_b[10] = UB1_q_b[2]_PORT_B_data_out_reg[1]; --E1_nx365 is ni2io_wt:wt_ni|nx365 --operation mode is normal E1_nx365 = V1_request_47 # V1_request_48 & (E1_or_mask_2) # !V1_request_48 & E1_sel_s_2; --E1_nx366 is ni2io_wt:wt_ni|nx366 --operation mode is normal E1_nx366 = V1_request_48 & (SB1_Q_2) # !V1_request_48 & SB2_Q_2 # !V1_request_47; --L1_RDATA_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_2 --operation mode is normal L1_RDATA_2 = L1_nx893 # L1_nx894 # L1_nx895 # L1_nx896; --F1_RDATA_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_2 --operation mode is normal F1_RDATA_2 = F1_nx831 # F1_nx832 # V1_request_46 & F1_config_2; --K1_RDATA_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_2 --operation mode is normal K1_RDATA_2 = K1_nx976 # K1_nx977 # K1_nx978 # K1_nx979; --J1_RDATA_2 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_2 --operation mode is normal J1_RDATA_2 = V1_request_38 & (J1_PAADC_Msel) # !V1_request_38 & Q1_q_b[2]; --SB1_Q_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_1 --operation mode is arithmetic SB1_Q_1_carry_eqn = SB1_Q_nx10; SB1_Q_1_lut_out = SB1_Q_1 $ (SB1_Q_1_carry_eqn); SB1_Q_1 = DFFEAS(SB1_Q_1_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx16 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx16 --operation mode is arithmetic SB1_Q_nx16 = CARRY(!SB1_Q_nx10 # !SB1_Q_1); --L1_nx897 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx897 --operation mode is normal L1_nx897 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_1) # !V1_request_48 & L1_adc_last_0_1); --L1_nx898 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx898 --operation mode is normal L1_nx898 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_1) # !V1_request_48 & L1_adc_last_4_1); --L1_nx899 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx899 --operation mode is normal L1_nx899 = V1_request_46 & !V1_request_47 & L1_cfr_1; --L1_nx900 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx900 --operation mode is normal L1_nx900 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_1 # !V1_request_48 & (!L1_NOT_climits_a_1)); --F1_nx833 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx833 --operation mode is normal F1_nx833 = F1_bytes2send_33 & (F1_a_3 # F1_bytes_rcvd_33 & F1_nx787) # !F1_bytes2send_33 & F1_bytes_rcvd_33 & (F1_nx787); --F1_nx834 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx834 --operation mode is normal F1_nx834 = F1_bytes2send_1 & (F1_a_1 # F1_bytes_rcvd_1 & F1_nx785) # !F1_bytes2send_1 & F1_bytes_rcvd_1 & (F1_nx785); --K1_nx980 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx980 --operation mode is normal K1_nx980 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_1) # !V1_request_48 & K1_adc_last_0_1); --K1_nx981 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx981 --operation mode is normal K1_nx981 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_1) # !V1_request_48 & K1_adc_last_4_1); --K1_nx982 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx982 --operation mode is normal K1_nx982 = V1_request_46 & !V1_request_47 & K1_cfr_1; --K1_nx983 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx983 --operation mode is normal K1_nx983 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_1 # !V1_request_48 & (!K1_NOT_climits_a_1)); --Q1_q_b[1] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[1] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[1]_PORT_A_data_in = J1_wdata_ram_1; Q1_q_b[1]_PORT_A_data_in_reg = DFFE(Q1_q_b[1]_PORT_A_data_in, Q1_q_b[1]_clock_0, , , Q1_q_b[1]_clock_enable_0); Q1_q_b[1]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[1]_PORT_A_address_reg = DFFE(Q1_q_b[1]_PORT_A_address, Q1_q_b[1]_clock_0, , , Q1_q_b[1]_clock_enable_0); Q1_q_b[1]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[1]_PORT_B_address_reg = DFFE(Q1_q_b[1]_PORT_B_address, Q1_q_b[1]_clock_1, , , ); Q1_q_b[1]_PORT_A_write_enable = VCC; Q1_q_b[1]_PORT_A_write_enable_reg = DFFE(Q1_q_b[1]_PORT_A_write_enable, Q1_q_b[1]_clock_0, , , Q1_q_b[1]_clock_enable_0); Q1_q_b[1]_PORT_B_read_enable = VCC; Q1_q_b[1]_PORT_B_read_enable_reg = DFFE(Q1_q_b[1]_PORT_B_read_enable, Q1_q_b[1]_clock_1, , , ); Q1_q_b[1]_clock_0 = S1__clk1; Q1_q_b[1]_clock_1 = S1__clk1; Q1_q_b[1]_clock_enable_0 = J1_sm; Q1_q_b[1]_PORT_B_data_out = MEMORY(Q1_q_b[1]_PORT_A_data_in_reg, , Q1_q_b[1]_PORT_A_address_reg, Q1_q_b[1]_PORT_B_address_reg, Q1_q_b[1]_PORT_A_write_enable_reg, Q1_q_b[1]_PORT_B_read_enable_reg, , , Q1_q_b[1]_clock_0, Q1_q_b[1]_clock_1, Q1_q_b[1]_clock_enable_0, , , ); Q1_q_b[1]_PORT_B_data_out_reg = DFFE(Q1_q_b[1]_PORT_B_data_out, Q1_q_b[1]_clock_1, , , ); Q1_q_b[1] = Q1_q_b[1]_PORT_B_data_out_reg[0]; --Q1_q_b[17] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[17] Q1_q_b[1]_PORT_A_data_in = J1_wdata_ram_1; Q1_q_b[1]_PORT_A_data_in_reg = DFFE(Q1_q_b[1]_PORT_A_data_in, Q1_q_b[1]_clock_0, , , Q1_q_b[1]_clock_enable_0); Q1_q_b[1]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[1]_PORT_A_address_reg = DFFE(Q1_q_b[1]_PORT_A_address, Q1_q_b[1]_clock_0, , , Q1_q_b[1]_clock_enable_0); Q1_q_b[1]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[1]_PORT_B_address_reg = DFFE(Q1_q_b[1]_PORT_B_address, Q1_q_b[1]_clock_1, , , ); Q1_q_b[1]_PORT_A_write_enable = VCC; Q1_q_b[1]_PORT_A_write_enable_reg = DFFE(Q1_q_b[1]_PORT_A_write_enable, Q1_q_b[1]_clock_0, , , Q1_q_b[1]_clock_enable_0); Q1_q_b[1]_PORT_B_read_enable = VCC; Q1_q_b[1]_PORT_B_read_enable_reg = DFFE(Q1_q_b[1]_PORT_B_read_enable, Q1_q_b[1]_clock_1, , , ); Q1_q_b[1]_clock_0 = S1__clk1; Q1_q_b[1]_clock_1 = S1__clk1; Q1_q_b[1]_clock_enable_0 = J1_sm; Q1_q_b[1]_PORT_B_data_out = MEMORY(Q1_q_b[1]_PORT_A_data_in_reg, , Q1_q_b[1]_PORT_A_address_reg, Q1_q_b[1]_PORT_B_address_reg, Q1_q_b[1]_PORT_A_write_enable_reg, Q1_q_b[1]_PORT_B_read_enable_reg, , , Q1_q_b[1]_clock_0, Q1_q_b[1]_clock_1, Q1_q_b[1]_clock_enable_0, , , ); Q1_q_b[1]_PORT_B_data_out_reg = DFFE(Q1_q_b[1]_PORT_B_data_out, Q1_q_b[1]_clock_1, , , ); Q1_q_b[17] = Q1_q_b[1]_PORT_B_data_out_reg[1]; --AB2_ob_data_23 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_23 --operation mode is normal AB2_ob_data_23_lut_out = AB2_ob_data_22; AB2_ob_data_23 = DFFEAS(AB2_ob_data_23_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_23, , , AB2_a_2); --LB2_d_to_dll_24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_24 --operation mode is normal LB2_d_to_dll_24 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_24 # !DB4_data_out_0 & (T1_reply_24)); --AB1_ob_data_22 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_22 --operation mode is normal AB1_ob_data_22_lut_out = AB1_ob_data_21; AB1_ob_data_22 = DFFEAS(AB1_ob_data_22_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_22, , , AB1_a_2); --LB1_d_to_dll_23 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_23 --operation mode is normal LB1_d_to_dll_23 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_23 # !DB3_data_out_0 & (T1_reply_23)); --T1_reply_24 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_24 --operation mode is normal T1_reply_24 = V1_request_24 & (T1_a_0_dup_53 # T1_read_data_7 & !T1_ix34_ix30_nx12) # !V1_request_24 & T1_read_data_7 & (!T1_ix34_ix30_nx12); --T1_read_data_6 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_6 --operation mode is normal T1_read_data_6_lut_out = H1_bus_dout_6; T1_read_data_6 = DFFEAS(T1_read_data_6_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_5 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_5 --operation mode is normal H1_bus_dout_5 = H1_nx201 # H1_nx202 # E1_rdata_5 & H1_sel_0; --E1_rdata_4 is ni2io_wt:wt_ni|rdata_4 --operation mode is normal E1_rdata_4 = V1_request_37 & UB1_q_b[4] # !V1_request_37 & (E1_nx361 & E1_nx362); --H1_nx203 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx203 --operation mode is normal H1_nx203 = L1_RDATA_4 & (H1_ce_sc_adc # F1_RDATA_4 & H1_ce_dds) # !L1_RDATA_4 & F1_RDATA_4 & H1_ce_dds; --H1_nx204 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx204 --operation mode is normal H1_nx204 = K1_RDATA_4 & (H1_ce_psply_adc # J1_RDATA_4 & H1_ce_pasa_adc) # !K1_RDATA_4 & J1_RDATA_4 & (H1_ce_pasa_adc); --UB1_q_b[3] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[3] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB1_q_b[3]_PORT_A_data_in = RB1_dout_3; UB1_q_b[3]_PORT_A_data_in_reg = DFFE(UB1_q_b[3]_PORT_A_data_in, UB1_q_b[3]_clock_0, UB1_q_b[3]_clear_0, , UB1_q_b[3]_clock_enable_0); UB1_q_b[3]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[3]_PORT_A_address_reg = DFFE(UB1_q_b[3]_PORT_A_address, UB1_q_b[3]_clock_0, UB1_q_b[3]_clear_0, , UB1_q_b[3]_clock_enable_0); UB1_q_b[3]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[3]_PORT_B_address_reg = DFFE(UB1_q_b[3]_PORT_B_address, UB1_q_b[3]_clock_1, , , ); UB1_q_b[3]_PORT_A_write_enable = VCC; UB1_q_b[3]_PORT_A_write_enable_reg = DFFE(UB1_q_b[3]_PORT_A_write_enable, UB1_q_b[3]_clock_0, UB1_q_b[3]_clear_0, , UB1_q_b[3]_clock_enable_0); UB1_q_b[3]_PORT_B_read_enable = VCC; UB1_q_b[3]_PORT_B_read_enable_reg = DFFE(UB1_q_b[3]_PORT_B_read_enable, UB1_q_b[3]_clock_1, , , ); UB1_q_b[3]_clock_0 = !WT_STR; UB1_q_b[3]_clock_1 = S1__clk1; UB1_q_b[3]_clock_enable_0 = PB1_we_p; UB1_q_b[3]_clear_0 = !E1_NOT_clear; UB1_q_b[3]_PORT_B_data_out = MEMORY(UB1_q_b[3]_PORT_A_data_in_reg, , UB1_q_b[3]_PORT_A_address_reg, UB1_q_b[3]_PORT_B_address_reg, UB1_q_b[3]_PORT_A_write_enable_reg, UB1_q_b[3]_PORT_B_read_enable_reg, , , UB1_q_b[3]_clock_0, UB1_q_b[3]_clock_1, UB1_q_b[3]_clock_enable_0, , UB1_q_b[3]_clear_0, ); UB1_q_b[3]_PORT_B_data_out_reg = DFFE(UB1_q_b[3]_PORT_B_data_out, UB1_q_b[3]_clock_1, , , ); UB1_q_b[3] = UB1_q_b[3]_PORT_B_data_out_reg[0]; --UB1_q_b[11] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[11] UB1_q_b[3]_PORT_A_data_in = RB1_dout_3; UB1_q_b[3]_PORT_A_data_in_reg = DFFE(UB1_q_b[3]_PORT_A_data_in, UB1_q_b[3]_clock_0, UB1_q_b[3]_clear_0, , UB1_q_b[3]_clock_enable_0); UB1_q_b[3]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[3]_PORT_A_address_reg = DFFE(UB1_q_b[3]_PORT_A_address, UB1_q_b[3]_clock_0, UB1_q_b[3]_clear_0, , UB1_q_b[3]_clock_enable_0); UB1_q_b[3]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[3]_PORT_B_address_reg = DFFE(UB1_q_b[3]_PORT_B_address, UB1_q_b[3]_clock_1, , , ); UB1_q_b[3]_PORT_A_write_enable = VCC; UB1_q_b[3]_PORT_A_write_enable_reg = DFFE(UB1_q_b[3]_PORT_A_write_enable, UB1_q_b[3]_clock_0, UB1_q_b[3]_clear_0, , UB1_q_b[3]_clock_enable_0); UB1_q_b[3]_PORT_B_read_enable = VCC; UB1_q_b[3]_PORT_B_read_enable_reg = DFFE(UB1_q_b[3]_PORT_B_read_enable, UB1_q_b[3]_clock_1, , , ); UB1_q_b[3]_clock_0 = !WT_STR; UB1_q_b[3]_clock_1 = S1__clk1; UB1_q_b[3]_clock_enable_0 = PB1_we_p; UB1_q_b[3]_clear_0 = !E1_NOT_clear; UB1_q_b[3]_PORT_B_data_out = MEMORY(UB1_q_b[3]_PORT_A_data_in_reg, , UB1_q_b[3]_PORT_A_address_reg, UB1_q_b[3]_PORT_B_address_reg, UB1_q_b[3]_PORT_A_write_enable_reg, UB1_q_b[3]_PORT_B_read_enable_reg, , , UB1_q_b[3]_clock_0, UB1_q_b[3]_clock_1, UB1_q_b[3]_clock_enable_0, , UB1_q_b[3]_clear_0, ); UB1_q_b[3]_PORT_B_data_out_reg = DFFE(UB1_q_b[3]_PORT_B_data_out, UB1_q_b[3]_clock_1, , , ); UB1_q_b[11] = UB1_q_b[3]_PORT_B_data_out_reg[1]; --E1_nx363 is ni2io_wt:wt_ni|nx363 --operation mode is normal E1_nx363 = V1_request_47 # V1_request_48 & (E1_or_mask_3) # !V1_request_48 & !E1_NOT_sel_s_3; --E1_nx364 is ni2io_wt:wt_ni|nx364 --operation mode is normal E1_nx364 = V1_request_48 & (SB1_Q_3) # !V1_request_48 & SB2_Q_3 # !V1_request_47; --L1_RDATA_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_3 --operation mode is normal L1_RDATA_3 = L1_nx889 # L1_nx890 # L1_nx891 # L1_nx892; --F1_RDATA_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_3 --operation mode is normal F1_RDATA_3 = F1_nx829 # F1_nx830 # V1_request_46 & F1_config_3; --K1_RDATA_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_3 --operation mode is normal K1_RDATA_3 = K1_nx972 # K1_nx973 # K1_nx974 # K1_nx975; --J1_RDATA_3 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_3 --operation mode is normal J1_RDATA_3 = V1_request_38 & (J1_cfr_3) # !V1_request_38 & Q1_q_b[3]; --SB1_Q_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_2 --operation mode is arithmetic SB1_Q_2_carry_eqn = SB1_Q_nx16; SB1_Q_2_lut_out = SB1_Q_2 $ (!SB1_Q_2_carry_eqn); SB1_Q_2 = DFFEAS(SB1_Q_2_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx22 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx22 --operation mode is arithmetic SB1_Q_nx22 = CARRY(SB1_Q_2 & (!SB1_Q_nx16)); --L1_nx893 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx893 --operation mode is normal L1_nx893 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_2) # !V1_request_48 & L1_adc_last_0_2); --L1_nx894 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx894 --operation mode is normal L1_nx894 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_2) # !V1_request_48 & L1_adc_last_4_2); --L1_nx895 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx895 --operation mode is normal L1_nx895 = V1_request_46 & !V1_request_47 & L1_cfr_2; --L1_nx896 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx896 --operation mode is normal L1_nx896 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_2 # !V1_request_48 & (!L1_NOT_climits_a_2)); --F1_nx831 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx831 --operation mode is normal F1_nx831 = F1_bytes2send_34 & (F1_a_3 # F1_bytes_rcvd_34 & F1_nx787) # !F1_bytes2send_34 & F1_bytes_rcvd_34 & (F1_nx787); --F1_nx832 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx832 --operation mode is normal F1_nx832 = F1_bytes2send_2 & (F1_a_1 # F1_bytes_rcvd_2 & F1_nx785) # !F1_bytes2send_2 & F1_bytes_rcvd_2 & (F1_nx785); --K1_nx976 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx976 --operation mode is normal K1_nx976 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_2) # !V1_request_48 & K1_adc_last_0_2); --K1_nx977 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx977 --operation mode is normal K1_nx977 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_2) # !V1_request_48 & K1_adc_last_4_2); --K1_nx978 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx978 --operation mode is normal K1_nx978 = V1_request_46 & !V1_request_47 & K1_cfr_2; --K1_nx979 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx979 --operation mode is normal K1_nx979 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_2 # !V1_request_48 & (!K1_NOT_climits_a_2)); --Q1_q_b[2] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[2] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[2]_PORT_A_data_in = J1_wdata_ram_2; Q1_q_b[2]_PORT_A_data_in_reg = DFFE(Q1_q_b[2]_PORT_A_data_in, Q1_q_b[2]_clock_0, , , Q1_q_b[2]_clock_enable_0); Q1_q_b[2]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[2]_PORT_A_address_reg = DFFE(Q1_q_b[2]_PORT_A_address, Q1_q_b[2]_clock_0, , , Q1_q_b[2]_clock_enable_0); Q1_q_b[2]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[2]_PORT_B_address_reg = DFFE(Q1_q_b[2]_PORT_B_address, Q1_q_b[2]_clock_1, , , ); Q1_q_b[2]_PORT_A_write_enable = VCC; Q1_q_b[2]_PORT_A_write_enable_reg = DFFE(Q1_q_b[2]_PORT_A_write_enable, Q1_q_b[2]_clock_0, , , Q1_q_b[2]_clock_enable_0); Q1_q_b[2]_PORT_B_read_enable = VCC; Q1_q_b[2]_PORT_B_read_enable_reg = DFFE(Q1_q_b[2]_PORT_B_read_enable, Q1_q_b[2]_clock_1, , , ); Q1_q_b[2]_clock_0 = S1__clk1; Q1_q_b[2]_clock_1 = S1__clk1; Q1_q_b[2]_clock_enable_0 = J1_sm; Q1_q_b[2]_PORT_B_data_out = MEMORY(Q1_q_b[2]_PORT_A_data_in_reg, , Q1_q_b[2]_PORT_A_address_reg, Q1_q_b[2]_PORT_B_address_reg, Q1_q_b[2]_PORT_A_write_enable_reg, Q1_q_b[2]_PORT_B_read_enable_reg, , , Q1_q_b[2]_clock_0, Q1_q_b[2]_clock_1, Q1_q_b[2]_clock_enable_0, , , ); Q1_q_b[2]_PORT_B_data_out_reg = DFFE(Q1_q_b[2]_PORT_B_data_out, Q1_q_b[2]_clock_1, , , ); Q1_q_b[2] = Q1_q_b[2]_PORT_B_data_out_reg[0]; --Q1_q_b[18] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[18] Q1_q_b[2]_PORT_A_data_in = J1_wdata_ram_2; Q1_q_b[2]_PORT_A_data_in_reg = DFFE(Q1_q_b[2]_PORT_A_data_in, Q1_q_b[2]_clock_0, , , Q1_q_b[2]_clock_enable_0); Q1_q_b[2]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[2]_PORT_A_address_reg = DFFE(Q1_q_b[2]_PORT_A_address, Q1_q_b[2]_clock_0, , , Q1_q_b[2]_clock_enable_0); Q1_q_b[2]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[2]_PORT_B_address_reg = DFFE(Q1_q_b[2]_PORT_B_address, Q1_q_b[2]_clock_1, , , ); Q1_q_b[2]_PORT_A_write_enable = VCC; Q1_q_b[2]_PORT_A_write_enable_reg = DFFE(Q1_q_b[2]_PORT_A_write_enable, Q1_q_b[2]_clock_0, , , Q1_q_b[2]_clock_enable_0); Q1_q_b[2]_PORT_B_read_enable = VCC; Q1_q_b[2]_PORT_B_read_enable_reg = DFFE(Q1_q_b[2]_PORT_B_read_enable, Q1_q_b[2]_clock_1, , , ); Q1_q_b[2]_clock_0 = S1__clk1; Q1_q_b[2]_clock_1 = S1__clk1; Q1_q_b[2]_clock_enable_0 = J1_sm; Q1_q_b[2]_PORT_B_data_out = MEMORY(Q1_q_b[2]_PORT_A_data_in_reg, , Q1_q_b[2]_PORT_A_address_reg, Q1_q_b[2]_PORT_B_address_reg, Q1_q_b[2]_PORT_A_write_enable_reg, Q1_q_b[2]_PORT_B_read_enable_reg, , , Q1_q_b[2]_clock_0, Q1_q_b[2]_clock_1, Q1_q_b[2]_clock_enable_0, , , ); Q1_q_b[2]_PORT_B_data_out_reg = DFFE(Q1_q_b[2]_PORT_B_data_out, Q1_q_b[2]_clock_1, , , ); Q1_q_b[18] = Q1_q_b[2]_PORT_B_data_out_reg[1]; --L1_adc_last_0_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_1 --operation mode is normal L1_adc_last_0_1_lut_out = R2_RDATA_1; L1_adc_last_0_1 = DFFEAS(L1_adc_last_0_1_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_1 --operation mode is normal L1_adc_last_2_1_lut_out = R2_RDATA_1; L1_adc_last_2_1 = DFFEAS(L1_adc_last_2_1_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_1 --operation mode is normal L1_adc_last_4_1_lut_out = R2_RDATA_1; L1_adc_last_4_1 = DFFEAS(L1_adc_last_4_1_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_1 --operation mode is normal L1_adc_last_6_1_lut_out = R2_RDATA_1; L1_adc_last_6_1 = DFFEAS(L1_adc_last_6_1_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_1 --operation mode is normal L1_NOT_climits_d_1_lut_out = !V1_request_30; L1_NOT_climits_d_1 = DFFEAS(L1_NOT_climits_d_1_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_1 --operation mode is normal L1_NOT_climits_a_1_lut_out = !V1_request_30; L1_NOT_climits_a_1 = DFFEAS(L1_NOT_climits_a_1_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_33 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_33 --operation mode is normal F1_bytes_rcvd_33_lut_out = F1_nx2243; F1_bytes_rcvd_33 = DFFEAS(F1_bytes_rcvd_33_lut_out, S1__clk1, VCC, , F1_NOT_nx2121, , , , ); --F1_bytes_rcvd_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_1 --operation mode is normal F1_bytes_rcvd_1_lut_out = F1_nx2243; F1_bytes_rcvd_1 = DFFEAS(F1_bytes_rcvd_1_lut_out, S1__clk1, VCC, , F1_NOT_nx2249, , , , ); --K1_adc_last_0_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_1 --operation mode is normal K1_adc_last_0_1_lut_out = R1_RDATA_1; K1_adc_last_0_1 = DFFEAS(K1_adc_last_0_1_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_1 --operation mode is normal K1_adc_last_2_1_lut_out = R1_RDATA_1; K1_adc_last_2_1 = DFFEAS(K1_adc_last_2_1_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_1 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_1 --operation mode is normal J1_wdata_ram_1_lut_out = PAADC_D[1]; J1_wdata_ram_1 = DFFEAS(J1_wdata_ram_1_lut_out, S1__clk1, VCC, , , , , , ); --AB2_ob_data_22 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_22 --operation mode is normal AB2_ob_data_22_lut_out = AB2_ob_data_21; AB2_ob_data_22 = DFFEAS(AB2_ob_data_22_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_22, , , AB2_a_2); --LB2_d_to_dll_23 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_23 --operation mode is normal LB2_d_to_dll_23 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_23 # !DB4_data_out_0 & (T1_reply_23)); --AB1_ob_data_21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_21 --operation mode is normal AB1_ob_data_21_lut_out = AB1_ob_data_20; AB1_ob_data_21 = DFFEAS(AB1_ob_data_21_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_21, , , AB1_a_2); --LB1_d_to_dll_22 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_22 --operation mode is normal LB1_d_to_dll_22 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_22 # !DB3_data_out_0 & (T1_reply_22)); --T1_reply_23 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_23 --operation mode is normal T1_reply_23 = V1_request_23 & (T1_a_0_dup_53 # T1_read_data_8 & !T1_ix34_ix30_nx12) # !V1_request_23 & T1_read_data_8 & (!T1_ix34_ix30_nx12); --T1_read_data_7 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_7 --operation mode is normal T1_read_data_7_lut_out = H1_bus_dout_7; T1_read_data_7 = DFFEAS(T1_read_data_7_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_6 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_6 --operation mode is normal H1_bus_dout_6 = H1_nx199 # H1_nx200 # E1_rdata_6 & H1_sel_0; --E1_rdata_5 is ni2io_wt:wt_ni|rdata_5 --operation mode is normal E1_rdata_5 = V1_request_37 & UB1_q_b[5] # !V1_request_37 & (E1_nx359 & E1_nx360); --H1_nx201 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx201 --operation mode is normal H1_nx201 = L1_RDATA_5 & (H1_ce_sc_adc # F1_RDATA_5 & H1_ce_dds) # !L1_RDATA_5 & F1_RDATA_5 & H1_ce_dds; --H1_nx202 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx202 --operation mode is normal H1_nx202 = K1_RDATA_5 & (H1_ce_psply_adc # J1_RDATA_5 & H1_ce_pasa_adc) # !K1_RDATA_5 & J1_RDATA_5 & (H1_ce_pasa_adc); --UB1_q_b[4] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[4] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB1_q_b[4]_PORT_A_data_in = RB1_dout_4; UB1_q_b[4]_PORT_A_data_in_reg = DFFE(UB1_q_b[4]_PORT_A_data_in, UB1_q_b[4]_clock_0, UB1_q_b[4]_clear_0, , UB1_q_b[4]_clock_enable_0); UB1_q_b[4]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[4]_PORT_A_address_reg = DFFE(UB1_q_b[4]_PORT_A_address, UB1_q_b[4]_clock_0, UB1_q_b[4]_clear_0, , UB1_q_b[4]_clock_enable_0); UB1_q_b[4]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[4]_PORT_B_address_reg = DFFE(UB1_q_b[4]_PORT_B_address, UB1_q_b[4]_clock_1, , , ); UB1_q_b[4]_PORT_A_write_enable = VCC; UB1_q_b[4]_PORT_A_write_enable_reg = DFFE(UB1_q_b[4]_PORT_A_write_enable, UB1_q_b[4]_clock_0, UB1_q_b[4]_clear_0, , UB1_q_b[4]_clock_enable_0); UB1_q_b[4]_PORT_B_read_enable = VCC; UB1_q_b[4]_PORT_B_read_enable_reg = DFFE(UB1_q_b[4]_PORT_B_read_enable, UB1_q_b[4]_clock_1, , , ); UB1_q_b[4]_clock_0 = !WT_STR; UB1_q_b[4]_clock_1 = S1__clk1; UB1_q_b[4]_clock_enable_0 = PB1_we_p; UB1_q_b[4]_clear_0 = !E1_NOT_clear; UB1_q_b[4]_PORT_B_data_out = MEMORY(UB1_q_b[4]_PORT_A_data_in_reg, , UB1_q_b[4]_PORT_A_address_reg, UB1_q_b[4]_PORT_B_address_reg, UB1_q_b[4]_PORT_A_write_enable_reg, UB1_q_b[4]_PORT_B_read_enable_reg, , , UB1_q_b[4]_clock_0, UB1_q_b[4]_clock_1, UB1_q_b[4]_clock_enable_0, , UB1_q_b[4]_clear_0, ); UB1_q_b[4]_PORT_B_data_out_reg = DFFE(UB1_q_b[4]_PORT_B_data_out, UB1_q_b[4]_clock_1, , , ); UB1_q_b[4] = UB1_q_b[4]_PORT_B_data_out_reg[0]; --UB1_q_b[12] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[12] UB1_q_b[4]_PORT_A_data_in = RB1_dout_4; UB1_q_b[4]_PORT_A_data_in_reg = DFFE(UB1_q_b[4]_PORT_A_data_in, UB1_q_b[4]_clock_0, UB1_q_b[4]_clear_0, , UB1_q_b[4]_clock_enable_0); UB1_q_b[4]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[4]_PORT_A_address_reg = DFFE(UB1_q_b[4]_PORT_A_address, UB1_q_b[4]_clock_0, UB1_q_b[4]_clear_0, , UB1_q_b[4]_clock_enable_0); UB1_q_b[4]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[4]_PORT_B_address_reg = DFFE(UB1_q_b[4]_PORT_B_address, UB1_q_b[4]_clock_1, , , ); UB1_q_b[4]_PORT_A_write_enable = VCC; UB1_q_b[4]_PORT_A_write_enable_reg = DFFE(UB1_q_b[4]_PORT_A_write_enable, UB1_q_b[4]_clock_0, UB1_q_b[4]_clear_0, , UB1_q_b[4]_clock_enable_0); UB1_q_b[4]_PORT_B_read_enable = VCC; UB1_q_b[4]_PORT_B_read_enable_reg = DFFE(UB1_q_b[4]_PORT_B_read_enable, UB1_q_b[4]_clock_1, , , ); UB1_q_b[4]_clock_0 = !WT_STR; UB1_q_b[4]_clock_1 = S1__clk1; UB1_q_b[4]_clock_enable_0 = PB1_we_p; UB1_q_b[4]_clear_0 = !E1_NOT_clear; UB1_q_b[4]_PORT_B_data_out = MEMORY(UB1_q_b[4]_PORT_A_data_in_reg, , UB1_q_b[4]_PORT_A_address_reg, UB1_q_b[4]_PORT_B_address_reg, UB1_q_b[4]_PORT_A_write_enable_reg, UB1_q_b[4]_PORT_B_read_enable_reg, , , UB1_q_b[4]_clock_0, UB1_q_b[4]_clock_1, UB1_q_b[4]_clock_enable_0, , UB1_q_b[4]_clear_0, ); UB1_q_b[4]_PORT_B_data_out_reg = DFFE(UB1_q_b[4]_PORT_B_data_out, UB1_q_b[4]_clock_1, , , ); UB1_q_b[12] = UB1_q_b[4]_PORT_B_data_out_reg[1]; --E1_nx361 is ni2io_wt:wt_ni|nx361 --operation mode is normal E1_nx361 = V1_request_47 # V1_request_48 & (E1_or_mask_4) # !V1_request_48 & !E1_NOT_sel_p_0; --E1_nx362 is ni2io_wt:wt_ni|nx362 --operation mode is normal E1_nx362 = V1_request_48 & (SB1_Q_4) # !V1_request_48 & SB2_Q_4 # !V1_request_47; --L1_RDATA_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_4 --operation mode is normal L1_RDATA_4 = L1_nx885 # L1_nx886 # L1_nx887 # L1_nx888; --F1_RDATA_4 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_4 --operation mode is normal F1_RDATA_4 = F1_nx827 # F1_nx828 # V1_request_46 & F1_DDS_ShKey; --K1_RDATA_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_4 --operation mode is normal K1_RDATA_4 = K1_nx968 # K1_nx969 # K1_nx970 # K1_nx971; --J1_RDATA_4 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_4 --operation mode is normal J1_RDATA_4 = V1_request_38 & (J1_PAADC_MuxnRS) # !V1_request_38 & Q1_q_b[4]; --SB1_Q_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_3 --operation mode is arithmetic SB1_Q_3_carry_eqn = SB1_Q_nx22; SB1_Q_3_lut_out = SB1_Q_3 $ (SB1_Q_3_carry_eqn); SB1_Q_3 = DFFEAS(SB1_Q_3_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx28 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx28 --operation mode is arithmetic SB1_Q_nx28 = CARRY(!SB1_Q_nx22 # !SB1_Q_3); --L1_nx889 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx889 --operation mode is normal L1_nx889 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_3) # !V1_request_48 & L1_adc_last_0_3); --L1_nx890 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx890 --operation mode is normal L1_nx890 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_3) # !V1_request_48 & L1_adc_last_4_3); --L1_nx891 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx891 --operation mode is normal L1_nx891 = V1_request_46 & !V1_request_47 & L1_cfr_3; --L1_nx892 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx892 --operation mode is normal L1_nx892 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_3 # !V1_request_48 & (!L1_NOT_climits_a_3)); --F1_nx829 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx829 --operation mode is normal F1_nx829 = F1_bytes2send_35 & (F1_a_3 # F1_bytes_rcvd_35 & F1_nx787) # !F1_bytes2send_35 & F1_bytes_rcvd_35 & (F1_nx787); --F1_nx830 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx830 --operation mode is normal F1_nx830 = F1_bytes2send_3 & (F1_a_1 # F1_bytes_rcvd_3 & F1_nx785) # !F1_bytes2send_3 & F1_bytes_rcvd_3 & (F1_nx785); --K1_nx972 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx972 --operation mode is normal K1_nx972 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_3) # !V1_request_48 & K1_adc_last_0_3); --K1_nx973 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx973 --operation mode is normal K1_nx973 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_3) # !V1_request_48 & K1_adc_last_4_3); --K1_nx974 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx974 --operation mode is normal K1_nx974 = V1_request_46 & !V1_request_47 & K1_cfr_3; --K1_nx975 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx975 --operation mode is normal K1_nx975 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_3 # !V1_request_48 & (!K1_NOT_climits_a_3)); --Q1_q_b[3] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[3] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[3]_PORT_A_data_in = J1_wdata_ram_3; Q1_q_b[3]_PORT_A_data_in_reg = DFFE(Q1_q_b[3]_PORT_A_data_in, Q1_q_b[3]_clock_0, , , Q1_q_b[3]_clock_enable_0); Q1_q_b[3]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[3]_PORT_A_address_reg = DFFE(Q1_q_b[3]_PORT_A_address, Q1_q_b[3]_clock_0, , , Q1_q_b[3]_clock_enable_0); Q1_q_b[3]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[3]_PORT_B_address_reg = DFFE(Q1_q_b[3]_PORT_B_address, Q1_q_b[3]_clock_1, , , ); Q1_q_b[3]_PORT_A_write_enable = VCC; Q1_q_b[3]_PORT_A_write_enable_reg = DFFE(Q1_q_b[3]_PORT_A_write_enable, Q1_q_b[3]_clock_0, , , Q1_q_b[3]_clock_enable_0); Q1_q_b[3]_PORT_B_read_enable = VCC; Q1_q_b[3]_PORT_B_read_enable_reg = DFFE(Q1_q_b[3]_PORT_B_read_enable, Q1_q_b[3]_clock_1, , , ); Q1_q_b[3]_clock_0 = S1__clk1; Q1_q_b[3]_clock_1 = S1__clk1; Q1_q_b[3]_clock_enable_0 = J1_sm; Q1_q_b[3]_PORT_B_data_out = MEMORY(Q1_q_b[3]_PORT_A_data_in_reg, , Q1_q_b[3]_PORT_A_address_reg, Q1_q_b[3]_PORT_B_address_reg, Q1_q_b[3]_PORT_A_write_enable_reg, Q1_q_b[3]_PORT_B_read_enable_reg, , , Q1_q_b[3]_clock_0, Q1_q_b[3]_clock_1, Q1_q_b[3]_clock_enable_0, , , ); Q1_q_b[3]_PORT_B_data_out_reg = DFFE(Q1_q_b[3]_PORT_B_data_out, Q1_q_b[3]_clock_1, , , ); Q1_q_b[3] = Q1_q_b[3]_PORT_B_data_out_reg[0]; --Q1_q_b[19] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[19] Q1_q_b[3]_PORT_A_data_in = J1_wdata_ram_3; Q1_q_b[3]_PORT_A_data_in_reg = DFFE(Q1_q_b[3]_PORT_A_data_in, Q1_q_b[3]_clock_0, , , Q1_q_b[3]_clock_enable_0); Q1_q_b[3]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[3]_PORT_A_address_reg = DFFE(Q1_q_b[3]_PORT_A_address, Q1_q_b[3]_clock_0, , , Q1_q_b[3]_clock_enable_0); Q1_q_b[3]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[3]_PORT_B_address_reg = DFFE(Q1_q_b[3]_PORT_B_address, Q1_q_b[3]_clock_1, , , ); Q1_q_b[3]_PORT_A_write_enable = VCC; Q1_q_b[3]_PORT_A_write_enable_reg = DFFE(Q1_q_b[3]_PORT_A_write_enable, Q1_q_b[3]_clock_0, , , Q1_q_b[3]_clock_enable_0); Q1_q_b[3]_PORT_B_read_enable = VCC; Q1_q_b[3]_PORT_B_read_enable_reg = DFFE(Q1_q_b[3]_PORT_B_read_enable, Q1_q_b[3]_clock_1, , , ); Q1_q_b[3]_clock_0 = S1__clk1; Q1_q_b[3]_clock_1 = S1__clk1; Q1_q_b[3]_clock_enable_0 = J1_sm; Q1_q_b[3]_PORT_B_data_out = MEMORY(Q1_q_b[3]_PORT_A_data_in_reg, , Q1_q_b[3]_PORT_A_address_reg, Q1_q_b[3]_PORT_B_address_reg, Q1_q_b[3]_PORT_A_write_enable_reg, Q1_q_b[3]_PORT_B_read_enable_reg, , , Q1_q_b[3]_clock_0, Q1_q_b[3]_clock_1, Q1_q_b[3]_clock_enable_0, , , ); Q1_q_b[3]_PORT_B_data_out_reg = DFFE(Q1_q_b[3]_PORT_B_data_out, Q1_q_b[3]_clock_1, , , ); Q1_q_b[19] = Q1_q_b[3]_PORT_B_data_out_reg[1]; --L1_adc_last_0_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_2 --operation mode is normal L1_adc_last_0_2_lut_out = R2_RDATA_2; L1_adc_last_0_2 = DFFEAS(L1_adc_last_0_2_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_2 --operation mode is normal L1_adc_last_2_2_lut_out = R2_RDATA_2; L1_adc_last_2_2 = DFFEAS(L1_adc_last_2_2_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_2 --operation mode is normal L1_adc_last_4_2_lut_out = R2_RDATA_2; L1_adc_last_4_2 = DFFEAS(L1_adc_last_4_2_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_2 --operation mode is normal L1_adc_last_6_2_lut_out = R2_RDATA_2; L1_adc_last_6_2 = DFFEAS(L1_adc_last_6_2_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_2 --operation mode is normal L1_NOT_climits_d_2_lut_out = !V1_request_29; L1_NOT_climits_d_2 = DFFEAS(L1_NOT_climits_d_2_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_2 --operation mode is normal L1_NOT_climits_a_2_lut_out = !V1_request_29; L1_NOT_climits_a_2 = DFFEAS(L1_NOT_climits_a_2_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_34 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_34 --operation mode is normal F1_bytes_rcvd_34_lut_out = F1_nx2239; F1_bytes_rcvd_34 = DFFEAS(F1_bytes_rcvd_34_lut_out, S1__clk1, VCC, , F1_NOT_nx2121, , , , ); --F1_bytes_rcvd_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_2 --operation mode is normal F1_bytes_rcvd_2_lut_out = F1_nx2239; F1_bytes_rcvd_2 = DFFEAS(F1_bytes_rcvd_2_lut_out, S1__clk1, VCC, , F1_NOT_nx2249, , , , ); --K1_adc_last_0_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_2 --operation mode is normal K1_adc_last_0_2_lut_out = R1_RDATA_2; K1_adc_last_0_2 = DFFEAS(K1_adc_last_0_2_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_2 --operation mode is normal K1_adc_last_2_2_lut_out = R1_RDATA_2; K1_adc_last_2_2 = DFFEAS(K1_adc_last_2_2_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_2 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_2 --operation mode is normal J1_wdata_ram_2_lut_out = PAADC_D[2]; J1_wdata_ram_2 = DFFEAS(J1_wdata_ram_2_lut_out, S1__clk1, VCC, , , , , , ); --R2_RDATA_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_1 --operation mode is normal R2_RDATA_1_lut_out = R2_RDATA_0; R2_RDATA_1 = DFFEAS(R2_RDATA_1_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --F1_nx2243 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2243 --operation mode is normal F1_nx2243 = F1_byte_recv_1 & (!F1_iword2send_7 # !F1_sm_top_1); --F1_bytes_rcvd_41 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_41 --operation mode is normal F1_bytes_rcvd_41 = DFFEAS(F1_nx2243, S1__clk1, VCC, , F1_NOT_nx2089, , , , ); --AB2_ob_data_21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_21 --operation mode is normal AB2_ob_data_21_lut_out = AB2_ob_data_20; AB2_ob_data_21 = DFFEAS(AB2_ob_data_21_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_21, , , AB2_a_2); --LB2_d_to_dll_22 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_22 --operation mode is normal LB2_d_to_dll_22 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_22 # !DB4_data_out_0 & (T1_reply_22)); --AB1_ob_data_20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_20 --operation mode is normal AB1_ob_data_20_lut_out = AB1_ob_data_19; AB1_ob_data_20 = DFFEAS(AB1_ob_data_20_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_20, , , AB1_a_2); --LB1_d_to_dll_21 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_21 --operation mode is normal LB1_d_to_dll_21 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_21 # !DB3_data_out_0 & (T1_reply_21)); --T1_reply_22 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_22 --operation mode is normal T1_reply_22 = V1_request_22 & (T1_a_0_dup_53 # T1_read_data_9 & !T1_ix34_ix30_nx12) # !V1_request_22 & T1_read_data_9 & (!T1_ix34_ix30_nx12); --T1_read_data_8 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_8 --operation mode is normal T1_read_data_8_lut_out = H1_bus_dout_8; T1_read_data_8 = DFFEAS(T1_read_data_8_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_7 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_7 --operation mode is normal H1_bus_dout_7 = H1_nx197 # H1_nx198 # E1_rdata_7 & H1_sel_0; --E1_rdata_6 is ni2io_wt:wt_ni|rdata_6 --operation mode is normal E1_rdata_6 = V1_request_37 & UB1_q_b[6] # !V1_request_37 & (E1_nx357 & E1_nx358); --H1_nx199 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx199 --operation mode is normal H1_nx199 = L1_RDATA_6 & (H1_ce_sc_adc # F1_RDATA_6 & H1_ce_dds) # !L1_RDATA_6 & F1_RDATA_6 & H1_ce_dds; --H1_nx200 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx200 --operation mode is normal H1_nx200 = K1_RDATA_6 & (H1_ce_psply_adc # J1_RDATA_6 & H1_ce_pasa_adc) # !K1_RDATA_6 & J1_RDATA_6 & (H1_ce_pasa_adc); --UB1_q_b[5] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[5] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB1_q_b[5]_PORT_A_data_in = RB1_dout_5; UB1_q_b[5]_PORT_A_data_in_reg = DFFE(UB1_q_b[5]_PORT_A_data_in, UB1_q_b[5]_clock_0, UB1_q_b[5]_clear_0, , UB1_q_b[5]_clock_enable_0); UB1_q_b[5]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[5]_PORT_A_address_reg = DFFE(UB1_q_b[5]_PORT_A_address, UB1_q_b[5]_clock_0, UB1_q_b[5]_clear_0, , UB1_q_b[5]_clock_enable_0); UB1_q_b[5]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[5]_PORT_B_address_reg = DFFE(UB1_q_b[5]_PORT_B_address, UB1_q_b[5]_clock_1, , , ); UB1_q_b[5]_PORT_A_write_enable = VCC; UB1_q_b[5]_PORT_A_write_enable_reg = DFFE(UB1_q_b[5]_PORT_A_write_enable, UB1_q_b[5]_clock_0, UB1_q_b[5]_clear_0, , UB1_q_b[5]_clock_enable_0); UB1_q_b[5]_PORT_B_read_enable = VCC; UB1_q_b[5]_PORT_B_read_enable_reg = DFFE(UB1_q_b[5]_PORT_B_read_enable, UB1_q_b[5]_clock_1, , , ); UB1_q_b[5]_clock_0 = !WT_STR; UB1_q_b[5]_clock_1 = S1__clk1; UB1_q_b[5]_clock_enable_0 = PB1_we_p; UB1_q_b[5]_clear_0 = !E1_NOT_clear; UB1_q_b[5]_PORT_B_data_out = MEMORY(UB1_q_b[5]_PORT_A_data_in_reg, , UB1_q_b[5]_PORT_A_address_reg, UB1_q_b[5]_PORT_B_address_reg, UB1_q_b[5]_PORT_A_write_enable_reg, UB1_q_b[5]_PORT_B_read_enable_reg, , , UB1_q_b[5]_clock_0, UB1_q_b[5]_clock_1, UB1_q_b[5]_clock_enable_0, , UB1_q_b[5]_clear_0, ); UB1_q_b[5]_PORT_B_data_out_reg = DFFE(UB1_q_b[5]_PORT_B_data_out, UB1_q_b[5]_clock_1, , , ); UB1_q_b[5] = UB1_q_b[5]_PORT_B_data_out_reg[0]; --UB1_q_b[13] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[13] UB1_q_b[5]_PORT_A_data_in = RB1_dout_5; UB1_q_b[5]_PORT_A_data_in_reg = DFFE(UB1_q_b[5]_PORT_A_data_in, UB1_q_b[5]_clock_0, UB1_q_b[5]_clear_0, , UB1_q_b[5]_clock_enable_0); UB1_q_b[5]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[5]_PORT_A_address_reg = DFFE(UB1_q_b[5]_PORT_A_address, UB1_q_b[5]_clock_0, UB1_q_b[5]_clear_0, , UB1_q_b[5]_clock_enable_0); UB1_q_b[5]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[5]_PORT_B_address_reg = DFFE(UB1_q_b[5]_PORT_B_address, UB1_q_b[5]_clock_1, , , ); UB1_q_b[5]_PORT_A_write_enable = VCC; UB1_q_b[5]_PORT_A_write_enable_reg = DFFE(UB1_q_b[5]_PORT_A_write_enable, UB1_q_b[5]_clock_0, UB1_q_b[5]_clear_0, , UB1_q_b[5]_clock_enable_0); UB1_q_b[5]_PORT_B_read_enable = VCC; UB1_q_b[5]_PORT_B_read_enable_reg = DFFE(UB1_q_b[5]_PORT_B_read_enable, UB1_q_b[5]_clock_1, , , ); UB1_q_b[5]_clock_0 = !WT_STR; UB1_q_b[5]_clock_1 = S1__clk1; UB1_q_b[5]_clock_enable_0 = PB1_we_p; UB1_q_b[5]_clear_0 = !E1_NOT_clear; UB1_q_b[5]_PORT_B_data_out = MEMORY(UB1_q_b[5]_PORT_A_data_in_reg, , UB1_q_b[5]_PORT_A_address_reg, UB1_q_b[5]_PORT_B_address_reg, UB1_q_b[5]_PORT_A_write_enable_reg, UB1_q_b[5]_PORT_B_read_enable_reg, , , UB1_q_b[5]_clock_0, UB1_q_b[5]_clock_1, UB1_q_b[5]_clock_enable_0, , UB1_q_b[5]_clear_0, ); UB1_q_b[5]_PORT_B_data_out_reg = DFFE(UB1_q_b[5]_PORT_B_data_out, UB1_q_b[5]_clock_1, , , ); UB1_q_b[13] = UB1_q_b[5]_PORT_B_data_out_reg[1]; --E1_nx359 is ni2io_wt:wt_ni|nx359 --operation mode is normal E1_nx359 = V1_request_47 # V1_request_48 & (E1_or_mask_5) # !V1_request_48 & E1_sel_p_1; --E1_nx360 is ni2io_wt:wt_ni|nx360 --operation mode is normal E1_nx360 = V1_request_48 & (SB1_Q_5) # !V1_request_48 & SB2_Q_5 # !V1_request_47; --L1_RDATA_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_5 --operation mode is normal L1_RDATA_5 = L1_nx881 # L1_nx882 # L1_nx883 # L1_nx884; --F1_RDATA_5 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_5 --operation mode is normal F1_RDATA_5 = F1_nx825 # F1_nx826 # V1_request_46 & F1_DDS_FSK; --K1_RDATA_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_5 --operation mode is normal K1_RDATA_5 = K1_nx964 # K1_nx965 # K1_nx966 # K1_nx967; --J1_RDATA_5 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_5 --operation mode is normal J1_RDATA_5 = V1_request_38 & (J1_cfr_5) # !V1_request_38 & Q1_q_b[5]; --SB1_Q_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_4 --operation mode is arithmetic SB1_Q_4_carry_eqn = SB1_Q_nx28; SB1_Q_4_lut_out = SB1_Q_4 $ (!SB1_Q_4_carry_eqn); SB1_Q_4 = DFFEAS(SB1_Q_4_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx34 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx34 --operation mode is arithmetic SB1_Q_nx34 = CARRY(SB1_Q_4 & (!SB1_Q_nx28)); --L1_nx885 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx885 --operation mode is normal L1_nx885 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_4) # !V1_request_48 & L1_adc_last_0_4); --L1_nx886 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx886 --operation mode is normal L1_nx886 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_4) # !V1_request_48 & L1_adc_last_4_4); --L1_nx887 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx887 --operation mode is normal L1_nx887 = V1_request_46 & !V1_request_47 & L1_cfr_4; --L1_nx888 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx888 --operation mode is normal L1_nx888 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_4 # !V1_request_48 & (!L1_NOT_climits_a_4)); --F1_nx827 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx827 --operation mode is normal F1_nx827 = F1_bytes2send_36 & (F1_a_3 # F1_bytes_rcvd_36 & F1_nx787) # !F1_bytes2send_36 & F1_bytes_rcvd_36 & (F1_nx787); --F1_nx828 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx828 --operation mode is normal F1_nx828 = F1_bytes2send_4 & (F1_a_1 # F1_bytes_rcvd_4 & F1_nx785) # !F1_bytes2send_4 & F1_bytes_rcvd_4 & (F1_nx785); --K1_nx968 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx968 --operation mode is normal K1_nx968 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_4) # !V1_request_48 & K1_adc_last_0_4); --K1_nx969 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx969 --operation mode is normal K1_nx969 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_4) # !V1_request_48 & K1_adc_last_4_4); --K1_nx970 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx970 --operation mode is normal K1_nx970 = V1_request_46 & !V1_request_47 & K1_cfr_4; --K1_nx971 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx971 --operation mode is normal K1_nx971 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_4 # !V1_request_48 & (!K1_NOT_climits_a_4)); --Q1_q_b[4] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[4] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[4]_PORT_A_data_in = J1_wdata_ram_4; Q1_q_b[4]_PORT_A_data_in_reg = DFFE(Q1_q_b[4]_PORT_A_data_in, Q1_q_b[4]_clock_0, , , Q1_q_b[4]_clock_enable_0); Q1_q_b[4]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[4]_PORT_A_address_reg = DFFE(Q1_q_b[4]_PORT_A_address, Q1_q_b[4]_clock_0, , , Q1_q_b[4]_clock_enable_0); Q1_q_b[4]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[4]_PORT_B_address_reg = DFFE(Q1_q_b[4]_PORT_B_address, Q1_q_b[4]_clock_1, , , ); Q1_q_b[4]_PORT_A_write_enable = VCC; Q1_q_b[4]_PORT_A_write_enable_reg = DFFE(Q1_q_b[4]_PORT_A_write_enable, Q1_q_b[4]_clock_0, , , Q1_q_b[4]_clock_enable_0); Q1_q_b[4]_PORT_B_read_enable = VCC; Q1_q_b[4]_PORT_B_read_enable_reg = DFFE(Q1_q_b[4]_PORT_B_read_enable, Q1_q_b[4]_clock_1, , , ); Q1_q_b[4]_clock_0 = S1__clk1; Q1_q_b[4]_clock_1 = S1__clk1; Q1_q_b[4]_clock_enable_0 = J1_sm; Q1_q_b[4]_PORT_B_data_out = MEMORY(Q1_q_b[4]_PORT_A_data_in_reg, , Q1_q_b[4]_PORT_A_address_reg, Q1_q_b[4]_PORT_B_address_reg, Q1_q_b[4]_PORT_A_write_enable_reg, Q1_q_b[4]_PORT_B_read_enable_reg, , , Q1_q_b[4]_clock_0, Q1_q_b[4]_clock_1, Q1_q_b[4]_clock_enable_0, , , ); Q1_q_b[4]_PORT_B_data_out_reg = DFFE(Q1_q_b[4]_PORT_B_data_out, Q1_q_b[4]_clock_1, , , ); Q1_q_b[4] = Q1_q_b[4]_PORT_B_data_out_reg[0]; --Q1_q_b[20] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[20] Q1_q_b[4]_PORT_A_data_in = J1_wdata_ram_4; Q1_q_b[4]_PORT_A_data_in_reg = DFFE(Q1_q_b[4]_PORT_A_data_in, Q1_q_b[4]_clock_0, , , Q1_q_b[4]_clock_enable_0); Q1_q_b[4]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[4]_PORT_A_address_reg = DFFE(Q1_q_b[4]_PORT_A_address, Q1_q_b[4]_clock_0, , , Q1_q_b[4]_clock_enable_0); Q1_q_b[4]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[4]_PORT_B_address_reg = DFFE(Q1_q_b[4]_PORT_B_address, Q1_q_b[4]_clock_1, , , ); Q1_q_b[4]_PORT_A_write_enable = VCC; Q1_q_b[4]_PORT_A_write_enable_reg = DFFE(Q1_q_b[4]_PORT_A_write_enable, Q1_q_b[4]_clock_0, , , Q1_q_b[4]_clock_enable_0); Q1_q_b[4]_PORT_B_read_enable = VCC; Q1_q_b[4]_PORT_B_read_enable_reg = DFFE(Q1_q_b[4]_PORT_B_read_enable, Q1_q_b[4]_clock_1, , , ); Q1_q_b[4]_clock_0 = S1__clk1; Q1_q_b[4]_clock_1 = S1__clk1; Q1_q_b[4]_clock_enable_0 = J1_sm; Q1_q_b[4]_PORT_B_data_out = MEMORY(Q1_q_b[4]_PORT_A_data_in_reg, , Q1_q_b[4]_PORT_A_address_reg, Q1_q_b[4]_PORT_B_address_reg, Q1_q_b[4]_PORT_A_write_enable_reg, Q1_q_b[4]_PORT_B_read_enable_reg, , , Q1_q_b[4]_clock_0, Q1_q_b[4]_clock_1, Q1_q_b[4]_clock_enable_0, , , ); Q1_q_b[4]_PORT_B_data_out_reg = DFFE(Q1_q_b[4]_PORT_B_data_out, Q1_q_b[4]_clock_1, , , ); Q1_q_b[20] = Q1_q_b[4]_PORT_B_data_out_reg[1]; --L1_adc_last_0_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_3 --operation mode is normal L1_adc_last_0_3_lut_out = R2_RDATA_3; L1_adc_last_0_3 = DFFEAS(L1_adc_last_0_3_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_3 --operation mode is normal L1_adc_last_2_3_lut_out = R2_RDATA_3; L1_adc_last_2_3 = DFFEAS(L1_adc_last_2_3_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_3 --operation mode is normal L1_adc_last_4_3_lut_out = R2_RDATA_3; L1_adc_last_4_3 = DFFEAS(L1_adc_last_4_3_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_3 --operation mode is normal L1_adc_last_6_3_lut_out = R2_RDATA_3; L1_adc_last_6_3 = DFFEAS(L1_adc_last_6_3_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_3 --operation mode is normal L1_NOT_climits_d_3_lut_out = !V1_request_28; L1_NOT_climits_d_3 = DFFEAS(L1_NOT_climits_d_3_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_3 --operation mode is normal L1_NOT_climits_a_3_lut_out = !V1_request_28; L1_NOT_climits_a_3 = DFFEAS(L1_NOT_climits_a_3_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_35 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_35 --operation mode is normal F1_bytes_rcvd_35_lut_out = F1_nx2235; F1_bytes_rcvd_35 = DFFEAS(F1_bytes_rcvd_35_lut_out, S1__clk1, VCC, , F1_NOT_nx2121, , , , ); --F1_bytes_rcvd_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_3 --operation mode is normal F1_bytes_rcvd_3_lut_out = F1_nx2235; F1_bytes_rcvd_3 = DFFEAS(F1_bytes_rcvd_3_lut_out, S1__clk1, VCC, , F1_NOT_nx2249, , , , ); --K1_adc_last_0_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_3 --operation mode is normal K1_adc_last_0_3_lut_out = R1_RDATA_3; K1_adc_last_0_3 = DFFEAS(K1_adc_last_0_3_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_3 --operation mode is normal K1_adc_last_2_3_lut_out = R1_RDATA_3; K1_adc_last_2_3 = DFFEAS(K1_adc_last_2_3_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_3 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_3 --operation mode is normal J1_wdata_ram_3_lut_out = PAADC_D[3]; J1_wdata_ram_3 = DFFEAS(J1_wdata_ram_3_lut_out, S1__clk1, VCC, , , , , , ); --R2_RDATA_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_2 --operation mode is normal R2_RDATA_2_lut_out = R2_RDATA_1; R2_RDATA_2 = DFFEAS(R2_RDATA_2_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --F1_nx2239 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2239 --operation mode is normal F1_nx2239 = F1_byte_recv_2 & (!F1_iword2send_7 # !F1_sm_top_1); --F1_bytes_rcvd_42 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_42 --operation mode is normal F1_bytes_rcvd_42 = DFFEAS(F1_nx2239, S1__clk1, VCC, , F1_NOT_nx2089, , , , ); --F1_byte_recv_1 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_recv_1 --operation mode is normal F1_byte_recv_1_lut_out = F1_byte_recv_0; F1_byte_recv_1 = DFFEAS(F1_byte_recv_1_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2793, , , , ); --AB2_ob_data_20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_20 --operation mode is normal AB2_ob_data_20_lut_out = AB2_ob_data_19; AB2_ob_data_20 = DFFEAS(AB2_ob_data_20_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_20, , , AB2_a_2); --LB2_d_to_dll_21 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_21 --operation mode is normal LB2_d_to_dll_21 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_21 # !DB4_data_out_0 & (T1_reply_21)); --AB1_ob_data_19 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_19 --operation mode is normal AB1_ob_data_19_lut_out = AB1_ob_data_18; AB1_ob_data_19 = DFFEAS(AB1_ob_data_19_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_19, , , AB1_a_2); --LB1_d_to_dll_20 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_20 --operation mode is normal LB1_d_to_dll_20 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_20 # !DB3_data_out_0 & (T1_reply_20)); --T1_reply_21 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_21 --operation mode is normal T1_reply_21 = V1_request_21 & (T1_a_0_dup_53 # T1_read_data_10 & !T1_ix34_ix30_nx12) # !V1_request_21 & T1_read_data_10 & (!T1_ix34_ix30_nx12); --T1_read_data_9 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_9 --operation mode is normal T1_read_data_9_lut_out = H1_bus_dout_9; T1_read_data_9 = DFFEAS(T1_read_data_9_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_8 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_8 --operation mode is normal H1_bus_dout_8 = H1_nx195 # H1_nx196 # E1_rdata_8 & H1_sel_0; --E1_rdata_7 is ni2io_wt:wt_ni|rdata_7 --operation mode is normal E1_rdata_7 = V1_request_37 & UB1_q_b[7] # !V1_request_37 & (E1_nx355 & E1_nx356); --H1_nx197 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx197 --operation mode is normal H1_nx197 = L1_RDATA_7 & (H1_ce_sc_adc # F1_RDATA_7 & H1_ce_dds) # !L1_RDATA_7 & F1_RDATA_7 & H1_ce_dds; --H1_nx198 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx198 --operation mode is normal H1_nx198 = K1_RDATA_7 & (H1_ce_psply_adc # J1_RDATA_7 & H1_ce_pasa_adc) # !K1_RDATA_7 & J1_RDATA_7 & (H1_ce_pasa_adc); --UB1_q_b[6] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[6] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB1_q_b[6]_PORT_A_data_in = RB1_dout_6; UB1_q_b[6]_PORT_A_data_in_reg = DFFE(UB1_q_b[6]_PORT_A_data_in, UB1_q_b[6]_clock_0, UB1_q_b[6]_clear_0, , UB1_q_b[6]_clock_enable_0); UB1_q_b[6]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[6]_PORT_A_address_reg = DFFE(UB1_q_b[6]_PORT_A_address, UB1_q_b[6]_clock_0, UB1_q_b[6]_clear_0, , UB1_q_b[6]_clock_enable_0); UB1_q_b[6]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[6]_PORT_B_address_reg = DFFE(UB1_q_b[6]_PORT_B_address, UB1_q_b[6]_clock_1, , , ); UB1_q_b[6]_PORT_A_write_enable = VCC; UB1_q_b[6]_PORT_A_write_enable_reg = DFFE(UB1_q_b[6]_PORT_A_write_enable, UB1_q_b[6]_clock_0, UB1_q_b[6]_clear_0, , UB1_q_b[6]_clock_enable_0); UB1_q_b[6]_PORT_B_read_enable = VCC; UB1_q_b[6]_PORT_B_read_enable_reg = DFFE(UB1_q_b[6]_PORT_B_read_enable, UB1_q_b[6]_clock_1, , , ); UB1_q_b[6]_clock_0 = !WT_STR; UB1_q_b[6]_clock_1 = S1__clk1; UB1_q_b[6]_clock_enable_0 = PB1_we_p; UB1_q_b[6]_clear_0 = !E1_NOT_clear; UB1_q_b[6]_PORT_B_data_out = MEMORY(UB1_q_b[6]_PORT_A_data_in_reg, , UB1_q_b[6]_PORT_A_address_reg, UB1_q_b[6]_PORT_B_address_reg, UB1_q_b[6]_PORT_A_write_enable_reg, UB1_q_b[6]_PORT_B_read_enable_reg, , , UB1_q_b[6]_clock_0, UB1_q_b[6]_clock_1, UB1_q_b[6]_clock_enable_0, , UB1_q_b[6]_clear_0, ); UB1_q_b[6]_PORT_B_data_out_reg = DFFE(UB1_q_b[6]_PORT_B_data_out, UB1_q_b[6]_clock_1, , , ); UB1_q_b[6] = UB1_q_b[6]_PORT_B_data_out_reg[0]; --UB1_q_b[14] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[14] UB1_q_b[6]_PORT_A_data_in = RB1_dout_6; UB1_q_b[6]_PORT_A_data_in_reg = DFFE(UB1_q_b[6]_PORT_A_data_in, UB1_q_b[6]_clock_0, UB1_q_b[6]_clear_0, , UB1_q_b[6]_clock_enable_0); UB1_q_b[6]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[6]_PORT_A_address_reg = DFFE(UB1_q_b[6]_PORT_A_address, UB1_q_b[6]_clock_0, UB1_q_b[6]_clear_0, , UB1_q_b[6]_clock_enable_0); UB1_q_b[6]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[6]_PORT_B_address_reg = DFFE(UB1_q_b[6]_PORT_B_address, UB1_q_b[6]_clock_1, , , ); UB1_q_b[6]_PORT_A_write_enable = VCC; UB1_q_b[6]_PORT_A_write_enable_reg = DFFE(UB1_q_b[6]_PORT_A_write_enable, UB1_q_b[6]_clock_0, UB1_q_b[6]_clear_0, , UB1_q_b[6]_clock_enable_0); UB1_q_b[6]_PORT_B_read_enable = VCC; UB1_q_b[6]_PORT_B_read_enable_reg = DFFE(UB1_q_b[6]_PORT_B_read_enable, UB1_q_b[6]_clock_1, , , ); UB1_q_b[6]_clock_0 = !WT_STR; UB1_q_b[6]_clock_1 = S1__clk1; UB1_q_b[6]_clock_enable_0 = PB1_we_p; UB1_q_b[6]_clear_0 = !E1_NOT_clear; UB1_q_b[6]_PORT_B_data_out = MEMORY(UB1_q_b[6]_PORT_A_data_in_reg, , UB1_q_b[6]_PORT_A_address_reg, UB1_q_b[6]_PORT_B_address_reg, UB1_q_b[6]_PORT_A_write_enable_reg, UB1_q_b[6]_PORT_B_read_enable_reg, , , UB1_q_b[6]_clock_0, UB1_q_b[6]_clock_1, UB1_q_b[6]_clock_enable_0, , UB1_q_b[6]_clear_0, ); UB1_q_b[6]_PORT_B_data_out_reg = DFFE(UB1_q_b[6]_PORT_B_data_out, UB1_q_b[6]_clock_1, , , ); UB1_q_b[14] = UB1_q_b[6]_PORT_B_data_out_reg[1]; --E1_nx357 is ni2io_wt:wt_ni|nx357 --operation mode is normal E1_nx357 = V1_request_47 # V1_request_48 & (E1_or_mask_6) # !V1_request_48 & E1_sel_p_2; --E1_nx358 is ni2io_wt:wt_ni|nx358 --operation mode is normal E1_nx358 = V1_request_48 & (SB1_Q_6) # !V1_request_48 & SB2_Q_6 # !V1_request_47; --L1_RDATA_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_6 --operation mode is normal L1_RDATA_6 = L1_nx877 # L1_nx878 # L1_nx879 # L1_nx880; --F1_RDATA_6 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_6 --operation mode is normal F1_RDATA_6 = F1_nx823 # F1_nx824 # V1_request_46 & F1_config_6; --K1_RDATA_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_6 --operation mode is normal K1_RDATA_6 = K1_nx960 # K1_nx961 # K1_nx962 # K1_nx963; --J1_RDATA_6 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_6 --operation mode is normal J1_RDATA_6 = V1_request_38 & (!J1_NOT_cfr_6) # !V1_request_38 & Q1_q_b[6]; --SB1_Q_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_5 --operation mode is arithmetic SB1_Q_5_carry_eqn = SB1_Q_nx34; SB1_Q_5_lut_out = SB1_Q_5 $ (SB1_Q_5_carry_eqn); SB1_Q_5 = DFFEAS(SB1_Q_5_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx40 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx40 --operation mode is arithmetic SB1_Q_nx40 = CARRY(!SB1_Q_nx34 # !SB1_Q_5); --L1_nx881 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx881 --operation mode is normal L1_nx881 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_5) # !V1_request_48 & L1_adc_last_0_5); --L1_nx882 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx882 --operation mode is normal L1_nx882 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_5) # !V1_request_48 & L1_adc_last_4_5); --L1_nx883 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx883 --operation mode is normal L1_nx883 = V1_request_46 & !V1_request_47 & L1_cfr_5; --L1_nx884 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx884 --operation mode is normal L1_nx884 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_5 # !V1_request_48 & (!L1_NOT_climits_a_5)); --F1_nx825 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx825 --operation mode is normal F1_nx825 = F1_bytes2send_37 & (F1_a_3 # F1_bytes_rcvd_37 & F1_nx787) # !F1_bytes2send_37 & F1_bytes_rcvd_37 & (F1_nx787); --F1_nx826 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx826 --operation mode is normal F1_nx826 = F1_bytes2send_5 & (F1_a_1 # F1_bytes_rcvd_5 & F1_nx785) # !F1_bytes2send_5 & F1_bytes_rcvd_5 & (F1_nx785); --K1_nx964 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx964 --operation mode is normal K1_nx964 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_5) # !V1_request_48 & K1_adc_last_0_5); --K1_nx965 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx965 --operation mode is normal K1_nx965 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_5) # !V1_request_48 & K1_adc_last_4_5); --K1_nx966 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx966 --operation mode is normal K1_nx966 = V1_request_46 & !V1_request_47 & K1_cfr_5; --K1_nx967 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx967 --operation mode is normal K1_nx967 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_5 # !V1_request_48 & (!K1_NOT_climits_a_5)); --Q1_q_b[5] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[5] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[5]_PORT_A_data_in = J1_wdata_ram_5; Q1_q_b[5]_PORT_A_data_in_reg = DFFE(Q1_q_b[5]_PORT_A_data_in, Q1_q_b[5]_clock_0, , , Q1_q_b[5]_clock_enable_0); Q1_q_b[5]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[5]_PORT_A_address_reg = DFFE(Q1_q_b[5]_PORT_A_address, Q1_q_b[5]_clock_0, , , Q1_q_b[5]_clock_enable_0); Q1_q_b[5]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[5]_PORT_B_address_reg = DFFE(Q1_q_b[5]_PORT_B_address, Q1_q_b[5]_clock_1, , , ); Q1_q_b[5]_PORT_A_write_enable = VCC; Q1_q_b[5]_PORT_A_write_enable_reg = DFFE(Q1_q_b[5]_PORT_A_write_enable, Q1_q_b[5]_clock_0, , , Q1_q_b[5]_clock_enable_0); Q1_q_b[5]_PORT_B_read_enable = VCC; Q1_q_b[5]_PORT_B_read_enable_reg = DFFE(Q1_q_b[5]_PORT_B_read_enable, Q1_q_b[5]_clock_1, , , ); Q1_q_b[5]_clock_0 = S1__clk1; Q1_q_b[5]_clock_1 = S1__clk1; Q1_q_b[5]_clock_enable_0 = J1_sm; Q1_q_b[5]_PORT_B_data_out = MEMORY(Q1_q_b[5]_PORT_A_data_in_reg, , Q1_q_b[5]_PORT_A_address_reg, Q1_q_b[5]_PORT_B_address_reg, Q1_q_b[5]_PORT_A_write_enable_reg, Q1_q_b[5]_PORT_B_read_enable_reg, , , Q1_q_b[5]_clock_0, Q1_q_b[5]_clock_1, Q1_q_b[5]_clock_enable_0, , , ); Q1_q_b[5]_PORT_B_data_out_reg = DFFE(Q1_q_b[5]_PORT_B_data_out, Q1_q_b[5]_clock_1, , , ); Q1_q_b[5] = Q1_q_b[5]_PORT_B_data_out_reg[0]; --Q1_q_b[21] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[21] Q1_q_b[5]_PORT_A_data_in = J1_wdata_ram_5; Q1_q_b[5]_PORT_A_data_in_reg = DFFE(Q1_q_b[5]_PORT_A_data_in, Q1_q_b[5]_clock_0, , , Q1_q_b[5]_clock_enable_0); Q1_q_b[5]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[5]_PORT_A_address_reg = DFFE(Q1_q_b[5]_PORT_A_address, Q1_q_b[5]_clock_0, , , Q1_q_b[5]_clock_enable_0); Q1_q_b[5]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[5]_PORT_B_address_reg = DFFE(Q1_q_b[5]_PORT_B_address, Q1_q_b[5]_clock_1, , , ); Q1_q_b[5]_PORT_A_write_enable = VCC; Q1_q_b[5]_PORT_A_write_enable_reg = DFFE(Q1_q_b[5]_PORT_A_write_enable, Q1_q_b[5]_clock_0, , , Q1_q_b[5]_clock_enable_0); Q1_q_b[5]_PORT_B_read_enable = VCC; Q1_q_b[5]_PORT_B_read_enable_reg = DFFE(Q1_q_b[5]_PORT_B_read_enable, Q1_q_b[5]_clock_1, , , ); Q1_q_b[5]_clock_0 = S1__clk1; Q1_q_b[5]_clock_1 = S1__clk1; Q1_q_b[5]_clock_enable_0 = J1_sm; Q1_q_b[5]_PORT_B_data_out = MEMORY(Q1_q_b[5]_PORT_A_data_in_reg, , Q1_q_b[5]_PORT_A_address_reg, Q1_q_b[5]_PORT_B_address_reg, Q1_q_b[5]_PORT_A_write_enable_reg, Q1_q_b[5]_PORT_B_read_enable_reg, , , Q1_q_b[5]_clock_0, Q1_q_b[5]_clock_1, Q1_q_b[5]_clock_enable_0, , , ); Q1_q_b[5]_PORT_B_data_out_reg = DFFE(Q1_q_b[5]_PORT_B_data_out, Q1_q_b[5]_clock_1, , , ); Q1_q_b[21] = Q1_q_b[5]_PORT_B_data_out_reg[1]; --L1_adc_last_0_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_4 --operation mode is normal L1_adc_last_0_4_lut_out = R2_RDATA_4; L1_adc_last_0_4 = DFFEAS(L1_adc_last_0_4_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_4 --operation mode is normal L1_adc_last_2_4_lut_out = R2_RDATA_4; L1_adc_last_2_4 = DFFEAS(L1_adc_last_2_4_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_4 --operation mode is normal L1_adc_last_4_4_lut_out = R2_RDATA_4; L1_adc_last_4_4 = DFFEAS(L1_adc_last_4_4_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_4 --operation mode is normal L1_adc_last_6_4_lut_out = R2_RDATA_4; L1_adc_last_6_4 = DFFEAS(L1_adc_last_6_4_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_4 --operation mode is normal L1_NOT_climits_d_4_lut_out = !V1_request_27; L1_NOT_climits_d_4 = DFFEAS(L1_NOT_climits_d_4_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_4 --operation mode is normal L1_NOT_climits_a_4_lut_out = !V1_request_27; L1_NOT_climits_a_4 = DFFEAS(L1_NOT_climits_a_4_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_36 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_36 --operation mode is normal F1_bytes_rcvd_36_lut_out = F1_nx2231; F1_bytes_rcvd_36 = DFFEAS(F1_bytes_rcvd_36_lut_out, S1__clk1, VCC, , F1_NOT_nx2121, , , , ); --F1_bytes_rcvd_4 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_4 --operation mode is normal F1_bytes_rcvd_4_lut_out = F1_nx2231; F1_bytes_rcvd_4 = DFFEAS(F1_bytes_rcvd_4_lut_out, S1__clk1, VCC, , F1_NOT_nx2249, , , , ); --K1_adc_last_0_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_4 --operation mode is normal K1_adc_last_0_4_lut_out = R1_RDATA_4; K1_adc_last_0_4 = DFFEAS(K1_adc_last_0_4_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_4 --operation mode is normal K1_adc_last_2_4_lut_out = R1_RDATA_4; K1_adc_last_2_4 = DFFEAS(K1_adc_last_2_4_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_4 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_4 --operation mode is normal J1_wdata_ram_4_lut_out = PAADC_D[4]; J1_wdata_ram_4 = DFFEAS(J1_wdata_ram_4_lut_out, S1__clk1, VCC, , , , , , ); --R2_RDATA_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_3 --operation mode is normal R2_RDATA_3_lut_out = R2_RDATA_2; R2_RDATA_3 = DFFEAS(R2_RDATA_3_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --F1_nx2235 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2235 --operation mode is normal F1_nx2235 = F1_byte_recv_3 & (!F1_iword2send_7 # !F1_sm_top_1); --F1_bytes_rcvd_43 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_43 --operation mode is normal F1_bytes_rcvd_43 = DFFEAS(F1_nx2235, S1__clk1, VCC, , F1_NOT_nx2089, , , , ); --F1_byte_recv_2 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_recv_2 --operation mode is normal F1_byte_recv_2_lut_out = F1_byte_recv_1; F1_byte_recv_2 = DFFEAS(F1_byte_recv_2_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2793, , , , ); --F1_NOT_nx2793 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx2793 --operation mode is normal F1_NOT_nx2793 = F1_sm_sr_1 & F1_clkdivs; --AB2_ob_data_19 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_19 --operation mode is normal AB2_ob_data_19_lut_out = AB2_ob_data_18; AB2_ob_data_19 = DFFEAS(AB2_ob_data_19_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_19, , , AB2_a_2); --LB2_d_to_dll_20 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_20 --operation mode is normal LB2_d_to_dll_20 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_20 # !DB4_data_out_0 & (T1_reply_20)); --AB1_ob_data_18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_18 --operation mode is normal AB1_ob_data_18_lut_out = AB1_ob_data_17; AB1_ob_data_18 = DFFEAS(AB1_ob_data_18_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_18, , , AB1_a_2); --LB1_d_to_dll_19 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_19 --operation mode is normal LB1_d_to_dll_19 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_19 # !DB3_data_out_0 & (T1_reply_19)); --T1_reply_20 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_20 --operation mode is normal T1_reply_20 = V1_request_20 & (T1_a_0_dup_53 # T1_read_data_11 & !T1_ix34_ix30_nx12) # !V1_request_20 & T1_read_data_11 & (!T1_ix34_ix30_nx12); --T1_read_data_10 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_10 --operation mode is normal T1_read_data_10_lut_out = H1_bus_dout_10; T1_read_data_10 = DFFEAS(T1_read_data_10_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_9 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_9 --operation mode is normal H1_bus_dout_9 = H1_nx193 # H1_nx194 # E1_rdata_9 & H1_sel_0; --E1_rdata_8 is ni2io_wt:wt_ni|rdata_8 --operation mode is normal E1_rdata_8 = V1_request_37 & UB2_q_b[0] # !V1_request_37 & (E1_nx353 & E1_nx354); --H1_nx195 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx195 --operation mode is normal H1_nx195 = L1_RDATA_8 & (H1_ce_sc_adc # F1_RDATA_8 & H1_ce_dds) # !L1_RDATA_8 & F1_RDATA_8 & H1_ce_dds; --H1_nx196 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx196 --operation mode is normal H1_nx196 = K1_RDATA_8 & (H1_ce_psply_adc # J1_RDATA_8 & H1_ce_pasa_adc) # !K1_RDATA_8 & J1_RDATA_8 & (H1_ce_pasa_adc); --UB1_q_b[7] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[7] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB1_q_b[7]_PORT_A_data_in = RB1_dout_7; UB1_q_b[7]_PORT_A_data_in_reg = DFFE(UB1_q_b[7]_PORT_A_data_in, UB1_q_b[7]_clock_0, UB1_q_b[7]_clear_0, , UB1_q_b[7]_clock_enable_0); UB1_q_b[7]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[7]_PORT_A_address_reg = DFFE(UB1_q_b[7]_PORT_A_address, UB1_q_b[7]_clock_0, UB1_q_b[7]_clear_0, , UB1_q_b[7]_clock_enable_0); UB1_q_b[7]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[7]_PORT_B_address_reg = DFFE(UB1_q_b[7]_PORT_B_address, UB1_q_b[7]_clock_1, , , ); UB1_q_b[7]_PORT_A_write_enable = VCC; UB1_q_b[7]_PORT_A_write_enable_reg = DFFE(UB1_q_b[7]_PORT_A_write_enable, UB1_q_b[7]_clock_0, UB1_q_b[7]_clear_0, , UB1_q_b[7]_clock_enable_0); UB1_q_b[7]_PORT_B_read_enable = VCC; UB1_q_b[7]_PORT_B_read_enable_reg = DFFE(UB1_q_b[7]_PORT_B_read_enable, UB1_q_b[7]_clock_1, , , ); UB1_q_b[7]_clock_0 = !WT_STR; UB1_q_b[7]_clock_1 = S1__clk1; UB1_q_b[7]_clock_enable_0 = PB1_we_p; UB1_q_b[7]_clear_0 = !E1_NOT_clear; UB1_q_b[7]_PORT_B_data_out = MEMORY(UB1_q_b[7]_PORT_A_data_in_reg, , UB1_q_b[7]_PORT_A_address_reg, UB1_q_b[7]_PORT_B_address_reg, UB1_q_b[7]_PORT_A_write_enable_reg, UB1_q_b[7]_PORT_B_read_enable_reg, , , UB1_q_b[7]_clock_0, UB1_q_b[7]_clock_1, UB1_q_b[7]_clock_enable_0, , UB1_q_b[7]_clear_0, ); UB1_q_b[7]_PORT_B_data_out_reg = DFFE(UB1_q_b[7]_PORT_B_data_out, UB1_q_b[7]_clock_1, , , ); UB1_q_b[7] = UB1_q_b[7]_PORT_B_data_out_reg[0]; --UB1_q_b[15] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[15] UB1_q_b[7]_PORT_A_data_in = RB1_dout_7; UB1_q_b[7]_PORT_A_data_in_reg = DFFE(UB1_q_b[7]_PORT_A_data_in, UB1_q_b[7]_clock_0, UB1_q_b[7]_clear_0, , UB1_q_b[7]_clock_enable_0); UB1_q_b[7]_PORT_A_address = BUS(SB2_Q_0, SB2_Q_1, SB2_Q_2, SB2_Q_3, SB2_Q_4, SB2_Q_5, SB2_Q_6, SB2_Q_7, SB2_Q_8, SB2_Q_9, SB2_Q_10, SB2_Q_11); UB1_q_b[7]_PORT_A_address_reg = DFFE(UB1_q_b[7]_PORT_A_address, UB1_q_b[7]_clock_0, UB1_q_b[7]_clear_0, , UB1_q_b[7]_clock_enable_0); UB1_q_b[7]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB1_q_b[7]_PORT_B_address_reg = DFFE(UB1_q_b[7]_PORT_B_address, UB1_q_b[7]_clock_1, , , ); UB1_q_b[7]_PORT_A_write_enable = VCC; UB1_q_b[7]_PORT_A_write_enable_reg = DFFE(UB1_q_b[7]_PORT_A_write_enable, UB1_q_b[7]_clock_0, UB1_q_b[7]_clear_0, , UB1_q_b[7]_clock_enable_0); UB1_q_b[7]_PORT_B_read_enable = VCC; UB1_q_b[7]_PORT_B_read_enable_reg = DFFE(UB1_q_b[7]_PORT_B_read_enable, UB1_q_b[7]_clock_1, , , ); UB1_q_b[7]_clock_0 = !WT_STR; UB1_q_b[7]_clock_1 = S1__clk1; UB1_q_b[7]_clock_enable_0 = PB1_we_p; UB1_q_b[7]_clear_0 = !E1_NOT_clear; UB1_q_b[7]_PORT_B_data_out = MEMORY(UB1_q_b[7]_PORT_A_data_in_reg, , UB1_q_b[7]_PORT_A_address_reg, UB1_q_b[7]_PORT_B_address_reg, UB1_q_b[7]_PORT_A_write_enable_reg, UB1_q_b[7]_PORT_B_read_enable_reg, , , UB1_q_b[7]_clock_0, UB1_q_b[7]_clock_1, UB1_q_b[7]_clock_enable_0, , UB1_q_b[7]_clear_0, ); UB1_q_b[7]_PORT_B_data_out_reg = DFFE(UB1_q_b[7]_PORT_B_data_out, UB1_q_b[7]_clock_1, , , ); UB1_q_b[15] = UB1_q_b[7]_PORT_B_data_out_reg[1]; --E1_nx355 is ni2io_wt:wt_ni|nx355 --operation mode is normal E1_nx355 = V1_request_47 # V1_request_48 & (E1_or_mask_7) # !V1_request_48 & !E1_NOT_sel_p_3; --E1_nx356 is ni2io_wt:wt_ni|nx356 --operation mode is normal E1_nx356 = V1_request_48 & (SB1_Q_7) # !V1_request_48 & SB2_Q_7 # !V1_request_47; --L1_RDATA_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_7 --operation mode is normal L1_RDATA_7 = L1_nx873 # L1_nx874 # L1_nx875 # L1_nx876; --F1_RDATA_7 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_7 --operation mode is normal F1_RDATA_7 = F1_nx821 # F1_nx822 # V1_request_46 & F1_config_7; --K1_RDATA_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_7 --operation mode is normal K1_RDATA_7 = K1_nx956 # K1_nx957 # K1_nx958 # K1_nx959; --J1_RDATA_7 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_7 --operation mode is normal J1_RDATA_7 = !V1_request_38 & Q1_q_b[7]; --SB1_Q_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_6 --operation mode is arithmetic SB1_Q_6_carry_eqn = SB1_Q_nx40; SB1_Q_6_lut_out = SB1_Q_6 $ (!SB1_Q_6_carry_eqn); SB1_Q_6 = DFFEAS(SB1_Q_6_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx44 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx44 --operation mode is arithmetic SB1_Q_nx44 = CARRY(SB1_Q_6 & (!SB1_Q_nx40)); --L1_nx877 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx877 --operation mode is normal L1_nx877 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_6) # !V1_request_48 & L1_adc_last_0_6); --L1_nx878 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx878 --operation mode is normal L1_nx878 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_6) # !V1_request_48 & L1_adc_last_4_6); --L1_nx879 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx879 --operation mode is normal L1_nx879 = V1_request_46 & !V1_request_47 & L1_cfr_6; --L1_nx880 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx880 --operation mode is normal L1_nx880 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_6 # !V1_request_48 & (!L1_NOT_climits_a_6)); --F1_config_6 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|config_6 --operation mode is normal F1_config_6_lut_out = V1_request_25; F1_config_6 = DFFEAS(F1_config_6_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx429, , , , ); --F1_nx823 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx823 --operation mode is normal F1_nx823 = F1_bytes2send_38 & (F1_a_3 # F1_bytes_rcvd_38 & F1_nx787) # !F1_bytes2send_38 & F1_bytes_rcvd_38 & (F1_nx787); --F1_nx824 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx824 --operation mode is normal F1_nx824 = F1_bytes2send_6 & (F1_a_1 # F1_bytes_rcvd_6 & F1_nx785) # !F1_bytes2send_6 & F1_bytes_rcvd_6 & (F1_nx785); --K1_nx960 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx960 --operation mode is normal K1_nx960 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_6) # !V1_request_48 & K1_adc_last_0_6); --K1_nx961 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx961 --operation mode is normal K1_nx961 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_6) # !V1_request_48 & K1_adc_last_4_6); --K1_nx962 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx962 --operation mode is normal K1_nx962 = V1_request_46 & !V1_request_47 & K1_cfr_6; --K1_nx963 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx963 --operation mode is normal K1_nx963 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_6 # !V1_request_48 & (!K1_NOT_climits_a_6)); --Q1_q_b[6] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[6] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[6]_PORT_A_data_in = J1_wdata_ram_6; Q1_q_b[6]_PORT_A_data_in_reg = DFFE(Q1_q_b[6]_PORT_A_data_in, Q1_q_b[6]_clock_0, , , Q1_q_b[6]_clock_enable_0); Q1_q_b[6]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[6]_PORT_A_address_reg = DFFE(Q1_q_b[6]_PORT_A_address, Q1_q_b[6]_clock_0, , , Q1_q_b[6]_clock_enable_0); Q1_q_b[6]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[6]_PORT_B_address_reg = DFFE(Q1_q_b[6]_PORT_B_address, Q1_q_b[6]_clock_1, , , ); Q1_q_b[6]_PORT_A_write_enable = VCC; Q1_q_b[6]_PORT_A_write_enable_reg = DFFE(Q1_q_b[6]_PORT_A_write_enable, Q1_q_b[6]_clock_0, , , Q1_q_b[6]_clock_enable_0); Q1_q_b[6]_PORT_B_read_enable = VCC; Q1_q_b[6]_PORT_B_read_enable_reg = DFFE(Q1_q_b[6]_PORT_B_read_enable, Q1_q_b[6]_clock_1, , , ); Q1_q_b[6]_clock_0 = S1__clk1; Q1_q_b[6]_clock_1 = S1__clk1; Q1_q_b[6]_clock_enable_0 = J1_sm; Q1_q_b[6]_PORT_B_data_out = MEMORY(Q1_q_b[6]_PORT_A_data_in_reg, , Q1_q_b[6]_PORT_A_address_reg, Q1_q_b[6]_PORT_B_address_reg, Q1_q_b[6]_PORT_A_write_enable_reg, Q1_q_b[6]_PORT_B_read_enable_reg, , , Q1_q_b[6]_clock_0, Q1_q_b[6]_clock_1, Q1_q_b[6]_clock_enable_0, , , ); Q1_q_b[6]_PORT_B_data_out_reg = DFFE(Q1_q_b[6]_PORT_B_data_out, Q1_q_b[6]_clock_1, , , ); Q1_q_b[6] = Q1_q_b[6]_PORT_B_data_out_reg[0]; --Q1_q_b[22] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[22] Q1_q_b[6]_PORT_A_data_in = J1_wdata_ram_6; Q1_q_b[6]_PORT_A_data_in_reg = DFFE(Q1_q_b[6]_PORT_A_data_in, Q1_q_b[6]_clock_0, , , Q1_q_b[6]_clock_enable_0); Q1_q_b[6]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[6]_PORT_A_address_reg = DFFE(Q1_q_b[6]_PORT_A_address, Q1_q_b[6]_clock_0, , , Q1_q_b[6]_clock_enable_0); Q1_q_b[6]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[6]_PORT_B_address_reg = DFFE(Q1_q_b[6]_PORT_B_address, Q1_q_b[6]_clock_1, , , ); Q1_q_b[6]_PORT_A_write_enable = VCC; Q1_q_b[6]_PORT_A_write_enable_reg = DFFE(Q1_q_b[6]_PORT_A_write_enable, Q1_q_b[6]_clock_0, , , Q1_q_b[6]_clock_enable_0); Q1_q_b[6]_PORT_B_read_enable = VCC; Q1_q_b[6]_PORT_B_read_enable_reg = DFFE(Q1_q_b[6]_PORT_B_read_enable, Q1_q_b[6]_clock_1, , , ); Q1_q_b[6]_clock_0 = S1__clk1; Q1_q_b[6]_clock_1 = S1__clk1; Q1_q_b[6]_clock_enable_0 = J1_sm; Q1_q_b[6]_PORT_B_data_out = MEMORY(Q1_q_b[6]_PORT_A_data_in_reg, , Q1_q_b[6]_PORT_A_address_reg, Q1_q_b[6]_PORT_B_address_reg, Q1_q_b[6]_PORT_A_write_enable_reg, Q1_q_b[6]_PORT_B_read_enable_reg, , , Q1_q_b[6]_clock_0, Q1_q_b[6]_clock_1, Q1_q_b[6]_clock_enable_0, , , ); Q1_q_b[6]_PORT_B_data_out_reg = DFFE(Q1_q_b[6]_PORT_B_data_out, Q1_q_b[6]_clock_1, , , ); Q1_q_b[22] = Q1_q_b[6]_PORT_B_data_out_reg[1]; --L1_adc_last_0_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_5 --operation mode is normal L1_adc_last_0_5_lut_out = R2_RDATA_5; L1_adc_last_0_5 = DFFEAS(L1_adc_last_0_5_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_5 --operation mode is normal L1_adc_last_2_5_lut_out = R2_RDATA_5; L1_adc_last_2_5 = DFFEAS(L1_adc_last_2_5_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_5 --operation mode is normal L1_adc_last_4_5_lut_out = R2_RDATA_5; L1_adc_last_4_5 = DFFEAS(L1_adc_last_4_5_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_5 --operation mode is normal L1_adc_last_6_5_lut_out = R2_RDATA_5; L1_adc_last_6_5 = DFFEAS(L1_adc_last_6_5_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_5 --operation mode is normal L1_NOT_climits_d_5_lut_out = !V1_request_26; L1_NOT_climits_d_5 = DFFEAS(L1_NOT_climits_d_5_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_5 --operation mode is normal L1_NOT_climits_a_5_lut_out = !V1_request_26; L1_NOT_climits_a_5 = DFFEAS(L1_NOT_climits_a_5_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_37 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_37 --operation mode is normal F1_bytes_rcvd_37_lut_out = F1_nx2227; F1_bytes_rcvd_37 = DFFEAS(F1_bytes_rcvd_37_lut_out, S1__clk1, VCC, , F1_NOT_nx2121, , , , ); --F1_bytes_rcvd_5 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_5 --operation mode is normal F1_bytes_rcvd_5_lut_out = F1_nx2227; F1_bytes_rcvd_5 = DFFEAS(F1_bytes_rcvd_5_lut_out, S1__clk1, VCC, , F1_NOT_nx2249, , , , ); --K1_adc_last_0_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_5 --operation mode is normal K1_adc_last_0_5_lut_out = R1_RDATA_5; K1_adc_last_0_5 = DFFEAS(K1_adc_last_0_5_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_5 --operation mode is normal K1_adc_last_2_5_lut_out = R1_RDATA_5; K1_adc_last_2_5 = DFFEAS(K1_adc_last_2_5_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_5 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_5 --operation mode is normal J1_wdata_ram_5_lut_out = PAADC_D[5]; J1_wdata_ram_5 = DFFEAS(J1_wdata_ram_5_lut_out, S1__clk1, VCC, , , , , , ); --R2_RDATA_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_4 --operation mode is normal R2_RDATA_4_lut_out = R2_RDATA_3; R2_RDATA_4 = DFFEAS(R2_RDATA_4_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --F1_nx2231 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2231 --operation mode is normal F1_nx2231 = F1_byte_recv_4 & (!F1_iword2send_7 # !F1_sm_top_1); --F1_bytes_rcvd_44 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_44 --operation mode is normal F1_bytes_rcvd_44 = DFFEAS(F1_nx2231, S1__clk1, VCC, , F1_NOT_nx2089, , , , ); --F1_byte_recv_3 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_recv_3 --operation mode is normal F1_byte_recv_3_lut_out = F1_byte_recv_2; F1_byte_recv_3 = DFFEAS(F1_byte_recv_3_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2793, , , , ); --AB2_ob_data_18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_18 --operation mode is normal AB2_ob_data_18_lut_out = AB2_ob_data_17; AB2_ob_data_18 = DFFEAS(AB2_ob_data_18_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_18, , , AB2_a_2); --LB2_d_to_dll_19 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_19 --operation mode is normal LB2_d_to_dll_19 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_19 # !DB4_data_out_0 & (T1_reply_19)); --AB1_ob_data_17 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_17 --operation mode is normal AB1_ob_data_17_lut_out = AB1_ob_data_16; AB1_ob_data_17 = DFFEAS(AB1_ob_data_17_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_17, , , AB1_a_2); --LB1_d_to_dll_18 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_18 --operation mode is normal LB1_d_to_dll_18 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_18 # !DB3_data_out_0 & (T1_reply_18)); --T1_reply_19 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_19 --operation mode is normal T1_reply_19 = V1_request_19 & (T1_a_0_dup_53 # T1_read_data_12 & !T1_ix34_ix30_nx12) # !V1_request_19 & T1_read_data_12 & (!T1_ix34_ix30_nx12); --T1_read_data_11 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_11 --operation mode is normal T1_read_data_11_lut_out = H1_bus_dout_11; T1_read_data_11 = DFFEAS(T1_read_data_11_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_10 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_10 --operation mode is normal H1_bus_dout_10 = H1_nx191 # H1_nx192 # E1_rdata_10 & H1_sel_0; --E1_rdata_9 is ni2io_wt:wt_ni|rdata_9 --operation mode is normal E1_rdata_9 = V1_request_37 & UB2_q_b[1] # !V1_request_37 & (E1_nx351 & E1_nx352); --H1_nx193 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx193 --operation mode is normal H1_nx193 = L1_RDATA_9 & (H1_ce_sc_adc # F1_RDATA_9 & H1_ce_dds) # !L1_RDATA_9 & F1_RDATA_9 & H1_ce_dds; --H1_nx194 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx194 --operation mode is normal H1_nx194 = K1_RDATA_9 & (H1_ce_psply_adc # J1_RDATA_9 & H1_ce_pasa_adc) # !K1_RDATA_9 & J1_RDATA_9 & (H1_ce_pasa_adc); --UB2_q_b[0] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[0] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB2_q_b[0]_PORT_A_data_in = RB2_dout_0; UB2_q_b[0]_PORT_A_data_in_reg = DFFE(UB2_q_b[0]_PORT_A_data_in, UB2_q_b[0]_clock_0, UB2_q_b[0]_clear_0, , UB2_q_b[0]_clock_enable_0); UB2_q_b[0]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[0]_PORT_A_address_reg = DFFE(UB2_q_b[0]_PORT_A_address, UB2_q_b[0]_clock_0, UB2_q_b[0]_clear_0, , UB2_q_b[0]_clock_enable_0); UB2_q_b[0]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[0]_PORT_B_address_reg = DFFE(UB2_q_b[0]_PORT_B_address, UB2_q_b[0]_clock_1, , , ); UB2_q_b[0]_PORT_A_write_enable = VCC; UB2_q_b[0]_PORT_A_write_enable_reg = DFFE(UB2_q_b[0]_PORT_A_write_enable, UB2_q_b[0]_clock_0, UB2_q_b[0]_clear_0, , UB2_q_b[0]_clock_enable_0); UB2_q_b[0]_PORT_B_read_enable = VCC; UB2_q_b[0]_PORT_B_read_enable_reg = DFFE(UB2_q_b[0]_PORT_B_read_enable, UB2_q_b[0]_clock_1, , , ); UB2_q_b[0]_clock_0 = WT_STR; UB2_q_b[0]_clock_1 = S1__clk1; UB2_q_b[0]_clock_enable_0 = PB2_we_p; UB2_q_b[0]_clear_0 = !E1_NOT_clear; UB2_q_b[0]_PORT_B_data_out = MEMORY(UB2_q_b[0]_PORT_A_data_in_reg, , UB2_q_b[0]_PORT_A_address_reg, UB2_q_b[0]_PORT_B_address_reg, UB2_q_b[0]_PORT_A_write_enable_reg, UB2_q_b[0]_PORT_B_read_enable_reg, , , UB2_q_b[0]_clock_0, UB2_q_b[0]_clock_1, UB2_q_b[0]_clock_enable_0, , UB2_q_b[0]_clear_0, ); UB2_q_b[0]_PORT_B_data_out_reg = DFFE(UB2_q_b[0]_PORT_B_data_out, UB2_q_b[0]_clock_1, , , ); UB2_q_b[0] = UB2_q_b[0]_PORT_B_data_out_reg[0]; --UB2_q_b[8] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[8] UB2_q_b[0]_PORT_A_data_in = RB2_dout_0; UB2_q_b[0]_PORT_A_data_in_reg = DFFE(UB2_q_b[0]_PORT_A_data_in, UB2_q_b[0]_clock_0, UB2_q_b[0]_clear_0, , UB2_q_b[0]_clock_enable_0); UB2_q_b[0]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[0]_PORT_A_address_reg = DFFE(UB2_q_b[0]_PORT_A_address, UB2_q_b[0]_clock_0, UB2_q_b[0]_clear_0, , UB2_q_b[0]_clock_enable_0); UB2_q_b[0]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[0]_PORT_B_address_reg = DFFE(UB2_q_b[0]_PORT_B_address, UB2_q_b[0]_clock_1, , , ); UB2_q_b[0]_PORT_A_write_enable = VCC; UB2_q_b[0]_PORT_A_write_enable_reg = DFFE(UB2_q_b[0]_PORT_A_write_enable, UB2_q_b[0]_clock_0, UB2_q_b[0]_clear_0, , UB2_q_b[0]_clock_enable_0); UB2_q_b[0]_PORT_B_read_enable = VCC; UB2_q_b[0]_PORT_B_read_enable_reg = DFFE(UB2_q_b[0]_PORT_B_read_enable, UB2_q_b[0]_clock_1, , , ); UB2_q_b[0]_clock_0 = WT_STR; UB2_q_b[0]_clock_1 = S1__clk1; UB2_q_b[0]_clock_enable_0 = PB2_we_p; UB2_q_b[0]_clear_0 = !E1_NOT_clear; UB2_q_b[0]_PORT_B_data_out = MEMORY(UB2_q_b[0]_PORT_A_data_in_reg, , UB2_q_b[0]_PORT_A_address_reg, UB2_q_b[0]_PORT_B_address_reg, UB2_q_b[0]_PORT_A_write_enable_reg, UB2_q_b[0]_PORT_B_read_enable_reg, , , UB2_q_b[0]_clock_0, UB2_q_b[0]_clock_1, UB2_q_b[0]_clock_enable_0, , UB2_q_b[0]_clear_0, ); UB2_q_b[0]_PORT_B_data_out_reg = DFFE(UB2_q_b[0]_PORT_B_data_out, UB2_q_b[0]_clock_1, , , ); UB2_q_b[8] = UB2_q_b[0]_PORT_B_data_out_reg[1]; --E1_nx353 is ni2io_wt:wt_ni|nx353 --operation mode is normal E1_nx353 = V1_request_47 # V1_request_48 & E1_or_mask_8 # !V1_request_48 & (!E1_NOT_rst_inv); --E1_nx354 is ni2io_wt:wt_ni|nx354 --operation mode is normal E1_nx354 = V1_request_48 & (SB1_Q_8) # !V1_request_48 & SB2_Q_8 # !V1_request_47; --L1_RDATA_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_8 --operation mode is normal L1_RDATA_8 = L1_nx869 # L1_nx870 # L1_nx871 # L1_nx872; --F1_RDATA_8 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_8 --operation mode is normal F1_RDATA_8 = F1_nx820 # F1_nx851 # F1_bytes2send_40 & F1_a_3; --K1_RDATA_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_8 --operation mode is normal K1_RDATA_8 = K1_nx952 # K1_nx953 # K1_nx954 # K1_nx955; --J1_RDATA_8 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_8 --operation mode is normal J1_RDATA_8 = !V1_request_38 & Q1_q_b[8]; --SB1_Q_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_7 --operation mode is arithmetic SB1_Q_7_carry_eqn = SB1_Q_nx44; SB1_Q_7_lut_out = SB1_Q_7 $ (SB1_Q_7_carry_eqn); SB1_Q_7 = DFFEAS(SB1_Q_7_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx48 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx48 --operation mode is arithmetic SB1_Q_nx48 = CARRY(!SB1_Q_nx44 # !SB1_Q_7); --L1_nx873 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx873 --operation mode is normal L1_nx873 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_7) # !V1_request_48 & L1_adc_last_0_7); --L1_nx874 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx874 --operation mode is normal L1_nx874 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_7) # !V1_request_48 & L1_adc_last_4_7); --L1_nx875 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx875 --operation mode is normal L1_nx875 = V1_request_46 & !V1_request_47 & L1_cfr_7; --L1_nx876 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx876 --operation mode is normal L1_nx876 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_7 # !V1_request_48 & (!L1_NOT_climits_a_7)); --F1_config_7 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|config_7 --operation mode is normal F1_config_7_lut_out = V1_request_24; F1_config_7 = DFFEAS(F1_config_7_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx429, , , , ); --F1_nx821 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx821 --operation mode is normal F1_nx821 = F1_bytes2send_39 & (F1_a_3 # F1_bytes_rcvd_39 & F1_nx787) # !F1_bytes2send_39 & F1_bytes_rcvd_39 & (F1_nx787); --F1_nx822 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx822 --operation mode is normal F1_nx822 = F1_bytes2send_7 & (F1_a_1 # F1_bytes_rcvd_7 & F1_nx785) # !F1_bytes2send_7 & F1_bytes_rcvd_7 & (F1_nx785); --K1_nx956 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx956 --operation mode is normal K1_nx956 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_7) # !V1_request_48 & K1_adc_last_0_7); --K1_nx957 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx957 --operation mode is normal K1_nx957 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_7) # !V1_request_48 & K1_adc_last_4_7); --K1_nx958 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx958 --operation mode is normal K1_nx958 = V1_request_46 & !V1_request_47 & K1_cfr_7; --K1_nx959 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx959 --operation mode is normal K1_nx959 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_7 # !V1_request_48 & (!K1_NOT_climits_a_7)); --Q1_q_b[7] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[7] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[7]_PORT_A_data_in = J1_wdata_ram_7; Q1_q_b[7]_PORT_A_data_in_reg = DFFE(Q1_q_b[7]_PORT_A_data_in, Q1_q_b[7]_clock_0, , , Q1_q_b[7]_clock_enable_0); Q1_q_b[7]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[7]_PORT_A_address_reg = DFFE(Q1_q_b[7]_PORT_A_address, Q1_q_b[7]_clock_0, , , Q1_q_b[7]_clock_enable_0); Q1_q_b[7]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[7]_PORT_B_address_reg = DFFE(Q1_q_b[7]_PORT_B_address, Q1_q_b[7]_clock_1, , , ); Q1_q_b[7]_PORT_A_write_enable = VCC; Q1_q_b[7]_PORT_A_write_enable_reg = DFFE(Q1_q_b[7]_PORT_A_write_enable, Q1_q_b[7]_clock_0, , , Q1_q_b[7]_clock_enable_0); Q1_q_b[7]_PORT_B_read_enable = VCC; Q1_q_b[7]_PORT_B_read_enable_reg = DFFE(Q1_q_b[7]_PORT_B_read_enable, Q1_q_b[7]_clock_1, , , ); Q1_q_b[7]_clock_0 = S1__clk1; Q1_q_b[7]_clock_1 = S1__clk1; Q1_q_b[7]_clock_enable_0 = J1_sm; Q1_q_b[7]_PORT_B_data_out = MEMORY(Q1_q_b[7]_PORT_A_data_in_reg, , Q1_q_b[7]_PORT_A_address_reg, Q1_q_b[7]_PORT_B_address_reg, Q1_q_b[7]_PORT_A_write_enable_reg, Q1_q_b[7]_PORT_B_read_enable_reg, , , Q1_q_b[7]_clock_0, Q1_q_b[7]_clock_1, Q1_q_b[7]_clock_enable_0, , , ); Q1_q_b[7]_PORT_B_data_out_reg = DFFE(Q1_q_b[7]_PORT_B_data_out, Q1_q_b[7]_clock_1, , , ); Q1_q_b[7] = Q1_q_b[7]_PORT_B_data_out_reg[0]; --Q1_q_b[23] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[23] Q1_q_b[7]_PORT_A_data_in = J1_wdata_ram_7; Q1_q_b[7]_PORT_A_data_in_reg = DFFE(Q1_q_b[7]_PORT_A_data_in, Q1_q_b[7]_clock_0, , , Q1_q_b[7]_clock_enable_0); Q1_q_b[7]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[7]_PORT_A_address_reg = DFFE(Q1_q_b[7]_PORT_A_address, Q1_q_b[7]_clock_0, , , Q1_q_b[7]_clock_enable_0); Q1_q_b[7]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[7]_PORT_B_address_reg = DFFE(Q1_q_b[7]_PORT_B_address, Q1_q_b[7]_clock_1, , , ); Q1_q_b[7]_PORT_A_write_enable = VCC; Q1_q_b[7]_PORT_A_write_enable_reg = DFFE(Q1_q_b[7]_PORT_A_write_enable, Q1_q_b[7]_clock_0, , , Q1_q_b[7]_clock_enable_0); Q1_q_b[7]_PORT_B_read_enable = VCC; Q1_q_b[7]_PORT_B_read_enable_reg = DFFE(Q1_q_b[7]_PORT_B_read_enable, Q1_q_b[7]_clock_1, , , ); Q1_q_b[7]_clock_0 = S1__clk1; Q1_q_b[7]_clock_1 = S1__clk1; Q1_q_b[7]_clock_enable_0 = J1_sm; Q1_q_b[7]_PORT_B_data_out = MEMORY(Q1_q_b[7]_PORT_A_data_in_reg, , Q1_q_b[7]_PORT_A_address_reg, Q1_q_b[7]_PORT_B_address_reg, Q1_q_b[7]_PORT_A_write_enable_reg, Q1_q_b[7]_PORT_B_read_enable_reg, , , Q1_q_b[7]_clock_0, Q1_q_b[7]_clock_1, Q1_q_b[7]_clock_enable_0, , , ); Q1_q_b[7]_PORT_B_data_out_reg = DFFE(Q1_q_b[7]_PORT_B_data_out, Q1_q_b[7]_clock_1, , , ); Q1_q_b[23] = Q1_q_b[7]_PORT_B_data_out_reg[1]; --L1_adc_last_0_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_6 --operation mode is normal L1_adc_last_0_6_lut_out = R2_RDATA_6; L1_adc_last_0_6 = DFFEAS(L1_adc_last_0_6_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_6 --operation mode is normal L1_adc_last_2_6_lut_out = R2_RDATA_6; L1_adc_last_2_6 = DFFEAS(L1_adc_last_2_6_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_6 --operation mode is normal L1_adc_last_4_6_lut_out = R2_RDATA_6; L1_adc_last_4_6 = DFFEAS(L1_adc_last_4_6_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_6 --operation mode is normal L1_adc_last_6_6_lut_out = R2_RDATA_6; L1_adc_last_6_6 = DFFEAS(L1_adc_last_6_6_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_6 --operation mode is normal L1_NOT_climits_d_6_lut_out = !V1_request_25; L1_NOT_climits_d_6 = DFFEAS(L1_NOT_climits_d_6_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_6 --operation mode is normal L1_NOT_climits_a_6_lut_out = !V1_request_25; L1_NOT_climits_a_6 = DFFEAS(L1_NOT_climits_a_6_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_38 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_38 --operation mode is normal F1_bytes_rcvd_38_lut_out = F1_nx2223; F1_bytes_rcvd_38 = DFFEAS(F1_bytes_rcvd_38_lut_out, S1__clk1, VCC, , F1_NOT_nx2121, , , , ); --F1_bytes_rcvd_6 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_6 --operation mode is normal F1_bytes_rcvd_6_lut_out = F1_nx2223; F1_bytes_rcvd_6 = DFFEAS(F1_bytes_rcvd_6_lut_out, S1__clk1, VCC, , F1_NOT_nx2249, , , , ); --K1_adc_last_0_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_6 --operation mode is normal K1_adc_last_0_6_lut_out = R1_RDATA_6; K1_adc_last_0_6 = DFFEAS(K1_adc_last_0_6_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_6 --operation mode is normal K1_adc_last_2_6_lut_out = R1_RDATA_6; K1_adc_last_2_6 = DFFEAS(K1_adc_last_2_6_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_6 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_6 --operation mode is normal J1_wdata_ram_6_lut_out = PAADC_D[6]; J1_wdata_ram_6 = DFFEAS(J1_wdata_ram_6_lut_out, S1__clk1, VCC, , , , , , ); --R2_RDATA_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_5 --operation mode is normal R2_RDATA_5_lut_out = R2_RDATA_4; R2_RDATA_5 = DFFEAS(R2_RDATA_5_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --F1_nx2227 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2227 --operation mode is normal F1_nx2227 = F1_byte_recv_5 & (!F1_iword2send_7 # !F1_sm_top_1); --F1_bytes_rcvd_45 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_45 --operation mode is normal F1_bytes_rcvd_45 = DFFEAS(F1_nx2227, S1__clk1, VCC, , F1_NOT_nx2089, , , , ); --F1_byte_recv_4 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_recv_4 --operation mode is normal F1_byte_recv_4_lut_out = F1_byte_recv_3; F1_byte_recv_4 = DFFEAS(F1_byte_recv_4_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2793, , , , ); --AB2_ob_data_17 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_17 --operation mode is normal AB2_ob_data_17_lut_out = AB2_ob_data_16; AB2_ob_data_17 = DFFEAS(AB2_ob_data_17_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_17, , , AB2_a_2); --LB2_d_to_dll_18 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_18 --operation mode is normal LB2_d_to_dll_18 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_18 # !DB4_data_out_0 & (T1_reply_18)); --AB1_ob_data_16 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_16 --operation mode is normal AB1_ob_data_16_lut_out = AB1_ob_data_15; AB1_ob_data_16 = DFFEAS(AB1_ob_data_16_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_16, , , AB1_a_2); --LB1_d_to_dll_17 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_17 --operation mode is normal LB1_d_to_dll_17 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_17 # !DB3_data_out_0 & (T1_reply_17)); --T1_reply_18 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_18 --operation mode is normal T1_reply_18 = V1_request_18 & (T1_a_0_dup_53 # T1_read_data_13 & !T1_ix34_ix30_nx12) # !V1_request_18 & T1_read_data_13 & (!T1_ix34_ix30_nx12); --T1_read_data_12 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_12 --operation mode is normal T1_read_data_12_lut_out = H1_bus_dout_12; T1_read_data_12 = DFFEAS(T1_read_data_12_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_11 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_11 --operation mode is normal H1_bus_dout_11 = H1_nx189 # H1_nx190 # E1_rdata_11 & H1_sel_0; --E1_rdata_10 is ni2io_wt:wt_ni|rdata_10 --operation mode is normal E1_rdata_10 = V1_request_37 & UB2_q_b[2] # !V1_request_37 & (E1_nx349 & E1_nx350); --H1_nx191 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx191 --operation mode is normal H1_nx191 = L1_RDATA_10 & (H1_ce_sc_adc # F1_RDATA_10 & H1_ce_dds) # !L1_RDATA_10 & F1_RDATA_10 & H1_ce_dds; --H1_nx192 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx192 --operation mode is normal H1_nx192 = K1_RDATA_10 & (H1_ce_psply_adc # J1_RDATA_10 & H1_ce_pasa_adc) # !K1_RDATA_10 & J1_RDATA_10 & (H1_ce_pasa_adc); --UB2_q_b[1] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[1] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB2_q_b[1]_PORT_A_data_in = RB2_dout_1; UB2_q_b[1]_PORT_A_data_in_reg = DFFE(UB2_q_b[1]_PORT_A_data_in, UB2_q_b[1]_clock_0, UB2_q_b[1]_clear_0, , UB2_q_b[1]_clock_enable_0); UB2_q_b[1]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[1]_PORT_A_address_reg = DFFE(UB2_q_b[1]_PORT_A_address, UB2_q_b[1]_clock_0, UB2_q_b[1]_clear_0, , UB2_q_b[1]_clock_enable_0); UB2_q_b[1]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[1]_PORT_B_address_reg = DFFE(UB2_q_b[1]_PORT_B_address, UB2_q_b[1]_clock_1, , , ); UB2_q_b[1]_PORT_A_write_enable = VCC; UB2_q_b[1]_PORT_A_write_enable_reg = DFFE(UB2_q_b[1]_PORT_A_write_enable, UB2_q_b[1]_clock_0, UB2_q_b[1]_clear_0, , UB2_q_b[1]_clock_enable_0); UB2_q_b[1]_PORT_B_read_enable = VCC; UB2_q_b[1]_PORT_B_read_enable_reg = DFFE(UB2_q_b[1]_PORT_B_read_enable, UB2_q_b[1]_clock_1, , , ); UB2_q_b[1]_clock_0 = WT_STR; UB2_q_b[1]_clock_1 = S1__clk1; UB2_q_b[1]_clock_enable_0 = PB2_we_p; UB2_q_b[1]_clear_0 = !E1_NOT_clear; UB2_q_b[1]_PORT_B_data_out = MEMORY(UB2_q_b[1]_PORT_A_data_in_reg, , UB2_q_b[1]_PORT_A_address_reg, UB2_q_b[1]_PORT_B_address_reg, UB2_q_b[1]_PORT_A_write_enable_reg, UB2_q_b[1]_PORT_B_read_enable_reg, , , UB2_q_b[1]_clock_0, UB2_q_b[1]_clock_1, UB2_q_b[1]_clock_enable_0, , UB2_q_b[1]_clear_0, ); UB2_q_b[1]_PORT_B_data_out_reg = DFFE(UB2_q_b[1]_PORT_B_data_out, UB2_q_b[1]_clock_1, , , ); UB2_q_b[1] = UB2_q_b[1]_PORT_B_data_out_reg[0]; --UB2_q_b[9] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[9] UB2_q_b[1]_PORT_A_data_in = RB2_dout_1; UB2_q_b[1]_PORT_A_data_in_reg = DFFE(UB2_q_b[1]_PORT_A_data_in, UB2_q_b[1]_clock_0, UB2_q_b[1]_clear_0, , UB2_q_b[1]_clock_enable_0); UB2_q_b[1]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[1]_PORT_A_address_reg = DFFE(UB2_q_b[1]_PORT_A_address, UB2_q_b[1]_clock_0, UB2_q_b[1]_clear_0, , UB2_q_b[1]_clock_enable_0); UB2_q_b[1]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[1]_PORT_B_address_reg = DFFE(UB2_q_b[1]_PORT_B_address, UB2_q_b[1]_clock_1, , , ); UB2_q_b[1]_PORT_A_write_enable = VCC; UB2_q_b[1]_PORT_A_write_enable_reg = DFFE(UB2_q_b[1]_PORT_A_write_enable, UB2_q_b[1]_clock_0, UB2_q_b[1]_clear_0, , UB2_q_b[1]_clock_enable_0); UB2_q_b[1]_PORT_B_read_enable = VCC; UB2_q_b[1]_PORT_B_read_enable_reg = DFFE(UB2_q_b[1]_PORT_B_read_enable, UB2_q_b[1]_clock_1, , , ); UB2_q_b[1]_clock_0 = WT_STR; UB2_q_b[1]_clock_1 = S1__clk1; UB2_q_b[1]_clock_enable_0 = PB2_we_p; UB2_q_b[1]_clear_0 = !E1_NOT_clear; UB2_q_b[1]_PORT_B_data_out = MEMORY(UB2_q_b[1]_PORT_A_data_in_reg, , UB2_q_b[1]_PORT_A_address_reg, UB2_q_b[1]_PORT_B_address_reg, UB2_q_b[1]_PORT_A_write_enable_reg, UB2_q_b[1]_PORT_B_read_enable_reg, , , UB2_q_b[1]_clock_0, UB2_q_b[1]_clock_1, UB2_q_b[1]_clock_enable_0, , UB2_q_b[1]_clear_0, ); UB2_q_b[1]_PORT_B_data_out_reg = DFFE(UB2_q_b[1]_PORT_B_data_out, UB2_q_b[1]_clock_1, , , ); UB2_q_b[9] = UB2_q_b[1]_PORT_B_data_out_reg[1]; --E1_nx351 is ni2io_wt:wt_ni|nx351 --operation mode is normal E1_nx351 = V1_request_47 # V1_request_48 & E1_or_mask_9 # !V1_request_48 & (E1_rst_opend); --E1_nx352 is ni2io_wt:wt_ni|nx352 --operation mode is normal E1_nx352 = V1_request_48 & (SB1_Q_9) # !V1_request_48 & SB2_Q_9 # !V1_request_47; --L1_RDATA_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_9 --operation mode is normal L1_RDATA_9 = L1_nx865 # L1_nx866 # L1_nx867 # L1_nx868; --F1_RDATA_9 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_9 --operation mode is normal F1_RDATA_9 = F1_nx819 # F1_nx852 # F1_bytes2send_41 & F1_a_3; --K1_RDATA_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_9 --operation mode is normal K1_RDATA_9 = K1_nx948 # K1_nx949 # K1_nx950 # K1_nx951; --J1_RDATA_9 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_9 --operation mode is normal J1_RDATA_9 = !V1_request_38 & Q1_q_b[9]; --PB2_we_p is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|we_p --operation mode is normal PB2_we_p_lut_out = !PB2_NOT_we_p_r & (PB2_nx48 # PB2_nx49 # PB2_nx50); PB2_we_p = DFFEAS(PB2_we_p_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --RB2_dout_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|dout_0 --operation mode is normal RB2_dout_0 = RB2_modgen_gt_34_nx56 & (RB2_q1pass_0) # !RB2_modgen_gt_34_nx56 & RB2_q1pass_1; --SB4_Q_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_0 --operation mode is arithmetic SB4_Q_0_lut_out = SB4_Q_0 $ PB2_we_p; SB4_Q_0 = DFFEAS(SB4_Q_0_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx10 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx10 --operation mode is arithmetic SB4_Q_nx10 = CARRY(SB4_Q_0 & PB2_we_p); --SB4_Q_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_1 --operation mode is arithmetic SB4_Q_1_carry_eqn = SB4_Q_nx10; SB4_Q_1_lut_out = SB4_Q_1 $ (SB4_Q_1_carry_eqn); SB4_Q_1 = DFFEAS(SB4_Q_1_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx16 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx16 --operation mode is arithmetic SB4_Q_nx16 = CARRY(!SB4_Q_nx10 # !SB4_Q_1); --SB4_Q_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_2 --operation mode is arithmetic SB4_Q_2_carry_eqn = SB4_Q_nx16; SB4_Q_2_lut_out = SB4_Q_2 $ (!SB4_Q_2_carry_eqn); SB4_Q_2 = DFFEAS(SB4_Q_2_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx22 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx22 --operation mode is arithmetic SB4_Q_nx22 = CARRY(SB4_Q_2 & (!SB4_Q_nx16)); --SB4_Q_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_3 --operation mode is arithmetic SB4_Q_3_carry_eqn = SB4_Q_nx22; SB4_Q_3_lut_out = SB4_Q_3 $ (SB4_Q_3_carry_eqn); SB4_Q_3 = DFFEAS(SB4_Q_3_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx28 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx28 --operation mode is arithmetic SB4_Q_nx28 = CARRY(!SB4_Q_nx22 # !SB4_Q_3); --SB4_Q_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_4 --operation mode is arithmetic SB4_Q_4_carry_eqn = SB4_Q_nx28; SB4_Q_4_lut_out = SB4_Q_4 $ (!SB4_Q_4_carry_eqn); SB4_Q_4 = DFFEAS(SB4_Q_4_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx34 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx34 --operation mode is arithmetic SB4_Q_nx34 = CARRY(SB4_Q_4 & (!SB4_Q_nx28)); --SB4_Q_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_5 --operation mode is arithmetic SB4_Q_5_carry_eqn = SB4_Q_nx34; SB4_Q_5_lut_out = SB4_Q_5 $ (SB4_Q_5_carry_eqn); SB4_Q_5 = DFFEAS(SB4_Q_5_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx40 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx40 --operation mode is arithmetic SB4_Q_nx40 = CARRY(!SB4_Q_nx34 # !SB4_Q_5); --SB4_Q_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_6 --operation mode is arithmetic SB4_Q_6_carry_eqn = SB4_Q_nx40; SB4_Q_6_lut_out = SB4_Q_6 $ (!SB4_Q_6_carry_eqn); SB4_Q_6 = DFFEAS(SB4_Q_6_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx44 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx44 --operation mode is arithmetic SB4_Q_nx44 = CARRY(SB4_Q_6 & (!SB4_Q_nx40)); --SB4_Q_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_7 --operation mode is arithmetic SB4_Q_7_carry_eqn = SB4_Q_nx44; SB4_Q_7_lut_out = SB4_Q_7 $ (SB4_Q_7_carry_eqn); SB4_Q_7 = DFFEAS(SB4_Q_7_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx48 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx48 --operation mode is arithmetic SB4_Q_nx48 = CARRY(!SB4_Q_nx44 # !SB4_Q_7); --SB4_Q_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_8 --operation mode is arithmetic SB4_Q_8_carry_eqn = SB4_Q_nx48; SB4_Q_8_lut_out = SB4_Q_8 $ (!SB4_Q_8_carry_eqn); SB4_Q_8 = DFFEAS(SB4_Q_8_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx52 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx52 --operation mode is arithmetic SB4_Q_nx52 = CARRY(SB4_Q_8 & (!SB4_Q_nx48)); --SB4_Q_9 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_9 --operation mode is arithmetic SB4_Q_9_carry_eqn = SB4_Q_nx52; SB4_Q_9_lut_out = SB4_Q_9 $ (SB4_Q_9_carry_eqn); SB4_Q_9 = DFFEAS(SB4_Q_9_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx57 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx57 --operation mode is arithmetic SB4_Q_nx57 = CARRY(!SB4_Q_nx52 # !SB4_Q_9); --SB4_Q_10 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_10 --operation mode is arithmetic SB4_Q_10_carry_eqn = SB4_Q_nx57; SB4_Q_10_lut_out = SB4_Q_10 $ (!SB4_Q_10_carry_eqn); SB4_Q_10 = DFFEAS(SB4_Q_10_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB4_Q_nx61 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_nx61 --operation mode is arithmetic SB4_Q_nx61 = CARRY(SB4_Q_10 & (!SB4_Q_nx57)); --SB4_Q_11 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:wa_p|Q_11 --operation mode is normal SB4_Q_11_carry_eqn = SB4_Q_nx61; SB4_Q_11_lut_out = SB4_Q_11 $ (SB4_Q_11_carry_eqn); SB4_Q_11 = DFFEAS(SB4_Q_11_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_8 --operation mode is arithmetic SB1_Q_8_carry_eqn = SB1_Q_nx48; SB1_Q_8_lut_out = SB1_Q_8 $ (!SB1_Q_8_carry_eqn); SB1_Q_8 = DFFEAS(SB1_Q_8_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx52 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx52 --operation mode is arithmetic SB1_Q_nx52 = CARRY(SB1_Q_8 & (!SB1_Q_nx48)); --L1_nx869 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx869 --operation mode is normal L1_nx869 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_8) # !V1_request_48 & L1_adc_last_0_8); --L1_nx870 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx870 --operation mode is normal L1_nx870 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_8) # !V1_request_48 & L1_adc_last_4_8); --L1_nx871 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx871 --operation mode is normal L1_nx871 = V1_request_46 & !V1_request_47 & L1_cfr_8; --L1_nx872 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx872 --operation mode is normal L1_nx872 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_8 # !V1_request_48 & (!L1_NOT_climits_a_8)); --F1_nx820 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx820 --operation mode is normal F1_nx820 = F1_bytes2send_8 & (F1_a_1 # F1_bytes_rcvd_8 & F1_nx785) # !F1_bytes2send_8 & F1_bytes_rcvd_8 & (F1_nx785); --F1_nx851 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx851 --operation mode is normal F1_nx851 = !V1_request_46 & V1_request_47 & V1_request_48 & F1_bytes_rcvd_40; --K1_nx952 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx952 --operation mode is normal K1_nx952 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_8) # !V1_request_48 & K1_adc_last_0_8); --K1_nx953 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx953 --operation mode is normal K1_nx953 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_8) # !V1_request_48 & K1_adc_last_4_8); --K1_nx954 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx954 --operation mode is normal K1_nx954 = V1_request_46 & !V1_request_47 & K1_cfr_8; --K1_nx955 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx955 --operation mode is normal K1_nx955 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_8 # !V1_request_48 & (!K1_NOT_climits_a_8)); --Q1_q_b[8] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[8] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[8]_PORT_A_data_in = J1_wdata_ram_8; Q1_q_b[8]_PORT_A_data_in_reg = DFFE(Q1_q_b[8]_PORT_A_data_in, Q1_q_b[8]_clock_0, , , Q1_q_b[8]_clock_enable_0); Q1_q_b[8]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[8]_PORT_A_address_reg = DFFE(Q1_q_b[8]_PORT_A_address, Q1_q_b[8]_clock_0, , , Q1_q_b[8]_clock_enable_0); Q1_q_b[8]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[8]_PORT_B_address_reg = DFFE(Q1_q_b[8]_PORT_B_address, Q1_q_b[8]_clock_1, , , ); Q1_q_b[8]_PORT_A_write_enable = VCC; Q1_q_b[8]_PORT_A_write_enable_reg = DFFE(Q1_q_b[8]_PORT_A_write_enable, Q1_q_b[8]_clock_0, , , Q1_q_b[8]_clock_enable_0); Q1_q_b[8]_PORT_B_read_enable = VCC; Q1_q_b[8]_PORT_B_read_enable_reg = DFFE(Q1_q_b[8]_PORT_B_read_enable, Q1_q_b[8]_clock_1, , , ); Q1_q_b[8]_clock_0 = S1__clk1; Q1_q_b[8]_clock_1 = S1__clk1; Q1_q_b[8]_clock_enable_0 = J1_sm; Q1_q_b[8]_PORT_B_data_out = MEMORY(Q1_q_b[8]_PORT_A_data_in_reg, , Q1_q_b[8]_PORT_A_address_reg, Q1_q_b[8]_PORT_B_address_reg, Q1_q_b[8]_PORT_A_write_enable_reg, Q1_q_b[8]_PORT_B_read_enable_reg, , , Q1_q_b[8]_clock_0, Q1_q_b[8]_clock_1, Q1_q_b[8]_clock_enable_0, , , ); Q1_q_b[8]_PORT_B_data_out_reg = DFFE(Q1_q_b[8]_PORT_B_data_out, Q1_q_b[8]_clock_1, , , ); Q1_q_b[8] = Q1_q_b[8]_PORT_B_data_out_reg[0]; --Q1_q_b[24] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[24] Q1_q_b[8]_PORT_A_data_in = J1_wdata_ram_8; Q1_q_b[8]_PORT_A_data_in_reg = DFFE(Q1_q_b[8]_PORT_A_data_in, Q1_q_b[8]_clock_0, , , Q1_q_b[8]_clock_enable_0); Q1_q_b[8]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[8]_PORT_A_address_reg = DFFE(Q1_q_b[8]_PORT_A_address, Q1_q_b[8]_clock_0, , , Q1_q_b[8]_clock_enable_0); Q1_q_b[8]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[8]_PORT_B_address_reg = DFFE(Q1_q_b[8]_PORT_B_address, Q1_q_b[8]_clock_1, , , ); Q1_q_b[8]_PORT_A_write_enable = VCC; Q1_q_b[8]_PORT_A_write_enable_reg = DFFE(Q1_q_b[8]_PORT_A_write_enable, Q1_q_b[8]_clock_0, , , Q1_q_b[8]_clock_enable_0); Q1_q_b[8]_PORT_B_read_enable = VCC; Q1_q_b[8]_PORT_B_read_enable_reg = DFFE(Q1_q_b[8]_PORT_B_read_enable, Q1_q_b[8]_clock_1, , , ); Q1_q_b[8]_clock_0 = S1__clk1; Q1_q_b[8]_clock_1 = S1__clk1; Q1_q_b[8]_clock_enable_0 = J1_sm; Q1_q_b[8]_PORT_B_data_out = MEMORY(Q1_q_b[8]_PORT_A_data_in_reg, , Q1_q_b[8]_PORT_A_address_reg, Q1_q_b[8]_PORT_B_address_reg, Q1_q_b[8]_PORT_A_write_enable_reg, Q1_q_b[8]_PORT_B_read_enable_reg, , , Q1_q_b[8]_clock_0, Q1_q_b[8]_clock_1, Q1_q_b[8]_clock_enable_0, , , ); Q1_q_b[8]_PORT_B_data_out_reg = DFFE(Q1_q_b[8]_PORT_B_data_out, Q1_q_b[8]_clock_1, , , ); Q1_q_b[24] = Q1_q_b[8]_PORT_B_data_out_reg[1]; --L1_adc_last_0_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_7 --operation mode is normal L1_adc_last_0_7_lut_out = R2_RDATA_7; L1_adc_last_0_7 = DFFEAS(L1_adc_last_0_7_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_7 --operation mode is normal L1_adc_last_2_7_lut_out = R2_RDATA_7; L1_adc_last_2_7 = DFFEAS(L1_adc_last_2_7_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_7 --operation mode is normal L1_adc_last_4_7_lut_out = R2_RDATA_7; L1_adc_last_4_7 = DFFEAS(L1_adc_last_4_7_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_7 --operation mode is normal L1_adc_last_6_7_lut_out = R2_RDATA_7; L1_adc_last_6_7 = DFFEAS(L1_adc_last_6_7_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_7 --operation mode is normal L1_NOT_climits_d_7_lut_out = !V1_request_24; L1_NOT_climits_d_7 = DFFEAS(L1_NOT_climits_d_7_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_7 --operation mode is normal L1_NOT_climits_a_7_lut_out = !V1_request_24; L1_NOT_climits_a_7 = DFFEAS(L1_NOT_climits_a_7_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_39 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_39 --operation mode is normal F1_bytes_rcvd_39_lut_out = F1_nx2219; F1_bytes_rcvd_39 = DFFEAS(F1_bytes_rcvd_39_lut_out, S1__clk1, VCC, , F1_NOT_nx2121, , , , ); --F1_bytes_rcvd_7 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_7 --operation mode is normal F1_bytes_rcvd_7_lut_out = F1_nx2219; F1_bytes_rcvd_7 = DFFEAS(F1_bytes_rcvd_7_lut_out, S1__clk1, VCC, , F1_NOT_nx2249, , , , ); --K1_adc_last_0_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_7 --operation mode is normal K1_adc_last_0_7_lut_out = R1_RDATA_7; K1_adc_last_0_7 = DFFEAS(K1_adc_last_0_7_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_7 --operation mode is normal K1_adc_last_2_7_lut_out = R1_RDATA_7; K1_adc_last_2_7 = DFFEAS(K1_adc_last_2_7_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_7 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_7 --operation mode is normal J1_wdata_ram_7_lut_out = PAADC_D[7]; J1_wdata_ram_7 = DFFEAS(J1_wdata_ram_7_lut_out, S1__clk1, VCC, , , , , , ); --R2_RDATA_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_6 --operation mode is normal R2_RDATA_6_lut_out = R2_RDATA_5; R2_RDATA_6 = DFFEAS(R2_RDATA_6_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --F1_nx2223 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2223 --operation mode is normal F1_nx2223 = F1_byte_recv_6 & (!F1_iword2send_7 # !F1_sm_top_1); --F1_bytes_rcvd_46 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_46 --operation mode is normal F1_bytes_rcvd_46 = DFFEAS(F1_nx2223, S1__clk1, VCC, , F1_NOT_nx2089, , , , ); --F1_byte_recv_5 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_recv_5 --operation mode is normal F1_byte_recv_5_lut_out = F1_byte_recv_4; F1_byte_recv_5 = DFFEAS(F1_byte_recv_5_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2793, , , , ); --AB2_ob_data_16 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_16 --operation mode is normal AB2_ob_data_16_lut_out = AB2_ob_data_15; AB2_ob_data_16 = DFFEAS(AB2_ob_data_16_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_16, , , AB2_a_2); --LB2_d_to_dll_17 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_17 --operation mode is normal LB2_d_to_dll_17 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_17 # !DB4_data_out_0 & (T1_reply_17)); --AB1_ob_data_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_15 --operation mode is normal AB1_ob_data_15_lut_out = AB1_ob_data_14; AB1_ob_data_15 = DFFEAS(AB1_ob_data_15_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_15, , , AB1_a_2); --LB1_d_to_dll_16 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_16 --operation mode is normal LB1_d_to_dll_16 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_16 # !DB3_data_out_0 & (T1_reply_16)); --T1_reply_17 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_17 --operation mode is normal T1_reply_17 = V1_request_17 & (T1_a_0_dup_53 # T1_read_data_14 & !T1_ix34_ix30_nx12) # !V1_request_17 & T1_read_data_14 & (!T1_ix34_ix30_nx12); --T1_read_data_13 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_13 --operation mode is normal T1_read_data_13_lut_out = H1_bus_dout_13; T1_read_data_13 = DFFEAS(T1_read_data_13_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_12 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_12 --operation mode is normal H1_bus_dout_12 = H1_nx187 # H1_nx188 # E1_rdata_12 & H1_sel_0; --E1_rdata_11 is ni2io_wt:wt_ni|rdata_11 --operation mode is normal E1_rdata_11 = V1_request_37 & UB2_q_b[3] # !V1_request_37 & (E1_nx323 # E1_nx324); --H1_nx189 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx189 --operation mode is normal H1_nx189 = L1_RDATA_11 & (H1_ce_sc_adc # F1_RDATA_11 & H1_ce_dds) # !L1_RDATA_11 & F1_RDATA_11 & H1_ce_dds; --H1_nx190 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx190 --operation mode is normal H1_nx190 = K1_RDATA_11 & (H1_ce_psply_adc # J1_RDATA_11 & H1_ce_pasa_adc) # !K1_RDATA_11 & J1_RDATA_11 & (H1_ce_pasa_adc); --UB2_q_b[2] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[2] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB2_q_b[2]_PORT_A_data_in = RB2_dout_2; UB2_q_b[2]_PORT_A_data_in_reg = DFFE(UB2_q_b[2]_PORT_A_data_in, UB2_q_b[2]_clock_0, UB2_q_b[2]_clear_0, , UB2_q_b[2]_clock_enable_0); UB2_q_b[2]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[2]_PORT_A_address_reg = DFFE(UB2_q_b[2]_PORT_A_address, UB2_q_b[2]_clock_0, UB2_q_b[2]_clear_0, , UB2_q_b[2]_clock_enable_0); UB2_q_b[2]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[2]_PORT_B_address_reg = DFFE(UB2_q_b[2]_PORT_B_address, UB2_q_b[2]_clock_1, , , ); UB2_q_b[2]_PORT_A_write_enable = VCC; UB2_q_b[2]_PORT_A_write_enable_reg = DFFE(UB2_q_b[2]_PORT_A_write_enable, UB2_q_b[2]_clock_0, UB2_q_b[2]_clear_0, , UB2_q_b[2]_clock_enable_0); UB2_q_b[2]_PORT_B_read_enable = VCC; UB2_q_b[2]_PORT_B_read_enable_reg = DFFE(UB2_q_b[2]_PORT_B_read_enable, UB2_q_b[2]_clock_1, , , ); UB2_q_b[2]_clock_0 = WT_STR; UB2_q_b[2]_clock_1 = S1__clk1; UB2_q_b[2]_clock_enable_0 = PB2_we_p; UB2_q_b[2]_clear_0 = !E1_NOT_clear; UB2_q_b[2]_PORT_B_data_out = MEMORY(UB2_q_b[2]_PORT_A_data_in_reg, , UB2_q_b[2]_PORT_A_address_reg, UB2_q_b[2]_PORT_B_address_reg, UB2_q_b[2]_PORT_A_write_enable_reg, UB2_q_b[2]_PORT_B_read_enable_reg, , , UB2_q_b[2]_clock_0, UB2_q_b[2]_clock_1, UB2_q_b[2]_clock_enable_0, , UB2_q_b[2]_clear_0, ); UB2_q_b[2]_PORT_B_data_out_reg = DFFE(UB2_q_b[2]_PORT_B_data_out, UB2_q_b[2]_clock_1, , , ); UB2_q_b[2] = UB2_q_b[2]_PORT_B_data_out_reg[0]; --UB2_q_b[10] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[10] UB2_q_b[2]_PORT_A_data_in = RB2_dout_2; UB2_q_b[2]_PORT_A_data_in_reg = DFFE(UB2_q_b[2]_PORT_A_data_in, UB2_q_b[2]_clock_0, UB2_q_b[2]_clear_0, , UB2_q_b[2]_clock_enable_0); UB2_q_b[2]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[2]_PORT_A_address_reg = DFFE(UB2_q_b[2]_PORT_A_address, UB2_q_b[2]_clock_0, UB2_q_b[2]_clear_0, , UB2_q_b[2]_clock_enable_0); UB2_q_b[2]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[2]_PORT_B_address_reg = DFFE(UB2_q_b[2]_PORT_B_address, UB2_q_b[2]_clock_1, , , ); UB2_q_b[2]_PORT_A_write_enable = VCC; UB2_q_b[2]_PORT_A_write_enable_reg = DFFE(UB2_q_b[2]_PORT_A_write_enable, UB2_q_b[2]_clock_0, UB2_q_b[2]_clear_0, , UB2_q_b[2]_clock_enable_0); UB2_q_b[2]_PORT_B_read_enable = VCC; UB2_q_b[2]_PORT_B_read_enable_reg = DFFE(UB2_q_b[2]_PORT_B_read_enable, UB2_q_b[2]_clock_1, , , ); UB2_q_b[2]_clock_0 = WT_STR; UB2_q_b[2]_clock_1 = S1__clk1; UB2_q_b[2]_clock_enable_0 = PB2_we_p; UB2_q_b[2]_clear_0 = !E1_NOT_clear; UB2_q_b[2]_PORT_B_data_out = MEMORY(UB2_q_b[2]_PORT_A_data_in_reg, , UB2_q_b[2]_PORT_A_address_reg, UB2_q_b[2]_PORT_B_address_reg, UB2_q_b[2]_PORT_A_write_enable_reg, UB2_q_b[2]_PORT_B_read_enable_reg, , , UB2_q_b[2]_clock_0, UB2_q_b[2]_clock_1, UB2_q_b[2]_clock_enable_0, , UB2_q_b[2]_clear_0, ); UB2_q_b[2]_PORT_B_data_out_reg = DFFE(UB2_q_b[2]_PORT_B_data_out, UB2_q_b[2]_clock_1, , , ); UB2_q_b[10] = UB2_q_b[2]_PORT_B_data_out_reg[1]; --E1_nx349 is ni2io_wt:wt_ni|nx349 --operation mode is normal E1_nx349 = V1_request_47 # V1_request_48 & (!E1_NOT_and_mask_0) # !V1_request_48 & A1L601; --E1_nx350 is ni2io_wt:wt_ni|nx350 --operation mode is normal E1_nx350 = V1_request_48 & (SB1_Q_10) # !V1_request_48 & SB2_Q_10 # !V1_request_47; --L1_RDATA_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_10 --operation mode is normal L1_RDATA_10 = L1_nx861 # L1_nx862 # L1_nx863 # L1_nx864; --F1_RDATA_10 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_10 --operation mode is normal F1_RDATA_10 = F1_nx818 # F1_nx853 # F1_bytes2send_42 & F1_a_3; --K1_RDATA_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_10 --operation mode is normal K1_RDATA_10 = K1_nx944 # K1_nx945 # K1_nx946 # K1_nx947; --J1_RDATA_10 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_10 --operation mode is normal J1_RDATA_10 = !V1_request_38 & Q1_q_b[10]; --RB2_dout_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|dout_1 --operation mode is normal RB2_dout_1 = E1_sel_p_1 & (RB2_q1pass_1) # !E1_sel_p_1 & (RB2_nx151 & (RB2_q1pass_1) # !RB2_nx151 & RB2_q1pass_2); --SB1_Q_9 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_9 --operation mode is arithmetic SB1_Q_9_carry_eqn = SB1_Q_nx52; SB1_Q_9_lut_out = SB1_Q_9 $ (SB1_Q_9_carry_eqn); SB1_Q_9 = DFFEAS(SB1_Q_9_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx57 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx57 --operation mode is arithmetic SB1_Q_nx57 = CARRY(!SB1_Q_nx52 # !SB1_Q_9); --L1_nx865 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx865 --operation mode is normal L1_nx865 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_9) # !V1_request_48 & L1_adc_last_0_9); --L1_nx866 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx866 --operation mode is normal L1_nx866 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_9) # !V1_request_48 & L1_adc_last_4_9); --L1_nx867 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx867 --operation mode is normal L1_nx867 = V1_request_46 & !V1_request_47 & L1_cfr_9; --L1_nx868 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx868 --operation mode is normal L1_nx868 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_9 # !V1_request_48 & (!L1_NOT_climits_a_9)); --F1_nx819 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx819 --operation mode is normal F1_nx819 = F1_bytes2send_9 & (F1_a_1 # F1_bytes_rcvd_9 & F1_nx785) # !F1_bytes2send_9 & F1_bytes_rcvd_9 & (F1_nx785); --F1_nx852 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx852 --operation mode is normal F1_nx852 = !V1_request_46 & V1_request_47 & V1_request_48 & F1_bytes_rcvd_41; --K1_nx948 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx948 --operation mode is normal K1_nx948 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_9) # !V1_request_48 & K1_adc_last_0_9); --K1_nx949 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx949 --operation mode is normal K1_nx949 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_9) # !V1_request_48 & K1_adc_last_4_9); --K1_nx950 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx950 --operation mode is normal K1_nx950 = V1_request_46 & !V1_request_47 & K1_cfr_9; --K1_nx951 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx951 --operation mode is normal K1_nx951 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_9 # !V1_request_48 & (!K1_NOT_climits_a_9)); --Q1_q_b[9] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[9] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[9]_PORT_A_data_in = J1_wdata_ram_9; Q1_q_b[9]_PORT_A_data_in_reg = DFFE(Q1_q_b[9]_PORT_A_data_in, Q1_q_b[9]_clock_0, , , Q1_q_b[9]_clock_enable_0); Q1_q_b[9]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[9]_PORT_A_address_reg = DFFE(Q1_q_b[9]_PORT_A_address, Q1_q_b[9]_clock_0, , , Q1_q_b[9]_clock_enable_0); Q1_q_b[9]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[9]_PORT_B_address_reg = DFFE(Q1_q_b[9]_PORT_B_address, Q1_q_b[9]_clock_1, , , ); Q1_q_b[9]_PORT_A_write_enable = VCC; Q1_q_b[9]_PORT_A_write_enable_reg = DFFE(Q1_q_b[9]_PORT_A_write_enable, Q1_q_b[9]_clock_0, , , Q1_q_b[9]_clock_enable_0); Q1_q_b[9]_PORT_B_read_enable = VCC; Q1_q_b[9]_PORT_B_read_enable_reg = DFFE(Q1_q_b[9]_PORT_B_read_enable, Q1_q_b[9]_clock_1, , , ); Q1_q_b[9]_clock_0 = S1__clk1; Q1_q_b[9]_clock_1 = S1__clk1; Q1_q_b[9]_clock_enable_0 = J1_sm; Q1_q_b[9]_PORT_B_data_out = MEMORY(Q1_q_b[9]_PORT_A_data_in_reg, , Q1_q_b[9]_PORT_A_address_reg, Q1_q_b[9]_PORT_B_address_reg, Q1_q_b[9]_PORT_A_write_enable_reg, Q1_q_b[9]_PORT_B_read_enable_reg, , , Q1_q_b[9]_clock_0, Q1_q_b[9]_clock_1, Q1_q_b[9]_clock_enable_0, , , ); Q1_q_b[9]_PORT_B_data_out_reg = DFFE(Q1_q_b[9]_PORT_B_data_out, Q1_q_b[9]_clock_1, , , ); Q1_q_b[9] = Q1_q_b[9]_PORT_B_data_out_reg[0]; --Q1_q_b[25] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[25] Q1_q_b[9]_PORT_A_data_in = J1_wdata_ram_9; Q1_q_b[9]_PORT_A_data_in_reg = DFFE(Q1_q_b[9]_PORT_A_data_in, Q1_q_b[9]_clock_0, , , Q1_q_b[9]_clock_enable_0); Q1_q_b[9]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[9]_PORT_A_address_reg = DFFE(Q1_q_b[9]_PORT_A_address, Q1_q_b[9]_clock_0, , , Q1_q_b[9]_clock_enable_0); Q1_q_b[9]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[9]_PORT_B_address_reg = DFFE(Q1_q_b[9]_PORT_B_address, Q1_q_b[9]_clock_1, , , ); Q1_q_b[9]_PORT_A_write_enable = VCC; Q1_q_b[9]_PORT_A_write_enable_reg = DFFE(Q1_q_b[9]_PORT_A_write_enable, Q1_q_b[9]_clock_0, , , Q1_q_b[9]_clock_enable_0); Q1_q_b[9]_PORT_B_read_enable = VCC; Q1_q_b[9]_PORT_B_read_enable_reg = DFFE(Q1_q_b[9]_PORT_B_read_enable, Q1_q_b[9]_clock_1, , , ); Q1_q_b[9]_clock_0 = S1__clk1; Q1_q_b[9]_clock_1 = S1__clk1; Q1_q_b[9]_clock_enable_0 = J1_sm; Q1_q_b[9]_PORT_B_data_out = MEMORY(Q1_q_b[9]_PORT_A_data_in_reg, , Q1_q_b[9]_PORT_A_address_reg, Q1_q_b[9]_PORT_B_address_reg, Q1_q_b[9]_PORT_A_write_enable_reg, Q1_q_b[9]_PORT_B_read_enable_reg, , , Q1_q_b[9]_clock_0, Q1_q_b[9]_clock_1, Q1_q_b[9]_clock_enable_0, , , ); Q1_q_b[9]_PORT_B_data_out_reg = DFFE(Q1_q_b[9]_PORT_B_data_out, Q1_q_b[9]_clock_1, , , ); Q1_q_b[25] = Q1_q_b[9]_PORT_B_data_out_reg[1]; --PB2_NOT_we_p_r is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|NOT_we_p_r --operation mode is normal PB2_NOT_we_p_r_lut_out = VCC; PB2_NOT_we_p_r = DFFEAS(PB2_NOT_we_p_r_lut_out, WT_STR, E1_NOT_clear, , PB2_NOT_modgen_eq_10_nx44, , , , ); --PB2_nx48 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|nx48 --operation mode is normal PB2_nx48 = SB4_Q_11 # !SB4_Q_8 # !SB4_Q_9 # !SB4_Q_10; --PB2_nx49 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|nx49 --operation mode is normal PB2_nx49 = !SB4_Q_4 # !SB4_Q_5 # !SB4_Q_6 # !SB4_Q_7; --PB2_nx50 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|nx50 --operation mode is normal PB2_nx50 = !SB4_Q_0 # !SB4_Q_1 # !SB4_Q_2 # !SB4_Q_3; --RB2_q1pass_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|q1pass_1 --operation mode is normal RB2_q1pass_1 = E1_sel_s_1 & (PB2_data_1p_m_1) # !E1_sel_s_1 & (RB2_nx152 & (PB2_data_1p_m_1) # !RB2_nx152 & PB2_data_1p_m_2); --RB2_q1pass_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|q1pass_0 --operation mode is normal RB2_q1pass_0 = E1_NOT_sel_s_3 & (RB2_modgen_gt_19_nx42 & (PB2_data_1p_m_0) # !RB2_modgen_gt_19_nx42 & PB2_data_1p_m_1) # !E1_NOT_sel_s_3 & (PB2_data_1p_m_0); --RB2_modgen_gt_34_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|modgen_gt_34_nx56 --operation mode is normal RB2_modgen_gt_34_nx56 = E1_sel_p_2 # E1_sel_p_1 # !E1_NOT_sel_p_0 # !E1_NOT_sel_p_3; --L1_adc_last_0_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_8 --operation mode is normal L1_adc_last_0_8_lut_out = R2_RDATA_8; L1_adc_last_0_8 = DFFEAS(L1_adc_last_0_8_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_8 --operation mode is normal L1_adc_last_2_8_lut_out = R2_RDATA_8; L1_adc_last_2_8 = DFFEAS(L1_adc_last_2_8_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_8 --operation mode is normal L1_adc_last_4_8_lut_out = R2_RDATA_8; L1_adc_last_4_8 = DFFEAS(L1_adc_last_4_8_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_8 --operation mode is normal L1_adc_last_6_8_lut_out = R2_RDATA_8; L1_adc_last_6_8 = DFFEAS(L1_adc_last_6_8_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_8 --operation mode is normal L1_NOT_climits_d_8_lut_out = !V1_request_23; L1_NOT_climits_d_8 = DFFEAS(L1_NOT_climits_d_8_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_8 --operation mode is normal L1_NOT_climits_a_8_lut_out = !V1_request_23; L1_NOT_climits_a_8 = DFFEAS(L1_NOT_climits_a_8_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_8 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_8 --operation mode is normal F1_bytes_rcvd_8_lut_out = F1_nx2247; F1_bytes_rcvd_8 = DFFEAS(F1_bytes_rcvd_8_lut_out, S1__clk1, VCC, , F1_NOT_nx2217, , , , ); --K1_adc_last_0_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_8 --operation mode is normal K1_adc_last_0_8_lut_out = R1_RDATA_8; K1_adc_last_0_8 = DFFEAS(K1_adc_last_0_8_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_8 --operation mode is normal K1_adc_last_2_8_lut_out = R1_RDATA_8; K1_adc_last_2_8 = DFFEAS(K1_adc_last_2_8_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_8 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_8 --operation mode is normal J1_wdata_ram_8_lut_out = PAADC_D[8]; J1_wdata_ram_8 = DFFEAS(J1_wdata_ram_8_lut_out, S1__clk1, VCC, , , , , , ); --R2_RDATA_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_7 --operation mode is normal R2_RDATA_7_lut_out = R2_RDATA_6; R2_RDATA_7 = DFFEAS(R2_RDATA_7_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --F1_nx2219 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx2219 --operation mode is normal F1_nx2219 = F1_byte_recv_7 & (!F1_iword2send_7 # !F1_sm_top_1); --F1_bytes_rcvd_47 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_47 --operation mode is normal F1_bytes_rcvd_47 = DFFEAS(F1_nx2219, S1__clk1, VCC, , F1_NOT_nx2089, , , , ); --F1_byte_recv_6 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_recv_6 --operation mode is normal F1_byte_recv_6_lut_out = F1_byte_recv_5; F1_byte_recv_6 = DFFEAS(F1_byte_recv_6_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2793, , , , ); --AB2_ob_data_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_15 --operation mode is normal AB2_ob_data_15_lut_out = AB2_ob_data_14; AB2_ob_data_15 = DFFEAS(AB2_ob_data_15_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_15, , , AB2_a_2); --LB2_d_to_dll_16 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_16 --operation mode is normal LB2_d_to_dll_16 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_16 # !DB4_data_out_0 & (T1_reply_16)); --AB1_ob_data_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_14 --operation mode is normal AB1_ob_data_14_lut_out = AB1_ob_data_13; AB1_ob_data_14 = DFFEAS(AB1_ob_data_14_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_14, , , AB1_a_2); --LB1_d_to_dll_15 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_15 --operation mode is normal LB1_d_to_dll_15 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_15 # !DB3_data_out_0 & (T1_reply_15)); --T1_reply_16 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_16 --operation mode is normal T1_reply_16 = V1_request_16 & (T1_a_0_dup_53 # T1_read_data_15 & !T1_ix34_ix30_nx12) # !V1_request_16 & T1_read_data_15 & (!T1_ix34_ix30_nx12); --T1_read_data_14 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_14 --operation mode is normal T1_read_data_14_lut_out = H1_bus_dout_14; T1_read_data_14 = DFFEAS(T1_read_data_14_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_13 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_13 --operation mode is normal H1_bus_dout_13 = H1_nx185 # H1_nx186 # E1_rdata_13 & H1_sel_0; --E1_rdata_12 is ni2io_wt:wt_ni|rdata_12 --operation mode is normal E1_rdata_12 = V1_request_37 & UB2_q_b[4] # !V1_request_37 & (E1_nx325 # E1_nx326); --H1_nx187 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx187 --operation mode is normal H1_nx187 = L1_RDATA_12 & (H1_ce_sc_adc # F1_RDATA_12 & H1_ce_dds) # !L1_RDATA_12 & F1_RDATA_12 & H1_ce_dds; --H1_nx188 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx188 --operation mode is normal H1_nx188 = K1_RDATA_12 & (H1_ce_psply_adc # J1_RDATA_12 & H1_ce_pasa_adc) # !K1_RDATA_12 & J1_RDATA_12 & (H1_ce_pasa_adc); --UB2_q_b[3] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[3] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB2_q_b[3]_PORT_A_data_in = RB2_dout_3; UB2_q_b[3]_PORT_A_data_in_reg = DFFE(UB2_q_b[3]_PORT_A_data_in, UB2_q_b[3]_clock_0, UB2_q_b[3]_clear_0, , UB2_q_b[3]_clock_enable_0); UB2_q_b[3]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[3]_PORT_A_address_reg = DFFE(UB2_q_b[3]_PORT_A_address, UB2_q_b[3]_clock_0, UB2_q_b[3]_clear_0, , UB2_q_b[3]_clock_enable_0); UB2_q_b[3]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[3]_PORT_B_address_reg = DFFE(UB2_q_b[3]_PORT_B_address, UB2_q_b[3]_clock_1, , , ); UB2_q_b[3]_PORT_A_write_enable = VCC; UB2_q_b[3]_PORT_A_write_enable_reg = DFFE(UB2_q_b[3]_PORT_A_write_enable, UB2_q_b[3]_clock_0, UB2_q_b[3]_clear_0, , UB2_q_b[3]_clock_enable_0); UB2_q_b[3]_PORT_B_read_enable = VCC; UB2_q_b[3]_PORT_B_read_enable_reg = DFFE(UB2_q_b[3]_PORT_B_read_enable, UB2_q_b[3]_clock_1, , , ); UB2_q_b[3]_clock_0 = WT_STR; UB2_q_b[3]_clock_1 = S1__clk1; UB2_q_b[3]_clock_enable_0 = PB2_we_p; UB2_q_b[3]_clear_0 = !E1_NOT_clear; UB2_q_b[3]_PORT_B_data_out = MEMORY(UB2_q_b[3]_PORT_A_data_in_reg, , UB2_q_b[3]_PORT_A_address_reg, UB2_q_b[3]_PORT_B_address_reg, UB2_q_b[3]_PORT_A_write_enable_reg, UB2_q_b[3]_PORT_B_read_enable_reg, , , UB2_q_b[3]_clock_0, UB2_q_b[3]_clock_1, UB2_q_b[3]_clock_enable_0, , UB2_q_b[3]_clear_0, ); UB2_q_b[3]_PORT_B_data_out_reg = DFFE(UB2_q_b[3]_PORT_B_data_out, UB2_q_b[3]_clock_1, , , ); UB2_q_b[3] = UB2_q_b[3]_PORT_B_data_out_reg[0]; --UB2_q_b[11] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[11] UB2_q_b[3]_PORT_A_data_in = RB2_dout_3; UB2_q_b[3]_PORT_A_data_in_reg = DFFE(UB2_q_b[3]_PORT_A_data_in, UB2_q_b[3]_clock_0, UB2_q_b[3]_clear_0, , UB2_q_b[3]_clock_enable_0); UB2_q_b[3]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[3]_PORT_A_address_reg = DFFE(UB2_q_b[3]_PORT_A_address, UB2_q_b[3]_clock_0, UB2_q_b[3]_clear_0, , UB2_q_b[3]_clock_enable_0); UB2_q_b[3]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[3]_PORT_B_address_reg = DFFE(UB2_q_b[3]_PORT_B_address, UB2_q_b[3]_clock_1, , , ); UB2_q_b[3]_PORT_A_write_enable = VCC; UB2_q_b[3]_PORT_A_write_enable_reg = DFFE(UB2_q_b[3]_PORT_A_write_enable, UB2_q_b[3]_clock_0, UB2_q_b[3]_clear_0, , UB2_q_b[3]_clock_enable_0); UB2_q_b[3]_PORT_B_read_enable = VCC; UB2_q_b[3]_PORT_B_read_enable_reg = DFFE(UB2_q_b[3]_PORT_B_read_enable, UB2_q_b[3]_clock_1, , , ); UB2_q_b[3]_clock_0 = WT_STR; UB2_q_b[3]_clock_1 = S1__clk1; UB2_q_b[3]_clock_enable_0 = PB2_we_p; UB2_q_b[3]_clear_0 = !E1_NOT_clear; UB2_q_b[3]_PORT_B_data_out = MEMORY(UB2_q_b[3]_PORT_A_data_in_reg, , UB2_q_b[3]_PORT_A_address_reg, UB2_q_b[3]_PORT_B_address_reg, UB2_q_b[3]_PORT_A_write_enable_reg, UB2_q_b[3]_PORT_B_read_enable_reg, , , UB2_q_b[3]_clock_0, UB2_q_b[3]_clock_1, UB2_q_b[3]_clock_enable_0, , UB2_q_b[3]_clear_0, ); UB2_q_b[3]_PORT_B_data_out_reg = DFFE(UB2_q_b[3]_PORT_B_data_out, UB2_q_b[3]_clock_1, , , ); UB2_q_b[11] = UB2_q_b[3]_PORT_B_data_out_reg[1]; --E1_nx323 is ni2io_wt:wt_ni|nx323 --operation mode is normal E1_nx323 = !V1_request_47 & V1_request_48 & !E1_NOT_and_mask_1; --E1_nx324 is ni2io_wt:wt_ni|nx324 --operation mode is normal E1_nx324 = V1_request_47 & (V1_request_48 & (SB1_Q_11) # !V1_request_48 & SB2_Q_11); --L1_RDATA_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_11 --operation mode is normal L1_RDATA_11 = L1_nx857 # L1_nx858 # L1_nx859 # L1_nx860; --F1_RDATA_11 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_11 --operation mode is normal F1_RDATA_11 = F1_nx817 # F1_nx854 # F1_bytes2send_43 & F1_a_3; --K1_RDATA_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_11 --operation mode is normal K1_RDATA_11 = K1_nx940 # K1_nx941 # K1_nx942 # K1_nx943; --J1_RDATA_11 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_11 --operation mode is normal J1_RDATA_11 = !V1_request_38 & Q1_q_b[11]; --RB2_dout_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|dout_2 --operation mode is normal RB2_dout_2 = RB2_modgen_gt_30_nx56 & (RB2_q1pass_2) # !RB2_modgen_gt_30_nx56 & RB2_q1pass_3; --SB1_Q_10 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_10 --operation mode is arithmetic SB1_Q_10_carry_eqn = SB1_Q_nx57; SB1_Q_10_lut_out = SB1_Q_10 $ (!SB1_Q_10_carry_eqn); SB1_Q_10 = DFFEAS(SB1_Q_10_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --SB1_Q_nx61 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_nx61 --operation mode is arithmetic SB1_Q_nx61 = CARRY(SB1_Q_10 & (!SB1_Q_nx57)); --L1_nx861 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx861 --operation mode is normal L1_nx861 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_10) # !V1_request_48 & L1_adc_last_0_10); --L1_nx862 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx862 --operation mode is normal L1_nx862 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_10) # !V1_request_48 & L1_adc_last_4_10); --L1_nx863 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx863 --operation mode is normal L1_nx863 = V1_request_46 & !V1_request_47 & L1_cfr_10; --L1_nx864 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx864 --operation mode is normal L1_nx864 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_10 # !V1_request_48 & (!L1_NOT_climits_a_10)); --F1_nx818 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx818 --operation mode is normal F1_nx818 = F1_bytes2send_10 & (F1_a_1 # F1_bytes_rcvd_10 & F1_nx785) # !F1_bytes2send_10 & F1_bytes_rcvd_10 & (F1_nx785); --F1_nx853 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx853 --operation mode is normal F1_nx853 = !V1_request_46 & V1_request_47 & V1_request_48 & F1_bytes_rcvd_42; --K1_nx944 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx944 --operation mode is normal K1_nx944 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_10) # !V1_request_48 & K1_adc_last_0_10); --K1_nx945 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx945 --operation mode is normal K1_nx945 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_10) # !V1_request_48 & K1_adc_last_4_10); --K1_nx946 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx946 --operation mode is normal K1_nx946 = V1_request_46 & !V1_request_47 & K1_cfr_10; --K1_nx947 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx947 --operation mode is normal K1_nx947 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_10 # !V1_request_48 & (!K1_NOT_climits_a_10)); --Q1_q_b[10] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[10] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[10]_PORT_A_data_in = J1_wdata_ram_10; Q1_q_b[10]_PORT_A_data_in_reg = DFFE(Q1_q_b[10]_PORT_A_data_in, Q1_q_b[10]_clock_0, , , Q1_q_b[10]_clock_enable_0); Q1_q_b[10]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[10]_PORT_A_address_reg = DFFE(Q1_q_b[10]_PORT_A_address, Q1_q_b[10]_clock_0, , , Q1_q_b[10]_clock_enable_0); Q1_q_b[10]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[10]_PORT_B_address_reg = DFFE(Q1_q_b[10]_PORT_B_address, Q1_q_b[10]_clock_1, , , ); Q1_q_b[10]_PORT_A_write_enable = VCC; Q1_q_b[10]_PORT_A_write_enable_reg = DFFE(Q1_q_b[10]_PORT_A_write_enable, Q1_q_b[10]_clock_0, , , Q1_q_b[10]_clock_enable_0); Q1_q_b[10]_PORT_B_read_enable = VCC; Q1_q_b[10]_PORT_B_read_enable_reg = DFFE(Q1_q_b[10]_PORT_B_read_enable, Q1_q_b[10]_clock_1, , , ); Q1_q_b[10]_clock_0 = S1__clk1; Q1_q_b[10]_clock_1 = S1__clk1; Q1_q_b[10]_clock_enable_0 = J1_sm; Q1_q_b[10]_PORT_B_data_out = MEMORY(Q1_q_b[10]_PORT_A_data_in_reg, , Q1_q_b[10]_PORT_A_address_reg, Q1_q_b[10]_PORT_B_address_reg, Q1_q_b[10]_PORT_A_write_enable_reg, Q1_q_b[10]_PORT_B_read_enable_reg, , , Q1_q_b[10]_clock_0, Q1_q_b[10]_clock_1, Q1_q_b[10]_clock_enable_0, , , ); Q1_q_b[10]_PORT_B_data_out_reg = DFFE(Q1_q_b[10]_PORT_B_data_out, Q1_q_b[10]_clock_1, , , ); Q1_q_b[10] = Q1_q_b[10]_PORT_B_data_out_reg[0]; --Q1_q_b[26] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[26] Q1_q_b[10]_PORT_A_data_in = J1_wdata_ram_10; Q1_q_b[10]_PORT_A_data_in_reg = DFFE(Q1_q_b[10]_PORT_A_data_in, Q1_q_b[10]_clock_0, , , Q1_q_b[10]_clock_enable_0); Q1_q_b[10]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[10]_PORT_A_address_reg = DFFE(Q1_q_b[10]_PORT_A_address, Q1_q_b[10]_clock_0, , , Q1_q_b[10]_clock_enable_0); Q1_q_b[10]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[10]_PORT_B_address_reg = DFFE(Q1_q_b[10]_PORT_B_address, Q1_q_b[10]_clock_1, , , ); Q1_q_b[10]_PORT_A_write_enable = VCC; Q1_q_b[10]_PORT_A_write_enable_reg = DFFE(Q1_q_b[10]_PORT_A_write_enable, Q1_q_b[10]_clock_0, , , Q1_q_b[10]_clock_enable_0); Q1_q_b[10]_PORT_B_read_enable = VCC; Q1_q_b[10]_PORT_B_read_enable_reg = DFFE(Q1_q_b[10]_PORT_B_read_enable, Q1_q_b[10]_clock_1, , , ); Q1_q_b[10]_clock_0 = S1__clk1; Q1_q_b[10]_clock_1 = S1__clk1; Q1_q_b[10]_clock_enable_0 = J1_sm; Q1_q_b[10]_PORT_B_data_out = MEMORY(Q1_q_b[10]_PORT_A_data_in_reg, , Q1_q_b[10]_PORT_A_address_reg, Q1_q_b[10]_PORT_B_address_reg, Q1_q_b[10]_PORT_A_write_enable_reg, Q1_q_b[10]_PORT_B_read_enable_reg, , , Q1_q_b[10]_clock_0, Q1_q_b[10]_clock_1, Q1_q_b[10]_clock_enable_0, , , ); Q1_q_b[10]_PORT_B_data_out_reg = DFFE(Q1_q_b[10]_PORT_B_data_out, Q1_q_b[10]_clock_1, , , ); Q1_q_b[26] = Q1_q_b[10]_PORT_B_data_out_reg[1]; --RB2_q1pass_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|q1pass_2 --operation mode is normal RB2_q1pass_2 = RB2_modgen_gt_17_nx56 & (PB2_data_1p_m_2) # !RB2_modgen_gt_17_nx56 & PB2_data_1p_m_3; --RB2_nx151 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx151 --operation mode is normal RB2_nx151 = E1_sel_p_2 # !E1_NOT_sel_p_3; --L1_adc_last_0_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_9 --operation mode is normal L1_adc_last_0_9_lut_out = R2_RDATA_9; L1_adc_last_0_9 = DFFEAS(L1_adc_last_0_9_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_9 --operation mode is normal L1_adc_last_2_9_lut_out = R2_RDATA_9; L1_adc_last_2_9 = DFFEAS(L1_adc_last_2_9_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_9 --operation mode is normal L1_adc_last_4_9_lut_out = R2_RDATA_9; L1_adc_last_4_9 = DFFEAS(L1_adc_last_4_9_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_9 --operation mode is normal L1_adc_last_6_9_lut_out = R2_RDATA_9; L1_adc_last_6_9 = DFFEAS(L1_adc_last_6_9_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_9 --operation mode is normal L1_NOT_climits_d_9_lut_out = !V1_request_22; L1_NOT_climits_d_9 = DFFEAS(L1_NOT_climits_d_9_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_9 --operation mode is normal L1_NOT_climits_a_9_lut_out = !V1_request_22; L1_NOT_climits_a_9 = DFFEAS(L1_NOT_climits_a_9_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_9 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_9 --operation mode is normal F1_bytes_rcvd_9_lut_out = F1_nx2243; F1_bytes_rcvd_9 = DFFEAS(F1_bytes_rcvd_9_lut_out, S1__clk1, VCC, , F1_NOT_nx2217, , , , ); --K1_adc_last_0_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_9 --operation mode is normal K1_adc_last_0_9_lut_out = R1_RDATA_9; K1_adc_last_0_9 = DFFEAS(K1_adc_last_0_9_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_9 --operation mode is normal K1_adc_last_2_9_lut_out = R1_RDATA_9; K1_adc_last_2_9 = DFFEAS(K1_adc_last_2_9_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_9 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_9 --operation mode is normal J1_wdata_ram_9_lut_out = PAADC_D[9]; J1_wdata_ram_9 = DFFEAS(J1_wdata_ram_9_lut_out, S1__clk1, VCC, , , , , , ); --PB2_NOT_modgen_eq_10_nx44 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|NOT_modgen_eq_10_nx44 --operation mode is normal PB2_NOT_modgen_eq_10_nx44 = !PB2_nx48 & !PB2_nx49 & !PB2_nx50; --PB2_data_1p_m_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_2 --operation mode is normal PB2_data_1p_m_2 = E1_or_mask_2 # !E1_NOT_and_mask_2 & (E1_NOT_xor_mask_2 $ !TB2_q_2); --PB2_data_1p_m_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_1 --operation mode is normal PB2_data_1p_m_1 = E1_or_mask_1 # !E1_NOT_and_mask_1 & (E1_NOT_xor_mask_1 $ !TB2_q_1); --RB2_nx152 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx152 --operation mode is normal RB2_nx152 = E1_sel_s_2 # !E1_NOT_sel_s_3; --PB2_data_1p_m_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_0 --operation mode is normal PB2_data_1p_m_0 = E1_or_mask_0 # !E1_NOT_and_mask_0 & (E1_NOT_xor_mask_0 $ !TB2_q_0); --RB2_modgen_gt_19_nx42 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|modgen_gt_19_nx42 --operation mode is normal RB2_modgen_gt_19_nx42 = E1_sel_s_2 # E1_sel_s_1 # E1_sel_s_0; --R2_RDATA_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_8 --operation mode is normal R2_RDATA_8_lut_out = R2_RDATA_7; R2_RDATA_8 = DFFEAS(R2_RDATA_8_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --F1_NOT_nx2217 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx2217 --operation mode is normal F1_NOT_nx2217 = F1_nx801 # !F1_byte_counter_2 & F1_byte_counter_1 & F1_nx802; --F1_byte_recv_7 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|byte_recv_7 --operation mode is normal F1_byte_recv_7_lut_out = F1_byte_recv_6; F1_byte_recv_7 = DFFEAS(F1_byte_recv_7_lut_out, S1__clk1, T1_chipRST_n, , F1_NOT_nx2793, , , , ); --AB2_ob_data_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_14 --operation mode is normal AB2_ob_data_14_lut_out = AB2_ob_data_13; AB2_ob_data_14 = DFFEAS(AB2_ob_data_14_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_14, , , AB2_a_2); --LB2_d_to_dll_15 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_15 --operation mode is normal LB2_d_to_dll_15 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_15 # !DB4_data_out_0 & (T1_reply_15)); --AB1_ob_data_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_13 --operation mode is normal AB1_ob_data_13_lut_out = AB1_ob_data_12; AB1_ob_data_13 = DFFEAS(AB1_ob_data_13_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_13, , , AB1_a_2); --LB1_d_to_dll_14 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_14 --operation mode is normal LB1_d_to_dll_14 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_14 # !DB3_data_out_0 & (T1_reply_14)); --T1_reply_15 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_15 --operation mode is normal T1_reply_15 = V1_request_15 & (T1_a_0_dup_53 # T1_read_data_16 & !T1_ix34_ix30_nx12) # !V1_request_15 & T1_read_data_16 & (!T1_ix34_ix30_nx12); --T1_read_data_15 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_15 --operation mode is normal T1_read_data_15_lut_out = H1_bus_dout_15; T1_read_data_15 = DFFEAS(T1_read_data_15_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_14 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_14 --operation mode is normal H1_bus_dout_14 = H1_nx183 # H1_nx184 # E1_rdata_14 & H1_sel_0; --E1_rdata_13 is ni2io_wt:wt_ni|rdata_13 --operation mode is normal E1_rdata_13 = V1_request_37 & UB2_q_b[5] # !V1_request_37 & (E1_nx327 # E1_nx328); --H1_nx185 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx185 --operation mode is normal H1_nx185 = L1_RDATA_13 & (H1_ce_sc_adc # F1_RDATA_13 & H1_ce_dds) # !L1_RDATA_13 & F1_RDATA_13 & H1_ce_dds; --H1_nx186 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx186 --operation mode is normal H1_nx186 = K1_RDATA_13 & (H1_ce_psply_adc # J1_RDATA_13 & H1_ce_pasa_adc) # !K1_RDATA_13 & J1_RDATA_13 & (H1_ce_pasa_adc); --UB2_q_b[4] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[4] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB2_q_b[4]_PORT_A_data_in = RB2_dout_4; UB2_q_b[4]_PORT_A_data_in_reg = DFFE(UB2_q_b[4]_PORT_A_data_in, UB2_q_b[4]_clock_0, UB2_q_b[4]_clear_0, , UB2_q_b[4]_clock_enable_0); UB2_q_b[4]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[4]_PORT_A_address_reg = DFFE(UB2_q_b[4]_PORT_A_address, UB2_q_b[4]_clock_0, UB2_q_b[4]_clear_0, , UB2_q_b[4]_clock_enable_0); UB2_q_b[4]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[4]_PORT_B_address_reg = DFFE(UB2_q_b[4]_PORT_B_address, UB2_q_b[4]_clock_1, , , ); UB2_q_b[4]_PORT_A_write_enable = VCC; UB2_q_b[4]_PORT_A_write_enable_reg = DFFE(UB2_q_b[4]_PORT_A_write_enable, UB2_q_b[4]_clock_0, UB2_q_b[4]_clear_0, , UB2_q_b[4]_clock_enable_0); UB2_q_b[4]_PORT_B_read_enable = VCC; UB2_q_b[4]_PORT_B_read_enable_reg = DFFE(UB2_q_b[4]_PORT_B_read_enable, UB2_q_b[4]_clock_1, , , ); UB2_q_b[4]_clock_0 = WT_STR; UB2_q_b[4]_clock_1 = S1__clk1; UB2_q_b[4]_clock_enable_0 = PB2_we_p; UB2_q_b[4]_clear_0 = !E1_NOT_clear; UB2_q_b[4]_PORT_B_data_out = MEMORY(UB2_q_b[4]_PORT_A_data_in_reg, , UB2_q_b[4]_PORT_A_address_reg, UB2_q_b[4]_PORT_B_address_reg, UB2_q_b[4]_PORT_A_write_enable_reg, UB2_q_b[4]_PORT_B_read_enable_reg, , , UB2_q_b[4]_clock_0, UB2_q_b[4]_clock_1, UB2_q_b[4]_clock_enable_0, , UB2_q_b[4]_clear_0, ); UB2_q_b[4]_PORT_B_data_out_reg = DFFE(UB2_q_b[4]_PORT_B_data_out, UB2_q_b[4]_clock_1, , , ); UB2_q_b[4] = UB2_q_b[4]_PORT_B_data_out_reg[0]; --UB2_q_b[12] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[12] UB2_q_b[4]_PORT_A_data_in = RB2_dout_4; UB2_q_b[4]_PORT_A_data_in_reg = DFFE(UB2_q_b[4]_PORT_A_data_in, UB2_q_b[4]_clock_0, UB2_q_b[4]_clear_0, , UB2_q_b[4]_clock_enable_0); UB2_q_b[4]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[4]_PORT_A_address_reg = DFFE(UB2_q_b[4]_PORT_A_address, UB2_q_b[4]_clock_0, UB2_q_b[4]_clear_0, , UB2_q_b[4]_clock_enable_0); UB2_q_b[4]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[4]_PORT_B_address_reg = DFFE(UB2_q_b[4]_PORT_B_address, UB2_q_b[4]_clock_1, , , ); UB2_q_b[4]_PORT_A_write_enable = VCC; UB2_q_b[4]_PORT_A_write_enable_reg = DFFE(UB2_q_b[4]_PORT_A_write_enable, UB2_q_b[4]_clock_0, UB2_q_b[4]_clear_0, , UB2_q_b[4]_clock_enable_0); UB2_q_b[4]_PORT_B_read_enable = VCC; UB2_q_b[4]_PORT_B_read_enable_reg = DFFE(UB2_q_b[4]_PORT_B_read_enable, UB2_q_b[4]_clock_1, , , ); UB2_q_b[4]_clock_0 = WT_STR; UB2_q_b[4]_clock_1 = S1__clk1; UB2_q_b[4]_clock_enable_0 = PB2_we_p; UB2_q_b[4]_clear_0 = !E1_NOT_clear; UB2_q_b[4]_PORT_B_data_out = MEMORY(UB2_q_b[4]_PORT_A_data_in_reg, , UB2_q_b[4]_PORT_A_address_reg, UB2_q_b[4]_PORT_B_address_reg, UB2_q_b[4]_PORT_A_write_enable_reg, UB2_q_b[4]_PORT_B_read_enable_reg, , , UB2_q_b[4]_clock_0, UB2_q_b[4]_clock_1, UB2_q_b[4]_clock_enable_0, , UB2_q_b[4]_clear_0, ); UB2_q_b[4]_PORT_B_data_out_reg = DFFE(UB2_q_b[4]_PORT_B_data_out, UB2_q_b[4]_clock_1, , , ); UB2_q_b[12] = UB2_q_b[4]_PORT_B_data_out_reg[1]; --E1_nx325 is ni2io_wt:wt_ni|nx325 --operation mode is normal E1_nx325 = !V1_request_47 & V1_request_48 & !E1_NOT_and_mask_2; --E1_nx326 is ni2io_wt:wt_ni|nx326 --operation mode is normal E1_nx326 = V1_request_47 & (V1_request_48 & (SB3_Q_0) # !V1_request_48 & SB4_Q_0); --L1_RDATA_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_12 --operation mode is normal L1_RDATA_12 = L1_nx853 # L1_nx854 # L1_nx855 # L1_nx856; --F1_RDATA_12 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_12 --operation mode is normal F1_RDATA_12 = F1_nx816 # F1_nx855 # F1_bytes2send_44 & F1_a_3; --K1_RDATA_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_12 --operation mode is normal K1_RDATA_12 = K1_nx936 # K1_nx937 # K1_nx938 # K1_nx939; --J1_RDATA_12 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_12 --operation mode is normal J1_RDATA_12 = !V1_request_38 & Q1_q_b[12]; --RB2_dout_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|dout_3 --operation mode is normal RB2_dout_3 = E1_NOT_sel_p_3 & (E1_sel_p_2 & (RB2_q1pass_3) # !E1_sel_p_2 & RB2_q1pass_4) # !E1_NOT_sel_p_3 & (RB2_q1pass_3); --SB1_Q_11 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_neg|counter_12:parc|Q_11 --operation mode is normal SB1_Q_11_carry_eqn = SB1_Q_nx61; SB1_Q_11_lut_out = SB1_Q_11 $ (SB1_Q_11_carry_eqn); SB1_Q_11 = DFFEAS(SB1_Q_11_lut_out, !WT_STR, E1_NOT_clear, , , , , , ); --L1_nx857 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx857 --operation mode is normal L1_nx857 = !L1_nx908 & (V1_request_48 & (L1_adc_last_2_11) # !V1_request_48 & L1_adc_last_0_11); --L1_nx858 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx858 --operation mode is normal L1_nx858 = !L1_nx907 & (V1_request_48 & (L1_adc_last_6_11) # !V1_request_48 & L1_adc_last_4_11); --L1_nx859 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx859 --operation mode is normal L1_nx859 = V1_request_46 & !V1_request_47 & L1_cfr_11; --L1_nx860 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx860 --operation mode is normal L1_nx860 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_11 # !V1_request_48 & (!L1_NOT_climits_a_11)); --F1_nx817 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx817 --operation mode is normal F1_nx817 = F1_bytes2send_11 & (F1_a_1 # F1_bytes_rcvd_11 & F1_nx785) # !F1_bytes2send_11 & F1_bytes_rcvd_11 & (F1_nx785); --F1_nx854 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx854 --operation mode is normal F1_nx854 = !V1_request_46 & V1_request_47 & V1_request_48 & F1_bytes_rcvd_43; --K1_nx940 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx940 --operation mode is normal K1_nx940 = !K1_nx991 & (V1_request_48 & (K1_adc_last_2_11) # !V1_request_48 & K1_adc_last_0_11); --K1_nx941 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx941 --operation mode is normal K1_nx941 = !K1_nx990 & (V1_request_48 & (K1_adc_last_6_11) # !V1_request_48 & K1_adc_last_4_11); --K1_nx942 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx942 --operation mode is normal K1_nx942 = V1_request_46 & !V1_request_47 & K1_cfr_11; --K1_nx943 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx943 --operation mode is normal K1_nx943 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_11 # !V1_request_48 & (!K1_NOT_climits_a_11)); --Q1_q_b[11] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[11] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[11]_PORT_A_data_in = J1_wdata_ram_11; Q1_q_b[11]_PORT_A_data_in_reg = DFFE(Q1_q_b[11]_PORT_A_data_in, Q1_q_b[11]_clock_0, , , Q1_q_b[11]_clock_enable_0); Q1_q_b[11]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[11]_PORT_A_address_reg = DFFE(Q1_q_b[11]_PORT_A_address, Q1_q_b[11]_clock_0, , , Q1_q_b[11]_clock_enable_0); Q1_q_b[11]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[11]_PORT_B_address_reg = DFFE(Q1_q_b[11]_PORT_B_address, Q1_q_b[11]_clock_1, , , ); Q1_q_b[11]_PORT_A_write_enable = VCC; Q1_q_b[11]_PORT_A_write_enable_reg = DFFE(Q1_q_b[11]_PORT_A_write_enable, Q1_q_b[11]_clock_0, , , Q1_q_b[11]_clock_enable_0); Q1_q_b[11]_PORT_B_read_enable = VCC; Q1_q_b[11]_PORT_B_read_enable_reg = DFFE(Q1_q_b[11]_PORT_B_read_enable, Q1_q_b[11]_clock_1, , , ); Q1_q_b[11]_clock_0 = S1__clk1; Q1_q_b[11]_clock_1 = S1__clk1; Q1_q_b[11]_clock_enable_0 = J1_sm; Q1_q_b[11]_PORT_B_data_out = MEMORY(Q1_q_b[11]_PORT_A_data_in_reg, , Q1_q_b[11]_PORT_A_address_reg, Q1_q_b[11]_PORT_B_address_reg, Q1_q_b[11]_PORT_A_write_enable_reg, Q1_q_b[11]_PORT_B_read_enable_reg, , , Q1_q_b[11]_clock_0, Q1_q_b[11]_clock_1, Q1_q_b[11]_clock_enable_0, , , ); Q1_q_b[11]_PORT_B_data_out_reg = DFFE(Q1_q_b[11]_PORT_B_data_out, Q1_q_b[11]_clock_1, , , ); Q1_q_b[11] = Q1_q_b[11]_PORT_B_data_out_reg[0]; --Q1_q_b[27] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[27] Q1_q_b[11]_PORT_A_data_in = J1_wdata_ram_11; Q1_q_b[11]_PORT_A_data_in_reg = DFFE(Q1_q_b[11]_PORT_A_data_in, Q1_q_b[11]_clock_0, , , Q1_q_b[11]_clock_enable_0); Q1_q_b[11]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[11]_PORT_A_address_reg = DFFE(Q1_q_b[11]_PORT_A_address, Q1_q_b[11]_clock_0, , , Q1_q_b[11]_clock_enable_0); Q1_q_b[11]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[11]_PORT_B_address_reg = DFFE(Q1_q_b[11]_PORT_B_address, Q1_q_b[11]_clock_1, , , ); Q1_q_b[11]_PORT_A_write_enable = VCC; Q1_q_b[11]_PORT_A_write_enable_reg = DFFE(Q1_q_b[11]_PORT_A_write_enable, Q1_q_b[11]_clock_0, , , Q1_q_b[11]_clock_enable_0); Q1_q_b[11]_PORT_B_read_enable = VCC; Q1_q_b[11]_PORT_B_read_enable_reg = DFFE(Q1_q_b[11]_PORT_B_read_enable, Q1_q_b[11]_clock_1, , , ); Q1_q_b[11]_clock_0 = S1__clk1; Q1_q_b[11]_clock_1 = S1__clk1; Q1_q_b[11]_clock_enable_0 = J1_sm; Q1_q_b[11]_PORT_B_data_out = MEMORY(Q1_q_b[11]_PORT_A_data_in_reg, , Q1_q_b[11]_PORT_A_address_reg, Q1_q_b[11]_PORT_B_address_reg, Q1_q_b[11]_PORT_A_write_enable_reg, Q1_q_b[11]_PORT_B_read_enable_reg, , , Q1_q_b[11]_clock_0, Q1_q_b[11]_clock_1, Q1_q_b[11]_clock_enable_0, , , ); Q1_q_b[11]_PORT_B_data_out_reg = DFFE(Q1_q_b[11]_PORT_B_data_out, Q1_q_b[11]_clock_1, , , ); Q1_q_b[27] = Q1_q_b[11]_PORT_B_data_out_reg[1]; --RB2_q1pass_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|q1pass_3 --operation mode is normal RB2_q1pass_3 = E1_NOT_sel_s_3 & (E1_sel_s_2 & (PB2_data_1p_m_3) # !E1_sel_s_2 & PB2_data_1p_m_4) # !E1_NOT_sel_s_3 & (PB2_data_1p_m_3); --RB2_modgen_gt_30_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|modgen_gt_30_nx56 --operation mode is normal RB2_modgen_gt_30_nx56 = E1_sel_p_2 # E1_sel_p_1 & !E1_NOT_sel_p_0 # !E1_NOT_sel_p_3; --L1_adc_last_0_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_10 --operation mode is normal L1_adc_last_0_10_lut_out = R2_RDATA_10; L1_adc_last_0_10 = DFFEAS(L1_adc_last_0_10_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_10 --operation mode is normal L1_adc_last_2_10_lut_out = R2_RDATA_10; L1_adc_last_2_10 = DFFEAS(L1_adc_last_2_10_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_10 --operation mode is normal L1_adc_last_4_10_lut_out = R2_RDATA_10; L1_adc_last_4_10 = DFFEAS(L1_adc_last_4_10_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_10 --operation mode is normal L1_adc_last_6_10_lut_out = R2_RDATA_10; L1_adc_last_6_10 = DFFEAS(L1_adc_last_6_10_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_10 --operation mode is normal L1_NOT_climits_d_10_lut_out = !V1_request_21; L1_NOT_climits_d_10 = DFFEAS(L1_NOT_climits_d_10_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_10 --operation mode is normal L1_NOT_climits_a_10_lut_out = !V1_request_21; L1_NOT_climits_a_10 = DFFEAS(L1_NOT_climits_a_10_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_10 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_10 --operation mode is normal F1_bytes_rcvd_10_lut_out = F1_nx2239; F1_bytes_rcvd_10 = DFFEAS(F1_bytes_rcvd_10_lut_out, S1__clk1, VCC, , F1_NOT_nx2217, , , , ); --K1_adc_last_0_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_10 --operation mode is normal K1_adc_last_0_10_lut_out = R1_RDATA_10; K1_adc_last_0_10 = DFFEAS(K1_adc_last_0_10_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_10 --operation mode is normal K1_adc_last_2_10_lut_out = R1_RDATA_10; K1_adc_last_2_10 = DFFEAS(K1_adc_last_2_10_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_10 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_10 --operation mode is normal J1_wdata_ram_10_lut_out = PAADC_D[10]; J1_wdata_ram_10 = DFFEAS(J1_wdata_ram_10_lut_out, S1__clk1, VCC, , , , , , ); --PB2_data_1p_m_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_3 --operation mode is normal PB2_data_1p_m_3 = E1_or_mask_3 # !E1_NOT_and_mask_3 & (E1_NOT_xor_mask_3 $ !TB2_q_3); --RB2_modgen_gt_17_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|modgen_gt_17_nx56 --operation mode is normal RB2_modgen_gt_17_nx56 = E1_sel_s_2 # E1_sel_s_1 & E1_sel_s_0 # !E1_NOT_sel_s_3; --R2_RDATA_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_9 --operation mode is normal R2_RDATA_9_lut_out = R2_RDATA_8; R2_RDATA_9 = DFFEAS(R2_RDATA_9_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --TB2_q_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_2 --operation mode is normal TB2_q_2_lut_out = WT_P4D[2]; TB2_q_2 = DFFEAS(TB2_q_2_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --TB2_q_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_1 --operation mode is normal TB2_q_1_lut_out = WT_P4D[1]; TB2_q_1 = DFFEAS(TB2_q_1_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --TB2_q_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_0 --operation mode is normal TB2_q_0_lut_out = WT_P4D[0]; TB2_q_0 = DFFEAS(TB2_q_0_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --AB2_ob_data_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_13 --operation mode is normal AB2_ob_data_13_lut_out = AB2_ob_data_12; AB2_ob_data_13 = DFFEAS(AB2_ob_data_13_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_13, , , AB2_a_2); --LB2_d_to_dll_14 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_14 --operation mode is normal LB2_d_to_dll_14 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_14 # !DB4_data_out_0 & (T1_reply_14)); --AB1_ob_data_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_12 --operation mode is normal AB1_ob_data_12_lut_out = AB1_ob_data_11; AB1_ob_data_12 = DFFEAS(AB1_ob_data_12_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_12, , , AB1_a_2); --LB1_d_to_dll_13 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_13 --operation mode is normal LB1_d_to_dll_13 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_13 # !DB3_data_out_0 & (T1_reply_13)); --T1_reply_14 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_14 --operation mode is normal T1_reply_14 = V1_request_14 & (T1_a_0_dup_53 # T1_read_data_17 & !T1_ix34_ix30_nx12) # !V1_request_14 & T1_read_data_17 & (!T1_ix34_ix30_nx12); --T1_read_data_16 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_16 --operation mode is normal T1_read_data_16_lut_out = H1_bus_dout_16; T1_read_data_16 = DFFEAS(T1_read_data_16_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_15 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_15 --operation mode is normal H1_bus_dout_15 = H1_nx181 # H1_nx182 # E1_rdata_15 & H1_sel_0; --E1_rdata_14 is ni2io_wt:wt_ni|rdata_14 --operation mode is normal E1_rdata_14 = V1_request_37 & UB2_q_b[6] # !V1_request_37 & (E1_nx329 # E1_nx330); --H1_nx183 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx183 --operation mode is normal H1_nx183 = L1_RDATA_14 & (H1_ce_sc_adc # F1_RDATA_14 & H1_ce_dds) # !L1_RDATA_14 & F1_RDATA_14 & H1_ce_dds; --H1_nx184 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx184 --operation mode is normal H1_nx184 = K1_RDATA_14 & (H1_ce_psply_adc # J1_RDATA_14 & H1_ce_pasa_adc) # !K1_RDATA_14 & J1_RDATA_14 & (H1_ce_pasa_adc); --UB2_q_b[5] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[5] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB2_q_b[5]_PORT_A_data_in = RB2_dout_5; UB2_q_b[5]_PORT_A_data_in_reg = DFFE(UB2_q_b[5]_PORT_A_data_in, UB2_q_b[5]_clock_0, UB2_q_b[5]_clear_0, , UB2_q_b[5]_clock_enable_0); UB2_q_b[5]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[5]_PORT_A_address_reg = DFFE(UB2_q_b[5]_PORT_A_address, UB2_q_b[5]_clock_0, UB2_q_b[5]_clear_0, , UB2_q_b[5]_clock_enable_0); UB2_q_b[5]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[5]_PORT_B_address_reg = DFFE(UB2_q_b[5]_PORT_B_address, UB2_q_b[5]_clock_1, , , ); UB2_q_b[5]_PORT_A_write_enable = VCC; UB2_q_b[5]_PORT_A_write_enable_reg = DFFE(UB2_q_b[5]_PORT_A_write_enable, UB2_q_b[5]_clock_0, UB2_q_b[5]_clear_0, , UB2_q_b[5]_clock_enable_0); UB2_q_b[5]_PORT_B_read_enable = VCC; UB2_q_b[5]_PORT_B_read_enable_reg = DFFE(UB2_q_b[5]_PORT_B_read_enable, UB2_q_b[5]_clock_1, , , ); UB2_q_b[5]_clock_0 = WT_STR; UB2_q_b[5]_clock_1 = S1__clk1; UB2_q_b[5]_clock_enable_0 = PB2_we_p; UB2_q_b[5]_clear_0 = !E1_NOT_clear; UB2_q_b[5]_PORT_B_data_out = MEMORY(UB2_q_b[5]_PORT_A_data_in_reg, , UB2_q_b[5]_PORT_A_address_reg, UB2_q_b[5]_PORT_B_address_reg, UB2_q_b[5]_PORT_A_write_enable_reg, UB2_q_b[5]_PORT_B_read_enable_reg, , , UB2_q_b[5]_clock_0, UB2_q_b[5]_clock_1, UB2_q_b[5]_clock_enable_0, , UB2_q_b[5]_clear_0, ); UB2_q_b[5]_PORT_B_data_out_reg = DFFE(UB2_q_b[5]_PORT_B_data_out, UB2_q_b[5]_clock_1, , , ); UB2_q_b[5] = UB2_q_b[5]_PORT_B_data_out_reg[0]; --UB2_q_b[13] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[13] UB2_q_b[5]_PORT_A_data_in = RB2_dout_5; UB2_q_b[5]_PORT_A_data_in_reg = DFFE(UB2_q_b[5]_PORT_A_data_in, UB2_q_b[5]_clock_0, UB2_q_b[5]_clear_0, , UB2_q_b[5]_clock_enable_0); UB2_q_b[5]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[5]_PORT_A_address_reg = DFFE(UB2_q_b[5]_PORT_A_address, UB2_q_b[5]_clock_0, UB2_q_b[5]_clear_0, , UB2_q_b[5]_clock_enable_0); UB2_q_b[5]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[5]_PORT_B_address_reg = DFFE(UB2_q_b[5]_PORT_B_address, UB2_q_b[5]_clock_1, , , ); UB2_q_b[5]_PORT_A_write_enable = VCC; UB2_q_b[5]_PORT_A_write_enable_reg = DFFE(UB2_q_b[5]_PORT_A_write_enable, UB2_q_b[5]_clock_0, UB2_q_b[5]_clear_0, , UB2_q_b[5]_clock_enable_0); UB2_q_b[5]_PORT_B_read_enable = VCC; UB2_q_b[5]_PORT_B_read_enable_reg = DFFE(UB2_q_b[5]_PORT_B_read_enable, UB2_q_b[5]_clock_1, , , ); UB2_q_b[5]_clock_0 = WT_STR; UB2_q_b[5]_clock_1 = S1__clk1; UB2_q_b[5]_clock_enable_0 = PB2_we_p; UB2_q_b[5]_clear_0 = !E1_NOT_clear; UB2_q_b[5]_PORT_B_data_out = MEMORY(UB2_q_b[5]_PORT_A_data_in_reg, , UB2_q_b[5]_PORT_A_address_reg, UB2_q_b[5]_PORT_B_address_reg, UB2_q_b[5]_PORT_A_write_enable_reg, UB2_q_b[5]_PORT_B_read_enable_reg, , , UB2_q_b[5]_clock_0, UB2_q_b[5]_clock_1, UB2_q_b[5]_clock_enable_0, , UB2_q_b[5]_clear_0, ); UB2_q_b[5]_PORT_B_data_out_reg = DFFE(UB2_q_b[5]_PORT_B_data_out, UB2_q_b[5]_clock_1, , , ); UB2_q_b[13] = UB2_q_b[5]_PORT_B_data_out_reg[1]; --E1_nx327 is ni2io_wt:wt_ni|nx327 --operation mode is normal E1_nx327 = !V1_request_47 & V1_request_48 & !E1_NOT_and_mask_3; --E1_nx328 is ni2io_wt:wt_ni|nx328 --operation mode is normal E1_nx328 = V1_request_47 & (V1_request_48 & (SB3_Q_1) # !V1_request_48 & SB4_Q_1); --L1_RDATA_13 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_13 --operation mode is normal L1_RDATA_13 = L1_nx850 # L1_nx851 # L1_nx852; --F1_RDATA_13 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_13 --operation mode is normal F1_RDATA_13 = F1_nx815 # F1_nx856 # F1_bytes2send_45 & F1_a_3; --K1_RDATA_13 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_13 --operation mode is normal K1_RDATA_13 = K1_nx933 # K1_nx934 # K1_nx935; --J1_RDATA_13 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_13 --operation mode is normal J1_RDATA_13 = !V1_request_38 & Q1_q_b[13]; --RB2_dout_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|dout_4 --operation mode is normal RB2_dout_4 = RB2_modgen_gt_26_nx56 & (RB2_q1pass_4) # !RB2_modgen_gt_26_nx56 & RB2_q1pass_5; --SB3_Q_0 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_0 --operation mode is arithmetic SB3_Q_0_lut_out = SB3_Q_0 $ PB2_par_en; SB3_Q_0 = DFFEAS(SB3_Q_0_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx10 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx10 --operation mode is arithmetic SB3_Q_nx10 = CARRY(SB3_Q_0 & PB2_par_en); --L1_nx853 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx853 --operation mode is normal L1_nx853 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_0) # !V1_request_48 & L1_adc_last_1_0); --L1_nx854 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx854 --operation mode is normal L1_nx854 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_0) # !V1_request_48 & L1_adc_last_5_0); --L1_nx855 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx855 --operation mode is normal L1_nx855 = V1_request_46 & !V1_request_47 & L1_cfr_12; --L1_nx856 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx856 --operation mode is normal L1_nx856 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_12 # !V1_request_48 & (!L1_NOT_climits_a_12)); --F1_nx816 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx816 --operation mode is normal F1_nx816 = F1_bytes2send_12 & (F1_a_1 # F1_bytes_rcvd_12 & F1_nx785) # !F1_bytes2send_12 & F1_bytes_rcvd_12 & (F1_nx785); --F1_nx855 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx855 --operation mode is normal F1_nx855 = !V1_request_46 & V1_request_47 & V1_request_48 & F1_bytes_rcvd_44; --K1_nx936 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx936 --operation mode is normal K1_nx936 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_0) # !V1_request_48 & K1_adc_last_1_0); --K1_nx937 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx937 --operation mode is normal K1_nx937 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_0) # !V1_request_48 & K1_adc_last_5_0); --K1_nx938 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx938 --operation mode is normal K1_nx938 = V1_request_46 & !V1_request_47 & K1_cfr_12; --K1_nx939 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx939 --operation mode is normal K1_nx939 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_12 # !V1_request_48 & (!K1_NOT_climits_a_12)); --Q1_q_b[12] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[12] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[12]_PORT_A_data_in = J1_wdata_ram_12; Q1_q_b[12]_PORT_A_data_in_reg = DFFE(Q1_q_b[12]_PORT_A_data_in, Q1_q_b[12]_clock_0, , , Q1_q_b[12]_clock_enable_0); Q1_q_b[12]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[12]_PORT_A_address_reg = DFFE(Q1_q_b[12]_PORT_A_address, Q1_q_b[12]_clock_0, , , Q1_q_b[12]_clock_enable_0); Q1_q_b[12]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[12]_PORT_B_address_reg = DFFE(Q1_q_b[12]_PORT_B_address, Q1_q_b[12]_clock_1, , , ); Q1_q_b[12]_PORT_A_write_enable = VCC; Q1_q_b[12]_PORT_A_write_enable_reg = DFFE(Q1_q_b[12]_PORT_A_write_enable, Q1_q_b[12]_clock_0, , , Q1_q_b[12]_clock_enable_0); Q1_q_b[12]_PORT_B_read_enable = VCC; Q1_q_b[12]_PORT_B_read_enable_reg = DFFE(Q1_q_b[12]_PORT_B_read_enable, Q1_q_b[12]_clock_1, , , ); Q1_q_b[12]_clock_0 = S1__clk1; Q1_q_b[12]_clock_1 = S1__clk1; Q1_q_b[12]_clock_enable_0 = J1_sm; Q1_q_b[12]_PORT_B_data_out = MEMORY(Q1_q_b[12]_PORT_A_data_in_reg, , Q1_q_b[12]_PORT_A_address_reg, Q1_q_b[12]_PORT_B_address_reg, Q1_q_b[12]_PORT_A_write_enable_reg, Q1_q_b[12]_PORT_B_read_enable_reg, , , Q1_q_b[12]_clock_0, Q1_q_b[12]_clock_1, Q1_q_b[12]_clock_enable_0, , , ); Q1_q_b[12]_PORT_B_data_out_reg = DFFE(Q1_q_b[12]_PORT_B_data_out, Q1_q_b[12]_clock_1, , , ); Q1_q_b[12] = Q1_q_b[12]_PORT_B_data_out_reg[0]; --Q1_q_b[28] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[28] Q1_q_b[12]_PORT_A_data_in = J1_wdata_ram_12; Q1_q_b[12]_PORT_A_data_in_reg = DFFE(Q1_q_b[12]_PORT_A_data_in, Q1_q_b[12]_clock_0, , , Q1_q_b[12]_clock_enable_0); Q1_q_b[12]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[12]_PORT_A_address_reg = DFFE(Q1_q_b[12]_PORT_A_address, Q1_q_b[12]_clock_0, , , Q1_q_b[12]_clock_enable_0); Q1_q_b[12]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[12]_PORT_B_address_reg = DFFE(Q1_q_b[12]_PORT_B_address, Q1_q_b[12]_clock_1, , , ); Q1_q_b[12]_PORT_A_write_enable = VCC; Q1_q_b[12]_PORT_A_write_enable_reg = DFFE(Q1_q_b[12]_PORT_A_write_enable, Q1_q_b[12]_clock_0, , , Q1_q_b[12]_clock_enable_0); Q1_q_b[12]_PORT_B_read_enable = VCC; Q1_q_b[12]_PORT_B_read_enable_reg = DFFE(Q1_q_b[12]_PORT_B_read_enable, Q1_q_b[12]_clock_1, , , ); Q1_q_b[12]_clock_0 = S1__clk1; Q1_q_b[12]_clock_1 = S1__clk1; Q1_q_b[12]_clock_enable_0 = J1_sm; Q1_q_b[12]_PORT_B_data_out = MEMORY(Q1_q_b[12]_PORT_A_data_in_reg, , Q1_q_b[12]_PORT_A_address_reg, Q1_q_b[12]_PORT_B_address_reg, Q1_q_b[12]_PORT_A_write_enable_reg, Q1_q_b[12]_PORT_B_read_enable_reg, , , Q1_q_b[12]_clock_0, Q1_q_b[12]_clock_1, Q1_q_b[12]_clock_enable_0, , , ); Q1_q_b[12]_PORT_B_data_out_reg = DFFE(Q1_q_b[12]_PORT_B_data_out, Q1_q_b[12]_clock_1, , , ); Q1_q_b[28] = Q1_q_b[12]_PORT_B_data_out_reg[1]; --RB2_q1pass_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|q1pass_4 --operation mode is normal RB2_q1pass_4 = RB2_modgen_gt_15_nx56 & (PB2_data_1p_m_4) # !RB2_modgen_gt_15_nx56 & PB2_data_1p_m_5; --L1_adc_last_0_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_0_11 --operation mode is normal L1_adc_last_0_11_lut_out = R2_RDATA_11; L1_adc_last_0_11 = DFFEAS(L1_adc_last_0_11_lut_out, S1__clk1, VCC, , L1_NOT_nx2189, , , , ); --L1_adc_last_2_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_2_11 --operation mode is normal L1_adc_last_2_11_lut_out = R2_RDATA_11; L1_adc_last_2_11 = DFFEAS(L1_adc_last_2_11_lut_out, S1__clk1, VCC, , L1_NOT_nx2237, , , , ); --L1_adc_last_4_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_4_11 --operation mode is normal L1_adc_last_4_11_lut_out = R2_RDATA_11; L1_adc_last_4_11 = DFFEAS(L1_adc_last_4_11_lut_out, S1__clk1, VCC, , L1_NOT_nx2285, , , , ); --L1_adc_last_6_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_6_11 --operation mode is normal L1_adc_last_6_11_lut_out = R2_RDATA_11; L1_adc_last_6_11 = DFFEAS(L1_adc_last_6_11_lut_out, S1__clk1, VCC, , L1_NOT_nx2333, , , , ); --L1_NOT_climits_d_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_11 --operation mode is normal L1_NOT_climits_d_11_lut_out = !V1_request_20; L1_NOT_climits_d_11 = DFFEAS(L1_NOT_climits_d_11_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_11 --operation mode is normal L1_NOT_climits_a_11_lut_out = !V1_request_20; L1_NOT_climits_a_11 = DFFEAS(L1_NOT_climits_a_11_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_11 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_11 --operation mode is normal F1_bytes_rcvd_11_lut_out = F1_nx2235; F1_bytes_rcvd_11 = DFFEAS(F1_bytes_rcvd_11_lut_out, S1__clk1, VCC, , F1_NOT_nx2217, , , , ); --K1_adc_last_0_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_0_11 --operation mode is normal K1_adc_last_0_11_lut_out = R1_RDATA_11; K1_adc_last_0_11 = DFFEAS(K1_adc_last_0_11_lut_out, S1__clk1, VCC, , K1_NOT_nx2189, , , , ); --K1_adc_last_2_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_2_11 --operation mode is normal K1_adc_last_2_11_lut_out = R1_RDATA_11; K1_adc_last_2_11 = DFFEAS(K1_adc_last_2_11_lut_out, S1__clk1, VCC, , K1_NOT_nx2237, , , , ); --J1_wdata_ram_11 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_11 --operation mode is normal J1_wdata_ram_11_lut_out = PAADC_D[11]; J1_wdata_ram_11 = DFFEAS(J1_wdata_ram_11_lut_out, S1__clk1, VCC, , , , , , ); --PB2_data_1p_m_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_4 --operation mode is normal PB2_data_1p_m_4 = E1_or_mask_4 # !E1_NOT_and_mask_4 & (E1_NOT_xor_mask_4 $ !TB2_q_4); --R2_RDATA_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_10 --operation mode is normal R2_RDATA_10_lut_out = R2_RDATA_9; R2_RDATA_10 = DFFEAS(R2_RDATA_10_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --TB2_q_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_3 --operation mode is normal TB2_q_3_lut_out = WT_P4D[3]; TB2_q_3 = DFFEAS(TB2_q_3_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --AB2_ob_data_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_12 --operation mode is normal AB2_ob_data_12_lut_out = AB2_ob_data_11; AB2_ob_data_12 = DFFEAS(AB2_ob_data_12_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_12, , , AB2_a_2); --LB2_d_to_dll_13 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_13 --operation mode is normal LB2_d_to_dll_13 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_13 # !DB4_data_out_0 & (T1_reply_13)); --AB1_ob_data_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_11 --operation mode is normal AB1_ob_data_11_lut_out = AB1_ob_data_10; AB1_ob_data_11 = DFFEAS(AB1_ob_data_11_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_11, , , AB1_a_2); --LB1_d_to_dll_12 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_12 --operation mode is normal LB1_d_to_dll_12 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_12 # !DB3_data_out_0 & (T1_reply_12)); --T1_reply_13 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_13 --operation mode is normal T1_reply_13 = V1_request_13 & (T1_a_0_dup_53 # T1_read_data_18 & !T1_ix34_ix30_nx12) # !V1_request_13 & T1_read_data_18 & (!T1_ix34_ix30_nx12); --T1_read_data_17 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_17 --operation mode is normal T1_read_data_17_lut_out = H1_bus_dout_17; T1_read_data_17 = DFFEAS(T1_read_data_17_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_16 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_16 --operation mode is normal H1_bus_dout_16 = H1_nx179 # H1_nx180 # E1_rdata_16 & H1_sel_0; --E1_rdata_15 is ni2io_wt:wt_ni|rdata_15 --operation mode is normal E1_rdata_15 = V1_request_37 & UB2_q_b[7] # !V1_request_37 & (E1_nx331 # E1_nx332); --H1_nx181 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx181 --operation mode is normal H1_nx181 = L1_RDATA_15 & (H1_ce_sc_adc # F1_RDATA_15 & H1_ce_dds) # !L1_RDATA_15 & F1_RDATA_15 & H1_ce_dds; --H1_nx182 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx182 --operation mode is normal H1_nx182 = K1_RDATA_15 & (H1_ce_psply_adc # J1_RDATA_15 & H1_ce_pasa_adc) # !K1_RDATA_15 & J1_RDATA_15 & (H1_ce_pasa_adc); --UB2_q_b[6] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[6] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB2_q_b[6]_PORT_A_data_in = RB2_dout_6; UB2_q_b[6]_PORT_A_data_in_reg = DFFE(UB2_q_b[6]_PORT_A_data_in, UB2_q_b[6]_clock_0, UB2_q_b[6]_clear_0, , UB2_q_b[6]_clock_enable_0); UB2_q_b[6]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[6]_PORT_A_address_reg = DFFE(UB2_q_b[6]_PORT_A_address, UB2_q_b[6]_clock_0, UB2_q_b[6]_clear_0, , UB2_q_b[6]_clock_enable_0); UB2_q_b[6]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[6]_PORT_B_address_reg = DFFE(UB2_q_b[6]_PORT_B_address, UB2_q_b[6]_clock_1, , , ); UB2_q_b[6]_PORT_A_write_enable = VCC; UB2_q_b[6]_PORT_A_write_enable_reg = DFFE(UB2_q_b[6]_PORT_A_write_enable, UB2_q_b[6]_clock_0, UB2_q_b[6]_clear_0, , UB2_q_b[6]_clock_enable_0); UB2_q_b[6]_PORT_B_read_enable = VCC; UB2_q_b[6]_PORT_B_read_enable_reg = DFFE(UB2_q_b[6]_PORT_B_read_enable, UB2_q_b[6]_clock_1, , , ); UB2_q_b[6]_clock_0 = WT_STR; UB2_q_b[6]_clock_1 = S1__clk1; UB2_q_b[6]_clock_enable_0 = PB2_we_p; UB2_q_b[6]_clear_0 = !E1_NOT_clear; UB2_q_b[6]_PORT_B_data_out = MEMORY(UB2_q_b[6]_PORT_A_data_in_reg, , UB2_q_b[6]_PORT_A_address_reg, UB2_q_b[6]_PORT_B_address_reg, UB2_q_b[6]_PORT_A_write_enable_reg, UB2_q_b[6]_PORT_B_read_enable_reg, , , UB2_q_b[6]_clock_0, UB2_q_b[6]_clock_1, UB2_q_b[6]_clock_enable_0, , UB2_q_b[6]_clear_0, ); UB2_q_b[6]_PORT_B_data_out_reg = DFFE(UB2_q_b[6]_PORT_B_data_out, UB2_q_b[6]_clock_1, , , ); UB2_q_b[6] = UB2_q_b[6]_PORT_B_data_out_reg[0]; --UB2_q_b[14] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[14] UB2_q_b[6]_PORT_A_data_in = RB2_dout_6; UB2_q_b[6]_PORT_A_data_in_reg = DFFE(UB2_q_b[6]_PORT_A_data_in, UB2_q_b[6]_clock_0, UB2_q_b[6]_clear_0, , UB2_q_b[6]_clock_enable_0); UB2_q_b[6]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[6]_PORT_A_address_reg = DFFE(UB2_q_b[6]_PORT_A_address, UB2_q_b[6]_clock_0, UB2_q_b[6]_clear_0, , UB2_q_b[6]_clock_enable_0); UB2_q_b[6]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[6]_PORT_B_address_reg = DFFE(UB2_q_b[6]_PORT_B_address, UB2_q_b[6]_clock_1, , , ); UB2_q_b[6]_PORT_A_write_enable = VCC; UB2_q_b[6]_PORT_A_write_enable_reg = DFFE(UB2_q_b[6]_PORT_A_write_enable, UB2_q_b[6]_clock_0, UB2_q_b[6]_clear_0, , UB2_q_b[6]_clock_enable_0); UB2_q_b[6]_PORT_B_read_enable = VCC; UB2_q_b[6]_PORT_B_read_enable_reg = DFFE(UB2_q_b[6]_PORT_B_read_enable, UB2_q_b[6]_clock_1, , , ); UB2_q_b[6]_clock_0 = WT_STR; UB2_q_b[6]_clock_1 = S1__clk1; UB2_q_b[6]_clock_enable_0 = PB2_we_p; UB2_q_b[6]_clear_0 = !E1_NOT_clear; UB2_q_b[6]_PORT_B_data_out = MEMORY(UB2_q_b[6]_PORT_A_data_in_reg, , UB2_q_b[6]_PORT_A_address_reg, UB2_q_b[6]_PORT_B_address_reg, UB2_q_b[6]_PORT_A_write_enable_reg, UB2_q_b[6]_PORT_B_read_enable_reg, , , UB2_q_b[6]_clock_0, UB2_q_b[6]_clock_1, UB2_q_b[6]_clock_enable_0, , UB2_q_b[6]_clear_0, ); UB2_q_b[6]_PORT_B_data_out_reg = DFFE(UB2_q_b[6]_PORT_B_data_out, UB2_q_b[6]_clock_1, , , ); UB2_q_b[14] = UB2_q_b[6]_PORT_B_data_out_reg[1]; --E1_nx329 is ni2io_wt:wt_ni|nx329 --operation mode is normal E1_nx329 = !V1_request_47 & V1_request_48 & !E1_NOT_and_mask_4; --E1_nx330 is ni2io_wt:wt_ni|nx330 --operation mode is normal E1_nx330 = V1_request_47 & (V1_request_48 & (SB3_Q_2) # !V1_request_48 & SB4_Q_2); --L1_RDATA_14 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_14 --operation mode is normal L1_RDATA_14 = L1_nx847 # L1_nx848 # L1_nx849; --F1_RDATA_14 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_14 --operation mode is normal F1_RDATA_14 = F1_nx814 # F1_nx857 # F1_bytes2send_46 & F1_a_3; --K1_RDATA_14 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_14 --operation mode is normal K1_RDATA_14 = K1_nx930 # K1_nx931 # K1_nx932; --J1_RDATA_14 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_14 --operation mode is normal J1_RDATA_14 = !V1_request_38 & Q1_q_b[14]; --RB2_dout_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|dout_5 --operation mode is normal RB2_dout_5 = E1_NOT_sel_p_3 & (RB2_nx153 & (RB2_q1pass_5) # !RB2_nx153 & RB2_q1pass_6) # !E1_NOT_sel_p_3 & (RB2_q1pass_5); --SB3_Q_1 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_1 --operation mode is arithmetic SB3_Q_1_carry_eqn = SB3_Q_nx10; SB3_Q_1_lut_out = SB3_Q_1 $ (SB3_Q_1_carry_eqn); SB3_Q_1 = DFFEAS(SB3_Q_1_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx16 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx16 --operation mode is arithmetic SB3_Q_nx16 = CARRY(!SB3_Q_nx10 # !SB3_Q_1); --L1_nx850 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx850 --operation mode is normal L1_nx850 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_1) # !V1_request_48 & L1_adc_last_1_1); --L1_nx851 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx851 --operation mode is normal L1_nx851 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_1) # !V1_request_48 & L1_adc_last_5_1); --L1_nx852 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx852 --operation mode is normal L1_nx852 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_13 # !V1_request_48 & (!L1_NOT_climits_a_13)); --F1_nx815 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx815 --operation mode is normal F1_nx815 = F1_bytes2send_13 & (F1_a_1 # F1_bytes_rcvd_13 & F1_nx785) # !F1_bytes2send_13 & F1_bytes_rcvd_13 & (F1_nx785); --F1_nx856 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx856 --operation mode is normal F1_nx856 = !V1_request_46 & V1_request_47 & V1_request_48 & F1_bytes_rcvd_45; --K1_nx933 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx933 --operation mode is normal K1_nx933 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_1) # !V1_request_48 & K1_adc_last_1_1); --K1_nx934 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx934 --operation mode is normal K1_nx934 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_1) # !V1_request_48 & K1_adc_last_5_1); --K1_nx935 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx935 --operation mode is normal K1_nx935 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_13 # !V1_request_48 & (!K1_NOT_climits_a_13)); --Q1_q_b[13] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[13] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[13]_PORT_A_data_in = J1_PAADC_MuxA_0; Q1_q_b[13]_PORT_A_data_in_reg = DFFE(Q1_q_b[13]_PORT_A_data_in, Q1_q_b[13]_clock_0, , , Q1_q_b[13]_clock_enable_0); Q1_q_b[13]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[13]_PORT_A_address_reg = DFFE(Q1_q_b[13]_PORT_A_address, Q1_q_b[13]_clock_0, , , Q1_q_b[13]_clock_enable_0); Q1_q_b[13]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[13]_PORT_B_address_reg = DFFE(Q1_q_b[13]_PORT_B_address, Q1_q_b[13]_clock_1, , , ); Q1_q_b[13]_PORT_A_write_enable = VCC; Q1_q_b[13]_PORT_A_write_enable_reg = DFFE(Q1_q_b[13]_PORT_A_write_enable, Q1_q_b[13]_clock_0, , , Q1_q_b[13]_clock_enable_0); Q1_q_b[13]_PORT_B_read_enable = VCC; Q1_q_b[13]_PORT_B_read_enable_reg = DFFE(Q1_q_b[13]_PORT_B_read_enable, Q1_q_b[13]_clock_1, , , ); Q1_q_b[13]_clock_0 = S1__clk1; Q1_q_b[13]_clock_1 = S1__clk1; Q1_q_b[13]_clock_enable_0 = J1_sm; Q1_q_b[13]_PORT_B_data_out = MEMORY(Q1_q_b[13]_PORT_A_data_in_reg, , Q1_q_b[13]_PORT_A_address_reg, Q1_q_b[13]_PORT_B_address_reg, Q1_q_b[13]_PORT_A_write_enable_reg, Q1_q_b[13]_PORT_B_read_enable_reg, , , Q1_q_b[13]_clock_0, Q1_q_b[13]_clock_1, Q1_q_b[13]_clock_enable_0, , , ); Q1_q_b[13]_PORT_B_data_out_reg = DFFE(Q1_q_b[13]_PORT_B_data_out, Q1_q_b[13]_clock_1, , , ); Q1_q_b[13] = Q1_q_b[13]_PORT_B_data_out_reg[0]; --Q1_q_b[29] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[29] Q1_q_b[13]_PORT_A_data_in = J1_PAADC_MuxA_0; Q1_q_b[13]_PORT_A_data_in_reg = DFFE(Q1_q_b[13]_PORT_A_data_in, Q1_q_b[13]_clock_0, , , Q1_q_b[13]_clock_enable_0); Q1_q_b[13]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[13]_PORT_A_address_reg = DFFE(Q1_q_b[13]_PORT_A_address, Q1_q_b[13]_clock_0, , , Q1_q_b[13]_clock_enable_0); Q1_q_b[13]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[13]_PORT_B_address_reg = DFFE(Q1_q_b[13]_PORT_B_address, Q1_q_b[13]_clock_1, , , ); Q1_q_b[13]_PORT_A_write_enable = VCC; Q1_q_b[13]_PORT_A_write_enable_reg = DFFE(Q1_q_b[13]_PORT_A_write_enable, Q1_q_b[13]_clock_0, , , Q1_q_b[13]_clock_enable_0); Q1_q_b[13]_PORT_B_read_enable = VCC; Q1_q_b[13]_PORT_B_read_enable_reg = DFFE(Q1_q_b[13]_PORT_B_read_enable, Q1_q_b[13]_clock_1, , , ); Q1_q_b[13]_clock_0 = S1__clk1; Q1_q_b[13]_clock_1 = S1__clk1; Q1_q_b[13]_clock_enable_0 = J1_sm; Q1_q_b[13]_PORT_B_data_out = MEMORY(Q1_q_b[13]_PORT_A_data_in_reg, , Q1_q_b[13]_PORT_A_address_reg, Q1_q_b[13]_PORT_B_address_reg, Q1_q_b[13]_PORT_A_write_enable_reg, Q1_q_b[13]_PORT_B_read_enable_reg, , , Q1_q_b[13]_clock_0, Q1_q_b[13]_clock_1, Q1_q_b[13]_clock_enable_0, , , ); Q1_q_b[13]_PORT_B_data_out_reg = DFFE(Q1_q_b[13]_PORT_B_data_out, Q1_q_b[13]_clock_1, , , ); Q1_q_b[29] = Q1_q_b[13]_PORT_B_data_out_reg[1]; --RB2_q1pass_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|q1pass_5 --operation mode is normal RB2_q1pass_5 = E1_NOT_sel_s_3 & (RB2_nx154 & (PB2_data_1p_m_5) # !RB2_nx154 & PB2_data_1p_m_6) # !E1_NOT_sel_s_3 & (PB2_data_1p_m_5); --RB2_modgen_gt_26_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|modgen_gt_26_nx56 --operation mode is normal RB2_modgen_gt_26_nx56 = E1_sel_p_2 & (E1_sel_p_1 # !E1_NOT_sel_p_0) # !E1_NOT_sel_p_3; --PB2_par_en is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|par_en --operation mode is normal PB2_par_en = PB2_we_p & PB2_nx152; --L1_adc_last_1_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_0 --operation mode is normal L1_adc_last_1_0_lut_out = R2_RDATA_0; L1_adc_last_1_0 = DFFEAS(L1_adc_last_1_0_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_0 --operation mode is normal L1_adc_last_3_0_lut_out = R2_RDATA_0; L1_adc_last_3_0 = DFFEAS(L1_adc_last_3_0_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_0 --operation mode is normal L1_adc_last_5_0_lut_out = R2_RDATA_0; L1_adc_last_5_0 = DFFEAS(L1_adc_last_5_0_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_0 --operation mode is normal L1_adc_last_7_0_lut_out = R2_RDATA_0; L1_adc_last_7_0 = DFFEAS(L1_adc_last_7_0_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_12 --operation mode is normal L1_NOT_climits_d_12_lut_out = !V1_request_19; L1_NOT_climits_d_12 = DFFEAS(L1_NOT_climits_d_12_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx462, , , , ); --L1_NOT_climits_a_12 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_12 --operation mode is normal L1_NOT_climits_a_12_lut_out = !V1_request_19; L1_NOT_climits_a_12 = DFFEAS(L1_NOT_climits_a_12_lut_out, S1__clk1, T1_chipRST_n, , L1_NOT_nx510, , , , ); --F1_bytes_rcvd_12 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_12 --operation mode is normal F1_bytes_rcvd_12_lut_out = F1_nx2231; F1_bytes_rcvd_12 = DFFEAS(F1_bytes_rcvd_12_lut_out, S1__clk1, VCC, , F1_NOT_nx2217, , , , ); --K1_adc_last_1_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_0 --operation mode is normal K1_adc_last_1_0_lut_out = R1_RDATA_0; K1_adc_last_1_0 = DFFEAS(K1_adc_last_1_0_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_0 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_0 --operation mode is normal K1_adc_last_3_0_lut_out = R1_RDATA_0; K1_adc_last_3_0 = DFFEAS(K1_adc_last_3_0_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --J1_wdata_ram_12 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|wdata_ram_12 --operation mode is normal J1_wdata_ram_12_lut_out = PAADC_OVR; J1_wdata_ram_12 = DFFEAS(J1_wdata_ram_12_lut_out, S1__clk1, VCC, , , , , , ); --PB2_data_1p_m_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_5 --operation mode is normal PB2_data_1p_m_5 = E1_or_mask_5 # !E1_NOT_and_mask_5 & (E1_NOT_xor_mask_5 $ !TB2_q_5); --RB2_modgen_gt_15_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|modgen_gt_15_nx56 --operation mode is normal RB2_modgen_gt_15_nx56 = E1_sel_s_2 & (E1_sel_s_1 # E1_sel_s_0) # !E1_NOT_sel_s_3; --R2_RDATA_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_11 --operation mode is normal R2_RDATA_11_lut_out = R2_RDATA_10; R2_RDATA_11 = DFFEAS(R2_RDATA_11_lut_out, S1__clk1, VCC, , R2_NOT_nx295, , , , ); --TB2_q_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_4 --operation mode is normal TB2_q_4_lut_out = WT_P4D[4]; TB2_q_4 = DFFEAS(TB2_q_4_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --AB2_ob_data_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_11 --operation mode is normal AB2_ob_data_11_lut_out = AB2_ob_data_10; AB2_ob_data_11 = DFFEAS(AB2_ob_data_11_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_11, , , AB2_a_2); --LB2_d_to_dll_12 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_12 --operation mode is normal LB2_d_to_dll_12 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_12 # !DB4_data_out_0 & (T1_reply_12)); --AB1_ob_data_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_10 --operation mode is normal AB1_ob_data_10_lut_out = AB1_ob_data_9; AB1_ob_data_10 = DFFEAS(AB1_ob_data_10_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_10, , , AB1_a_2); --LB1_d_to_dll_11 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_11 --operation mode is normal LB1_d_to_dll_11 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_11 # !DB3_data_out_0 & (T1_reply_11)); --T1_reply_12 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_12 --operation mode is normal T1_reply_12 = V1_request_12 & (T1_a_0_dup_53 # T1_read_data_19 & !T1_ix34_ix30_nx12) # !V1_request_12 & T1_read_data_19 & (!T1_ix34_ix30_nx12); --T1_read_data_18 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_18 --operation mode is normal T1_read_data_18_lut_out = H1_bus_dout_18; T1_read_data_18 = DFFEAS(T1_read_data_18_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_17 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_17 --operation mode is normal H1_bus_dout_17 = H1_nx177 # H1_nx178 # E1_rdata_17 & H1_sel_0; --E1_rdata_16 is ni2io_wt:wt_ni|rdata_16 --operation mode is normal E1_rdata_16 = V1_request_37 & UB1_q_b[8] # !V1_request_37 & (E1_nx333 # E1_nx334); --H1_nx179 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx179 --operation mode is normal H1_nx179 = L1_RDATA_16 & (H1_ce_sc_adc # F1_RDATA_16 & H1_ce_dds) # !L1_RDATA_16 & F1_RDATA_16 & H1_ce_dds; --H1_nx180 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx180 --operation mode is normal H1_nx180 = K1_RDATA_16 & (H1_ce_psply_adc # J1_RDATA_16 & H1_ce_pasa_adc) # !K1_RDATA_16 & J1_RDATA_16 & (H1_ce_pasa_adc); --UB2_q_b[7] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[7] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 4096, Port A Width: 1, Port B Depth: 2048, Port B Width: 2 --Port A Logical Depth: 4096, Port A Logical Width: 8, Port B Logical Depth: 2048, Port B Logical Width: 16 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered UB2_q_b[7]_PORT_A_data_in = RB2_dout_7; UB2_q_b[7]_PORT_A_data_in_reg = DFFE(UB2_q_b[7]_PORT_A_data_in, UB2_q_b[7]_clock_0, UB2_q_b[7]_clear_0, , UB2_q_b[7]_clock_enable_0); UB2_q_b[7]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[7]_PORT_A_address_reg = DFFE(UB2_q_b[7]_PORT_A_address, UB2_q_b[7]_clock_0, UB2_q_b[7]_clear_0, , UB2_q_b[7]_clock_enable_0); UB2_q_b[7]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[7]_PORT_B_address_reg = DFFE(UB2_q_b[7]_PORT_B_address, UB2_q_b[7]_clock_1, , , ); UB2_q_b[7]_PORT_A_write_enable = VCC; UB2_q_b[7]_PORT_A_write_enable_reg = DFFE(UB2_q_b[7]_PORT_A_write_enable, UB2_q_b[7]_clock_0, UB2_q_b[7]_clear_0, , UB2_q_b[7]_clock_enable_0); UB2_q_b[7]_PORT_B_read_enable = VCC; UB2_q_b[7]_PORT_B_read_enable_reg = DFFE(UB2_q_b[7]_PORT_B_read_enable, UB2_q_b[7]_clock_1, , , ); UB2_q_b[7]_clock_0 = WT_STR; UB2_q_b[7]_clock_1 = S1__clk1; UB2_q_b[7]_clock_enable_0 = PB2_we_p; UB2_q_b[7]_clear_0 = !E1_NOT_clear; UB2_q_b[7]_PORT_B_data_out = MEMORY(UB2_q_b[7]_PORT_A_data_in_reg, , UB2_q_b[7]_PORT_A_address_reg, UB2_q_b[7]_PORT_B_address_reg, UB2_q_b[7]_PORT_A_write_enable_reg, UB2_q_b[7]_PORT_B_read_enable_reg, , , UB2_q_b[7]_clock_0, UB2_q_b[7]_clock_1, UB2_q_b[7]_clock_enable_0, , UB2_q_b[7]_clear_0, ); UB2_q_b[7]_PORT_B_data_out_reg = DFFE(UB2_q_b[7]_PORT_B_data_out, UB2_q_b[7]_clock_1, , , ); UB2_q_b[7] = UB2_q_b[7]_PORT_B_data_out_reg[0]; --UB2_q_b[15] is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_dpram:dpram|altsyncram:altsyncram_component|altsyncram_oj71:auto_generated|q_b[15] UB2_q_b[7]_PORT_A_data_in = RB2_dout_7; UB2_q_b[7]_PORT_A_data_in_reg = DFFE(UB2_q_b[7]_PORT_A_data_in, UB2_q_b[7]_clock_0, UB2_q_b[7]_clear_0, , UB2_q_b[7]_clock_enable_0); UB2_q_b[7]_PORT_A_address = BUS(SB4_Q_0, SB4_Q_1, SB4_Q_2, SB4_Q_3, SB4_Q_4, SB4_Q_5, SB4_Q_6, SB4_Q_7, SB4_Q_8, SB4_Q_9, SB4_Q_10, SB4_Q_11); UB2_q_b[7]_PORT_A_address_reg = DFFE(UB2_q_b[7]_PORT_A_address, UB2_q_b[7]_clock_0, UB2_q_b[7]_clear_0, , UB2_q_b[7]_clock_enable_0); UB2_q_b[7]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40, V1_request_39, V1_request_38); UB2_q_b[7]_PORT_B_address_reg = DFFE(UB2_q_b[7]_PORT_B_address, UB2_q_b[7]_clock_1, , , ); UB2_q_b[7]_PORT_A_write_enable = VCC; UB2_q_b[7]_PORT_A_write_enable_reg = DFFE(UB2_q_b[7]_PORT_A_write_enable, UB2_q_b[7]_clock_0, UB2_q_b[7]_clear_0, , UB2_q_b[7]_clock_enable_0); UB2_q_b[7]_PORT_B_read_enable = VCC; UB2_q_b[7]_PORT_B_read_enable_reg = DFFE(UB2_q_b[7]_PORT_B_read_enable, UB2_q_b[7]_clock_1, , , ); UB2_q_b[7]_clock_0 = WT_STR; UB2_q_b[7]_clock_1 = S1__clk1; UB2_q_b[7]_clock_enable_0 = PB2_we_p; UB2_q_b[7]_clear_0 = !E1_NOT_clear; UB2_q_b[7]_PORT_B_data_out = MEMORY(UB2_q_b[7]_PORT_A_data_in_reg, , UB2_q_b[7]_PORT_A_address_reg, UB2_q_b[7]_PORT_B_address_reg, UB2_q_b[7]_PORT_A_write_enable_reg, UB2_q_b[7]_PORT_B_read_enable_reg, , , UB2_q_b[7]_clock_0, UB2_q_b[7]_clock_1, UB2_q_b[7]_clock_enable_0, , UB2_q_b[7]_clear_0, ); UB2_q_b[7]_PORT_B_data_out_reg = DFFE(UB2_q_b[7]_PORT_B_data_out, UB2_q_b[7]_clock_1, , , ); UB2_q_b[15] = UB2_q_b[7]_PORT_B_data_out_reg[1]; --E1_nx331 is ni2io_wt:wt_ni|nx331 --operation mode is normal E1_nx331 = !V1_request_47 & V1_request_48 & !E1_NOT_and_mask_5; --E1_nx332 is ni2io_wt:wt_ni|nx332 --operation mode is normal E1_nx332 = V1_request_47 & (V1_request_48 & (SB3_Q_3) # !V1_request_48 & SB4_Q_3); --L1_RDATA_15 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_15 --operation mode is normal L1_RDATA_15 = L1_nx844 # L1_nx845 # L1_nx846; --F1_RDATA_15 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_15 --operation mode is normal F1_RDATA_15 = F1_nx813 # F1_nx858 # F1_bytes2send_47 & F1_a_3; --K1_RDATA_15 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_15 --operation mode is normal K1_RDATA_15 = K1_nx927 # K1_nx928 # K1_nx929; --J1_RDATA_15 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_15 --operation mode is normal J1_RDATA_15 = !V1_request_38 & Q1_q_b[15]; --RB2_dout_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|dout_6 --operation mode is normal RB2_dout_6 = RB2_modgen_gt_22_nx56 & (RB2_q1pass_6) # !RB2_modgen_gt_22_nx56 & RB2_q1pass_7; --SB3_Q_2 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_2 --operation mode is arithmetic SB3_Q_2_carry_eqn = SB3_Q_nx16; SB3_Q_2_lut_out = SB3_Q_2 $ (!SB3_Q_2_carry_eqn); SB3_Q_2 = DFFEAS(SB3_Q_2_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx22 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx22 --operation mode is arithmetic SB3_Q_nx22 = CARRY(SB3_Q_2 & (!SB3_Q_nx16)); --L1_nx847 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx847 --operation mode is normal L1_nx847 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_2) # !V1_request_48 & L1_adc_last_1_2); --L1_nx848 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx848 --operation mode is normal L1_nx848 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_2) # !V1_request_48 & L1_adc_last_5_2); --L1_nx849 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx849 --operation mode is normal L1_nx849 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_14 # !V1_request_48 & (!L1_NOT_climits_a_14)); --F1_nx814 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx814 --operation mode is normal F1_nx814 = F1_bytes2send_14 & (F1_a_1 # F1_bytes_rcvd_14 & F1_nx785) # !F1_bytes2send_14 & F1_bytes_rcvd_14 & (F1_nx785); --F1_nx857 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx857 --operation mode is normal F1_nx857 = !V1_request_46 & V1_request_47 & V1_request_48 & F1_bytes_rcvd_46; --K1_nx930 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx930 --operation mode is normal K1_nx930 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_2) # !V1_request_48 & K1_adc_last_1_2); --K1_nx931 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx931 --operation mode is normal K1_nx931 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_2) # !V1_request_48 & K1_adc_last_5_2); --K1_nx932 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx932 --operation mode is normal K1_nx932 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_14 # !V1_request_48 & (!K1_NOT_climits_a_14)); --Q1_q_b[14] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[14] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[14]_PORT_A_data_in = J1_PAADC_MuxA_1; Q1_q_b[14]_PORT_A_data_in_reg = DFFE(Q1_q_b[14]_PORT_A_data_in, Q1_q_b[14]_clock_0, , , Q1_q_b[14]_clock_enable_0); Q1_q_b[14]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[14]_PORT_A_address_reg = DFFE(Q1_q_b[14]_PORT_A_address, Q1_q_b[14]_clock_0, , , Q1_q_b[14]_clock_enable_0); Q1_q_b[14]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[14]_PORT_B_address_reg = DFFE(Q1_q_b[14]_PORT_B_address, Q1_q_b[14]_clock_1, , , ); Q1_q_b[14]_PORT_A_write_enable = VCC; Q1_q_b[14]_PORT_A_write_enable_reg = DFFE(Q1_q_b[14]_PORT_A_write_enable, Q1_q_b[14]_clock_0, , , Q1_q_b[14]_clock_enable_0); Q1_q_b[14]_PORT_B_read_enable = VCC; Q1_q_b[14]_PORT_B_read_enable_reg = DFFE(Q1_q_b[14]_PORT_B_read_enable, Q1_q_b[14]_clock_1, , , ); Q1_q_b[14]_clock_0 = S1__clk1; Q1_q_b[14]_clock_1 = S1__clk1; Q1_q_b[14]_clock_enable_0 = J1_sm; Q1_q_b[14]_PORT_B_data_out = MEMORY(Q1_q_b[14]_PORT_A_data_in_reg, , Q1_q_b[14]_PORT_A_address_reg, Q1_q_b[14]_PORT_B_address_reg, Q1_q_b[14]_PORT_A_write_enable_reg, Q1_q_b[14]_PORT_B_read_enable_reg, , , Q1_q_b[14]_clock_0, Q1_q_b[14]_clock_1, Q1_q_b[14]_clock_enable_0, , , ); Q1_q_b[14]_PORT_B_data_out_reg = DFFE(Q1_q_b[14]_PORT_B_data_out, Q1_q_b[14]_clock_1, , , ); Q1_q_b[14] = Q1_q_b[14]_PORT_B_data_out_reg[0]; --Q1_q_b[30] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[30] Q1_q_b[14]_PORT_A_data_in = J1_PAADC_MuxA_1; Q1_q_b[14]_PORT_A_data_in_reg = DFFE(Q1_q_b[14]_PORT_A_data_in, Q1_q_b[14]_clock_0, , , Q1_q_b[14]_clock_enable_0); Q1_q_b[14]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[14]_PORT_A_address_reg = DFFE(Q1_q_b[14]_PORT_A_address, Q1_q_b[14]_clock_0, , , Q1_q_b[14]_clock_enable_0); Q1_q_b[14]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[14]_PORT_B_address_reg = DFFE(Q1_q_b[14]_PORT_B_address, Q1_q_b[14]_clock_1, , , ); Q1_q_b[14]_PORT_A_write_enable = VCC; Q1_q_b[14]_PORT_A_write_enable_reg = DFFE(Q1_q_b[14]_PORT_A_write_enable, Q1_q_b[14]_clock_0, , , Q1_q_b[14]_clock_enable_0); Q1_q_b[14]_PORT_B_read_enable = VCC; Q1_q_b[14]_PORT_B_read_enable_reg = DFFE(Q1_q_b[14]_PORT_B_read_enable, Q1_q_b[14]_clock_1, , , ); Q1_q_b[14]_clock_0 = S1__clk1; Q1_q_b[14]_clock_1 = S1__clk1; Q1_q_b[14]_clock_enable_0 = J1_sm; Q1_q_b[14]_PORT_B_data_out = MEMORY(Q1_q_b[14]_PORT_A_data_in_reg, , Q1_q_b[14]_PORT_A_address_reg, Q1_q_b[14]_PORT_B_address_reg, Q1_q_b[14]_PORT_A_write_enable_reg, Q1_q_b[14]_PORT_B_read_enable_reg, , , Q1_q_b[14]_clock_0, Q1_q_b[14]_clock_1, Q1_q_b[14]_clock_enable_0, , , ); Q1_q_b[14]_PORT_B_data_out_reg = DFFE(Q1_q_b[14]_PORT_B_data_out, Q1_q_b[14]_clock_1, , , ); Q1_q_b[30] = Q1_q_b[14]_PORT_B_data_out_reg[1]; --RB2_q1pass_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|q1pass_6 --operation mode is normal RB2_q1pass_6 = RB2_modgen_gt_13_nx56 & (PB2_data_1p_m_6) # !RB2_modgen_gt_13_nx56 & PB2_data_1p_m_7; --RB2_nx153 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx153 --operation mode is normal RB2_nx153 = E1_sel_p_2 & E1_sel_p_1; --L1_adc_last_1_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_1 --operation mode is normal L1_adc_last_1_1_lut_out = R2_RDATA_1; L1_adc_last_1_1 = DFFEAS(L1_adc_last_1_1_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_1 --operation mode is normal L1_adc_last_3_1_lut_out = R2_RDATA_1; L1_adc_last_3_1 = DFFEAS(L1_adc_last_3_1_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_1 --operation mode is normal L1_adc_last_5_1_lut_out = R2_RDATA_1; L1_adc_last_5_1 = DFFEAS(L1_adc_last_5_1_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_1 --operation mode is normal L1_adc_last_7_1_lut_out = R2_RDATA_1; L1_adc_last_7_1 = DFFEAS(L1_adc_last_7_1_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_13 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_13 --operation mode is normal L1_NOT_climits_d_13_lut_out = L1_NOT_climits_d_13; L1_NOT_climits_d_13 = DFFEAS(L1_NOT_climits_d_13_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L541, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_13 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_13 --operation mode is normal L1_NOT_climits_a_13_lut_out = L1_NOT_climits_a_13; L1_NOT_climits_a_13 = DFFEAS(L1_NOT_climits_a_13_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L541, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_13 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_13 --operation mode is normal F1_bytes_rcvd_13_lut_out = F1_nx2227; F1_bytes_rcvd_13 = DFFEAS(F1_bytes_rcvd_13_lut_out, S1__clk1, VCC, , F1_NOT_nx2217, , , , ); --K1_adc_last_1_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_1 --operation mode is normal K1_adc_last_1_1_lut_out = R1_RDATA_1; K1_adc_last_1_1 = DFFEAS(K1_adc_last_1_1_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_1 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_1 --operation mode is normal K1_adc_last_3_1_lut_out = R1_RDATA_1; K1_adc_last_3_1 = DFFEAS(K1_adc_last_3_1_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --PB2_data_1p_m_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_6 --operation mode is normal PB2_data_1p_m_6 = E1_or_mask_6 # !E1_NOT_and_mask_6 & (E1_NOT_xor_mask_6 $ !TB2_q_6); --RB2_nx154 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx154 --operation mode is normal RB2_nx154 = E1_sel_s_2 & E1_sel_s_1; --PB2_nx152 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|nx152 --operation mode is normal PB2_nx152 = PB2_modgen_xor_1035_nx14 $ PB2_modgen_xor_1035_nx18 $ RB2_dout_7 $ RB2_prty_bit; --L1_NOT_nx2213 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx2213 --operation mode is normal L1_NOT_nx2213 = L1_sm_4 & !L1_counter_2 & !L1_counter_1 & L1_counter_0; --L1_NOT_nx2261 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx2261 --operation mode is normal L1_NOT_nx2261 = L1_sm_4 & !L1_counter_2 & L1_counter_1 & L1_counter_0; --L1_NOT_nx2309 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_nx2309 --operation mode is normal L1_NOT_nx2309 = L1_sm_4 & L1_counter_2 & !L1_counter_1 & L1_counter_0; --K1_NOT_nx2213 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx2213 --operation mode is normal K1_NOT_nx2213 = K1_sm_4 & !K1_counter_2 & !K1_counter_1 & K1_counter_0; --K1_NOT_nx2261 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|NOT_nx2261 --operation mode is normal K1_NOT_nx2261 = K1_sm_4 & !K1_counter_2 & K1_counter_1 & K1_counter_0; --TB2_q_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_5 --operation mode is normal TB2_q_5_lut_out = WT_P4D[5]; TB2_q_5 = DFFEAS(TB2_q_5_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --AB2_ob_data_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_10 --operation mode is normal AB2_ob_data_10_lut_out = AB2_ob_data_9; AB2_ob_data_10 = DFFEAS(AB2_ob_data_10_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_10, , , AB2_a_2); --LB2_d_to_dll_11 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_11 --operation mode is normal LB2_d_to_dll_11 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_11 # !DB4_data_out_0 & (T1_reply_11)); --AB1_ob_data_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_9 --operation mode is normal AB1_ob_data_9_lut_out = AB1_ob_data_8; AB1_ob_data_9 = DFFEAS(AB1_ob_data_9_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_9, , , AB1_a_2); --LB1_d_to_dll_10 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_10 --operation mode is normal LB1_d_to_dll_10 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_10 # !DB3_data_out_0 & (T1_reply_10)); --T1_reply_11 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_11 --operation mode is normal T1_reply_11 = V1_request_11 & (T1_a_0_dup_53 # T1_read_data_20 & !T1_ix34_ix30_nx12) # !V1_request_11 & T1_read_data_20 & (!T1_ix34_ix30_nx12); --T1_read_data_19 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_19 --operation mode is normal T1_read_data_19_lut_out = H1_bus_dout_19; T1_read_data_19 = DFFEAS(T1_read_data_19_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_18 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_18 --operation mode is normal H1_bus_dout_18 = H1_nx175 # H1_nx176 # E1_rdata_18 & H1_sel_0; --E1_rdata_17 is ni2io_wt:wt_ni|rdata_17 --operation mode is normal E1_rdata_17 = V1_request_37 & UB1_q_b[9] # !V1_request_37 & (E1_nx335 # E1_nx336); --H1_nx177 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx177 --operation mode is normal H1_nx177 = L1_RDATA_17 & (H1_ce_sc_adc # F1_RDATA_17 & H1_ce_dds) # !L1_RDATA_17 & F1_RDATA_17 & H1_ce_dds; --H1_nx178 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx178 --operation mode is normal H1_nx178 = K1_RDATA_17 & (H1_ce_psply_adc # J1_RDATA_17 & H1_ce_pasa_adc) # !K1_RDATA_17 & J1_RDATA_17 & (H1_ce_pasa_adc); --E1_nx333 is ni2io_wt:wt_ni|nx333 --operation mode is normal E1_nx333 = !V1_request_47 & V1_request_48 & !E1_NOT_and_mask_6; --E1_nx334 is ni2io_wt:wt_ni|nx334 --operation mode is normal E1_nx334 = V1_request_47 & (V1_request_48 & (SB3_Q_4) # !V1_request_48 & SB4_Q_4); --L1_RDATA_16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_16 --operation mode is normal L1_RDATA_16 = L1_nx841 # L1_nx842 # L1_nx843; --F1_RDATA_16 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_16 --operation mode is normal F1_RDATA_16 = F1_nx812 # F1_bytes2send_16 & F1_a_1; --K1_RDATA_16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_16 --operation mode is normal K1_RDATA_16 = K1_nx924 # K1_nx925 # K1_nx926; --J1_RDATA_16 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_16 --operation mode is normal J1_RDATA_16 = !V1_request_38 & Q1_q_b[16]; --RB2_dout_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|dout_7 --operation mode is normal RB2_dout_7 = E1_NOT_sel_p_3 & RB2_q1pass_8 # !E1_NOT_sel_p_3 & (RB2_q1pass_7); --SB3_Q_3 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_3 --operation mode is arithmetic SB3_Q_3_carry_eqn = SB3_Q_nx22; SB3_Q_3_lut_out = SB3_Q_3 $ (SB3_Q_3_carry_eqn); SB3_Q_3 = DFFEAS(SB3_Q_3_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx28 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx28 --operation mode is arithmetic SB3_Q_nx28 = CARRY(!SB3_Q_nx22 # !SB3_Q_3); --L1_nx844 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx844 --operation mode is normal L1_nx844 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_3) # !V1_request_48 & L1_adc_last_1_3); --L1_nx845 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx845 --operation mode is normal L1_nx845 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_3) # !V1_request_48 & L1_adc_last_5_3); --L1_nx846 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx846 --operation mode is normal L1_nx846 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_15 # !V1_request_48 & (!L1_NOT_climits_a_15)); --F1_nx813 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx813 --operation mode is normal F1_nx813 = F1_bytes2send_15 & (F1_a_1 # F1_bytes_rcvd_15 & F1_nx785) # !F1_bytes2send_15 & F1_bytes_rcvd_15 & (F1_nx785); --F1_nx858 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx858 --operation mode is normal F1_nx858 = !V1_request_46 & V1_request_47 & V1_request_48 & F1_bytes_rcvd_47; --K1_nx927 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx927 --operation mode is normal K1_nx927 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_3) # !V1_request_48 & K1_adc_last_1_3); --K1_nx928 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx928 --operation mode is normal K1_nx928 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_3) # !V1_request_48 & K1_adc_last_5_3); --K1_nx929 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx929 --operation mode is normal K1_nx929 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_15 # !V1_request_48 & (!K1_NOT_climits_a_15)); --Q1_q_b[15] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[15] --RAM Block Operation Mode: Simple Dual-Port --Port A Depth: 1024, Port A Width: 1, Port B Depth: 512, Port B Width: 2 --Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 32 --Port A Input: Registered, Port B Input: Registered, Port B Output: Registered Q1_q_b[15]_PORT_A_data_in = ~GND; Q1_q_b[15]_PORT_A_data_in_reg = DFFE(Q1_q_b[15]_PORT_A_data_in, Q1_q_b[15]_clock_0, , , Q1_q_b[15]_clock_enable_0); Q1_q_b[15]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[15]_PORT_A_address_reg = DFFE(Q1_q_b[15]_PORT_A_address, Q1_q_b[15]_clock_0, , , Q1_q_b[15]_clock_enable_0); Q1_q_b[15]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[15]_PORT_B_address_reg = DFFE(Q1_q_b[15]_PORT_B_address, Q1_q_b[15]_clock_1, , , ); Q1_q_b[15]_PORT_A_write_enable = VCC; Q1_q_b[15]_PORT_A_write_enable_reg = DFFE(Q1_q_b[15]_PORT_A_write_enable, Q1_q_b[15]_clock_0, , , Q1_q_b[15]_clock_enable_0); Q1_q_b[15]_PORT_B_read_enable = VCC; Q1_q_b[15]_PORT_B_read_enable_reg = DFFE(Q1_q_b[15]_PORT_B_read_enable, Q1_q_b[15]_clock_1, , , ); Q1_q_b[15]_clock_0 = S1__clk1; Q1_q_b[15]_clock_1 = S1__clk1; Q1_q_b[15]_clock_enable_0 = J1_sm; Q1_q_b[15]_PORT_B_data_out = MEMORY(Q1_q_b[15]_PORT_A_data_in_reg, , Q1_q_b[15]_PORT_A_address_reg, Q1_q_b[15]_PORT_B_address_reg, Q1_q_b[15]_PORT_A_write_enable_reg, Q1_q_b[15]_PORT_B_read_enable_reg, , , Q1_q_b[15]_clock_0, Q1_q_b[15]_clock_1, Q1_q_b[15]_clock_enable_0, , , ); Q1_q_b[15]_PORT_B_data_out_reg = DFFE(Q1_q_b[15]_PORT_B_data_out, Q1_q_b[15]_clock_1, , , ); Q1_q_b[15] = Q1_q_b[15]_PORT_B_data_out_reg[0]; --Q1_q_b[31] is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_hl61:auto_generated|q_b[31] Q1_q_b[15]_PORT_A_data_in = ~GND; Q1_q_b[15]_PORT_A_data_in_reg = DFFE(Q1_q_b[15]_PORT_A_data_in, Q1_q_b[15]_clock_0, , , Q1_q_b[15]_clock_enable_0); Q1_q_b[15]_PORT_A_address = BUS(J1_samples_0, J1_samples_1, J1_samples_2, J1_samples_3, J1_samples_4, J1_samples_5, J1_samples_6, J1_samples_7, J1_samples_8, J1_samples_9); Q1_q_b[15]_PORT_A_address_reg = DFFE(Q1_q_b[15]_PORT_A_address, Q1_q_b[15]_clock_0, , , Q1_q_b[15]_clock_enable_0); Q1_q_b[15]_PORT_B_address = BUS(V1_request_48, V1_request_47, V1_request_46, V1_request_45, V1_request_44, V1_request_43, V1_request_42, V1_request_41, V1_request_40); Q1_q_b[15]_PORT_B_address_reg = DFFE(Q1_q_b[15]_PORT_B_address, Q1_q_b[15]_clock_1, , , ); Q1_q_b[15]_PORT_A_write_enable = VCC; Q1_q_b[15]_PORT_A_write_enable_reg = DFFE(Q1_q_b[15]_PORT_A_write_enable, Q1_q_b[15]_clock_0, , , Q1_q_b[15]_clock_enable_0); Q1_q_b[15]_PORT_B_read_enable = VCC; Q1_q_b[15]_PORT_B_read_enable_reg = DFFE(Q1_q_b[15]_PORT_B_read_enable, Q1_q_b[15]_clock_1, , , ); Q1_q_b[15]_clock_0 = S1__clk1; Q1_q_b[15]_clock_1 = S1__clk1; Q1_q_b[15]_clock_enable_0 = J1_sm; Q1_q_b[15]_PORT_B_data_out = MEMORY(Q1_q_b[15]_PORT_A_data_in_reg, , Q1_q_b[15]_PORT_A_address_reg, Q1_q_b[15]_PORT_B_address_reg, Q1_q_b[15]_PORT_A_write_enable_reg, Q1_q_b[15]_PORT_B_read_enable_reg, , , Q1_q_b[15]_clock_0, Q1_q_b[15]_clock_1, Q1_q_b[15]_clock_enable_0, , , ); Q1_q_b[15]_PORT_B_data_out_reg = DFFE(Q1_q_b[15]_PORT_B_data_out, Q1_q_b[15]_clock_1, , , ); Q1_q_b[31] = Q1_q_b[15]_PORT_B_data_out_reg[1]; --RB2_q1pass_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|q1pass_7 --operation mode is normal RB2_q1pass_7 = E1_NOT_sel_s_3 & PB2_data_1p_m_8 # !E1_NOT_sel_s_3 & (PB2_data_1p_m_7); --RB2_modgen_gt_22_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|modgen_gt_22_nx56 --operation mode is normal RB2_modgen_gt_22_nx56 = E1_sel_p_2 & E1_sel_p_1 & !E1_NOT_sel_p_0 # !E1_NOT_sel_p_3; --L1_adc_last_1_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_2 --operation mode is normal L1_adc_last_1_2_lut_out = R2_RDATA_2; L1_adc_last_1_2 = DFFEAS(L1_adc_last_1_2_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_2 --operation mode is normal L1_adc_last_3_2_lut_out = R2_RDATA_2; L1_adc_last_3_2 = DFFEAS(L1_adc_last_3_2_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_2 --operation mode is normal L1_adc_last_5_2_lut_out = R2_RDATA_2; L1_adc_last_5_2 = DFFEAS(L1_adc_last_5_2_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_2 --operation mode is normal L1_adc_last_7_2_lut_out = R2_RDATA_2; L1_adc_last_7_2 = DFFEAS(L1_adc_last_7_2_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_14 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_14 --operation mode is normal L1_NOT_climits_d_14_lut_out = L1_NOT_climits_d_14; L1_NOT_climits_d_14 = DFFEAS(L1_NOT_climits_d_14_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L341, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_14 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_14 --operation mode is normal L1_NOT_climits_a_14_lut_out = L1_NOT_climits_a_14; L1_NOT_climits_a_14 = DFFEAS(L1_NOT_climits_a_14_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L341, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_14 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_14 --operation mode is normal F1_bytes_rcvd_14_lut_out = F1_nx2223; F1_bytes_rcvd_14 = DFFEAS(F1_bytes_rcvd_14_lut_out, S1__clk1, VCC, , F1_NOT_nx2217, , , , ); --K1_adc_last_1_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_2 --operation mode is normal K1_adc_last_1_2_lut_out = R1_RDATA_2; K1_adc_last_1_2 = DFFEAS(K1_adc_last_1_2_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_2 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_2 --operation mode is normal K1_adc_last_3_2_lut_out = R1_RDATA_2; K1_adc_last_3_2 = DFFEAS(K1_adc_last_3_2_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --PB2_data_1p_m_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_7 --operation mode is normal PB2_data_1p_m_7 = E1_or_mask_7 # !E1_NOT_and_mask_7 & (E1_NOT_xor_mask_7 $ !TB2_q_7); --RB2_modgen_gt_13_nx56 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|modgen_gt_13_nx56 --operation mode is normal RB2_modgen_gt_13_nx56 = E1_sel_s_2 & E1_sel_s_1 & E1_sel_s_0 # !E1_NOT_sel_s_3; --L1_NOT_ix37_ix7_nx8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_ix37_ix7_nx8 --operation mode is normal L1_NOT_ix37_ix7_nx8 = V1_request_46 & V1_request_47 & V1_request_48; --L1_nx10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx10 --operation mode is normal L1_nx10 = H1_ce_sc_adc & !T1_rd_wr_oase; --L1_NOT_ix37_ix9_nx8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_ix37_ix9_nx8 --operation mode is normal L1_NOT_ix37_ix9_nx8 = V1_request_46 & V1_request_47 & !V1_request_48; --TB2_q_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_6 --operation mode is normal TB2_q_6_lut_out = WT_P4D[6]; TB2_q_6 = DFFEAS(TB2_q_6_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --PB2_modgen_xor_1035_nx14 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|modgen_xor_1035_nx14 --operation mode is normal PB2_modgen_xor_1035_nx14 = RB2_dout_0 $ RB2_dout_1 $ RB2_dout_2 $ RB2_dout_3; --PB2_modgen_xor_1035_nx18 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|modgen_xor_1035_nx18 --operation mode is normal PB2_modgen_xor_1035_nx18 = RB2_dout_6 $ RB2_dout_5 $ RB2_dout_4; --RB2_prty_bit is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|prty_bit --operation mode is normal RB2_prty_bit = E1_NOT_sel_p_3 & (RB2_nx157 & RB2_nx158) # !E1_NOT_sel_p_3 & RB2_q1pass_8; --AB2_ob_data_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_9 --operation mode is normal AB2_ob_data_9_lut_out = AB2_ob_data_8; AB2_ob_data_9 = DFFEAS(AB2_ob_data_9_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_9, , , AB2_a_2); --LB2_d_to_dll_10 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_10 --operation mode is normal LB2_d_to_dll_10 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_10 # !DB4_data_out_0 & (T1_reply_10)); --AB1_ob_data_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_8 --operation mode is normal AB1_ob_data_8_lut_out = AB1_ob_data_7; AB1_ob_data_8 = DFFEAS(AB1_ob_data_8_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_8, , , AB1_a_2); --LB1_d_to_dll_9 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_9 --operation mode is normal LB1_d_to_dll_9 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_9 # !DB3_data_out_0 & (T1_reply_9)); --T1_reply_10 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_10 --operation mode is normal T1_reply_10 = V1_request_10 & (T1_a_0_dup_53 # T1_read_data_21 & !T1_ix34_ix30_nx12) # !V1_request_10 & T1_read_data_21 & (!T1_ix34_ix30_nx12); --T1_read_data_20 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_20 --operation mode is normal T1_read_data_20_lut_out = H1_bus_dout_20; T1_read_data_20 = DFFEAS(T1_read_data_20_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_19 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_19 --operation mode is normal H1_bus_dout_19 = H1_nx173 # H1_nx174 # E1_rdata_19 & H1_sel_0; --E1_rdata_18 is ni2io_wt:wt_ni|rdata_18 --operation mode is normal E1_rdata_18 = V1_request_37 & UB1_q_b[10] # !V1_request_37 & (E1_nx337 # E1_nx338); --H1_nx175 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx175 --operation mode is normal H1_nx175 = L1_RDATA_18 & (H1_ce_sc_adc # F1_RDATA_18 & H1_ce_dds) # !L1_RDATA_18 & F1_RDATA_18 & H1_ce_dds; --H1_nx176 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx176 --operation mode is normal H1_nx176 = K1_RDATA_18 & (H1_ce_psply_adc # J1_RDATA_18 & H1_ce_pasa_adc) # !K1_RDATA_18 & J1_RDATA_18 & (H1_ce_pasa_adc); --E1_nx335 is ni2io_wt:wt_ni|nx335 --operation mode is normal E1_nx335 = !V1_request_47 & V1_request_48 & !E1_NOT_and_mask_7; --E1_nx336 is ni2io_wt:wt_ni|nx336 --operation mode is normal E1_nx336 = V1_request_47 & (V1_request_48 & (SB3_Q_5) # !V1_request_48 & SB4_Q_5); --L1_RDATA_17 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_17 --operation mode is normal L1_RDATA_17 = L1_nx838 # L1_nx839 # L1_nx840; --F1_RDATA_17 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_17 --operation mode is normal F1_RDATA_17 = F1_nx811 # F1_bytes2send_17 & F1_a_1; --K1_RDATA_17 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_17 --operation mode is normal K1_RDATA_17 = K1_nx921 # K1_nx922 # K1_nx923; --J1_RDATA_17 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_17 --operation mode is normal J1_RDATA_17 = !V1_request_38 & Q1_q_b[17]; --SB3_Q_4 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_4 --operation mode is arithmetic SB3_Q_4_carry_eqn = SB3_Q_nx28; SB3_Q_4_lut_out = SB3_Q_4 $ (!SB3_Q_4_carry_eqn); SB3_Q_4 = DFFEAS(SB3_Q_4_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx34 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx34 --operation mode is arithmetic SB3_Q_nx34 = CARRY(SB3_Q_4 & (!SB3_Q_nx28)); --L1_nx841 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx841 --operation mode is normal L1_nx841 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_4) # !V1_request_48 & L1_adc_last_1_4); --L1_nx842 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx842 --operation mode is normal L1_nx842 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_4) # !V1_request_48 & L1_adc_last_5_4); --L1_nx843 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx843 --operation mode is normal L1_nx843 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_16 # !V1_request_48 & (!L1_NOT_climits_a_16)); --F1_nx812 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx812 --operation mode is normal F1_nx812 = F1_iword2send_0 & (F1_a_3 # F1_bytes_rcvd_16 & F1_nx785) # !F1_iword2send_0 & F1_bytes_rcvd_16 & F1_nx785; --K1_nx924 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx924 --operation mode is normal K1_nx924 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_4) # !V1_request_48 & K1_adc_last_1_4); --K1_nx925 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx925 --operation mode is normal K1_nx925 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_4) # !V1_request_48 & K1_adc_last_5_4); --K1_nx926 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx926 --operation mode is normal K1_nx926 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_16 # !V1_request_48 & (!K1_NOT_climits_a_16)); --RB2_q1pass_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|q1pass_8 --operation mode is normal RB2_q1pass_8 = E1_NOT_sel_s_3 & PB2_data_1p_m_9 # !E1_NOT_sel_s_3 & (RB2_modgen_gt_19_nx42 & (PB2_data_1p_m_8) # !RB2_modgen_gt_19_nx42 & PB2_data_1p_m_9); --L1_adc_last_1_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_3 --operation mode is normal L1_adc_last_1_3_lut_out = R2_RDATA_3; L1_adc_last_1_3 = DFFEAS(L1_adc_last_1_3_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_3 --operation mode is normal L1_adc_last_3_3_lut_out = R2_RDATA_3; L1_adc_last_3_3 = DFFEAS(L1_adc_last_3_3_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_3 --operation mode is normal L1_adc_last_5_3_lut_out = R2_RDATA_3; L1_adc_last_5_3 = DFFEAS(L1_adc_last_5_3_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_3 --operation mode is normal L1_adc_last_7_3_lut_out = R2_RDATA_3; L1_adc_last_7_3 = DFFEAS(L1_adc_last_7_3_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_15 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_15 --operation mode is normal L1_NOT_climits_d_15_lut_out = L1_NOT_climits_d_15; L1_NOT_climits_d_15 = DFFEAS(L1_NOT_climits_d_15_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L141, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_15 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_15 --operation mode is normal L1_NOT_climits_a_15_lut_out = L1_NOT_climits_a_15; L1_NOT_climits_a_15 = DFFEAS(L1_NOT_climits_a_15_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L141, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_15 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_15 --operation mode is normal F1_bytes_rcvd_15_lut_out = F1_nx2219; F1_bytes_rcvd_15 = DFFEAS(F1_bytes_rcvd_15_lut_out, S1__clk1, VCC, , F1_NOT_nx2217, , , , ); --K1_adc_last_1_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_3 --operation mode is normal K1_adc_last_1_3_lut_out = R1_RDATA_3; K1_adc_last_1_3 = DFFEAS(K1_adc_last_1_3_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_3 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_3 --operation mode is normal K1_adc_last_3_3_lut_out = R1_RDATA_3; K1_adc_last_3_3 = DFFEAS(K1_adc_last_3_3_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --PB2_data_1p_m_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_8 --operation mode is normal PB2_data_1p_m_8 = E1_or_mask_8 # !E1_NOT_and_mask_8 & (E1_NOT_xor_mask_8 $ !TB2_q_8); --TB2_q_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_7 --operation mode is normal TB2_q_7_lut_out = WT_P4D[7]; TB2_q_7 = DFFEAS(TB2_q_7_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --RB2_nx157 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx157 --operation mode is normal RB2_nx157 = E1_sel_p_2 # RB2_nx155 & (RB2_nx149 # !E1_sel_p_1); --RB2_nx158 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx158 --operation mode is normal RB2_nx158 = RB2_nx156 & (RB2_nx150 # !E1_sel_p_1) # !E1_sel_p_2; --AB2_ob_data_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_8 --operation mode is normal AB2_ob_data_8_lut_out = AB2_ob_data_7; AB2_ob_data_8 = DFFEAS(AB2_ob_data_8_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_8, , , AB2_a_2); --LB2_d_to_dll_9 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_9 --operation mode is normal LB2_d_to_dll_9 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_9 # !DB4_data_out_0 & (T1_reply_9)); --AB1_ob_data_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_7 --operation mode is normal AB1_ob_data_7_lut_out = AB1_ob_data_6; AB1_ob_data_7 = DFFEAS(AB1_ob_data_7_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_7, , , AB1_a_2); --LB1_d_to_dll_8 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_8 --operation mode is normal LB1_d_to_dll_8 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_8 # !DB3_data_out_0 & (T1_reply_8)); --T1_reply_9 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_9 --operation mode is normal T1_reply_9 = V1_request_9 & (T1_a_0_dup_53 # T1_read_data_22 & !T1_ix34_ix30_nx12) # !V1_request_9 & T1_read_data_22 & (!T1_ix34_ix30_nx12); --T1_read_data_21 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_21 --operation mode is normal T1_read_data_21_lut_out = H1_bus_dout_21; T1_read_data_21 = DFFEAS(T1_read_data_21_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_20 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_20 --operation mode is normal H1_bus_dout_20 = H1_nx171 # H1_nx172 # E1_rdata_20 & H1_sel_0; --E1_rdata_19 is ni2io_wt:wt_ni|rdata_19 --operation mode is normal E1_rdata_19 = V1_request_37 & UB1_q_b[11] # !V1_request_37 & (E1_nx339 # E1_nx340); --H1_nx173 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx173 --operation mode is normal H1_nx173 = L1_RDATA_19 & (H1_ce_sc_adc # F1_RDATA_19 & H1_ce_dds) # !L1_RDATA_19 & F1_RDATA_19 & H1_ce_dds; --H1_nx174 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx174 --operation mode is normal H1_nx174 = K1_RDATA_19 & (H1_ce_psply_adc # J1_RDATA_19 & H1_ce_pasa_adc) # !K1_RDATA_19 & J1_RDATA_19 & (H1_ce_pasa_adc); --E1_nx337 is ni2io_wt:wt_ni|nx337 --operation mode is normal E1_nx337 = !V1_request_47 & V1_request_48 & !E1_NOT_and_mask_8; --E1_nx338 is ni2io_wt:wt_ni|nx338 --operation mode is normal E1_nx338 = V1_request_47 & (V1_request_48 & (SB3_Q_6) # !V1_request_48 & SB4_Q_6); --L1_RDATA_18 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_18 --operation mode is normal L1_RDATA_18 = L1_nx835 # L1_nx836 # L1_nx837; --F1_RDATA_18 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_18 --operation mode is normal F1_RDATA_18 = F1_nx810 # F1_bytes2send_18 & F1_a_1; --K1_RDATA_18 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_18 --operation mode is normal K1_RDATA_18 = K1_nx918 # K1_nx919 # K1_nx920; --J1_RDATA_18 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_18 --operation mode is normal J1_RDATA_18 = !V1_request_38 & Q1_q_b[18]; --SB3_Q_5 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_5 --operation mode is arithmetic SB3_Q_5_carry_eqn = SB3_Q_nx34; SB3_Q_5_lut_out = SB3_Q_5 $ (SB3_Q_5_carry_eqn); SB3_Q_5 = DFFEAS(SB3_Q_5_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx40 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx40 --operation mode is arithmetic SB3_Q_nx40 = CARRY(!SB3_Q_nx34 # !SB3_Q_5); --L1_nx838 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx838 --operation mode is normal L1_nx838 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_5) # !V1_request_48 & L1_adc_last_1_5); --L1_nx839 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx839 --operation mode is normal L1_nx839 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_5) # !V1_request_48 & L1_adc_last_5_5); --L1_nx840 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx840 --operation mode is normal L1_nx840 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_17 # !V1_request_48 & (!L1_NOT_climits_a_17)); --F1_nx811 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx811 --operation mode is normal F1_nx811 = F1_iword2send_1 & (F1_a_3 # F1_bytes_rcvd_17 & F1_nx785) # !F1_iword2send_1 & F1_bytes_rcvd_17 & F1_nx785; --K1_nx921 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx921 --operation mode is normal K1_nx921 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_5) # !V1_request_48 & K1_adc_last_1_5); --K1_nx922 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx922 --operation mode is normal K1_nx922 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_5) # !V1_request_48 & K1_adc_last_5_5); --K1_nx923 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx923 --operation mode is normal K1_nx923 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_17 # !V1_request_48 & (!K1_NOT_climits_a_17)); --L1_adc_last_1_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_4 --operation mode is normal L1_adc_last_1_4_lut_out = R2_RDATA_4; L1_adc_last_1_4 = DFFEAS(L1_adc_last_1_4_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_4 --operation mode is normal L1_adc_last_3_4_lut_out = R2_RDATA_4; L1_adc_last_3_4 = DFFEAS(L1_adc_last_3_4_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_4 --operation mode is normal L1_adc_last_5_4_lut_out = R2_RDATA_4; L1_adc_last_5_4 = DFFEAS(L1_adc_last_5_4_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_4 --operation mode is normal L1_adc_last_7_4_lut_out = R2_RDATA_4; L1_adc_last_7_4 = DFFEAS(L1_adc_last_7_4_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_16 --operation mode is normal L1_NOT_climits_d_16_lut_out = L1_NOT_climits_d_16; L1_NOT_climits_d_16 = DFFEAS(L1_NOT_climits_d_16_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L931, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_16 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_16 --operation mode is normal L1_NOT_climits_a_16_lut_out = L1_NOT_climits_a_16; L1_NOT_climits_a_16 = DFFEAS(L1_NOT_climits_a_16_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L931, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_16 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_16 --operation mode is normal F1_bytes_rcvd_16_lut_out = F1_nx2247; F1_bytes_rcvd_16 = DFFEAS(F1_bytes_rcvd_16_lut_out, S1__clk1, VCC, , F1_NOT_nx2185, , , , ); --K1_adc_last_1_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_4 --operation mode is normal K1_adc_last_1_4_lut_out = R1_RDATA_4; K1_adc_last_1_4 = DFFEAS(K1_adc_last_1_4_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_4 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_4 --operation mode is normal K1_adc_last_3_4_lut_out = R1_RDATA_4; K1_adc_last_3_4 = DFFEAS(K1_adc_last_3_4_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --PB2_data_1p_m_9 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|data_1p_m_9 --operation mode is normal PB2_data_1p_m_9 = E1_or_mask_9 # !E1_NOT_and_mask_9 & (E1_NOT_xor_mask_9 $ !TB2_q_9); --TB2_q_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_8 --operation mode is normal TB2_q_8_lut_out = WT_P4D[8]; TB2_q_8 = DFFEAS(TB2_q_8_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --RB2_nx149 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx149 --operation mode is normal RB2_nx149 = E1_NOT_sel_p_0 & (RB2_q1pass_2) # !E1_NOT_sel_p_0 & RB2_q1pass_3; --RB2_nx155 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx155 --operation mode is normal RB2_nx155 = E1_sel_p_1 # E1_NOT_sel_p_0 & (RB2_q1pass_0) # !E1_NOT_sel_p_0 & RB2_q1pass_1; --RB2_nx150 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx150 --operation mode is normal RB2_nx150 = E1_NOT_sel_p_0 & (RB2_q1pass_6) # !E1_NOT_sel_p_0 & RB2_q1pass_7; --RB2_nx156 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|ni_exclude_in_10_4:ex_p|nx156 --operation mode is normal RB2_nx156 = E1_sel_p_1 # E1_NOT_sel_p_0 & (RB2_q1pass_4) # !E1_NOT_sel_p_0 & RB2_q1pass_5; --AB2_ob_data_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_7 --operation mode is normal AB2_ob_data_7_lut_out = AB2_ob_data_6; AB2_ob_data_7 = DFFEAS(AB2_ob_data_7_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_7, , , AB2_a_2); --LB2_d_to_dll_8 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_8 --operation mode is normal LB2_d_to_dll_8 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_8 # !DB4_data_out_0 & (T1_reply_8)); --AB1_ob_data_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_6 --operation mode is normal AB1_ob_data_6_lut_out = AB1_ob_data_5; AB1_ob_data_6 = DFFEAS(AB1_ob_data_6_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_6, , , AB1_a_2); --LB1_d_to_dll_7 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_7 --operation mode is normal LB1_d_to_dll_7 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_7 # !DB3_data_out_0 & (T1_reply_7)); --T1_reply_8 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_8 --operation mode is normal T1_reply_8 = V1_request_8 & (T1_a_0_dup_53 # T1_read_data_23 & !T1_ix34_ix30_nx12) # !V1_request_8 & T1_read_data_23 & (!T1_ix34_ix30_nx12); --T1_read_data_22 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_22 --operation mode is normal T1_read_data_22_lut_out = H1_bus_dout_22; T1_read_data_22 = DFFEAS(T1_read_data_22_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_21 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_21 --operation mode is normal H1_bus_dout_21 = H1_nx169 # H1_nx170 # E1_rdata_21 & H1_sel_0; --E1_rdata_20 is ni2io_wt:wt_ni|rdata_20 --operation mode is normal E1_rdata_20 = V1_request_37 & UB1_q_b[12] # !V1_request_37 & (E1_nx341 # E1_nx342); --H1_nx171 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx171 --operation mode is normal H1_nx171 = L1_RDATA_20 & (H1_ce_sc_adc # F1_RDATA_20 & H1_ce_dds) # !L1_RDATA_20 & F1_RDATA_20 & H1_ce_dds; --H1_nx172 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx172 --operation mode is normal H1_nx172 = K1_RDATA_20 & (H1_ce_psply_adc # J1_RDATA_20 & H1_ce_pasa_adc) # !K1_RDATA_20 & J1_RDATA_20 & (H1_ce_pasa_adc); --E1_nx339 is ni2io_wt:wt_ni|nx339 --operation mode is normal E1_nx339 = !V1_request_47 & V1_request_48 & !E1_NOT_and_mask_9; --E1_nx340 is ni2io_wt:wt_ni|nx340 --operation mode is normal E1_nx340 = V1_request_47 & (V1_request_48 & (SB3_Q_7) # !V1_request_48 & SB4_Q_7); --L1_RDATA_19 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_19 --operation mode is normal L1_RDATA_19 = L1_nx832 # L1_nx833 # L1_nx834; --F1_RDATA_19 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_19 --operation mode is normal F1_RDATA_19 = F1_nx809 # F1_bytes2send_19 & F1_a_1; --K1_RDATA_19 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_19 --operation mode is normal K1_RDATA_19 = K1_nx915 # K1_nx916 # K1_nx917; --J1_RDATA_19 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_19 --operation mode is normal J1_RDATA_19 = !V1_request_38 & Q1_q_b[19]; --SB3_Q_6 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_6 --operation mode is arithmetic SB3_Q_6_carry_eqn = SB3_Q_nx40; SB3_Q_6_lut_out = SB3_Q_6 $ (!SB3_Q_6_carry_eqn); SB3_Q_6 = DFFEAS(SB3_Q_6_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx44 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx44 --operation mode is arithmetic SB3_Q_nx44 = CARRY(SB3_Q_6 & (!SB3_Q_nx40)); --L1_nx835 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx835 --operation mode is normal L1_nx835 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_6) # !V1_request_48 & L1_adc_last_1_6); --L1_nx836 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx836 --operation mode is normal L1_nx836 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_6) # !V1_request_48 & L1_adc_last_5_6); --L1_nx837 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx837 --operation mode is normal L1_nx837 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_18 # !V1_request_48 & (!L1_NOT_climits_a_18)); --F1_nx810 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx810 --operation mode is normal F1_nx810 = F1_iword2send_2 & (F1_a_3 # F1_bytes_rcvd_18 & F1_nx785) # !F1_iword2send_2 & F1_bytes_rcvd_18 & F1_nx785; --K1_nx918 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx918 --operation mode is normal K1_nx918 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_6) # !V1_request_48 & K1_adc_last_1_6); --K1_nx919 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx919 --operation mode is normal K1_nx919 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_6) # !V1_request_48 & K1_adc_last_5_6); --K1_nx920 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx920 --operation mode is normal K1_nx920 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_18 # !V1_request_48 & (!K1_NOT_climits_a_18)); --L1_adc_last_1_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_5 --operation mode is normal L1_adc_last_1_5_lut_out = R2_RDATA_5; L1_adc_last_1_5 = DFFEAS(L1_adc_last_1_5_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_5 --operation mode is normal L1_adc_last_3_5_lut_out = R2_RDATA_5; L1_adc_last_3_5 = DFFEAS(L1_adc_last_3_5_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_5 --operation mode is normal L1_adc_last_5_5_lut_out = R2_RDATA_5; L1_adc_last_5_5 = DFFEAS(L1_adc_last_5_5_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_5 --operation mode is normal L1_adc_last_7_5_lut_out = R2_RDATA_5; L1_adc_last_7_5 = DFFEAS(L1_adc_last_7_5_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_17 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_17 --operation mode is normal L1_NOT_climits_d_17_lut_out = L1_NOT_climits_d_17; L1_NOT_climits_d_17 = DFFEAS(L1_NOT_climits_d_17_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L731, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_17 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_17 --operation mode is normal L1_NOT_climits_a_17_lut_out = L1_NOT_climits_a_17; L1_NOT_climits_a_17 = DFFEAS(L1_NOT_climits_a_17_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L731, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_17 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_17 --operation mode is normal F1_bytes_rcvd_17_lut_out = F1_nx2243; F1_bytes_rcvd_17 = DFFEAS(F1_bytes_rcvd_17_lut_out, S1__clk1, VCC, , F1_NOT_nx2185, , , , ); --K1_adc_last_1_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_5 --operation mode is normal K1_adc_last_1_5_lut_out = R1_RDATA_5; K1_adc_last_1_5 = DFFEAS(K1_adc_last_1_5_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_5 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_5 --operation mode is normal K1_adc_last_3_5_lut_out = R1_RDATA_5; K1_adc_last_3_5 = DFFEAS(K1_adc_last_3_5_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --F1_NOT_nx2185 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx2185 --operation mode is normal F1_NOT_nx2185 = F1_nx801 # !F1_byte_counter_2 & F1_byte_counter_1 & F1_nx804; --TB2_q_9 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|reg_clr_10:rg1p|q_9 --operation mode is normal TB2_q_9_lut_out = WT_P4D[9]; TB2_q_9 = DFFEAS(TB2_q_9_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --AB2_ob_data_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_6 --operation mode is normal AB2_ob_data_6_lut_out = AB2_ob_data_5; AB2_ob_data_6 = DFFEAS(AB2_ob_data_6_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_6, , , AB2_a_2); --LB2_d_to_dll_7 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_7 --operation mode is normal LB2_d_to_dll_7 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_7 # !DB4_data_out_0 & (T1_reply_7)); --AB1_ob_data_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_5 --operation mode is normal AB1_ob_data_5_lut_out = AB1_ob_data_4; AB1_ob_data_5 = DFFEAS(AB1_ob_data_5_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_5, , , AB1_a_2); --LB1_d_to_dll_6 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_6 --operation mode is normal LB1_d_to_dll_6 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_6 # !DB3_data_out_0 & (T1_reply_6)); --T1_reply_7 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_7 --operation mode is normal T1_reply_7 = V1_request_7 & (T1_a_0_dup_53 # T1_read_data_24 & !T1_ix34_ix30_nx12) # !V1_request_7 & T1_read_data_24 & (!T1_ix34_ix30_nx12); --T1_read_data_23 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_23 --operation mode is normal T1_read_data_23_lut_out = H1_bus_dout_23; T1_read_data_23 = DFFEAS(T1_read_data_23_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_22 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_22 --operation mode is normal H1_bus_dout_22 = H1_nx167 # H1_nx168 # E1_rdata_22 & H1_sel_0; --E1_rdata_21 is ni2io_wt:wt_ni|rdata_21 --operation mode is normal E1_rdata_21 = V1_request_37 & UB1_q_b[13] # !V1_request_37 & (E1_nx343 # E1_nx344); --H1_nx169 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx169 --operation mode is normal H1_nx169 = L1_RDATA_21 & (H1_ce_sc_adc # F1_RDATA_21 & H1_ce_dds) # !L1_RDATA_21 & F1_RDATA_21 & H1_ce_dds; --H1_nx170 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx170 --operation mode is normal H1_nx170 = K1_RDATA_21 & (H1_ce_psply_adc # J1_RDATA_21 & H1_ce_pasa_adc) # !K1_RDATA_21 & J1_RDATA_21 & (H1_ce_pasa_adc); --E1_nx341 is ni2io_wt:wt_ni|nx341 --operation mode is normal E1_nx341 = !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_0; --E1_nx342 is ni2io_wt:wt_ni|nx342 --operation mode is normal E1_nx342 = V1_request_47 & (V1_request_48 & (SB3_Q_8) # !V1_request_48 & SB4_Q_8); --L1_RDATA_20 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_20 --operation mode is normal L1_RDATA_20 = L1_nx829 # L1_nx830 # L1_nx831; --F1_RDATA_20 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_20 --operation mode is normal F1_RDATA_20 = F1_nx808 # F1_bytes2send_20 & F1_a_1; --K1_RDATA_20 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_20 --operation mode is normal K1_RDATA_20 = K1_nx912 # K1_nx913 # K1_nx914; --J1_RDATA_20 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_20 --operation mode is normal J1_RDATA_20 = !V1_request_38 & Q1_q_b[20]; --SB3_Q_7 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_7 --operation mode is arithmetic SB3_Q_7_carry_eqn = SB3_Q_nx44; SB3_Q_7_lut_out = SB3_Q_7 $ (SB3_Q_7_carry_eqn); SB3_Q_7 = DFFEAS(SB3_Q_7_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx48 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx48 --operation mode is arithmetic SB3_Q_nx48 = CARRY(!SB3_Q_nx44 # !SB3_Q_7); --L1_nx832 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx832 --operation mode is normal L1_nx832 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_7) # !V1_request_48 & L1_adc_last_1_7); --L1_nx833 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx833 --operation mode is normal L1_nx833 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_7) # !V1_request_48 & L1_adc_last_5_7); --L1_nx834 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx834 --operation mode is normal L1_nx834 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_19 # !V1_request_48 & (!L1_NOT_climits_a_19)); --F1_nx809 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx809 --operation mode is normal F1_nx809 = F1_iword2send_3 & (F1_a_3 # F1_bytes_rcvd_19 & F1_nx785) # !F1_iword2send_3 & F1_bytes_rcvd_19 & F1_nx785; --K1_nx915 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx915 --operation mode is normal K1_nx915 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_7) # !V1_request_48 & K1_adc_last_1_7); --K1_nx916 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx916 --operation mode is normal K1_nx916 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_7) # !V1_request_48 & K1_adc_last_5_7); --K1_nx917 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx917 --operation mode is normal K1_nx917 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_19 # !V1_request_48 & (!K1_NOT_climits_a_19)); --L1_adc_last_1_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_6 --operation mode is normal L1_adc_last_1_6_lut_out = R2_RDATA_6; L1_adc_last_1_6 = DFFEAS(L1_adc_last_1_6_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_6 --operation mode is normal L1_adc_last_3_6_lut_out = R2_RDATA_6; L1_adc_last_3_6 = DFFEAS(L1_adc_last_3_6_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_6 --operation mode is normal L1_adc_last_5_6_lut_out = R2_RDATA_6; L1_adc_last_5_6 = DFFEAS(L1_adc_last_5_6_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_6 --operation mode is normal L1_adc_last_7_6_lut_out = R2_RDATA_6; L1_adc_last_7_6 = DFFEAS(L1_adc_last_7_6_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_18 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_18 --operation mode is normal L1_NOT_climits_d_18_lut_out = L1_NOT_climits_d_18; L1_NOT_climits_d_18 = DFFEAS(L1_NOT_climits_d_18_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L531, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_18 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_18 --operation mode is normal L1_NOT_climits_a_18_lut_out = L1_NOT_climits_a_18; L1_NOT_climits_a_18 = DFFEAS(L1_NOT_climits_a_18_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L531, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_18 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_18 --operation mode is normal F1_bytes_rcvd_18_lut_out = F1_nx2239; F1_bytes_rcvd_18 = DFFEAS(F1_bytes_rcvd_18_lut_out, S1__clk1, VCC, , F1_NOT_nx2185, , , , ); --K1_adc_last_1_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_6 --operation mode is normal K1_adc_last_1_6_lut_out = R1_RDATA_6; K1_adc_last_1_6 = DFFEAS(K1_adc_last_1_6_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_6 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_6 --operation mode is normal K1_adc_last_3_6_lut_out = R1_RDATA_6; K1_adc_last_3_6 = DFFEAS(K1_adc_last_3_6_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --AB2_ob_data_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_5 --operation mode is normal AB2_ob_data_5_lut_out = AB2_ob_data_4; AB2_ob_data_5 = DFFEAS(AB2_ob_data_5_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_5, , , AB2_a_2); --LB2_d_to_dll_6 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_6 --operation mode is normal LB2_d_to_dll_6 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_6 # !DB4_data_out_0 & (T1_reply_6)); --AB1_ob_data_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_4 --operation mode is normal AB1_ob_data_4_lut_out = AB1_ob_data_3; AB1_ob_data_4 = DFFEAS(AB1_ob_data_4_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_4, , , AB1_a_2); --LB1_d_to_dll_5 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_5 --operation mode is normal LB1_d_to_dll_5 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_5 # !DB3_data_out_0 & (T1_reply_5)); --T1_reply_6 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_6 --operation mode is normal T1_reply_6 = V1_request_6 & (T1_a_0_dup_53 # T1_read_data_25 & !T1_ix34_ix30_nx12) # !V1_request_6 & T1_read_data_25 & (!T1_ix34_ix30_nx12); --T1_read_data_24 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_24 --operation mode is normal T1_read_data_24_lut_out = H1_bus_dout_24; T1_read_data_24 = DFFEAS(T1_read_data_24_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_23 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_23 --operation mode is normal H1_bus_dout_23 = H1_nx165 # H1_nx166 # E1_rdata_23 & H1_sel_0; --E1_rdata_22 is ni2io_wt:wt_ni|rdata_22 --operation mode is normal E1_rdata_22 = V1_request_37 & UB1_q_b[14] # !V1_request_37 & (E1_nx345 # E1_nx346); --H1_nx167 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx167 --operation mode is normal H1_nx167 = L1_RDATA_22 & (H1_ce_sc_adc # F1_RDATA_22 & H1_ce_dds) # !L1_RDATA_22 & F1_RDATA_22 & H1_ce_dds; --H1_nx168 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx168 --operation mode is normal H1_nx168 = K1_RDATA_22 & (H1_ce_psply_adc # J1_RDATA_22 & H1_ce_pasa_adc) # !K1_RDATA_22 & J1_RDATA_22 & (H1_ce_pasa_adc); --E1_nx343 is ni2io_wt:wt_ni|nx343 --operation mode is normal E1_nx343 = !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_1; --E1_nx344 is ni2io_wt:wt_ni|nx344 --operation mode is normal E1_nx344 = V1_request_47 & (V1_request_48 & (SB3_Q_9) # !V1_request_48 & SB4_Q_9); --L1_RDATA_21 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_21 --operation mode is normal L1_RDATA_21 = L1_nx826 # L1_nx827 # L1_nx828; --F1_RDATA_21 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_21 --operation mode is normal F1_RDATA_21 = F1_nx807 # F1_bytes2send_21 & F1_a_1; --K1_RDATA_21 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_21 --operation mode is normal K1_RDATA_21 = K1_nx909 # K1_nx910 # K1_nx911; --J1_RDATA_21 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_21 --operation mode is normal J1_RDATA_21 = !V1_request_38 & Q1_q_b[21]; --SB3_Q_8 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_8 --operation mode is arithmetic SB3_Q_8_carry_eqn = SB3_Q_nx48; SB3_Q_8_lut_out = SB3_Q_8 $ (!SB3_Q_8_carry_eqn); SB3_Q_8 = DFFEAS(SB3_Q_8_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx52 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx52 --operation mode is arithmetic SB3_Q_nx52 = CARRY(SB3_Q_8 & (!SB3_Q_nx48)); --L1_nx829 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx829 --operation mode is normal L1_nx829 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_8) # !V1_request_48 & L1_adc_last_1_8); --L1_nx830 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx830 --operation mode is normal L1_nx830 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_8) # !V1_request_48 & L1_adc_last_5_8); --L1_nx831 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx831 --operation mode is normal L1_nx831 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_20 # !V1_request_48 & (!L1_NOT_climits_a_20)); --F1_nx808 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx808 --operation mode is normal F1_nx808 = F1_iword2send_4 & (F1_a_3 # F1_bytes_rcvd_20 & F1_nx785) # !F1_iword2send_4 & F1_bytes_rcvd_20 & F1_nx785; --K1_nx912 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx912 --operation mode is normal K1_nx912 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_8) # !V1_request_48 & K1_adc_last_1_8); --K1_nx913 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx913 --operation mode is normal K1_nx913 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_8) # !V1_request_48 & K1_adc_last_5_8); --K1_nx914 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx914 --operation mode is normal K1_nx914 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_20 # !V1_request_48 & (!K1_NOT_climits_a_20)); --L1_adc_last_1_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_7 --operation mode is normal L1_adc_last_1_7_lut_out = R2_RDATA_7; L1_adc_last_1_7 = DFFEAS(L1_adc_last_1_7_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_7 --operation mode is normal L1_adc_last_3_7_lut_out = R2_RDATA_7; L1_adc_last_3_7 = DFFEAS(L1_adc_last_3_7_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_7 --operation mode is normal L1_adc_last_5_7_lut_out = R2_RDATA_7; L1_adc_last_5_7 = DFFEAS(L1_adc_last_5_7_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_7 --operation mode is normal L1_adc_last_7_7_lut_out = R2_RDATA_7; L1_adc_last_7_7 = DFFEAS(L1_adc_last_7_7_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_19 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_19 --operation mode is normal L1_NOT_climits_d_19_lut_out = L1_NOT_climits_d_19; L1_NOT_climits_d_19 = DFFEAS(L1_NOT_climits_d_19_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L331, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_19 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_19 --operation mode is normal L1_NOT_climits_a_19_lut_out = L1_NOT_climits_a_19; L1_NOT_climits_a_19 = DFFEAS(L1_NOT_climits_a_19_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L331, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_19 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_19 --operation mode is normal F1_bytes_rcvd_19_lut_out = F1_nx2235; F1_bytes_rcvd_19 = DFFEAS(F1_bytes_rcvd_19_lut_out, S1__clk1, VCC, , F1_NOT_nx2185, , , , ); --K1_adc_last_1_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_7 --operation mode is normal K1_adc_last_1_7_lut_out = R1_RDATA_7; K1_adc_last_1_7 = DFFEAS(K1_adc_last_1_7_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_7 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_7 --operation mode is normal K1_adc_last_3_7_lut_out = R1_RDATA_7; K1_adc_last_3_7 = DFFEAS(K1_adc_last_3_7_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --AB2_ob_data_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_4 --operation mode is normal AB2_ob_data_4_lut_out = AB2_ob_data_3; AB2_ob_data_4 = DFFEAS(AB2_ob_data_4_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_4, , , AB2_a_2); --LB2_d_to_dll_5 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_5 --operation mode is normal LB2_d_to_dll_5 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_5 # !DB4_data_out_0 & (T1_reply_5)); --AB1_ob_data_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_3 --operation mode is normal AB1_ob_data_3_lut_out = AB1_ob_data_2; AB1_ob_data_3 = DFFEAS(AB1_ob_data_3_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_3, , , AB1_a_2); --LB1_d_to_dll_4 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_4 --operation mode is normal LB1_d_to_dll_4 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_4 # !DB3_data_out_0 & (T1_reply_4)); --T1_reply_5 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_5 --operation mode is normal T1_reply_5 = V1_request_5 & (T1_a_0_dup_53 # T1_read_data_26 & !T1_ix34_ix30_nx12) # !V1_request_5 & T1_read_data_26 & (!T1_ix34_ix30_nx12); --T1_read_data_25 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_25 --operation mode is normal T1_read_data_25_lut_out = H1_bus_dout_25; T1_read_data_25 = DFFEAS(T1_read_data_25_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_24 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_24 --operation mode is normal H1_bus_dout_24 = H1_nx164 # E1_rdata_24 & H1_sel_0; --E1_rdata_23 is ni2io_wt:wt_ni|rdata_23 --operation mode is normal E1_rdata_23 = V1_request_37 & UB1_q_b[15] # !V1_request_37 & (E1_nx347 # E1_nx348); --H1_nx165 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx165 --operation mode is normal H1_nx165 = L1_RDATA_23 & (H1_ce_sc_adc # F1_RDATA_23 & H1_ce_dds) # !L1_RDATA_23 & F1_RDATA_23 & H1_ce_dds; --H1_nx166 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx166 --operation mode is normal H1_nx166 = K1_RDATA_23 & (H1_ce_psply_adc # J1_RDATA_23 & H1_ce_pasa_adc) # !K1_RDATA_23 & J1_RDATA_23 & (H1_ce_pasa_adc); --E1_nx345 is ni2io_wt:wt_ni|nx345 --operation mode is normal E1_nx345 = !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_2; --E1_nx346 is ni2io_wt:wt_ni|nx346 --operation mode is normal E1_nx346 = V1_request_47 & (V1_request_48 & (SB3_Q_10) # !V1_request_48 & SB4_Q_10); --L1_RDATA_22 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_22 --operation mode is normal L1_RDATA_22 = L1_nx823 # L1_nx824 # L1_nx825; --F1_RDATA_22 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_22 --operation mode is normal F1_RDATA_22 = F1_nx806 # F1_bytes2send_22 & F1_a_1; --K1_RDATA_22 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_22 --operation mode is normal K1_RDATA_22 = K1_nx906 # K1_nx907 # K1_nx908; --J1_RDATA_22 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_22 --operation mode is normal J1_RDATA_22 = !V1_request_38 & Q1_q_b[22]; --SB3_Q_9 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_9 --operation mode is arithmetic SB3_Q_9_carry_eqn = SB3_Q_nx52; SB3_Q_9_lut_out = SB3_Q_9 $ (SB3_Q_9_carry_eqn); SB3_Q_9 = DFFEAS(SB3_Q_9_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx57 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx57 --operation mode is arithmetic SB3_Q_nx57 = CARRY(!SB3_Q_nx52 # !SB3_Q_9); --L1_nx826 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx826 --operation mode is normal L1_nx826 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_9) # !V1_request_48 & L1_adc_last_1_9); --L1_nx827 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx827 --operation mode is normal L1_nx827 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_9) # !V1_request_48 & L1_adc_last_5_9); --L1_nx828 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx828 --operation mode is normal L1_nx828 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_21 # !V1_request_48 & (!L1_NOT_climits_a_21)); --F1_nx807 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx807 --operation mode is normal F1_nx807 = F1_iword2send_5 & (F1_a_3 # F1_bytes_rcvd_21 & F1_nx785) # !F1_iword2send_5 & F1_bytes_rcvd_21 & F1_nx785; --K1_nx909 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx909 --operation mode is normal K1_nx909 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_9) # !V1_request_48 & K1_adc_last_1_9); --K1_nx910 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx910 --operation mode is normal K1_nx910 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_9) # !V1_request_48 & K1_adc_last_5_9); --K1_nx911 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx911 --operation mode is normal K1_nx911 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_21 # !V1_request_48 & (!K1_NOT_climits_a_21)); --L1_adc_last_1_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_8 --operation mode is normal L1_adc_last_1_8_lut_out = R2_RDATA_8; L1_adc_last_1_8 = DFFEAS(L1_adc_last_1_8_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_8 --operation mode is normal L1_adc_last_3_8_lut_out = R2_RDATA_8; L1_adc_last_3_8 = DFFEAS(L1_adc_last_3_8_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_8 --operation mode is normal L1_adc_last_5_8_lut_out = R2_RDATA_8; L1_adc_last_5_8 = DFFEAS(L1_adc_last_5_8_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_8 --operation mode is normal L1_adc_last_7_8_lut_out = R2_RDATA_8; L1_adc_last_7_8 = DFFEAS(L1_adc_last_7_8_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_20 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_20 --operation mode is normal L1_NOT_climits_d_20_lut_out = L1_NOT_climits_d_20; L1_NOT_climits_d_20 = DFFEAS(L1_NOT_climits_d_20_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L131, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_20 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_20 --operation mode is normal L1_NOT_climits_a_20_lut_out = L1_NOT_climits_a_20; L1_NOT_climits_a_20 = DFFEAS(L1_NOT_climits_a_20_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L131, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_20 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_20 --operation mode is normal F1_bytes_rcvd_20_lut_out = F1_nx2231; F1_bytes_rcvd_20 = DFFEAS(F1_bytes_rcvd_20_lut_out, S1__clk1, VCC, , F1_NOT_nx2185, , , , ); --K1_adc_last_1_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_8 --operation mode is normal K1_adc_last_1_8_lut_out = R1_RDATA_8; K1_adc_last_1_8 = DFFEAS(K1_adc_last_1_8_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_8 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_8 --operation mode is normal K1_adc_last_3_8_lut_out = R1_RDATA_8; K1_adc_last_3_8 = DFFEAS(K1_adc_last_3_8_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --AB2_ob_data_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_3 --operation mode is normal AB2_ob_data_3_lut_out = AB2_ob_data_2; AB2_ob_data_3 = DFFEAS(AB2_ob_data_3_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_3, , , AB2_a_2); --LB2_d_to_dll_4 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_4 --operation mode is normal LB2_d_to_dll_4 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_4 # !DB4_data_out_0 & (T1_reply_4)); --AB1_ob_data_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_2 --operation mode is normal AB1_ob_data_2_lut_out = AB1_ob_data_1; AB1_ob_data_2 = DFFEAS(AB1_ob_data_2_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_2, , , AB1_a_2); --LB1_d_to_dll_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_3 --operation mode is normal LB1_d_to_dll_3 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_3 # !DB3_data_out_0 & (T1_reply_3)); --T1_reply_4 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_4 --operation mode is normal T1_reply_4 = V1_request_4 & (T1_a_0_dup_53 # T1_read_data_27 & !T1_ix34_ix30_nx12) # !V1_request_4 & T1_read_data_27 & (!T1_ix34_ix30_nx12); --T1_read_data_26 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_26 --operation mode is normal T1_read_data_26_lut_out = H1_bus_dout_26; T1_read_data_26 = DFFEAS(T1_read_data_26_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_25 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_25 --operation mode is normal H1_bus_dout_25 = H1_nx163 # E1_rdata_25 & H1_sel_0; --E1_rdata_24 is ni2io_wt:wt_ni|rdata_24 --operation mode is normal E1_rdata_24 = V1_request_37 & UB2_q_b[8] # !V1_request_37 & (E1_nx322); --H1_nx164 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx164 --operation mode is normal H1_nx164 = F1_RDATA_24 & (H1_ce_dds # J1_RDATA_24 & H1_ce_pasa_adc) # !F1_RDATA_24 & J1_RDATA_24 & (H1_ce_pasa_adc); --E1_nx347 is ni2io_wt:wt_ni|nx347 --operation mode is normal E1_nx347 = !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_3; --E1_nx348 is ni2io_wt:wt_ni|nx348 --operation mode is normal E1_nx348 = V1_request_47 & (V1_request_48 & (SB3_Q_11) # !V1_request_48 & SB4_Q_11); --L1_RDATA_23 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|RDATA_23 --operation mode is normal L1_RDATA_23 = L1_nx820 # L1_nx821 # L1_nx822; --F1_RDATA_23 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_23 --operation mode is normal F1_RDATA_23 = F1_nx805 # F1_bytes2send_23 & F1_a_1; --K1_RDATA_23 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|RDATA_23 --operation mode is normal K1_RDATA_23 = K1_nx903 # K1_nx904 # K1_nx905; --J1_RDATA_23 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_23 --operation mode is normal J1_RDATA_23 = !V1_request_38 & Q1_q_b[23]; --SB3_Q_10 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_10 --operation mode is arithmetic SB3_Q_10_carry_eqn = SB3_Q_nx57; SB3_Q_10_lut_out = SB3_Q_10 $ (!SB3_Q_10_carry_eqn); SB3_Q_10 = DFFEAS(SB3_Q_10_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --SB3_Q_nx61 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_nx61 --operation mode is arithmetic SB3_Q_nx61 = CARRY(SB3_Q_10 & (!SB3_Q_nx57)); --L1_nx823 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx823 --operation mode is normal L1_nx823 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_10) # !V1_request_48 & L1_adc_last_1_10); --L1_nx824 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx824 --operation mode is normal L1_nx824 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_10) # !V1_request_48 & L1_adc_last_5_10); --L1_nx825 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx825 --operation mode is normal L1_nx825 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_22 # !V1_request_48 & (!L1_NOT_climits_a_22)); --F1_nx806 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx806 --operation mode is normal F1_nx806 = F1_iword2send_6 & (F1_a_3 # F1_bytes_rcvd_22 & F1_nx785) # !F1_iword2send_6 & F1_bytes_rcvd_22 & F1_nx785; --K1_nx906 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx906 --operation mode is normal K1_nx906 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_10) # !V1_request_48 & K1_adc_last_1_10); --K1_nx907 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx907 --operation mode is normal K1_nx907 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_10) # !V1_request_48 & K1_adc_last_5_10); --K1_nx908 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx908 --operation mode is normal K1_nx908 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_22 # !V1_request_48 & (!K1_NOT_climits_a_22)); --L1_adc_last_1_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_9 --operation mode is normal L1_adc_last_1_9_lut_out = R2_RDATA_9; L1_adc_last_1_9 = DFFEAS(L1_adc_last_1_9_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_9 --operation mode is normal L1_adc_last_3_9_lut_out = R2_RDATA_9; L1_adc_last_3_9 = DFFEAS(L1_adc_last_3_9_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_9 --operation mode is normal L1_adc_last_5_9_lut_out = R2_RDATA_9; L1_adc_last_5_9 = DFFEAS(L1_adc_last_5_9_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_9 --operation mode is normal L1_adc_last_7_9_lut_out = R2_RDATA_9; L1_adc_last_7_9 = DFFEAS(L1_adc_last_7_9_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_21 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_21 --operation mode is normal L1_NOT_climits_d_21_lut_out = L1_NOT_climits_d_21; L1_NOT_climits_d_21 = DFFEAS(L1_NOT_climits_d_21_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L921, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_21 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_21 --operation mode is normal L1_NOT_climits_a_21_lut_out = L1_NOT_climits_a_21; L1_NOT_climits_a_21 = DFFEAS(L1_NOT_climits_a_21_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L921, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_21 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_21 --operation mode is normal F1_bytes_rcvd_21_lut_out = F1_nx2227; F1_bytes_rcvd_21 = DFFEAS(F1_bytes_rcvd_21_lut_out, S1__clk1, VCC, , F1_NOT_nx2185, , , , ); --K1_adc_last_1_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_9 --operation mode is normal K1_adc_last_1_9_lut_out = R1_RDATA_9; K1_adc_last_1_9 = DFFEAS(K1_adc_last_1_9_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_9 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_9 --operation mode is normal K1_adc_last_3_9_lut_out = R1_RDATA_9; K1_adc_last_3_9 = DFFEAS(K1_adc_last_3_9_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --AB2_ob_data_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_2 --operation mode is normal AB2_ob_data_2_lut_out = AB2_ob_data_1; AB2_ob_data_2 = DFFEAS(AB2_ob_data_2_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_2, , , AB2_a_2); --LB2_d_to_dll_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_3 --operation mode is normal LB2_d_to_dll_3 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_3 # !DB4_data_out_0 & (T1_reply_3)); --AB1_ob_data_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_1 --operation mode is normal AB1_ob_data_1_lut_out = AB1_ob_data_0; AB1_ob_data_1 = DFFEAS(AB1_ob_data_1_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, LB1_d_to_dll_1, , , AB1_a_2); --LB1_d_to_dll_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_2 --operation mode is normal LB1_d_to_dll_2 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_2 # !DB3_data_out_0 & (T1_reply_2)); --T1_reply_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_3 --operation mode is normal T1_reply_3 = V1_request_3 & (T1_a_0_dup_53 # T1_read_data_28 & !T1_ix34_ix30_nx12) # !V1_request_3 & T1_read_data_28 & (!T1_ix34_ix30_nx12); --T1_read_data_27 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_27 --operation mode is normal T1_read_data_27_lut_out = H1_bus_dout_27; T1_read_data_27 = DFFEAS(T1_read_data_27_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_26 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_26 --operation mode is normal H1_bus_dout_26 = H1_nx162 # E1_rdata_26 & H1_sel_0; --E1_rdata_25 is ni2io_wt:wt_ni|rdata_25 --operation mode is normal E1_rdata_25 = V1_request_37 & UB2_q_b[9] # !V1_request_37 & (E1_nx321); --H1_nx163 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx163 --operation mode is normal H1_nx163 = F1_RDATA_25 & (H1_ce_dds # J1_RDATA_25 & H1_ce_pasa_adc) # !F1_RDATA_25 & J1_RDATA_25 & (H1_ce_pasa_adc); --E1_nx322 is ni2io_wt:wt_ni|nx322 --operation mode is normal E1_nx322 = V1_request_47 & !V1_request_48 & (VB2_Q_0) # !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_4; --F1_RDATA_24 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_24 --operation mode is normal F1_RDATA_24 = F1_bytes2send_24 & (F1_a_1 # F1_bytes_rcvd_24 & F1_nx785) # !F1_bytes2send_24 & F1_bytes_rcvd_24 & (F1_nx785); --J1_RDATA_24 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_24 --operation mode is normal J1_RDATA_24 = !V1_request_38 & Q1_q_b[24]; --SB3_Q_11 is ni2io_wt:wt_ni|ni2io:ni|ni2dpm_12:ni_pos|counter_12:parc|Q_11 --operation mode is normal SB3_Q_11_carry_eqn = SB3_Q_nx61; SB3_Q_11_lut_out = SB3_Q_11 $ (SB3_Q_11_carry_eqn); SB3_Q_11 = DFFEAS(SB3_Q_11_lut_out, WT_STR, E1_NOT_clear, , , , , , ); --L1_nx820 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx820 --operation mode is normal L1_nx820 = !L1_nx908 & (V1_request_48 & (L1_adc_last_3_11) # !V1_request_48 & L1_adc_last_1_11); --L1_nx821 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx821 --operation mode is normal L1_nx821 = !L1_nx907 & (V1_request_48 & (L1_adc_last_7_11) # !V1_request_48 & L1_adc_last_5_11); --L1_nx822 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|nx822 --operation mode is normal L1_nx822 = !L1_nx910 & (V1_request_48 & !L1_NOT_climits_d_23 # !V1_request_48 & (!L1_NOT_climits_a_23)); --F1_nx805 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|nx805 --operation mode is normal F1_nx805 = F1_iword2send_7 & (F1_a_3 # F1_bytes_rcvd_23 & F1_nx785) # !F1_iword2send_7 & F1_bytes_rcvd_23 & F1_nx785; --K1_nx903 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx903 --operation mode is normal K1_nx903 = !K1_nx991 & (V1_request_48 & (K1_adc_last_3_11) # !V1_request_48 & K1_adc_last_1_11); --K1_nx904 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx904 --operation mode is normal K1_nx904 = !K1_nx990 & (V1_request_48 & (K1_adc_last_7_11) # !V1_request_48 & K1_adc_last_5_11); --K1_nx905 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|nx905 --operation mode is normal K1_nx905 = !K1_nx993 & (V1_request_48 & !K1_NOT_climits_d_23 # !V1_request_48 & (!K1_NOT_climits_a_23)); --L1_adc_last_1_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_10 --operation mode is normal L1_adc_last_1_10_lut_out = R2_RDATA_10; L1_adc_last_1_10 = DFFEAS(L1_adc_last_1_10_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_10 --operation mode is normal L1_adc_last_3_10_lut_out = R2_RDATA_10; L1_adc_last_3_10 = DFFEAS(L1_adc_last_3_10_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_10 --operation mode is normal L1_adc_last_5_10_lut_out = R2_RDATA_10; L1_adc_last_5_10 = DFFEAS(L1_adc_last_5_10_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_10 --operation mode is normal L1_adc_last_7_10_lut_out = R2_RDATA_10; L1_adc_last_7_10 = DFFEAS(L1_adc_last_7_10_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_22 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_22 --operation mode is normal L1_NOT_climits_d_22_lut_out = L1_NOT_climits_d_22; L1_NOT_climits_d_22 = DFFEAS(L1_NOT_climits_d_22_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L721, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_22 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_22 --operation mode is normal L1_NOT_climits_a_22_lut_out = L1_NOT_climits_a_22; L1_NOT_climits_a_22 = DFFEAS(L1_NOT_climits_a_22_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L721, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_22 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_22 --operation mode is normal F1_bytes_rcvd_22_lut_out = F1_nx2223; F1_bytes_rcvd_22 = DFFEAS(F1_bytes_rcvd_22_lut_out, S1__clk1, VCC, , F1_NOT_nx2185, , , , ); --K1_adc_last_1_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_10 --operation mode is normal K1_adc_last_1_10_lut_out = R1_RDATA_10; K1_adc_last_1_10 = DFFEAS(K1_adc_last_1_10_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_10 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_10 --operation mode is normal K1_adc_last_3_10_lut_out = R1_RDATA_10; K1_adc_last_3_10 = DFFEAS(K1_adc_last_3_10_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --AB2_ob_data_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_1 --operation mode is normal AB2_ob_data_1_lut_out = AB2_ob_data_0; AB2_ob_data_1 = DFFEAS(AB2_ob_data_1_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, LB2_d_to_dll_1, , , AB2_a_2); --LB2_d_to_dll_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_2 --operation mode is normal LB2_d_to_dll_2 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_2 # !DB4_data_out_0 & (T1_reply_2)); --AB1_ob_data_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_0 --operation mode is normal AB1_ob_data_0_lut_out = !BB1_freeze_buffer & LB1_d_to_dll_0 & LB1_d_we; AB1_ob_data_0 = DFFEAS(AB1_ob_data_0_lut_out, S1__clk0, VCC, , AB1_NOT_nx714, , , , ); --LB1_d_to_dll_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_1 --operation mode is normal LB1_d_to_dll_1 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_1 # !DB3_data_out_0 & (T1_reply_1)); --T1_reply_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_2 --operation mode is normal T1_reply_2 = V1_request_2 & (T1_a_0_dup_53 # T1_read_data_29 & !T1_ix34_ix30_nx12) # !V1_request_2 & T1_read_data_29 & (!T1_ix34_ix30_nx12); --T1_read_data_28 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_28 --operation mode is normal T1_read_data_28_lut_out = H1_bus_dout_28; T1_read_data_28 = DFFEAS(T1_read_data_28_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_27 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_27 --operation mode is normal H1_bus_dout_27 = H1_nx161 # E1_rdata_27 & H1_sel_0; --E1_rdata_26 is ni2io_wt:wt_ni|rdata_26 --operation mode is normal E1_rdata_26 = V1_request_37 & UB2_q_b[10] # !V1_request_37 & (E1_nx320); --H1_nx162 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx162 --operation mode is normal H1_nx162 = F1_RDATA_26 & (H1_ce_dds # J1_RDATA_26 & H1_ce_pasa_adc) # !F1_RDATA_26 & J1_RDATA_26 & (H1_ce_pasa_adc); --E1_nx321 is ni2io_wt:wt_ni|nx321 --operation mode is normal E1_nx321 = V1_request_47 & !V1_request_48 & (VB2_Q_1) # !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_5; --F1_RDATA_25 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_25 --operation mode is normal F1_RDATA_25 = F1_bytes2send_25 & (F1_a_1 # F1_bytes_rcvd_25 & F1_nx785) # !F1_bytes2send_25 & F1_bytes_rcvd_25 & (F1_nx785); --J1_RDATA_25 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_25 --operation mode is normal J1_RDATA_25 = !V1_request_38 & Q1_q_b[25]; --VB2_Q_0 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_0 --operation mode is arithmetic VB2_Q_0_lut_out = VB2_Q_0 $ NB1_count_en_s; VB2_Q_0 = DFFEAS(VB2_Q_0_lut_out, WT_STR, NB1_NOT_reset_cnt, , , , , , ); --VB2_Q_nx10 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_nx10 --operation mode is arithmetic VB2_Q_nx10 = CARRY(VB2_Q_0 & NB1_count_en_s); --F1_bytes_rcvd_24 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_24 --operation mode is normal F1_bytes_rcvd_24_lut_out = F1_nx2247; F1_bytes_rcvd_24 = DFFEAS(F1_bytes_rcvd_24_lut_out, S1__clk1, VCC, , F1_NOT_nx2153, , , , ); --L1_adc_last_1_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_1_11 --operation mode is normal L1_adc_last_1_11_lut_out = R2_RDATA_11; L1_adc_last_1_11 = DFFEAS(L1_adc_last_1_11_lut_out, S1__clk1, VCC, , L1_NOT_nx2213, , , , ); --L1_adc_last_3_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_3_11 --operation mode is normal L1_adc_last_3_11_lut_out = R2_RDATA_11; L1_adc_last_3_11 = DFFEAS(L1_adc_last_3_11_lut_out, S1__clk1, VCC, , L1_NOT_nx2261, , , , ); --L1_adc_last_5_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_5_11 --operation mode is normal L1_adc_last_5_11_lut_out = R2_RDATA_11; L1_adc_last_5_11 = DFFEAS(L1_adc_last_5_11_lut_out, S1__clk1, VCC, , L1_NOT_nx2309, , , , ); --L1_adc_last_7_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|adc_last_7_11 --operation mode is normal L1_adc_last_7_11_lut_out = R2_RDATA_11; L1_adc_last_7_11 = DFFEAS(L1_adc_last_7_11_lut_out, S1__clk1, VCC, , L1_modgen_select_210_nx2, , , , ); --L1_NOT_climits_d_23 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_d_23 --operation mode is normal L1_NOT_climits_d_23_lut_out = L1_NOT_climits_d_23; L1_NOT_climits_d_23 = DFFEAS(L1_NOT_climits_d_23_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L521, , , L1_NOT_ix37_ix7_nx8); --L1_NOT_climits_a_23 is ADC_DAC_1_notri:adcdac_notri|seradc_auto_unfolded0:sc_adc|NOT_climits_a_23 --operation mode is normal L1_NOT_climits_a_23_lut_out = L1_NOT_climits_a_23; L1_NOT_climits_a_23 = DFFEAS(L1_NOT_climits_a_23_lut_out, S1__clk1, T1_chipRST_n, , L1_nx10, V1L521, , , L1_NOT_ix37_ix9_nx8); --F1_bytes_rcvd_23 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_23 --operation mode is normal F1_bytes_rcvd_23_lut_out = F1_nx2219; F1_bytes_rcvd_23 = DFFEAS(F1_bytes_rcvd_23_lut_out, S1__clk1, VCC, , F1_NOT_nx2185, , , , ); --K1_adc_last_1_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_1_11 --operation mode is normal K1_adc_last_1_11_lut_out = R1_RDATA_11; K1_adc_last_1_11 = DFFEAS(K1_adc_last_1_11_lut_out, S1__clk1, VCC, , K1_NOT_nx2213, , , , ); --K1_adc_last_3_11 is ADC_DAC_1_notri:adcdac_notri|seradc_auto:power_adc|adc_last_3_11 --operation mode is normal K1_adc_last_3_11_lut_out = R1_RDATA_11; K1_adc_last_3_11 = DFFEAS(K1_adc_last_3_11_lut_out, S1__clk1, VCC, , K1_NOT_nx2261, , , , ); --AB2_ob_data_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_0 --operation mode is normal AB2_ob_data_0_lut_out = !BB2_freeze_buffer & LB2_d_to_dll_0 & LB2_d_we; AB2_ob_data_0 = DFFEAS(AB2_ob_data_0_lut_out, S1__clk0, VCC, , AB2_NOT_nx714, , , , ); --LB2_d_to_dll_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_1 --operation mode is normal LB2_d_to_dll_1 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_1 # !DB4_data_out_0 & (T1_reply_1)); --LB1_d_to_dll_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_0 --operation mode is normal LB1_d_to_dll_0 = !DB3_data_out_2 & (DB3_data_out_0 & Z1_data_out_0 # !DB3_data_out_0 & (T1_reply_0)); --T1_reply_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_1 --operation mode is normal T1_reply_1 = V1_request_1 & (T1_a_0_dup_53 # T1_read_data_30 & !T1_ix34_ix30_nx12) # !V1_request_1 & T1_read_data_30 & (!T1_ix34_ix30_nx12); --T1_read_data_29 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_29 --operation mode is normal T1_read_data_29_lut_out = H1_bus_dout_29; T1_read_data_29 = DFFEAS(T1_read_data_29_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_28 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_28 --operation mode is normal H1_bus_dout_28 = H1_nx160 # E1_rdata_28 & H1_sel_0; --E1_rdata_27 is ni2io_wt:wt_ni|rdata_27 --operation mode is normal E1_rdata_27 = V1_request_37 & UB2_q_b[11] # !V1_request_37 & (E1_nx319); --H1_nx161 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx161 --operation mode is normal H1_nx161 = F1_RDATA_27 & (H1_ce_dds # J1_RDATA_27 & H1_ce_pasa_adc) # !F1_RDATA_27 & J1_RDATA_27 & (H1_ce_pasa_adc); --E1_nx320 is ni2io_wt:wt_ni|nx320 --operation mode is normal E1_nx320 = V1_request_47 & !V1_request_48 & (VB2_Q_2) # !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_6; --F1_RDATA_26 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_26 --operation mode is normal F1_RDATA_26 = F1_bytes2send_26 & (F1_a_1 # F1_bytes_rcvd_26 & F1_nx785) # !F1_bytes2send_26 & F1_bytes_rcvd_26 & (F1_nx785); --J1_RDATA_26 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_26 --operation mode is normal J1_RDATA_26 = !V1_request_38 & Q1_q_b[26]; --VB2_Q_1 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_1 --operation mode is arithmetic VB2_Q_1_carry_eqn = VB2_Q_nx10; VB2_Q_1_lut_out = VB2_Q_1 $ (VB2_Q_1_carry_eqn); VB2_Q_1 = DFFEAS(VB2_Q_1_lut_out, WT_STR, NB1_NOT_reset_cnt, , , , , , ); --VB2_Q_nx16 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_nx16 --operation mode is arithmetic VB2_Q_nx16 = CARRY(!VB2_Q_nx10 # !VB2_Q_1); --F1_bytes_rcvd_25 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_25 --operation mode is normal F1_bytes_rcvd_25_lut_out = F1_nx2243; F1_bytes_rcvd_25 = DFFEAS(F1_bytes_rcvd_25_lut_out, S1__clk1, VCC, , F1_NOT_nx2153, , , , ); --NB1_count_en_s is ni2io_wt:wt_ni|clk_counter:scnt|count_en_s --operation mode is normal NB1_count_en_s_lut_out = NB1_count_en_c; NB1_count_en_s = DFFEAS(NB1_count_en_s_lut_out, WT_STR, NB1_NOT_reset_cnt, , , , , , ); --NB1_NOT_reset_cnt is ni2io_wt:wt_ni|clk_counter:scnt|NOT_reset_cnt --operation mode is normal NB1_NOT_reset_cnt_lut_out = NB1_sm_1 # NB1_sm_0 # !NB1_restart_s; NB1_NOT_reset_cnt = DFFEAS(NB1_NOT_reset_cnt_lut_out, S1__clk0, T1_chipRST_n, , , , , , ); --F1_NOT_nx2153 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|NOT_nx2153 --operation mode is normal F1_NOT_nx2153 = F1_nx801 # F1_byte_counter_2 & !F1_byte_counter_1 & F1_nx802; --LB2_d_to_dll_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_0 --operation mode is normal LB2_d_to_dll_0 = !DB4_data_out_2 & (DB4_data_out_0 & Z2_data_out_0 # !DB4_data_out_0 & (T1_reply_0)); --T1_reply_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_0 --operation mode is normal T1_reply_0 = V1_request_0 & (T1_a_0_dup_53 # T1_read_data_31 & !T1_ix34_ix30_nx12) # !V1_request_0 & T1_read_data_31 & (!T1_ix34_ix30_nx12); --T1_read_data_30 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_30 --operation mode is normal T1_read_data_30_lut_out = H1_bus_dout_30; T1_read_data_30 = DFFEAS(T1_read_data_30_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_29 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_29 --operation mode is normal H1_bus_dout_29 = H1_nx159 # E1_rdata_29 & H1_sel_0; --E1_rdata_28 is ni2io_wt:wt_ni|rdata_28 --operation mode is normal E1_rdata_28 = V1_request_37 & UB2_q_b[12] # !V1_request_37 & (E1_nx318); --H1_nx160 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx160 --operation mode is normal H1_nx160 = F1_RDATA_28 & (H1_ce_dds # J1_RDATA_28 & H1_ce_pasa_adc) # !F1_RDATA_28 & J1_RDATA_28 & (H1_ce_pasa_adc); --E1_nx319 is ni2io_wt:wt_ni|nx319 --operation mode is normal E1_nx319 = V1_request_47 & !V1_request_48 & (VB2_Q_3) # !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_7; --F1_RDATA_27 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_27 --operation mode is normal F1_RDATA_27 = F1_bytes2send_27 & (F1_a_1 # F1_bytes_rcvd_27 & F1_nx785) # !F1_bytes2send_27 & F1_bytes_rcvd_27 & (F1_nx785); --J1_RDATA_27 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_27 --operation mode is normal J1_RDATA_27 = !V1_request_38 & Q1_q_b[27]; --VB2_Q_2 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_2 --operation mode is arithmetic VB2_Q_2_carry_eqn = VB2_Q_nx16; VB2_Q_2_lut_out = VB2_Q_2 $ (!VB2_Q_2_carry_eqn); VB2_Q_2 = DFFEAS(VB2_Q_2_lut_out, WT_STR, NB1_NOT_reset_cnt, , , , , , ); --VB2_Q_nx22 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_nx22 --operation mode is arithmetic VB2_Q_nx22 = CARRY(VB2_Q_2 & (!VB2_Q_nx16)); --F1_bytes_rcvd_26 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_26 --operation mode is normal F1_bytes_rcvd_26_lut_out = F1_nx2239; F1_bytes_rcvd_26 = DFFEAS(F1_bytes_rcvd_26_lut_out, S1__clk1, VCC, , F1_NOT_nx2153, , , , ); --NB1_count_en_c is ni2io_wt:wt_ni|clk_counter:scnt|count_en_c --operation mode is normal NB1_count_en_c_lut_out = NB1_sm_1 & NB1_sm_0; NB1_count_en_c = DFFEAS(NB1_count_en_c_lut_out, S1__clk0, T1_chipRST_n, , , , , , ); --NB1_restart_s is ni2io_wt:wt_ni|clk_counter:scnt|restart_s --operation mode is normal NB1_restart_s_lut_out = E1_NOT_clear & NB1_ce_s; NB1_restart_s = DFFEAS(NB1_restart_s_lut_out, S1__clk0, T1_chipRST_n, , , , , , ); --NB1_sm_1 is ni2io_wt:wt_ni|clk_counter:scnt|sm_1 --operation mode is normal NB1_sm_1_lut_out = NB1_sm_0 & (!NB1_sm_1 # !NB1_count_rdy); NB1_sm_1 = DFFEAS(NB1_sm_1_lut_out, S1__clk0, T1_chipRST_n, , , , , , ); --NB1_sm_0 is ni2io_wt:wt_ni|clk_counter:scnt|sm_0 --operation mode is normal NB1_sm_0_lut_out = NB1_sm_1 & (!NB1_count_rdy & NB1_sm_0) # !NB1_sm_1 & (NB1_restart_s # NB1_sm_0); NB1_sm_0 = DFFEAS(NB1_sm_0_lut_out, S1__clk0, T1_chipRST_n, , , , , , ); --T1_read_data_31 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_31 --operation mode is normal T1_read_data_31_lut_out = H1_bus_dout_31; T1_read_data_31 = DFFEAS(T1_read_data_31_lut_out, S1__clk0, VCC, , T1_nx397, , , , ); --H1_bus_dout_30 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_30 --operation mode is normal H1_bus_dout_30 = H1_nx158 # H1_nx215 # E1_rdata_30 & H1_sel_0; --E1_rdata_29 is ni2io_wt:wt_ni|rdata_29 --operation mode is normal E1_rdata_29 = V1_request_37 & UB2_q_b[13] # !V1_request_37 & (E1_nx317); --H1_nx159 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx159 --operation mode is normal H1_nx159 = F1_RDATA_29 & (H1_ce_dds # J1_RDATA_29 & H1_ce_pasa_adc) # !F1_RDATA_29 & J1_RDATA_29 & (H1_ce_pasa_adc); --E1_nx318 is ni2io_wt:wt_ni|nx318 --operation mode is normal E1_nx318 = V1_request_47 & !V1_request_48 & (VB2_Q_4) # !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_8; --F1_RDATA_28 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_28 --operation mode is normal F1_RDATA_28 = F1_bytes2send_28 & (F1_a_1 # F1_bytes_rcvd_28 & F1_nx785) # !F1_bytes2send_28 & F1_bytes_rcvd_28 & (F1_nx785); --J1_RDATA_28 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_28 --operation mode is normal J1_RDATA_28 = !V1_request_38 & Q1_q_b[28]; --VB2_Q_3 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_3 --operation mode is arithmetic VB2_Q_3_carry_eqn = VB2_Q_nx22; VB2_Q_3_lut_out = VB2_Q_3 $ (VB2_Q_3_carry_eqn); VB2_Q_3 = DFFEAS(VB2_Q_3_lut_out, WT_STR, NB1_NOT_reset_cnt, , , , , , ); --VB2_Q_nx28 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_nx28 --operation mode is arithmetic VB2_Q_nx28 = CARRY(!VB2_Q_nx22 # !VB2_Q_3); --F1_bytes_rcvd_27 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_27 --operation mode is normal F1_bytes_rcvd_27_lut_out = F1_nx2235; F1_bytes_rcvd_27 = DFFEAS(F1_bytes_rcvd_27_lut_out, S1__clk1, VCC, , F1_NOT_nx2153, , , , ); --NB1_ce_s is ni2io_wt:wt_ni|clk_counter:scnt|ce_s --operation mode is normal NB1_ce_s_lut_out = !E1_NOT_clear; NB1_ce_s = DFFEAS(NB1_ce_s_lut_out, S1__clk0, T1_chipRST_n, , , , , , ); --NB1_count_rdy is ni2io_wt:wt_ni|clk_counter:scnt|count_rdy --operation mode is normal NB1_count_rdy_lut_out = VB1_Q_1 & VB1_Q_0 & NB1_nx179 & NB1_nx180; NB1_count_rdy = DFFEAS(NB1_count_rdy_lut_out, S1__clk0, T1_chipRST_n, , , , , , ); --H1_bus_dout_31 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|bus_dout_31 --operation mode is normal H1_bus_dout_31 = H1_nx157 # H1_nx216 # E1_rdata_31 & H1_sel_0; --E1_rdata_30 is ni2io_wt:wt_ni|rdata_30 --operation mode is normal E1_rdata_30 = E1_nx316 # V1_request_37 & UB2_q_b[14]; --H1_nx158 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx158 --operation mode is normal H1_nx158 = B1_VMCM_Shdwn_a & (H1_ce_psply_adc # J1_RDATA_30 & H1_ce_pasa_adc) # !B1_VMCM_Shdwn_a & J1_RDATA_30 & (H1_ce_pasa_adc); --H1_nx215 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx215 --operation mode is normal H1_nx215 = F1_RDATA_30 & H1_ce_dds; --E1_nx317 is ni2io_wt:wt_ni|nx317 --operation mode is normal E1_nx317 = V1_request_47 & !V1_request_48 & (VB2_Q_5) # !V1_request_47 & V1_request_48 & !E1_NOT_xor_mask_9; --F1_RDATA_29 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_29 --operation mode is normal F1_RDATA_29 = F1_bytes2send_29 & (F1_a_1 # F1_bytes_rcvd_29 & F1_nx785) # !F1_bytes2send_29 & F1_bytes_rcvd_29 & (F1_nx785); --J1_RDATA_29 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_29 --operation mode is normal J1_RDATA_29 = !V1_request_38 & Q1_q_b[29]; --VB2_Q_4 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_4 --operation mode is arithmetic VB2_Q_4_carry_eqn = VB2_Q_nx28; VB2_Q_4_lut_out = VB2_Q_4 $ (!VB2_Q_4_carry_eqn); VB2_Q_4 = DFFEAS(VB2_Q_4_lut_out, WT_STR, NB1_NOT_reset_cnt, , , , , , ); --VB2_Q_nx32 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_nx32 --operation mode is arithmetic VB2_Q_nx32 = CARRY(VB2_Q_4 & (!VB2_Q_nx28)); --F1_bytes_rcvd_28 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_28 --operation mode is normal F1_bytes_rcvd_28_lut_out = F1_nx2231; F1_bytes_rcvd_28 = DFFEAS(F1_bytes_rcvd_28_lut_out, S1__clk1, VCC, , F1_NOT_nx2153, , , , ); --VB1_Q_1 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_1 --operation mode is arithmetic VB1_Q_1_carry_eqn = VB1_Q_nx10; VB1_Q_1_lut_out = VB1_Q_1 $ (VB1_Q_1_carry_eqn); VB1_Q_1 = DFFEAS(VB1_Q_1_lut_out, S1__clk0, NB1_NOT_reset_cnt, , , , , , ); --VB1_Q_nx16 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_nx16 --operation mode is arithmetic VB1_Q_nx16 = CARRY(!VB1_Q_nx10 # !VB1_Q_1); --VB1_Q_0 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_0 --operation mode is arithmetic VB1_Q_0_lut_out = VB1_Q_0 $ NB1_count_en_c; VB1_Q_0 = DFFEAS(VB1_Q_0_lut_out, S1__clk0, NB1_NOT_reset_cnt, , , , , , ); --VB1_Q_nx10 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_nx10 --operation mode is arithmetic VB1_Q_nx10 = CARRY(VB1_Q_0 & NB1_count_en_c); --NB1_nx179 is ni2io_wt:wt_ni|clk_counter:scnt|nx179 --operation mode is normal NB1_nx179 = VB1_Q_7 & VB1_Q_6 & !VB1_Q_5 & !VB1_Q_4; --NB1_nx180 is ni2io_wt:wt_ni|clk_counter:scnt|nx180 --operation mode is normal NB1_nx180 = !VB1_Q_3 & VB1_Q_2; --E1_rdata_31 is ni2io_wt:wt_ni|rdata_31 --operation mode is normal E1_rdata_31 = E1_nx315 # V1_request_37 & UB2_q_b[15]; --H1_nx157 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx157 --operation mode is normal H1_nx157 = B1_VMCM_Shdwn_d & (H1_ce_psply_adc # J1_RDATA_31 & H1_ce_pasa_adc) # !B1_VMCM_Shdwn_d & J1_RDATA_31 & (H1_ce_pasa_adc); --H1_nx216 is ADC_DAC_1_notri:adcdac_notri|gio_devices_adc:gio|nx216 --operation mode is normal H1_nx216 = F1_RDATA_31 & H1_ce_dds; --E1_nx316 is ni2io_wt:wt_ni|nx316 --operation mode is normal E1_nx316 = !V1_request_37 & V1_request_47 & !V1_request_48 & VB2_Q_6; --J1_RDATA_30 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_30 --operation mode is normal J1_RDATA_30 = !V1_request_38 & Q1_q_b[30]; --F1_RDATA_30 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_30 --operation mode is normal F1_RDATA_30 = F1_bytes2send_30 & (F1_a_1 # F1_bytes_rcvd_30 & F1_nx785) # !F1_bytes2send_30 & F1_bytes_rcvd_30 & (F1_nx785); --VB2_Q_5 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_5 --operation mode is arithmetic VB2_Q_5_carry_eqn = VB2_Q_nx32; VB2_Q_5_lut_out = VB2_Q_5 $ (VB2_Q_5_carry_eqn); VB2_Q_5 = DFFEAS(VB2_Q_5_lut_out, WT_STR, NB1_NOT_reset_cnt, , , , , , ); --VB2_Q_nx36 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_nx36 --operation mode is arithmetic VB2_Q_nx36 = CARRY(!VB2_Q_nx32 # !VB2_Q_5); --F1_bytes_rcvd_29 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_29 --operation mode is normal F1_bytes_rcvd_29_lut_out = F1_nx2227; F1_bytes_rcvd_29 = DFFEAS(F1_bytes_rcvd_29_lut_out, S1__clk1, VCC, , F1_NOT_nx2153, , , , ); --VB1_Q_7 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_7 --operation mode is normal VB1_Q_7_carry_eqn = VB1_Q_nx41; VB1_Q_7_lut_out = VB1_Q_7 $ (VB1_Q_7_carry_eqn); VB1_Q_7 = DFFEAS(VB1_Q_7_lut_out, S1__clk0, NB1_NOT_reset_cnt, , , , , , ); --VB1_Q_6 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_6 --operation mode is arithmetic VB1_Q_6_carry_eqn = VB1_Q_nx36; VB1_Q_6_lut_out = VB1_Q_6 $ (!VB1_Q_6_carry_eqn); VB1_Q_6 = DFFEAS(VB1_Q_6_lut_out, S1__clk0, NB1_NOT_reset_cnt, , , , , , ); --VB1_Q_nx41 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_nx41 --operation mode is arithmetic VB1_Q_nx41 = CARRY(VB1_Q_6 & (!VB1_Q_nx36)); --VB1_Q_5 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_5 --operation mode is arithmetic VB1_Q_5_carry_eqn = VB1_Q_nx32; VB1_Q_5_lut_out = VB1_Q_5 $ (VB1_Q_5_carry_eqn); VB1_Q_5 = DFFEAS(VB1_Q_5_lut_out, S1__clk0, NB1_NOT_reset_cnt, , , , , , ); --VB1_Q_nx36 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_nx36 --operation mode is arithmetic VB1_Q_nx36 = CARRY(!VB1_Q_nx32 # !VB1_Q_5); --VB1_Q_4 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_4 --operation mode is arithmetic VB1_Q_4_carry_eqn = VB1_Q_nx28; VB1_Q_4_lut_out = VB1_Q_4 $ (!VB1_Q_4_carry_eqn); VB1_Q_4 = DFFEAS(VB1_Q_4_lut_out, S1__clk0, NB1_NOT_reset_cnt, , , , , , ); --VB1_Q_nx32 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_nx32 --operation mode is arithmetic VB1_Q_nx32 = CARRY(VB1_Q_4 & (!VB1_Q_nx28)); --VB1_Q_3 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_3 --operation mode is arithmetic VB1_Q_3_carry_eqn = VB1_Q_nx22; VB1_Q_3_lut_out = VB1_Q_3 $ (VB1_Q_3_carry_eqn); VB1_Q_3 = DFFEAS(VB1_Q_3_lut_out, S1__clk0, NB1_NOT_reset_cnt, , , , , , ); --VB1_Q_nx28 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_nx28 --operation mode is arithmetic VB1_Q_nx28 = CARRY(!VB1_Q_nx22 # !VB1_Q_3); --VB1_Q_2 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_2 --operation mode is arithmetic VB1_Q_2_carry_eqn = VB1_Q_nx16; VB1_Q_2_lut_out = VB1_Q_2 $ (!VB1_Q_2_carry_eqn); VB1_Q_2 = DFFEAS(VB1_Q_2_lut_out, S1__clk0, NB1_NOT_reset_cnt, , , , , , ); --VB1_Q_nx22 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_c|Q_nx22 --operation mode is arithmetic VB1_Q_nx22 = CARRY(VB1_Q_2 & (!VB1_Q_nx16)); --E1_nx315 is ni2io_wt:wt_ni|nx315 --operation mode is normal E1_nx315 = !V1_request_37 & V1_request_47 & !V1_request_48 & VB2_Q_7; --J1_RDATA_31 is ADC_DAC_1_notri:adcdac_notri|pasaadc:padc|RDATA_31 --operation mode is normal J1_RDATA_31 = !V1_request_38 & Q1_q_b[31]; --F1_RDATA_31 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|RDATA_31 --operation mode is normal F1_RDATA_31 = F1_bytes2send_31 & (F1_a_1 # F1_bytes_rcvd_31 & F1_nx785) # !F1_bytes2send_31 & F1_bytes_rcvd_31 & (F1_nx785); --VB2_Q_6 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_6 --operation mode is arithmetic VB2_Q_6_carry_eqn = VB2_Q_nx36; VB2_Q_6_lut_out = VB2_Q_6 $ (!VB2_Q_6_carry_eqn); VB2_Q_6 = DFFEAS(VB2_Q_6_lut_out, WT_STR, NB1_NOT_reset_cnt, , , , , , ); --VB2_Q_nx41 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_nx41 --operation mode is arithmetic VB2_Q_nx41 = CARRY(VB2_Q_6 & (!VB2_Q_nx36)); --F1_bytes_rcvd_30 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_30 --operation mode is normal F1_bytes_rcvd_30_lut_out = F1_nx2223; F1_bytes_rcvd_30 = DFFEAS(F1_bytes_rcvd_30_lut_out, S1__clk1, VCC, , F1_NOT_nx2153, , , , ); --VB2_Q_7 is ni2io_wt:wt_ni|clk_counter:scnt|counter_8:cnt_s|Q_7 --operation mode is normal VB2_Q_7_carry_eqn = VB2_Q_nx41; VB2_Q_7_lut_out = VB2_Q_7 $ (VB2_Q_7_carry_eqn); VB2_Q_7 = DFFEAS(VB2_Q_7_lut_out, WT_STR, NB1_NOT_reset_cnt, , , , , , ); --F1_bytes_rcvd_31 is ADC_DAC_1_notri:adcdac_notri|DDS:ddsi|bytes_rcvd_31 --operation mode is normal F1_bytes_rcvd_31_lut_out = F1_nx2219; F1_bytes_rcvd_31 = DFFEAS(F1_bytes_rcvd_31_lut_out, S1__clk1, VCC, , F1_NOT_nx2153, , , , ); --~GND is ~GND --operation mode is normal ~GND = GND; --MSply_ADC_INTn is MSply_ADC_INTn --operation mode is input MSply_ADC_INTn = INPUT(); --PA_SCLK is PA_SCLK --operation mode is input PA_SCLK = INPUT(); --PA_SDAT is PA_SDAT --operation mode is input PA_SDAT = INPUT(); --PA_SSTR is PA_SSTR --operation mode is input PA_SSTR = INPUT(); --SC_ADC_INTn is SC_ADC_INTn --operation mode is input SC_ADC_INTn = INPUT(); --AD_SYNC_IN[0] is AD_SYNC_IN[0] --operation mode is input AD_SYNC_IN[0] = INPUT(); --AD_SYNC_IN[1] is AD_SYNC_IN[1] --operation mode is input AD_SYNC_IN[1] = INPUT(); --CLK_gen is CLK_gen --operation mode is input CLK_gen = INPUT(); --SER0_IN is SER0_IN --operation mode is input SER0_IN = INPUT(); --SER1_IN is SER1_IN --operation mode is input SER1_IN = INPUT(); --WT_STR is WT_STR --operation mode is input WT_STR = INPUT(); --PAADC_D[0] is PAADC_D[0] --operation mode is input PAADC_D[0] = INPUT(); --SC_ADC_SDO is SC_ADC_SDO --operation mode is input SC_ADC_SDO = INPUT(); --MSply_ADC_SDO is MSply_ADC_SDO --operation mode is input MSply_ADC_SDO = INPUT(); --DDS_SDO is DDS_SDO --operation mode is input DDS_SDO = INPUT(); --WT_P4D[2] is WT_P4D[2] --operation mode is input WT_P4D[2] = INPUT(); --WT_P4D[1] is WT_P4D[1] --operation mode is input WT_P4D[1] = INPUT(); --WT_P4D[0] is WT_P4D[0] --operation mode is input WT_P4D[0] = INPUT(); --WT_P4D[9] is WT_P4D[9] --operation mode is input WT_P4D[9] = INPUT(); --WT_P4D[8] is WT_P4D[8] --operation mode is input WT_P4D[8] = INPUT(); --WT_P4D[7] is WT_P4D[7] --operation mode is input WT_P4D[7] = INPUT(); --WT_P4D[3] is WT_P4D[3] --operation mode is input WT_P4D[3] = INPUT(); --WT_P4D[4] is WT_P4D[4] --operation mode is input WT_P4D[4] = INPUT(); --WT_P4D[5] is WT_P4D[5] --operation mode is input WT_P4D[5] = INPUT(); --WT_P4D[6] is WT_P4D[6] --operation mode is input WT_P4D[6] = INPUT(); --PAADC_D[1] is PAADC_D[1] --operation mode is input PAADC_D[1] = INPUT(); --PAADC_D[2] is PAADC_D[2] --operation mode is input PAADC_D[2] = INPUT(); --PAADC_D[3] is PAADC_D[3] --operation mode is input PAADC_D[3] = INPUT(); --PAADC_D[4] is PAADC_D[4] --operation mode is input PAADC_D[4] = INPUT(); --PAADC_D[5] is PAADC_D[5] --operation mode is input PAADC_D[5] = INPUT(); --PAADC_D[6] is PAADC_D[6] --operation mode is input PAADC_D[6] = INPUT(); --PAADC_D[7] is PAADC_D[7] --operation mode is input PAADC_D[7] = INPUT(); --PAADC_D[8] is PAADC_D[8] --operation mode is input PAADC_D[8] = INPUT(); --PAADC_D[9] is PAADC_D[9] --operation mode is input PAADC_D[9] = INPUT(); --PAADC_D[10] is PAADC_D[10] --operation mode is input PAADC_D[10] = INPUT(); --PAADC_D[11] is PAADC_D[11] --operation mode is input PAADC_D[11] = INPUT(); --PAADC_OVR is PAADC_OVR --operation mode is input PAADC_OVR = INPUT(); --AD_SYNC_OUT[0] is AD_SYNC_OUT[0] --operation mode is output AD_SYNC_OUT[0] = OUTPUT(B1_AD_SYNC_OUT_0); --AD_SYNC_OUT[1] is AD_SYNC_OUT[1] --operation mode is output AD_SYNC_OUT[1] = OUTPUT(B1_AD_SYNC_OUT_1); --DDS_CSn is DDS_CSn --operation mode is output DDS_CSn = OUTPUT(!F1_NOT_DDS_CSn); --DDS_FSK is DDS_FSK --operation mode is output DDS_FSK = OUTPUT(F1_DDS_FSK); --DDS_IORST is DDS_IORST --operation mode is output DDS_IORST = OUTPUT(!F1_NOT_DDS_IORST); --DDS_MCLK is DDS_MCLK --operation mode is output DDS_MCLK = OUTPUT(F1_DDS_MCLK); --DDS_MRST is DDS_MRST --operation mode is output DDS_MRST = OUTPUT(F1_DDS_MRST); --DDS_SCLK is DDS_SCLK --operation mode is output DDS_SCLK = OUTPUT(F1_DDS_SCLK); --DDS_SDI is DDS_SDI --operation mode is output DDS_SDI = OUTPUT(F1_DDS_SDI); --DDS_ShKey is DDS_ShKey --operation mode is output DDS_ShKey = OUTPUT(F1_DDS_ShKey); --DDS_UDCLK is DDS_UDCLK --operation mode is output DDS_UDCLK = OUTPUT(F1_DDS_UDCLK); --MSply_ADC_nCS is MSply_ADC_nCS --operation mode is output MSply_ADC_nCS = OUTPUT(R1_RDY); --MSply_ADC_nCSStrt is MSply_ADC_nCSStrt --operation mode is output MSply_ADC_nCSStrt = OUTPUT(!K1_NOT_ADC_nCSStrt); --MSply_ADC_SCLK is MSply_ADC_SCLK --operation mode is output MSply_ADC_SCLK = OUTPUT(R1_ADC_SCLK); --MSply_ADC_SDI is MSply_ADC_SDI --operation mode is output MSply_ADC_SDI = OUTPUT(R1_ADC_SDI); --PA_VDD is PA_VDD --operation mode is output PA_VDD = OUTPUT(VCC); --PAADC_CLK is PAADC_CLK --operation mode is output PAADC_CLK = OUTPUT(J1_PAADC_CLK); --PAADC_Msel is PAADC_Msel --operation mode is output PAADC_Msel = OUTPUT(J1_PAADC_Msel); --PAADC_MuxA[0] is PAADC_MuxA[0] --operation mode is output PAADC_MuxA[0] = OUTPUT(J1_PAADC_MuxA_0); --PAADC_MuxA[1] is PAADC_MuxA[1] --operation mode is output PAADC_MuxA[1] = OUTPUT(J1_PAADC_MuxA_1); --PAADC_MuxnRS is PAADC_MuxnRS --operation mode is output PAADC_MuxnRS = OUTPUT(J1_PAADC_MuxnRS); --PAADC_STDP is PAADC_STDP --operation mode is output PAADC_STDP = OUTPUT(J1_PAADC_STDP); --PasaDAC1_CLK is PasaDAC1_CLK --operation mode is output PasaDAC1_CLK = OUTPUT(GND); --PasaDAC2_CLK is PasaDAC2_CLK --operation mode is output PasaDAC2_CLK = OUTPUT(GND); --PasaDAC_D[0] is PasaDAC_D[0] --operation mode is output PasaDAC_D[0] = OUTPUT(GND); --PasaDAC_D[1] is PasaDAC_D[1] --operation mode is output PasaDAC_D[1] = OUTPUT(GND); --PasaDAC_D[2] is PasaDAC_D[2] --operation mode is output PasaDAC_D[2] = OUTPUT(GND); --PasaDAC_D[3] is PasaDAC_D[3] --operation mode is output PasaDAC_D[3] = OUTPUT(GND); --PasaDAC_D[4] is PasaDAC_D[4] --operation mode is output PasaDAC_D[4] = OUTPUT(GND); --PasaDAC_D[5] is PasaDAC_D[5] --operation mode is output PasaDAC_D[5] = OUTPUT(GND); --PasaDAC_D[6] is PasaDAC_D[6] --operation mode is output PasaDAC_D[6] = OUTPUT(GND); --PasaDAC_D[7] is PasaDAC_D[7] --operation mode is output PasaDAC_D[7] = OUTPUT(GND); --PasaDAC_D[8] is PasaDAC_D[8] --operation mode is output PasaDAC_D[8] = OUTPUT(GND); --PasaDAC_D[9] is PasaDAC_D[9] --operation mode is output PasaDAC_D[9] = OUTPUT(GND); --PasaDAC_D[10] is PasaDAC_D[10] --operation mode is output PasaDAC_D[10] = OUTPUT(GND); --PasaDAC_D[11] is PasaDAC_D[11] --operation mode is output PasaDAC_D[11] = OUTPUT(GND); --PasaDAC_D[12] is PasaDAC_D[12] --operation mode is output PasaDAC_D[12] = OUTPUT(GND); --PasaDAC_D[13] is PasaDAC_D[13] --operation mode is output PasaDAC_D[13] = OUTPUT(GND); --PasaDAC_Sleep is PasaDAC_Sleep --operation mode is output PasaDAC_Sleep = OUTPUT(VCC); --PW_CSn[0] is PW_CSn[0] --operation mode is output PW_CSn[0] = OUTPUT(!G1_NOT_CSn); --PW_CSn[1] is PW_CSn[1] --operation mode is output PW_CSn[1] = OUTPUT(!G2_NOT_CSn); --PW_CSn[2] is PW_CSn[2] --operation mode is output PW_CSn[2] = OUTPUT(!G3_NOT_CSn); --PW_CSn[3] is PW_CSn[3] --operation mode is output PW_CSn[3] = OUTPUT(!G4_NOT_CSn); --PW_INCn[0] is PW_INCn[0] --operation mode is output PW_INCn[0] = OUTPUT(!G1_NOT_INCn); --PW_INCn[1] is PW_INCn[1] --operation mode is output PW_INCn[1] = OUTPUT(!G2_NOT_INCn); --PW_INCn[2] is PW_INCn[2] --operation mode is output PW_INCn[2] = OUTPUT(!G3_NOT_INCn); --PW_INCn[3] is PW_INCn[3] --operation mode is output PW_INCn[3] = OUTPUT(!G4_NOT_INCn); --PW_UDn[0] is PW_UDn[0] --operation mode is output PW_UDn[0] = OUTPUT(!G1_NOT_UDn); --PW_UDn[1] is PW_UDn[1] --operation mode is output PW_UDn[1] = OUTPUT(!G2_NOT_UDn); --PW_UDn[2] is PW_UDn[2] --operation mode is output PW_UDn[2] = OUTPUT(!G3_NOT_UDn); --PW_UDn[3] is PW_UDn[3] --operation mode is output PW_UDn[3] = OUTPUT(!G4_NOT_UDn); --SC_ADC_nCS is SC_ADC_nCS --operation mode is output SC_ADC_nCS = OUTPUT(R2_RDY); --SC_ADC_nCSStrt is SC_ADC_nCSStrt --operation mode is output SC_ADC_nCSStrt = OUTPUT(!L1_NOT_ADC_nCSStrt); --SC_ADC_SCLK is SC_ADC_SCLK --operation mode is output SC_ADC_SCLK = OUTPUT(R2_ADC_SCLK); --SC_ADC_SDI is SC_ADC_SDI --operation mode is output SC_ADC_SDI = OUTPUT(R2_ADC_SDI); --SER0_OUT is SER0_OUT --operation mode is output SER0_OUT = OUTPUT(U1_d0_to_pl); --SER1_OUT is SER1_OUT --operation mode is output SER1_OUT = OUTPUT(U1_d1_to_pl); --SlowDAC1_FS is SlowDAC1_FS --operation mode is output SlowDAC1_FS = OUTPUT(OPNDRN(VCC)); --SlowDAC1_LDACn is SlowDAC1_LDACn --operation mode is output SlowDAC1_LDACn = OUTPUT(OPNDRN(VCC)); --SlowDAC1_SCLK is SlowDAC1_SCLK --operation mode is output SlowDAC1_SCLK = OUTPUT(OPNDRN(VCC)); --SlowDAC2_FS is SlowDAC2_FS --operation mode is output SlowDAC2_FS = OUTPUT(M1_SSTR); --SlowDAC2_LDACn is SlowDAC2_LDACn --operation mode is output SlowDAC2_LDACn = OUTPUT(!M1_NOT_LDACn); --SlowDAC2_SCLK is SlowDAC2_SCLK --operation mode is output SlowDAC2_SCLK = OUTPUT(M1_SCLK); --SlowDAC_Din is SlowDAC_Din --operation mode is output SlowDAC_Din = OUTPUT(M1_SDAT); --VGND[0] is VGND[0] --operation mode is output VGND[0] = OUTPUT(GND); --VGND[1] is VGND[1] --operation mode is output VGND[1] = OUTPUT(GND); --VGND[2] is VGND[2] --operation mode is output VGND[2] = OUTPUT(GND); --VMCM_Shdwn_a is VMCM_Shdwn_a --operation mode is output VMCM_Shdwn_a = OUTPUT(OPNDRN(B1_VMCM_Shdwn_a)); --VMCM_Shdwn_d is VMCM_Shdwn_d --operation mode is output VMCM_Shdwn_d = OUTPUT(OPNDRN(B1_VMCM_Shdwn_d)); --WT_CTR is WT_CTR --operation mode is output WT_CTR = OUTPUT(AD_SYNC_IN[0]); --A1L601 is WRST_n~0 --operation mode is bidir A1L601 = WRST_n; --WRST_n is WRST_n --operation mode is bidir WRST_n_tri_out = TRI(E1_wrst_n, E1_wrst_n_oe); WRST_n = BIDIR(WRST_n_tri_out); --V1L921 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_10~0 --operation mode is normal V1L921 = !V1_request_10; --V1L131 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_11~0 --operation mode is normal V1L131 = !V1_request_11; --V1L331 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_12~0 --operation mode is normal V1L331 = !V1_request_12; --V1L531 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_13~0 --operation mode is normal V1L531 = !V1_request_13; --V1L731 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_14~0 --operation mode is normal V1L731 = !V1_request_14; --V1L931 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_15~0 --operation mode is normal V1L931 = !V1_request_15; --V1L141 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_16~0 --operation mode is normal V1L141 = !V1_request_16; --V1L341 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_17~0 --operation mode is normal V1L341 = !V1_request_17; --V1L541 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_18~0 --operation mode is normal V1L541 = !V1_request_18; --V1L741 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_19~0 --operation mode is normal V1L741 = !V1_request_19; --V1L311 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_2~0 --operation mode is normal V1L311 = !V1_request_2; --V1L941 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_20~0 --operation mode is normal V1L941 = !V1_request_20; --V1L151 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_21~0 --operation mode is normal V1L151 = !V1_request_21; --V1L451 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_23~0 --operation mode is normal V1L451 = !V1_request_23; --V1L651 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_24~0 --operation mode is normal V1L651 = !V1_request_24; --V1L061 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_27~0 --operation mode is normal V1L061 = !V1_request_27; --V1L261 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_28~0 --operation mode is normal V1L261 = !V1_request_28; --V1L511 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_3~0 --operation mode is normal V1L511 = !V1_request_3; --V1L711 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_4~0 --operation mode is normal V1L711 = !V1_request_4; --V1L911 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_5~0 --operation mode is normal V1L911 = !V1_request_5; --V1L121 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_6~0 --operation mode is normal V1L121 = !V1_request_6; --V1L321 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_7~0 --operation mode is normal V1L321 = !V1_request_7; --V1L521 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_8~0 --operation mode is normal V1L521 = !V1_request_8; --V1L721 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_9~0 --operation mode is normal V1L721 = !V1_request_9;