# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any other # associated documentation or information provided by Altera or a partner # under Altera's Megafunction Partnership Program may be used only # to program PLD devices (but not masked PLD devices) from Altera. Any # other use of such megafunction design, netlist, support information, # device programming or simulation file, or any other related documentation # or information is prohibited for any other purpose, including, but not # limited to modification, reverse engineering, de-compiling, or use with # any other silicon devices, unless such use is explicitly licensed under # a separate agreement with Altera or a megafunction partner. Title to the # intellectual property, including patents, copyrights, trademarks, trade # secrets, or maskworks, embodied in any such megafunction design, netlist, # support information, device programming or simulation file, or any other # related documentation or information provided by Altera or a megafunction # partner, remains with Altera, the megafunction partner, or their respective # licensors. No other licenses, including any licenses needed under any third # party's intellectual property, are provided herein. # The default values for assignments are stored in the file # assignment_defaults.qdf # Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:05:36 APRIL 15, 2004" set_global_assignment -name LAST_QUARTUS_VERSION 9.0 set_global_assignment -name VHDL_FILE pasaadc_ram.vhd set_global_assignment -name VHDL_FILE pasadac_ram.vhd set_global_assignment -name VHDL_FILE pll120.vhd set_global_assignment -name EDIF_FILE top.edf set_global_assignment -name SLOW_SLEW_RATE ON # Pin & Location Assignments # ========================== set_location_assignment PIN_120 -to rst_n set_location_assignment PIN_7 -to AD_SYNC_OUT\[0\] set_location_assignment PIN_8 -to AD_SYNC_OUT\[1\] set_location_assignment PIN_12 -to AD_SYNC_IN\[0\] set_location_assignment PIN_13 -to AD_SYNC_IN\[1\] set_location_assignment PIN_28 -to CLK_gen set_location_assignment PIN_53 -to DDS_CSn set_location_assignment PIN_49 -to DDS_FSK set_location_assignment PIN_58 -to DDS_IORST set_location_assignment PIN_60 -to DDS_MCLK set_location_assignment PIN_59 -to DDS_MRST set_location_assignment PIN_54 -to DDS_SCLK set_location_assignment PIN_56 -to DDS_SDI set_location_assignment PIN_57 -to DDS_SDO set_location_assignment PIN_55 -to DDS_UDCLK set_location_assignment PIN_46 -to MSply_ADC_nCS set_location_assignment PIN_42 -to MSply_ADC_INTn set_location_assignment PIN_44 -to MSply_ADC_SDI set_location_assignment PIN_45 -to MSply_ADC_SDO set_location_assignment PIN_43 -to MSply_ADC_SCLK set_location_assignment PIN_47 -to MSply_ADC_nCSStrt set_location_assignment PIN_78 -to PAADC_CLK set_location_assignment PIN_61 -to PAADC_D\[0\] set_location_assignment PIN_76 -to PAADC_D\[10\] set_location_assignment PIN_77 -to PAADC_D\[11\] set_location_assignment PIN_62 -to PAADC_D\[1\] set_location_assignment PIN_63 -to PAADC_D\[2\] set_location_assignment PIN_64 -to PAADC_D\[3\] set_location_assignment PIN_65 -to PAADC_D\[4\] set_location_assignment PIN_66 -to PAADC_D\[5\] set_location_assignment PIN_67 -to PAADC_D\[6\] set_location_assignment PIN_68 -to PAADC_D\[7\] set_location_assignment PIN_74 -to PAADC_D\[8\] set_location_assignment PIN_75 -to PAADC_D\[9\] set_location_assignment PIN_82 -to PAADC_Msel set_location_assignment PIN_87 -to PAADC_OVR set_location_assignment PIN_86 -to PAADC_MuxA\[0\] set_location_assignment PIN_85 -to PAADC_MuxA\[1\] set_location_assignment PIN_84 -to PAADC_MuxnRS set_location_assignment PIN_83 -to PAADC_STDP set_location_assignment PIN_88 -to PasaDAC1_CLK set_location_assignment PIN_93 -to PasaDAC2_CLK set_location_assignment PIN_95 -to PasaDAC_D\[0\] set_location_assignment PIN_113 -to PasaDAC_D\[10\] set_location_assignment PIN_114 -to PasaDAC_D\[11\] set_location_assignment PIN_115 -to PasaDAC_D\[12\] set_location_assignment PIN_116 -to PasaDAC_D\[13\] set_location_assignment PIN_98 -to PasaDAC_D\[1\] set_location_assignment PIN_99 -to PasaDAC_D\[2\] set_location_assignment PIN_100 -to PasaDAC_D\[3\] set_location_assignment PIN_101 -to PasaDAC_D\[4\] set_location_assignment PIN_104 -to PasaDAC_D\[5\] set_location_assignment PIN_105 -to PasaDAC_D\[6\] set_location_assignment PIN_106 -to PasaDAC_D\[7\] set_location_assignment PIN_107 -to PasaDAC_D\[8\] set_location_assignment PIN_108 -to PasaDAC_D\[9\] set_location_assignment PIN_94 -to PasaDAC_Sleep set_location_assignment PIN_134 -to SC_ADC_SCLK set_location_assignment PIN_135 -to SC_ADC_SDI set_location_assignment PIN_136 -to SC_ADC_SDO set_location_assignment PIN_133 -to SC_ADC_INTn set_location_assignment PIN_137 -to SC_ADC_nCS set_location_assignment PIN_132 -to SC_ADC_nCSStrt set_location_assignment PIN_126 -to SlowDAC_Din set_location_assignment PIN_122 -to SlowDAC1_FS set_location_assignment PIN_123 -to SlowDAC1_LDACn set_location_assignment PIN_124 -to SlowDAC1_SCLK set_location_assignment PIN_127 -to SlowDAC2_FS set_location_assignment PIN_128 -to SlowDAC2_LDACn set_location_assignment PIN_125 -to SlowDAC2_SCLK set_location_assignment PIN_41 -to VMCM_Shdwn_a set_location_assignment PIN_21 -to VMCM_Shdwn_d set_location_assignment PIN_240 -to PW_INCn\[0\] set_location_assignment PIN_236 -to PW_INCn\[1\] set_location_assignment PIN_16 -to PW_INCn\[2\] set_location_assignment PIN_18 -to PW_INCn\[3\] set_location_assignment PIN_239 -to PW_UDn\[0\] set_location_assignment PIN_235 -to PW_UDn\[1\] set_location_assignment PIN_15 -to PW_UDn\[2\] set_location_assignment PIN_19 -to PW_UDn\[3\] set_location_assignment PIN_238 -to PW_CSn\[0\] set_location_assignment PIN_234 -to PW_CSn\[1\] set_location_assignment PIN_233 -to PW_CSn\[2\] set_location_assignment PIN_20 -to PW_CSn\[3\] set_location_assignment PIN_224 -to WT_CTR set_location_assignment PIN_219 -to WT_STR set_location_assignment PIN_217 -to WT_P4D\[9\] set_location_assignment PIN_215 -to WT_P4D\[8\] set_location_assignment PIN_207 -to WT_P4D\[7\] set_location_assignment PIN_203 -to WT_P4D\[6\] set_location_assignment PIN_201 -to WT_P4D\[5\] set_location_assignment PIN_197 -to WT_P4D\[4\] set_location_assignment PIN_188 -to WT_P4D\[3\] set_location_assignment PIN_186 -to WT_P4D\[2\] set_location_assignment PIN_184 -to WT_P4D\[1\] set_location_assignment PIN_182 -to WT_P4D\[0\] set_location_assignment PIN_1 -to SER0_IN set_location_assignment PIN_2 -to SER0_OUT set_location_assignment PIN_3 -to SER1_IN set_location_assignment PIN_4 -to SER1_OUT # Timing Assignments # ================== set_global_assignment -name REPORT_IO_PATHS_SEPARATELY ON set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY Cyclone set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL LeonardoSpectrum set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST set_global_assignment -name TOP_LEVEL_ENTITY top # Fitter Assignments # ================== set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL" set_global_assignment -name DEVICE EP1C6Q240C6 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL set_instance_assignment -name IO_STANDARD LVCMOS -to CLK_gen set_instance_assignment -name IO_STANDARD LVCMOS -to SER0_IN set_instance_assignment -name IO_STANDARD LVCMOS -to SER0_OUT set_instance_assignment -name IO_STANDARD LVCMOS -to SER1_IN set_instance_assignment -name IO_STANDARD LVCMOS -to SER1_OUT set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_INCn\[0\] set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_INCn\[1\] # set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_INCn\[2\] # set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_INCn\[3\] set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_UDn\[0\] set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_UDn\[1\] # set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_UDn\[2\] # set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_UDn\[3\] set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_CSn\[0\] set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_CSn\[1\] set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_CSn\[2\] # set_instance_assignment -name IO_STANDARD "2.5 V" -to PW_CSn\[3\] set_instance_assignment -name IO_STANDARD LVDS -to WT_CTR set_instance_assignment -name IO_STANDARD LVDS -to WT_STR set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[9\] set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[8\] set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[7\] set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[6\] set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[5\] set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[4\] set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[3\] set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[2\] set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[1\] set_instance_assignment -name IO_STANDARD LVDS -to WT_P4D\[0\] set_global_assignment -name DEVICE_MIGRATION_LIST "EP1C12Q240C6,EP1C6Q240C6" # Timing Analysis Assignments # =========================== set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 2000 # Assembler Assignments # ===================== set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS4 # ----------------------- # start CLOCK(inputclock) # Timing Assignments # ================== set_global_assignment -name FMAX_REQUIREMENT "60.0 MHz" -section_id inputclock set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id inputclock set_global_assignment -name DUTY_CYCLE 50 -section_id inputclock set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id inputclock set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id inputclock set_global_assignment -name INVERT_BASE_CLOCK OFF -section_id inputclock # end CLOCK(inputclock) # --------------------- # --------------------------------------------- # start EDA_TOOL_SETTINGS(eda_design_synthesis) # Analysis & Synthesis Assignments # ================================ set_global_assignment -name EDA_LMF_FILE exemplar.lmf -section_id eda_design_synthesis # end EDA_TOOL_SETTINGS(eda_design_synthesis) # ------------------------------------------- # ----------------- # start ENTITY(top) # Timing Assignments # ================== set_instance_assignment -name CLOCK_SETTINGS inputclock -to CLK_gen # end ENTITY(top) # ---------------