Analysis & Synthesis report for top Fri Dec 17 14:21:29 2004 Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Default Parameter Settings 5. Hierarchy 6. Analysis & Synthesis Resource Utilization by Entity 7. Analysis & Synthesis Equations 8. Analysis & Synthesis Files Read 9. Analysis & Synthesis Resource Usage Summary 10. Analysis & Synthesis RAM Summary 11. WYSIWYG Cells 12. General Register Statistics 13. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2004 Altera Corporation Any megafunction design, and related netlist (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, netlist, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, netlist, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. +---------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------+ ; Analysis & Synthesis Status ; Successful - Fri Dec 17 14:21:29 2004 ; ; Revision Name ; top ; ; Top-level Entity Name ; top ; ; Family ; Cyclone ; ; Total logic elements ; 2,933 ; ; Total pins ; 100 ; ; Total memory bits ; 17,152 ; ; Total PLLs ; 1 ; +-----------------------------+---------------------------------------+ +----------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +----------------------------------------------------------------------------------------- ; Option ; Setting ; Default Value ; +---------------------------------------------------------+--------------+---------------+ ; Use Generated Physical Constraints File ; On ; ; ; Physical Synthesis Level for Resynthesis ; Normal ; ; ; Resynthesis Optimization Effort ; Normal ; ; ; Type of Retiming Performed During Resynthesis ; Full ; ; ; Top-level entity name ; top ; ; ; Family name ; Cyclone ; Stratix ; ; Auto Resource Sharing ; Off ; Off ; ; Auto Shift Register Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto ROM Replacement ; On ; On ; ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ; ; Perform gate-level register retiming ; Off ; Off ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Remove Duplicate Logic ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Auto Carry Chains ; On ; On ; ; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II ; 70 ; 70 ; ; Optimization Technique -- Cyclone ; Balanced ; Balanced ; ; Auto Global Register Control Signals ; On ; On ; ; Auto Global Clock ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore CARRY Buffers ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Power-Up Don't Care ; On ; On ; ; NOT Gate Push-Back ; On ; On ; ; State Machine Processing ; Auto ; Auto ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; Preserve fewer node names ; On ; On ; ; Disk space/compilation speed tradeoff ; Normal ; Normal ; ; Create Debugging Nodes for IP Cores ; off ; off ; +---------------------------------------------------------+--------------+---------------+ +-------------------------------------------------+ ; Analysis & Synthesis Default Parameter Settings ; +-------------------------------------------------- ; Name ; Setting ; +--------------------+----------------------------+ ; CARRY_CHAIN ; MANUAL ; ; CASCADE_CHAIN ; MANUAL ; ; OPTIMIZE_FOR_SPEED ; 5 ; ; STYLE ; FAST ; +--------------------+----------------------------+ +------------+ ; Hierarchy ; +------------+ top |-- ADC_DAC_0:adcdac |-- DDS:ddsi |-- digpot4:dgi_0_dgpot |-- digpot4:dgi_1_dgpot |-- digpot4:dgi_2_dgpot |-- digpot4:dgi_3_dgpot |-- gio_devices_adc:gio |-- pasaadc:padc |-- pasaadc_ram:adcram |-- altsyncram:altsyncram_component |-- altsyncram_0c21:auto_generated |-- pasadac:pdac |-- pasadac_ram:dacram |-- altsyncram:altsyncram_component |-- altsyncram_hpj1:auto_generated |-- seradc_auto:power_adc |-- TLV2548:adc |-- seradc_auto_unfolded0:sc_adc |-- TLV2548:adc |-- TLV5630_16:slow_dac1 |-- TLV5630_16:slow_dac2 |-- pll120:PLL |-- altpll:altpll_component |-- mcm_network_interface:scsn_slave |-- mcm_nw_apl:nw_apl |-- hamm_reg_4_0_1_unfolded0:h1 |-- mcm_nw_dll_4_2_7_63_69_4_7:nw_dll |-- mcm_nw_bittiming_4_2_7_7_2:bt0 |-- mcm_nw_destuffing_7:destuff_in |-- hamm_reg_4_0_1:h1 |-- mcm_nw_timer_4_2:timer_in |-- mcm_nw_bittiming_4_2_7_7_2:bt1 |-- mcm_nw_destuffing_7:destuff_in |-- hamm_reg_4_0_1:h1 |-- mcm_nw_timer_4_2:timer_in |-- mcm_nw_inbuf_69_4_7:ib0 |-- mcm_nw_inbuf_69_4_7:ib1 |-- mcm_nw_outbuf_69_7:ob0 |-- mcm_nw_outbuf_69_7:ob1 |-- mcm_nw_sendtiming_4_7_63:st0 |-- hamm_reg_3_0_1:h1 |-- mcm_nw_timer_63_63:sleeptimer |-- mcm_nw_stuffing_7:stuff_in |-- mcm_nw_timer_4_0:timer_in |-- mcm_nw_sendtiming_4_7_63:st1 |-- hamm_reg_3_0_1:h1 |-- mcm_nw_timer_63_63:sleeptimer |-- mcm_nw_stuffing_7:stuff_in |-- mcm_nw_timer_4_0:timer_in |-- mcm_nw_nwl:nw_nwl |-- hamm_reg_3_0_1_unfolded0:h1 |-- mcm_nw_nwsl:sl0 |-- hamm_reg_4_0_1:h1 |-- mcm_nw_nwsl:sl1 |-- hamm_reg_4_0_1:h1 |-- mcm_nw_pl_1:nw_pl +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ; Compilation Hierarchy Node ; Logic Cells ; Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ; +-------------------------------------------------+-------------+-----------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------+ ; |top ; 2933 (1) ; 1375 ; 17152 ; 100 ; 0 ; 1558 (1) ; 947 (0) ; 428 (0) ; 330 (0) ; |top ; ; |ADC_DAC_0:adcdac| ; 1710 (7) ; 861 ; 17152 ; 0 ; 0 ; 849 (3) ; 577 (2) ; 284 (2) ; 238 (0) ; |top|ADC_DAC_0:adcdac ; ; |DDS:ddsi| ; 331 (331) ; 156 ; 0 ; 0 ; 0 ; 175 (175) ; 119 (119) ; 37 (37) ; 6 (6) ; |top|ADC_DAC_0:adcdac|DDS:ddsi ; ; |TLV5630_16:slow_dac1| ; 46 (46) ; 37 ; 0 ; 0 ; 0 ; 9 (9) ; 20 (20) ; 17 (17) ; 8 (8) ; |top|ADC_DAC_0:adcdac|TLV5630_16:slow_dac1 ; ; |TLV5630_16:slow_dac2| ; 46 (46) ; 37 ; 0 ; 0 ; 0 ; 9 (9) ; 20 (20) ; 17 (17) ; 8 (8) ; |top|ADC_DAC_0:adcdac|TLV5630_16:slow_dac2 ; ; |digpot4:dgi_0_dgpot| ; 50 (50) ; 25 ; 0 ; 0 ; 0 ; 25 (25) ; 8 (8) ; 17 (17) ; 29 (29) ; |top|ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot ; ; |digpot4:dgi_1_dgpot| ; 50 (50) ; 25 ; 0 ; 0 ; 0 ; 25 (25) ; 8 (8) ; 17 (17) ; 29 (29) ; |top|ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot ; ; |digpot4:dgi_2_dgpot| ; 50 (50) ; 25 ; 0 ; 0 ; 0 ; 25 (25) ; 8 (8) ; 17 (17) ; 29 (29) ; |top|ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot ; ; |digpot4:dgi_3_dgpot| ; 50 (50) ; 25 ; 0 ; 0 ; 0 ; 25 (25) ; 8 (8) ; 17 (17) ; 29 (29) ; |top|ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot ; ; |gio_devices_adc:gio| ; 106 (106) ; 13 ; 0 ; 0 ; 0 ; 93 (93) ; 1 (1) ; 12 (12) ; 0 (0) ; |top|ADC_DAC_0:adcdac|gio_devices_adc:gio ; ; |pasaadc:padc| ; 71 (71) ; 33 ; 16384 ; 0 ; 0 ; 38 (38) ; 20 (20) ; 13 (13) ; 10 (10) ; |top|ADC_DAC_0:adcdac|pasaadc:padc ; ; |pasaadc_ram:adcram| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component ; ; |altsyncram_0c21:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated ; ; |pasadac:pdac| ; 103 (103) ; 39 ; 768 ; 0 ; 0 ; 64 (64) ; 17 (17) ; 22 (22) ; 14 (14) ; |top|ADC_DAC_0:adcdac|pasadac:pdac ; ; |pasadac_ram:dacram| ; 0 (0) ; 0 ; 768 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram ; ; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 768 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component ; ; |altsyncram_hpj1:auto_generated| ; 0 (0) ; 0 ; 768 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated ; ; |seradc_auto:power_adc| ; 425 (380) ; 222 ; 0 ; 0 ; 0 ; 203 (197) ; 173 (160) ; 49 (23) ; 62 (58) ; |top|ADC_DAC_0:adcdac|seradc_auto:power_adc ; ; |TLV2548:adc| ; 45 (45) ; 39 ; 0 ; 0 ; 0 ; 6 (6) ; 13 (13) ; 26 (26) ; 4 (4) ; |top|ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc ; ; |seradc_auto_unfolded0:sc_adc| ; 375 (330) ; 220 ; 0 ; 0 ; 0 ; 155 (149) ; 173 (160) ; 47 (21) ; 14 (10) ; |top|ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc ; ; |TLV2548:adc| ; 45 (45) ; 39 ; 0 ; 0 ; 0 ; 6 (6) ; 13 (13) ; 26 (26) ; 4 (4) ; |top|ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc ; ; |mcm_network_interface:scsn_slave| ; 1222 (0) ; 514 ; 0 ; 0 ; 0 ; 708 (0) ; 370 (0) ; 144 (0) ; 92 (0) ; |top|mcm_network_interface:scsn_slave ; ; |mcm_nw_apl:nw_apl| ; 160 (156) ; 50 ; 0 ; 0 ; 0 ; 110 (110) ; 38 (34) ; 12 (12) ; 6 (6) ; |top|mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl ; ; |hamm_reg_4_0_1_unfolded0:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1 ; ; |mcm_nw_dll_4_2_7_63_69_4_7:nw_dll| ; 692 (4) ; 442 ; 0 ; 0 ; 0 ; 250 (4) ; 316 (0) ; 126 (0) ; 70 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll ; ; |mcm_nw_bittiming_4_2_7_7_2:bt0| ; 79 (49) ; 17 ; 0 ; 0 ; 0 ; 62 (45) ; 5 (1) ; 12 (3) ; 9 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0 ; ; |hamm_reg_4_0_1:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1 ; ; |mcm_nw_destuffing_7:destuff_in| ; 10 (10) ; 6 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 6 (6) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in ; ; |mcm_nw_timer_4_2:timer_in| ; 16 (16) ; 3 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 3 (3) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in ; ; |mcm_nw_bittiming_4_2_7_7_2:bt1| ; 79 (49) ; 17 ; 0 ; 0 ; 0 ; 62 (45) ; 5 (1) ; 12 (3) ; 9 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1 ; ; |hamm_reg_4_0_1:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1 ; ; |mcm_nw_destuffing_7:destuff_in| ; 10 (10) ; 6 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 6 (6) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in ; ; |mcm_nw_timer_4_2:timer_in| ; 16 (16) ; 3 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 3 (3) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in ; ; |mcm_nw_inbuf_69_4_7:ib0| ; 107 (107) ; 92 ; 0 ; 0 ; 0 ; 15 (15) ; 69 (69) ; 23 (23) ; 7 (7) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0 ; ; |mcm_nw_inbuf_69_4_7:ib1| ; 107 (107) ; 92 ; 0 ; 0 ; 0 ; 15 (15) ; 69 (69) ; 23 (23) ; 7 (7) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1 ; ; |mcm_nw_outbuf_69_7:ob0| ; 102 (102) ; 92 ; 0 ; 0 ; 0 ; 10 (10) ; 81 (81) ; 11 (11) ; 7 (7) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0 ; ; |mcm_nw_outbuf_69_7:ob1| ; 102 (102) ; 92 ; 0 ; 0 ; 0 ; 10 (10) ; 81 (81) ; 11 (11) ; 7 (7) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1 ; ; |mcm_nw_sendtiming_4_7_63:st0| ; 56 (16) ; 20 ; 0 ; 0 ; 0 ; 36 (15) ; 3 (0) ; 17 (1) ; 12 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0 ; ; |hamm_reg_3_0_1:h1| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|hamm_reg_3_0_1:h1 ; ; |mcm_nw_stuffing_7:stuff_in| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in ; ; |mcm_nw_timer_4_0:timer_in| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in ; ; |mcm_nw_timer_63_63:sleeptimer| ; 18 (18) ; 7 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 7 (7) ; 6 (6) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer ; ; |mcm_nw_sendtiming_4_7_63:st1| ; 56 (16) ; 20 ; 0 ; 0 ; 0 ; 36 (15) ; 3 (0) ; 17 (1) ; 12 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1 ; ; |hamm_reg_3_0_1:h1| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|hamm_reg_3_0_1:h1 ; ; |mcm_nw_stuffing_7:stuff_in| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in ; ; |mcm_nw_timer_4_0:timer_in| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 3 (3) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in ; ; |mcm_nw_timer_63_63:sleeptimer| ; 18 (18) ; 7 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 7 (7) ; 6 (6) ; |top|mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer ; ; |mcm_nw_nwl:nw_nwl| ; 362 (93) ; 16 ; 0 ; 0 ; 0 ; 346 (90) ; 12 (1) ; 4 (2) ; 16 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl ; ; |hamm_reg_3_0_1_unfolded0:h1| ; 3 (3) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|hamm_reg_3_0_1_unfolded0:h1 ; ; |mcm_nw_nwsl:sl0| ; 133 (129) ; 5 ; 0 ; 0 ; 0 ; 128 (128) ; 4 (0) ; 1 (1) ; 8 (8) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0 ; ; |hamm_reg_4_0_1:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1 ; ; |mcm_nw_nwsl:sl1| ; 133 (129) ; 5 ; 0 ; 0 ; 0 ; 128 (128) ; 4 (0) ; 1 (1) ; 8 (8) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1 ; ; |hamm_reg_4_0_1:h1| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1 ; ; |mcm_nw_pl_1:nw_pl| ; 8 (8) ; 6 ; 0 ; 0 ; 0 ; 2 (2) ; 4 (4) ; 2 (2) ; 0 (0) ; |top|mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl ; ; |pll120:PLL| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|pll120:PLL ; ; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|pll120:PLL|altpll:altpll_component ; +-------------------------------------------------+-------------+-----------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------+ ; Analysis & Synthesis Equations ; +---------------------------------+ The equations can be found in M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_adcdac_60MHz/top.map.eqn. +-----------------------------------------------------------------------------------------+ ; Analysis & Synthesis Files Read ; +------------------------------------------------------------------------------------------ ; File Name ; Read ; +----------------------------------------------------------------------------------+------+ ; pasaadc_ram.vhd ; Read ; ; pasadac_ram.vhd ; Read ; ; pll120.vhd ; Read ; ; top.edf ; Read ; ; d:/quartus4.0/libraries/megafunctions/altsyncram.tdf ; Read ; ; M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_adcdac_60MHz/db/altsyncram_0c21.tdf ; Read ; ; M:/REFERENCE/SIM/PROJECTS/mcm_tester/quartus_adcdac_60MHz/db/altsyncram_hpj1.tdf ; Read ; ; d:/quartus4.0/libraries/megafunctions/altpll.tdf ; Read ; +----------------------------------------------------------------------------------+------+ +--------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +--------------------------------------------------------------------------- ; Resource ; Usage ; +-------------------------------+------------------------------------------+ ; Logic cells ; 2,933 ; ; Total combinational functions ; 1986 ; ; Total registers ; 1375 ; ; I/O pins ; 100 ; ; Total memory bits ; 17152 ; ; Total PLLs ; 1 ; ; Maximum fan-out node ; pll120:PLL|altpll:altpll_component|_clk0 ; ; Maximum fan-out ; 1417 ; ; Total fan-out ; 11966 ; ; Average fan-out ; 3.89 ; +-------------------------------+------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; +----------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ ; ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024 ; 16 ; 512 ; 32 ; 16384 ; None ; ; ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 32 ; 24 ; 32 ; 24 ; 768 ; None ; +----------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +----------------------------------------------------------------+ ; WYSIWYG Cells ; +----------------------------------------------------------------- ; Statistic ; Value ; +--------------------------------------------------------+-------+ ; Number of WYSIWYG cells ; 2921 ; ; Number of synthesis-generated cells ; 12 ; ; Number of WYSIWYG LUTs ; 1974 ; ; Number of synthesis-generated LUTs ; 12 ; ; Number of WYSIWYG registers ; 1375 ; ; Number of synthesis-generated registers ; 0 ; ; Number of cells with combinational logic only ; 1558 ; ; Number of cells with registers only ; 947 ; ; Number of cells with combinational logic and registers ; 428 ; +--------------------------------------------------------+-------+ +----------------------------------------------+ ; General Register Statistics ; +----------------------------------------------- ; Statistic ; Value ; +--------------------------------------+-------+ ; Number of registers using SCLR ; 267 ; ; Number of registers using SLOAD ; 301 ; ; Number of registers using ACLR ; 455 ; ; Number of registers using ALOAD ; 0 ; ; Number of registers using CLK_ENABLE ; 1099 ; ; Number of registers using OE ; 0 ; ; Number of registers using PRESET ; 0 ; +--------------------------------------+-------+ +--------------------------------+ ; Analysis & Synthesis Messages ; +--------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version Info: Processing started: Fri Dec 17 14:21:03 2004 Info: Command: quartus_map --import_settings_files=on --export_settings_files=off top -c top Info: Found 2 design units and 1 entities in source file pasaadc_ram.vhd Info: Found design unit 1: pasaadc_ram-SYN Info: Found entity 1: pasaadc_ram Info: Found 2 design units and 1 entities in source file pasadac_ram.vhd Info: Found design unit 1: pasadac_ram-SYN Info: Found entity 1: pasadac_ram Info: Found 2 design units and 1 entities in source file pll120.vhd Info: Found design unit 1: pll120-SYN Info: Found entity 1: pll120 Info: Found 30 design units and 30 entities in source file top.edf Info: Found entity 1: ADC_DAC_0 Info: Found entity 2: DDS Info: Found entity 3: digpot4 Info: Found entity 4: gio_devices_adc Info: Found entity 5: hamm_reg_3_0_1 Info: Found entity 6: hamm_reg_3_0_1_unfolded0 Info: Found entity 7: hamm_reg_4_0_1 Info: Found entity 8: hamm_reg_4_0_1_unfolded0 Info: Found entity 9: mcm_network_interface Info: Found entity 10: mcm_nw_apl Info: Found entity 11: mcm_nw_bittiming_4_2_7_7_2 Info: Found entity 12: mcm_nw_destuffing_7 Info: Found entity 13: mcm_nw_dll_4_2_7_63_69_4_7 Info: Found entity 14: mcm_nw_inbuf_69_4_7 Info: Found entity 15: mcm_nw_nwl Info: Found entity 16: mcm_nw_nwsl Info: Found entity 17: mcm_nw_outbuf_69_7 Info: Found entity 18: mcm_nw_pl_1 Info: Found entity 19: mcm_nw_sendtiming_4_7_63 Info: Found entity 20: mcm_nw_stuffing_7 Info: Found entity 21: mcm_nw_timer_4_0 Info: Found entity 22: mcm_nw_timer_4_2 Info: Found entity 23: mcm_nw_timer_63_63 Info: Found entity 24: pasaadc Info: Found entity 25: pasadac Info: Found entity 26: seradc_auto Info: Found entity 27: seradc_auto_unfolded0 Info: Found entity 28: TLV2548 Info: Found entity 29: TLV5630_16 Info: Found entity 30: top Info: Found 1 design units and 1 entities in source file d:/quartus4.0/libraries/megafunctions/altsyncram.tdf Info: Found entity 1: altsyncram Info: Found 1 design units and 1 entities in source file db/altsyncram_0c21.tdf Info: Found entity 1: altsyncram_0c21 Info: Found 1 design units and 1 entities in source file db/altsyncram_hpj1.tdf Info: Found entity 1: altsyncram_hpj1 Info: Found 1 design units and 1 entities in source file d:/quartus4.0/libraries/megafunctions/altpll.tdf Info: Found entity 1: altpll Warning: Output pins are stuck at VCC or GND Warning: Pin WT_CTR stuck at GND Info: Found the following redundant logic cells in design Info: Logic cell mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_60 Info: Logic cell mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_60 Info: Logic cell mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx151 Info: Logic cell mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx149 Info: Logic cell mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx151 Info: Logic cell mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx149 Info: Logic cell mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx142 Info: Logic cell mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx142 Info: Logic cell ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx1229 Info: Logic cell ADC_DAC_0:adcdac|seradc_auto:power_adc|nx1229 Info: Logic cell ADC_DAC_0:adcdac|DDS:ddsi|b_0_dup_240 Info: Logic cell ADC_DAC_0:adcdac|DDS:ddsi|b_1_dup_418 Warning: Design contains 13 input pin(s) that do not drive logic Warning: No output dependent on input pin MSply_ADC_INTn Warning: No output dependent on input pin SC_ADC_INTn Warning: No output dependent on input pin WT_P4D[0] Warning: No output dependent on input pin WT_P4D[1] Warning: No output dependent on input pin WT_P4D[2] Warning: No output dependent on input pin WT_P4D[3] Warning: No output dependent on input pin WT_P4D[4] Warning: No output dependent on input pin WT_P4D[5] Warning: No output dependent on input pin WT_P4D[6] Warning: No output dependent on input pin WT_P4D[7] Warning: No output dependent on input pin WT_P4D[8] Warning: No output dependent on input pin WT_P4D[9] Warning: No output dependent on input pin WT_STR Info: Implemented 3074 device resources after synthesis - the final resource count might be different Info: Implemented 34 input pins Info: Implemented 66 output pins Info: Implemented 2933 logic cells Info: Implemented 40 RAM segments Info: Implemented 1 ClockLock PLLs Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings Info: Processing ended: Fri Dec 17 14:21:29 2004 Info: Elapsed time: 00:00:25