--Y1_nx181 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|nx181
--operation mode is normal

Y1_nx181 = Y1_SAMPLES0_1 $ !Y1_SAMPLES0_0;


--Y1_nx183 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|nx183
--operation mode is normal

Y1_nx183 = Y1_SAMPLES1_1 $ !Y1_SAMPLES1_0;


--Y1_d0_to_dll is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|d0_to_dll
--operation mode is normal

Y1_d0_to_dll_lut_out = Y1_SAMPLES0_1 & Y1_SAMPLES0_0;
Y1_d0_to_dll = DFFEA(Y1_d0_to_dll_lut_out, U1__clk0, VCC, , Y1_nx181, , );


--Y1_d1_to_dll is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|d1_to_dll
--operation mode is normal

Y1_d1_to_dll_lut_out = Y1_SAMPLES1_1 & Y1_SAMPLES1_0;
Y1_d1_to_dll = DFFEA(Y1_d1_to_dll_lut_out, U1__clk0, VCC, , Y1_nx183, , );


--Y1_SAMPLES0_0 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|SAMPLES0_0
--operation mode is normal

Y1_SAMPLES0_0_lut_out = SER0_IN;
Y1_SAMPLES0_0 = DFFEA(Y1_SAMPLES0_0_lut_out, U1__clk0, VCC, , , , );


--Y1_SAMPLES0_1 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|SAMPLES0_1
--operation mode is normal

Y1_SAMPLES0_1_lut_out = Y1_SAMPLES0_0;
Y1_SAMPLES0_1 = DFFEA(Y1_SAMPLES0_1_lut_out, U1__clk0, VCC, , , , );


--Y1_SAMPLES1_0 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|SAMPLES1_0
--operation mode is normal

Y1_SAMPLES1_0_lut_out = SER1_IN;
Y1_SAMPLES1_0 = DFFEA(Y1_SAMPLES1_0_lut_out, U1__clk0, VCC, , , , );


--Y1_SAMPLES1_1 is mcm_network_interface:scsn_slave|mcm_nw_pl_1:nw_pl|SAMPLES1_1
--operation mode is normal

Y1_SAMPLES1_1_lut_out = Y1_SAMPLES1_0;
Y1_SAMPLES1_1 = DFFEA(Y1_SAMPLES1_1_lut_out, U1__clk0, VCC, , , , );


--X1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|next_state_2
--operation mode is normal

X1_next_state_2 = MB1_data_out_2 & X1_nx223 # !MB1_data_out_2 & MB1_data_out_1 & X1_nx222;


--X1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|next_state_1
--operation mode is normal

X1_next_state_1 = MB1_data_out_0 & !MB1_data_out_2 & X1_nx226 # !MB1_data_out_0 & X1_nx224;


--X1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|next_state_0
--operation mode is normal

X1_next_state_0 = X1_nx227 # V1_bridge_alter & !MB1_data_out_2 & MB1_data_out_0;


--X1_reply0_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|reply0_valid
--operation mode is normal

X1_reply0_valid = V1_reply_valid & MB1_data_out_0 & (X1_nx234 # X1_nx235);


--X1_reply1_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|reply1_valid
--operation mode is normal

X1_reply1_valid = V1_reply_valid & !MB1_data_out_0 & X1_nx221;


--X1_nx771 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx771
--operation mode is normal

X1_nx771 = V1_bridge_alter & (MB1_data_out_1 $ !MB1_data_out_0 # !MB1_data_out_2);


--X1_nx777 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx777
--operation mode is normal

X1_nx777 = MB1_data_out_2 & (MB1_data_out_1 $ MB1_data_out_0);


--X1_nx818 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx818
--operation mode is normal

X1_nx818 = X1_bridge_buffered $ !X1_bridge;


--X1_altered_frame0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|altered_frame0
--operation mode is normal

X1_altered_frame0 = V1_altered_frame & MB1_data_out_0 & (!MB1_data_out_1 # !MB1_data_out_2);


--X1_wait_for_bridge is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|wait_for_bridge
--operation mode is normal

X1_wait_for_bridge = MB1_data_out_2 $ (MB1_data_out_1 & MB1_data_out_0);


--X1_altered_frame1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|altered_frame1
--operation mode is normal

X1_altered_frame1 = V1_altered_frame & !MB1_data_out_0 & (MB1_data_out_2 # MB1_data_out_1);


--X1_nx221 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx221
--operation mode is normal

X1_nx221 = MB1_data_out_2 & (MB1_data_out_1 & X1_nx818 # !MB1_data_out_1 & !V1_bridge_alter) # !MB1_data_out_2 & !V1_bridge_alter & MB1_data_out_1;


--X1_nx222 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx222
--operation mode is normal

X1_nx222 = MB1_data_out_0 & !DB1_freeze_buffer & !DB2_freeze_buffer # !MB1_data_out_0 & V1_bridge_alter;


--X1_nx223 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx223
--operation mode is normal

X1_nx223 = MB1_data_out_1 & !MB1_data_out_0 & NB2_request_valid # !MB1_data_out_1 & (NB1_request_valid # !MB1_data_out_0);


--X1_nx224 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx224
--operation mode is normal

X1_nx224 = MB1_data_out_1 & NB2_request_valid & !X1_nx231 # !MB1_data_out_1 & X1_nx225;


--X1_nx225 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx225
--operation mode is normal

X1_nx225 = MB1_data_out_2 & X1_nx232 # !MB1_data_out_2 & !NB1_request_valid & NB2_request_valid;


--X1_nx226 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx226
--operation mode is normal

X1_nx226 = MB1_data_out_1 & (DB1_freeze_buffer # DB2_freeze_buffer) # !MB1_data_out_1 & V1_bridge_alter;


--X1_nx227 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx227
--operation mode is normal

X1_nx227 = MB1_data_out_1 & !MB1_data_out_2 & MB1_data_out_0 # !MB1_data_out_1 & NB1_request_valid & (MB1_data_out_0 # !MB1_data_out_2);


--X1_nx228 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx228
--operation mode is normal

X1_nx228 = !MB1_data_out_0 & NB2_request_valid & (MB1_data_out_2 # MB1_data_out_1);


--X1_nx229 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx229
--operation mode is normal

X1_nx229 = !MB1_data_out_0 & (MB1_data_out_2 & !MB1_data_out_1 # !MB1_data_out_2 & V1_bridge_alter & MB1_data_out_1);


--X1_nx230 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx230
--operation mode is normal

X1_nx230 = !MB1_data_out_1 # !MB1_data_out_2;


--X1_nx231 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx231
--operation mode is normal

X1_nx231 = V1_bridge_alter & !MB1_data_out_2;


--X1_nx232 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx232
--operation mode is normal

X1_nx232 = !DB1_freeze_buffer & !DB2_freeze_buffer;


--X1_nx233 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx233
--operation mode is normal

X1_nx233 = !MB1_data_out_1 & NB1_request_valid;


--X1_nx234 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx234
--operation mode is normal

X1_nx234 = MB1_data_out_2 & !MB1_data_out_1 & (X1_bridge_buffered $ !X1_bridge);


--X1_nx235 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|nx235
--operation mode is normal

X1_nx235 = !V1_bridge_alter & !MB1_data_out_2;


--X1_request_52 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_52
--operation mode is normal

X1_request_52 = BB1_data_out_52 & (BB2_data_out_52 # !X1_select_rq) # !BB1_data_out_52 & BB2_data_out_52 & X1_select_rq;


--X1_request_51 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_51
--operation mode is normal

X1_request_51 = BB1_data_out_51 & (BB2_data_out_51 # !X1_select_rq) # !BB1_data_out_51 & BB2_data_out_51 & X1_select_rq;


--X1_request_50 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_50
--operation mode is normal

X1_request_50 = BB1_data_out_50 & (BB2_data_out_50 # !X1_select_rq) # !BB1_data_out_50 & BB2_data_out_50 & X1_select_rq;


--X1_request_49 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_49
--operation mode is normal

X1_request_49 = BB1_data_out_49 & (BB2_data_out_49 # !X1_select_rq) # !BB1_data_out_49 & BB2_data_out_49 & X1_select_rq;


--X1_request_48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_48
--operation mode is normal

X1_request_48 = BB1_data_out_48 & (BB2_data_out_48 # !X1_select_rq) # !BB1_data_out_48 & BB2_data_out_48 & X1_select_rq;


--X1_request_47 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_47
--operation mode is normal

X1_request_47 = BB1_data_out_47 & (BB2_data_out_47 # !X1_select_rq) # !BB1_data_out_47 & BB2_data_out_47 & X1_select_rq;


--X1_request_46 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_46
--operation mode is normal

X1_request_46 = BB1_data_out_46 & (BB2_data_out_46 # !X1_select_rq) # !BB1_data_out_46 & BB2_data_out_46 & X1_select_rq;


--X1_request_45 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_45
--operation mode is normal

X1_request_45 = BB1_data_out_45 & (BB2_data_out_45 # !X1_select_rq) # !BB1_data_out_45 & BB2_data_out_45 & X1_select_rq;


--X1_request_44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_44
--operation mode is normal

X1_request_44 = BB1_data_out_44 & (BB2_data_out_44 # !X1_select_rq) # !BB1_data_out_44 & BB2_data_out_44 & X1_select_rq;


--X1_request_43 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_43
--operation mode is normal

X1_request_43 = BB1_data_out_43 & (BB2_data_out_43 # !X1_select_rq) # !BB1_data_out_43 & BB2_data_out_43 & X1_select_rq;


--X1_request_42 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_42
--operation mode is normal

X1_request_42 = BB1_data_out_42 & (BB2_data_out_42 # !X1_select_rq) # !BB1_data_out_42 & BB2_data_out_42 & X1_select_rq;


--X1_request_41 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_41
--operation mode is normal

X1_request_41 = BB1_data_out_41 & (BB2_data_out_41 # !X1_select_rq) # !BB1_data_out_41 & BB2_data_out_41 & X1_select_rq;


--X1_request_40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_40
--operation mode is normal

X1_request_40 = BB1_data_out_40 & (BB2_data_out_40 # !X1_select_rq) # !BB1_data_out_40 & BB2_data_out_40 & X1_select_rq;


--X1_request_39 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_39
--operation mode is normal

X1_request_39 = BB1_data_out_39 & (BB2_data_out_39 # !X1_select_rq) # !BB1_data_out_39 & BB2_data_out_39 & X1_select_rq;


--X1_request_38 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_38
--operation mode is normal

X1_request_38 = BB1_data_out_38 & (BB2_data_out_38 # !X1_select_rq) # !BB1_data_out_38 & BB2_data_out_38 & X1_select_rq;


--X1_request_37 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_37
--operation mode is normal

X1_request_37 = BB1_data_out_37 & (BB2_data_out_37 # !X1_select_rq) # !BB1_data_out_37 & BB2_data_out_37 & X1_select_rq;


--X1_request_36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_36
--operation mode is normal

X1_request_36 = BB1_data_out_36 & (BB2_data_out_36 # !X1_select_rq) # !BB1_data_out_36 & BB2_data_out_36 & X1_select_rq;


--X1_request_35 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_35
--operation mode is normal

X1_request_35 = BB1_data_out_35 & (BB2_data_out_35 # !X1_select_rq) # !BB1_data_out_35 & BB2_data_out_35 & X1_select_rq;


--X1_request_34 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_34
--operation mode is normal

X1_request_34 = BB1_data_out_34 & (BB2_data_out_34 # !X1_select_rq) # !BB1_data_out_34 & BB2_data_out_34 & X1_select_rq;


--X1_request_33 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_33
--operation mode is normal

X1_request_33 = BB1_data_out_33 & (BB2_data_out_33 # !X1_select_rq) # !BB1_data_out_33 & BB2_data_out_33 & X1_select_rq;


--X1_request_32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_32
--operation mode is normal

X1_request_32 = BB1_data_out_32 & (BB2_data_out_32 # !X1_select_rq) # !BB1_data_out_32 & BB2_data_out_32 & X1_select_rq;


--X1_request_30 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_30
--operation mode is normal

X1_request_30 = BB1_data_out_30 & (BB2_data_out_30 # !X1_select_rq) # !BB1_data_out_30 & BB2_data_out_30 & X1_select_rq;


--X1_request_29 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_29
--operation mode is normal

X1_request_29 = BB1_data_out_29 & (BB2_data_out_29 # !X1_select_rq) # !BB1_data_out_29 & BB2_data_out_29 & X1_select_rq;


--X1_request_28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_28
--operation mode is normal

X1_request_28 = BB1_data_out_28 & (BB2_data_out_28 # !X1_select_rq) # !BB1_data_out_28 & BB2_data_out_28 & X1_select_rq;


--X1_request_27 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_27
--operation mode is normal

X1_request_27 = BB1_data_out_27 & (BB2_data_out_27 # !X1_select_rq) # !BB1_data_out_27 & BB2_data_out_27 & X1_select_rq;


--X1_request_26 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_26
--operation mode is normal

X1_request_26 = BB1_data_out_26 & (BB2_data_out_26 # !X1_select_rq) # !BB1_data_out_26 & BB2_data_out_26 & X1_select_rq;


--X1_request_25 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_25
--operation mode is normal

X1_request_25 = BB1_data_out_25 & (BB2_data_out_25 # !X1_select_rq) # !BB1_data_out_25 & BB2_data_out_25 & X1_select_rq;


--X1_request_24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_24
--operation mode is normal

X1_request_24 = BB1_data_out_24 & (BB2_data_out_24 # !X1_select_rq) # !BB1_data_out_24 & BB2_data_out_24 & X1_select_rq;


--X1_request_23 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_23
--operation mode is normal

X1_request_23 = BB1_data_out_23 & (BB2_data_out_23 # !X1_select_rq) # !BB1_data_out_23 & BB2_data_out_23 & X1_select_rq;


--X1_request_22 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_22
--operation mode is normal

X1_request_22 = BB1_data_out_22 & (BB2_data_out_22 # !X1_select_rq) # !BB1_data_out_22 & BB2_data_out_22 & X1_select_rq;


--X1_request_21 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_21
--operation mode is normal

X1_request_21 = BB1_data_out_21 & (BB2_data_out_21 # !X1_select_rq) # !BB1_data_out_21 & BB2_data_out_21 & X1_select_rq;


--X1_request_20 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_20
--operation mode is normal

X1_request_20 = BB1_data_out_20 & (BB2_data_out_20 # !X1_select_rq) # !BB1_data_out_20 & BB2_data_out_20 & X1_select_rq;


--X1_request_19 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_19
--operation mode is normal

X1_request_19 = BB1_data_out_19 & (BB2_data_out_19 # !X1_select_rq) # !BB1_data_out_19 & BB2_data_out_19 & X1_select_rq;


--X1_request_18 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_18
--operation mode is normal

X1_request_18 = BB1_data_out_18 & (BB2_data_out_18 # !X1_select_rq) # !BB1_data_out_18 & BB2_data_out_18 & X1_select_rq;


--X1_request_17 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_17
--operation mode is normal

X1_request_17 = BB1_data_out_17 & (BB2_data_out_17 # !X1_select_rq) # !BB1_data_out_17 & BB2_data_out_17 & X1_select_rq;


--X1_request_16 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_16
--operation mode is normal

X1_request_16 = BB1_data_out_16 & (BB2_data_out_16 # !X1_select_rq) # !BB1_data_out_16 & BB2_data_out_16 & X1_select_rq;


--X1_request_15 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_15
--operation mode is normal

X1_request_15 = BB1_data_out_15 & (BB2_data_out_15 # !X1_select_rq) # !BB1_data_out_15 & BB2_data_out_15 & X1_select_rq;


--X1_request_14 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_14
--operation mode is normal

X1_request_14 = BB1_data_out_14 & (BB2_data_out_14 # !X1_select_rq) # !BB1_data_out_14 & BB2_data_out_14 & X1_select_rq;


--X1_request_13 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_13
--operation mode is normal

X1_request_13 = BB1_data_out_13 & (BB2_data_out_13 # !X1_select_rq) # !BB1_data_out_13 & BB2_data_out_13 & X1_select_rq;


--X1_request_12 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_12
--operation mode is normal

X1_request_12 = BB1_data_out_12 & (BB2_data_out_12 # !X1_select_rq) # !BB1_data_out_12 & BB2_data_out_12 & X1_select_rq;


--X1_request_11 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_11
--operation mode is normal

X1_request_11 = BB1_data_out_11 & (BB2_data_out_11 # !X1_select_rq) # !BB1_data_out_11 & BB2_data_out_11 & X1_select_rq;


--X1_request_10 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_10
--operation mode is normal

X1_request_10 = BB1_data_out_10 & (BB2_data_out_10 # !X1_select_rq) # !BB1_data_out_10 & BB2_data_out_10 & X1_select_rq;


--X1_request_9 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_9
--operation mode is normal

X1_request_9 = BB1_data_out_9 & (BB2_data_out_9 # !X1_select_rq) # !BB1_data_out_9 & BB2_data_out_9 & X1_select_rq;


--X1_request_8 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_8
--operation mode is normal

X1_request_8 = BB1_data_out_8 & (BB2_data_out_8 # !X1_select_rq) # !BB1_data_out_8 & BB2_data_out_8 & X1_select_rq;


--X1_request_7 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_7
--operation mode is normal

X1_request_7 = BB1_data_out_7 & (BB2_data_out_7 # !X1_select_rq) # !BB1_data_out_7 & BB2_data_out_7 & X1_select_rq;


--X1_request_6 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_6
--operation mode is normal

X1_request_6 = BB1_data_out_6 & (BB2_data_out_6 # !X1_select_rq) # !BB1_data_out_6 & BB2_data_out_6 & X1_select_rq;


--X1_request_5 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_5
--operation mode is normal

X1_request_5 = BB1_data_out_5 & (BB2_data_out_5 # !X1_select_rq) # !BB1_data_out_5 & BB2_data_out_5 & X1_select_rq;


--X1_request_4 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_4
--operation mode is normal

X1_request_4 = BB1_data_out_4 & (BB2_data_out_4 # !X1_select_rq) # !BB1_data_out_4 & BB2_data_out_4 & X1_select_rq;


--X1_request_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_3
--operation mode is normal

X1_request_3 = BB1_data_out_3 & (BB2_data_out_3 # !X1_select_rq) # !BB1_data_out_3 & BB2_data_out_3 & X1_select_rq;


--X1_request_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_2
--operation mode is normal

X1_request_2 = BB1_data_out_2 & (BB2_data_out_2 # !X1_select_rq) # !BB1_data_out_2 & BB2_data_out_2 & X1_select_rq;


--X1_request_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_1
--operation mode is normal

X1_request_1 = BB1_data_out_1 & (BB2_data_out_1 # !X1_select_rq) # !BB1_data_out_1 & BB2_data_out_1 & X1_select_rq;


--X1_request_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_0
--operation mode is normal

X1_request_0 = BB1_data_out_0 & (BB2_data_out_0 # !X1_select_rq) # !BB1_data_out_0 & BB2_data_out_0 & X1_select_rq;


--X1_request_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_valid
--operation mode is normal

X1_request_valid = X1_nx228 # MB1_data_out_0 & NB1_request_valid & X1_nx230;


--X1_request_31 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_31
--operation mode is normal

X1_request_31 = BB1_data_out_31 & (BB2_data_out_31 # !X1_select_rq) # !BB1_data_out_31 & BB2_data_out_31 & X1_select_rq;

--X1_bridge_buffered is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|bridge_buffered
--operation mode is normal

X1_bridge_buffered = DFFEA(X1_request_31, U1__clk0, VCC, , X1_nx771, , );


--X1_bridge is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|bridge
--operation mode is normal

X1_bridge_lut_out = X1_bridge_buffered;
X1_bridge = DFFEA(X1_bridge_lut_out, U1__clk0, VCC, , X1_nx777, , );


--X1_select_rq is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|select_rq
--operation mode is normal

X1_select_rq_lut_out = X1_nx229 # !MB1_data_out_0 & NB2_request_valid & !X1_nx233;
X1_select_rq = DFFEA(X1_select_rq_lut_out, U1__clk0, VCC, , , , );


--NB2_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|next_state_3
--operation mode is normal

NB2_next_state_3 = NB2_nx155 # !DB2_freeze_buffer & FB4_data_out_2 & NB2_nx182;


--NB2_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|next_state_2
--operation mode is normal

NB2_next_state_2 = NB2_nx156 # NB2_nx160 # NB2_nx178 # NB2_nx179;


--NB2_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|next_state_1
--operation mode is normal

NB2_next_state_1 = NB2_nx157 # NB2_nx145 & (W1_buf1_err # NB2_nx150);


--NB2_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|next_state_0
--operation mode is normal

NB2_next_state_0 = NB2_nx163 # NB2_nx170 # NB2_nx164 & NB2_nx165;


--NB2_nx354 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx354
--operation mode is normal

NB2_nx354 = NB2_b_dirty & NB2_nx145 & (BB2_data_valid # W1_buf1_err) # !NB2_b_dirty & !BB2_data_valid & !W1_buf1_err;


--NB2_modgen_eq_717_nx24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|modgen_eq_717_nx24
--operation mode is normal

NB2_modgen_eq_717_nx24 = NB2_nx162 # !BB2_data_out_66 # !BB2_data_out_67 # !BB2_data_out_68;


--NB2_modgen_eq_718_nx0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|modgen_eq_718_nx0
--operation mode is normal

NB2_modgen_eq_718_nx0 = BB2_data_out_62 $ NB2_forward_buffer_54;


--NB2_nx143 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx143
--operation mode is normal

NB2_nx143 = !FB4_data_out_2 & FB4_data_out_0;


--NB2_nx144 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx144
--operation mode is normal

NB2_nx144 = !FB4_data_out_3 & !FB4_data_out_1;


--NB2_nx145 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx145
--operation mode is normal

NB2_nx145 = !FB4_data_out_3 & !FB4_data_out_2 & !FB4_data_out_1 & FB4_data_out_0;


--NB2_nx146 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx146
--operation mode is normal

NB2_nx146 = !FB4_data_out_2 & !FB4_data_out_0;


--NB2_nx147 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx147
--operation mode is normal

NB2_nx147 = !W1_buf1_err & NB2_modgen_eq_717_nx24 & NB2_nx143 & NB2_nx144;


--NB2_nx148 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx148
--operation mode is normal

NB2_nx148 = !FB4_data_out_2 & (FB4_data_out_0 # !X1_altered_frame1);


--NB2_nx149 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx149
--operation mode is normal

NB2_nx149 = !FB4_data_out_3 & FB4_data_out_1;


--NB2_nx150 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx150
--operation mode is normal

NB2_nx150 = NB2_forward_buffer_60 # NB2_forward_buffer_59;


--NB2_nx151 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx151
--operation mode is normal

NB2_nx151 = X1_altered_frame1 & !FB4_data_out_2 & !FB4_data_out_0;


--NB2_nx152 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx152
--operation mode is normal

NB2_nx152 = FB4_data_out_0 # !FB4_data_out_2;


--NB2_nx153 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx153
--operation mode is normal

NB2_nx153 = FB4_data_out_3 & !FB4_data_out_1;


--NB2_nx154 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx154
--operation mode is normal

NB2_nx154 = NB2_nx182 # NB2_nx144 & (BB2_data_valid # !BB2_buffer_half);


--NB2_nx155 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx155
--operation mode is normal

NB2_nx155 = !FB4_data_out_2 & NB2_nx153 & (DB2_freeze_buffer # !FB4_data_out_0);


--NB2_nx156 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx156
--operation mode is normal

NB2_nx156 = W1_buf1_err & !FB4_data_out_2 & FB4_data_out_0 & NB2_nx144;


--NB2_nx157 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx157
--operation mode is normal

NB2_nx157 = NB2_nx158 # NB2_nx159 # NB2_nx160 # NB2_nx161;


--NB2_nx158 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx158
--operation mode is normal

NB2_nx158 = NB2_nx149 & (DB2_freeze_buffer # !BB2_data_valid & !FB4_data_out_2);


--NB2_nx159 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx159
--operation mode is normal

NB2_nx159 = !FB4_data_out_0 & NB2_nx149 & (FB4_data_out_2 # !X1_reply1_valid);


--NB2_nx160 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx160
--operation mode is normal

NB2_nx160 = !BB2_data_valid & BB2_buffer_half & FB4_data_out_2 & NB2_nx144;


--NB2_nx161 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx161
--operation mode is normal

NB2_nx161 = NB2_nx145 & (NB2_forward_buffer_54 # NB2_forward_buffer_53 # NB2_nx177);


--NB2_nx162 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx162
--operation mode is normal

NB2_nx162 = !BB2_data_out_62 # !BB2_data_out_63 # !BB2_data_out_64 # !BB2_data_out_65;


--NB2_nx163 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx163
--operation mode is normal

NB2_nx163 = NB2_nx172 # NB2_nx144 & NB2_nx146 & NB2_nx173;


--NB2_nx164 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx164
--operation mode is normal

NB2_nx164 = NB2_nx175 # NB2_nx147 & (NB2_nx168 # NB2_nx169);


--NB2_nx165 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx165
--operation mode is normal

NB2_nx165 = NB2_forward_buffer_58 # NB2_forward_buffer_57 # NB2_nx150 # NB2_nx171;


--NB2_nx166 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx166
--operation mode is normal

NB2_nx166 = !X1_altered_frame1 & NB2_nx146 & (NB2_modgen_eq_717_nx24 # !X1_bridge);


--NB2_nx167 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx167
--operation mode is normal

NB2_nx167 = BB2_data_out_66 & (BB2_data_out_65 $ NB2_forward_buffer_57 # !NB2_forward_buffer_58) # !BB2_data_out_66 & (NB2_forward_buffer_58 # BB2_data_out_65 $ NB2_forward_buffer_57);


--NB2_nx168 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx168
--operation mode is normal

NB2_nx168 = BB2_data_out_64 & (BB2_data_out_63 $ NB2_forward_buffer_55 # !NB2_forward_buffer_56) # !BB2_data_out_64 & (NB2_forward_buffer_56 # BB2_data_out_63 $ NB2_forward_buffer_55);


--NB2_nx169 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx169
--operation mode is normal

NB2_nx169 = BB2_data_out_68 & (BB2_data_out_67 $ NB2_forward_buffer_59 # !NB2_forward_buffer_60) # !BB2_data_out_68 & (NB2_forward_buffer_60 # BB2_data_out_67 $ NB2_forward_buffer_59);


--NB2_nx170 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx170
--operation mode is normal

NB2_nx170 = DB2_freeze_buffer & (FB4_data_out_2 & NB2_nx154 # !FB4_data_out_2 & NB2_nx153);


--NB2_nx171 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx171
--operation mode is normal

NB2_nx171 = NB2_forward_buffer_56 # NB2_forward_buffer_55 # NB2_forward_buffer_54 # NB2_forward_buffer_53;


--NB2_nx172 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx172
--operation mode is normal

NB2_nx172 = NB2_nx149 & (NB2_nx174 # !X1_wait_for_bridge & !NB2_nx152);


--NB2_nx173 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx173
--operation mode is normal

NB2_nx173 = !X1_wait_for_bridge & NB2_b_dirty & (BB2_data_valid # W1_buf1_err);


--NB2_nx174 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx174
--operation mode is normal

NB2_nx174 = BB2_data_valid & DB2_freeze_buffer & !FB4_data_out_2 & FB4_data_out_0;


--NB2_nx175 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx175
--operation mode is normal

NB2_nx175 = NB2_nx176 # NB2_nx147 & (NB2_modgen_eq_718_nx0 # NB2_nx167);


--NB2_nx176 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx176
--operation mode is normal

NB2_nx176 = !BB2_data_out_61 & !W1_buf1_err & NB2_nx145;


--NB2_nx177 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx177
--operation mode is normal

NB2_nx177 = NB2_forward_buffer_58 # NB2_forward_buffer_57 # NB2_forward_buffer_56 # NB2_forward_buffer_55;


--NB2_nx178 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx178
--operation mode is normal

NB2_nx178 = !FB4_data_out_3 & FB4_data_out_1 & (NB2_nx180 # NB2_nx181);


--NB2_nx179 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx179
--operation mode is normal

NB2_nx179 = !FB4_data_out_3 & FB4_data_out_2 & (DB2_freeze_buffer # !FB4_data_out_0);


--NB2_nx180 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx180
--operation mode is normal

NB2_nx180 = !FB4_data_out_0 & (!DB2_freeze_buffer & X1_reply1_valid # !BB2_data_valid);


--NB2_nx181 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx181
--operation mode is normal

NB2_nx181 = !FB4_data_out_2 & FB4_data_out_0 & (!DB2_freeze_buffer # !BB2_data_valid);


--NB2_nx182 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|nx182
--operation mode is normal

NB2_nx182 = !FB4_data_out_3 & FB4_data_out_1 & FB4_data_out_0;


--NB2_d_to_dll_68 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_68
--operation mode is normal

NB2_d_to_dll_68 = BB2_data_out_68 & (NB2_nx148 # NB2_forward_buffer_60 & NB2_nx151) # !BB2_data_out_68 & NB2_forward_buffer_60 & NB2_nx151;


--NB2_d_to_dll_67 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_67
--operation mode is normal

NB2_d_to_dll_67 = BB2_data_out_67 & (NB2_nx148 # NB2_forward_buffer_59 & NB2_nx151) # !BB2_data_out_67 & NB2_forward_buffer_59 & NB2_nx151;


--NB2_d_to_dll_66 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_66
--operation mode is normal

NB2_d_to_dll_66 = BB2_data_out_66 & (NB2_nx148 # NB2_forward_buffer_58 & NB2_nx151) # !BB2_data_out_66 & NB2_forward_buffer_58 & NB2_nx151;


--NB2_d_to_dll_65 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_65
--operation mode is normal

NB2_d_to_dll_65 = BB2_data_out_65 & (NB2_nx148 # NB2_forward_buffer_57 & NB2_nx151) # !BB2_data_out_65 & NB2_forward_buffer_57 & NB2_nx151;


--NB2_d_to_dll_64 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_64
--operation mode is normal

NB2_d_to_dll_64 = BB2_data_out_64 & (NB2_nx148 # NB2_forward_buffer_56 & NB2_nx151) # !BB2_data_out_64 & NB2_forward_buffer_56 & NB2_nx151;


--NB2_d_to_dll_63 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_63
--operation mode is normal

NB2_d_to_dll_63 = BB2_data_out_63 & (NB2_nx148 # NB2_forward_buffer_55 & NB2_nx151) # !BB2_data_out_63 & NB2_forward_buffer_55 & NB2_nx151;


--NB2_d_to_dll_62 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_62
--operation mode is normal

NB2_d_to_dll_62 = BB2_data_out_62 & (NB2_nx148 # NB2_forward_buffer_54 & NB2_nx151) # !BB2_data_out_62 & NB2_forward_buffer_54 & NB2_nx151;


--NB2_d_to_dll_61 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_61
--operation mode is normal

NB2_d_to_dll_61 = NB2_nx166 # BB2_data_out_61 & !FB4_data_out_2 & FB4_data_out_0;


--NB2_d_to_dll_60 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_60
--operation mode is normal

NB2_d_to_dll_60 = !FB4_data_out_2 & NB2_forward_buffer_60 & (FB4_data_out_0 # !X1_altered_frame1);


--NB2_d_to_dll_59 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_59
--operation mode is normal

NB2_d_to_dll_59 = !FB4_data_out_2 & NB2_forward_buffer_59 & (FB4_data_out_0 # !X1_altered_frame1);


--NB2_d_to_dll_58 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_58
--operation mode is normal

NB2_d_to_dll_58 = !FB4_data_out_2 & NB2_forward_buffer_58 & (FB4_data_out_0 # !X1_altered_frame1);


--NB2_d_to_dll_57 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_57
--operation mode is normal

NB2_d_to_dll_57 = !FB4_data_out_2 & NB2_forward_buffer_57 & (FB4_data_out_0 # !X1_altered_frame1);


--NB2_d_to_dll_56 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_56
--operation mode is normal

NB2_d_to_dll_56 = !FB4_data_out_2 & NB2_forward_buffer_56 & (FB4_data_out_0 # !X1_altered_frame1);


--NB2_d_to_dll_55 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_55
--operation mode is normal

NB2_d_to_dll_55 = !FB4_data_out_2 & NB2_forward_buffer_55 & (FB4_data_out_0 # !X1_altered_frame1);


--NB2_d_to_dll_54 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_54
--operation mode is normal

NB2_d_to_dll_54 = !FB4_data_out_2 & NB2_forward_buffer_54 & (FB4_data_out_0 # !X1_altered_frame1);


--NB2_d_to_dll_53 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_53
--operation mode is normal

NB2_d_to_dll_53 = !FB4_data_out_2 & NB2_forward_buffer_53 & (FB4_data_out_0 # !X1_altered_frame1);


--NB2_d_to_dll_52 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_52
--operation mode is normal

NB2_d_to_dll_52 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_52 # !FB4_data_out_0 & V1_reply_52);


--NB2_d_to_dll_51 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_51
--operation mode is normal

NB2_d_to_dll_51 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_51 # !FB4_data_out_0 & V1_reply_51);


--NB2_d_to_dll_50 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_50
--operation mode is normal

NB2_d_to_dll_50 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_50 # !FB4_data_out_0 & V1_reply_50);


--NB2_d_to_dll_49 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_49
--operation mode is normal

NB2_d_to_dll_49 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_49 # !FB4_data_out_0 & V1_reply_49);


--NB2_d_to_dll_48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_48
--operation mode is normal

NB2_d_to_dll_48 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_48 # !FB4_data_out_0 & V1_reply_48);


--NB2_d_to_dll_47 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_47
--operation mode is normal

NB2_d_to_dll_47 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_47 # !FB4_data_out_0 & V1_reply_47);


--NB2_d_to_dll_46 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_46
--operation mode is normal

NB2_d_to_dll_46 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_46 # !FB4_data_out_0 & V1_reply_46);


--NB2_d_to_dll_45 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_45
--operation mode is normal

NB2_d_to_dll_45 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_45 # !FB4_data_out_0 & V1_reply_45);


--NB2_d_to_dll_44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_44
--operation mode is normal

NB2_d_to_dll_44 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_44 # !FB4_data_out_0 & V1_reply_44);


--NB2_d_to_dll_43 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_43
--operation mode is normal

NB2_d_to_dll_43 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_43 # !FB4_data_out_0 & V1_reply_43);


--NB2_d_to_dll_42 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_42
--operation mode is normal

NB2_d_to_dll_42 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_42 # !FB4_data_out_0 & V1_reply_42);


--NB2_d_to_dll_41 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_41
--operation mode is normal

NB2_d_to_dll_41 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_41 # !FB4_data_out_0 & V1_reply_41);


--NB2_d_to_dll_40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_40
--operation mode is normal

NB2_d_to_dll_40 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_40 # !FB4_data_out_0 & V1_reply_40);


--NB2_d_to_dll_39 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_39
--operation mode is normal

NB2_d_to_dll_39 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_39 # !FB4_data_out_0 & V1_reply_39);


--NB2_d_to_dll_38 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_38
--operation mode is normal

NB2_d_to_dll_38 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_38 # !FB4_data_out_0 & V1_reply_38);


--NB2_d_to_dll_37 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_37
--operation mode is normal

NB2_d_to_dll_37 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_37 # !FB4_data_out_0 & V1_reply_37);


--NB2_d_to_dll_36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_36
--operation mode is normal

NB2_d_to_dll_36 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_36 # !FB4_data_out_0 & V1_reply_36);


--NB2_d_to_dll_35 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_35
--operation mode is normal

NB2_d_to_dll_35 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_35 # !FB4_data_out_0 & V1_reply_35);


--NB2_d_to_dll_34 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_34
--operation mode is normal

NB2_d_to_dll_34 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_34 # !FB4_data_out_0 & V1_reply_34);


--NB2_d_to_dll_33 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_33
--operation mode is normal

NB2_d_to_dll_33 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_33 # !FB4_data_out_0 & V1_reply_33);


--NB2_d_to_dll_32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_32
--operation mode is normal

NB2_d_to_dll_32 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_32 # !FB4_data_out_0 & V1_reply_32);


--NB2_d_to_dll_31 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_31
--operation mode is normal

NB2_d_to_dll_31 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_31 # !FB4_data_out_0 & V1_reply_31);


--NB2_d_to_dll_30 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_30
--operation mode is normal

NB2_d_to_dll_30 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_30 # !FB4_data_out_0 & V1_reply_30);


--NB2_d_to_dll_29 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_29
--operation mode is normal

NB2_d_to_dll_29 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_29 # !FB4_data_out_0 & V1_reply_29);


--NB2_d_to_dll_28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_28
--operation mode is normal

NB2_d_to_dll_28 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_28 # !FB4_data_out_0 & V1_reply_28);


--NB2_d_to_dll_27 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_27
--operation mode is normal

NB2_d_to_dll_27 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_27 # !FB4_data_out_0 & V1_reply_27);


--NB2_d_to_dll_26 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_26
--operation mode is normal

NB2_d_to_dll_26 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_26 # !FB4_data_out_0 & V1_reply_26);


--NB2_d_to_dll_25 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_25
--operation mode is normal

NB2_d_to_dll_25 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_25 # !FB4_data_out_0 & V1_reply_25);


--NB2_d_to_dll_24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_24
--operation mode is normal

NB2_d_to_dll_24 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_24 # !FB4_data_out_0 & V1_reply_24);


--NB2_d_to_dll_23 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_23
--operation mode is normal

NB2_d_to_dll_23 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_23 # !FB4_data_out_0 & V1_reply_23);


--NB2_d_to_dll_22 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_22
--operation mode is normal

NB2_d_to_dll_22 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_22 # !FB4_data_out_0 & V1_reply_22);


--NB2_d_to_dll_21 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_21
--operation mode is normal

NB2_d_to_dll_21 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_21 # !FB4_data_out_0 & V1_reply_21);


--NB2_d_to_dll_20 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_20
--operation mode is normal

NB2_d_to_dll_20 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_20 # !FB4_data_out_0 & V1_reply_20);


--NB2_d_to_dll_19 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_19
--operation mode is normal

NB2_d_to_dll_19 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_19 # !FB4_data_out_0 & V1_reply_19);


--NB2_d_to_dll_18 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_18
--operation mode is normal

NB2_d_to_dll_18 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_18 # !FB4_data_out_0 & V1_reply_18);


--NB2_d_to_dll_17 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_17
--operation mode is normal

NB2_d_to_dll_17 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_17 # !FB4_data_out_0 & V1_reply_17);


--NB2_d_to_dll_16 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_16
--operation mode is normal

NB2_d_to_dll_16 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_16 # !FB4_data_out_0 & V1_reply_16);


--NB2_d_to_dll_15 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_15
--operation mode is normal

NB2_d_to_dll_15 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_15 # !FB4_data_out_0 & V1_reply_15);


--NB2_d_to_dll_14 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_14
--operation mode is normal

NB2_d_to_dll_14 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_14 # !FB4_data_out_0 & V1_reply_14);


--NB2_d_to_dll_13 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_13
--operation mode is normal

NB2_d_to_dll_13 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_13 # !FB4_data_out_0 & V1_reply_13);


--NB2_d_to_dll_12 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_12
--operation mode is normal

NB2_d_to_dll_12 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_12 # !FB4_data_out_0 & V1_reply_12);


--NB2_d_to_dll_11 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_11
--operation mode is normal

NB2_d_to_dll_11 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_11 # !FB4_data_out_0 & V1_reply_11);


--NB2_d_to_dll_10 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_10
--operation mode is normal

NB2_d_to_dll_10 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_10 # !FB4_data_out_0 & V1_reply_10);


--NB2_d_to_dll_9 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_9
--operation mode is normal

NB2_d_to_dll_9 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_9 # !FB4_data_out_0 & V1_reply_9);


--NB2_d_to_dll_8 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_8
--operation mode is normal

NB2_d_to_dll_8 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_8 # !FB4_data_out_0 & V1_reply_8);


--NB2_d_to_dll_7 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_7
--operation mode is normal

NB2_d_to_dll_7 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_7 # !FB4_data_out_0 & V1_reply_7);


--NB2_d_to_dll_6 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_6
--operation mode is normal

NB2_d_to_dll_6 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_6 # !FB4_data_out_0 & V1_reply_6);


--NB2_d_to_dll_5 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_5
--operation mode is normal

NB2_d_to_dll_5 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_5 # !FB4_data_out_0 & V1_reply_5);


--NB2_d_to_dll_4 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_4
--operation mode is normal

NB2_d_to_dll_4 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_4 # !FB4_data_out_0 & V1_reply_4);


--NB2_d_to_dll_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_3
--operation mode is normal

NB2_d_to_dll_3 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_3 # !FB4_data_out_0 & V1_reply_3);


--NB2_d_to_dll_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_2
--operation mode is normal

NB2_d_to_dll_2 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_2 # !FB4_data_out_0 & V1_reply_2);


--NB2_d_to_dll_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_1
--operation mode is normal

NB2_d_to_dll_1 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_1 # !FB4_data_out_0 & V1_reply_1);


--NB2_d_to_dll_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_to_dll_0
--operation mode is normal

NB2_d_to_dll_0 = !FB4_data_out_2 & (FB4_data_out_0 & BB2_data_out_0 # !FB4_data_out_0 & V1_reply_0);


--NB2_d_we is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_we
--operation mode is normal

NB2_d_we = !FB4_data_out_3 & FB4_data_out_1 & (FB4_data_out_0 # !FB4_data_out_2);


--NB2_d_initiate_send is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|d_initiate_send
--operation mode is normal

NB2_d_initiate_send = !FB4_data_out_1 & !FB4_data_out_0 & (FB4_data_out_3 $ FB4_data_out_2);


--NB2_request_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|request_valid
--operation mode is normal

NB2_request_valid = !FB4_data_out_3 & !FB4_data_out_2 & FB4_data_out_1 & !FB4_data_out_0;


--NB2_b_dirty is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|b_dirty
--operation mode is normal

NB2_b_dirty_lut_out = !BB2_data_valid & !W1_buf1_err & !NB2_b_dirty;
NB2_b_dirty = DFFEA(NB2_b_dirty_lut_out, U1__clk0, VCC, , NB2_nx354, , );


--NB2_forward_buffer_60 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_60
--operation mode is normal

NB2_forward_buffer_60 = !BB2_data_out_60;


--NB2_result_inc_805_nx24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_805_nx24
--operation mode is arithmetic

NB2_result_inc_805_nx24 = CARRY(BB2_data_out_60);


--NB2_forward_buffer_59 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_59
--operation mode is arithmetic

NB2_forward_buffer_59_carry_eqn = NB2_result_inc_805_nx24;
NB2_forward_buffer_59 = BB2_data_out_59 $ NB2_forward_buffer_59_carry_eqn;

--NB2_result_inc_805_nx28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_805_nx28
--operation mode is arithmetic

NB2_result_inc_805_nx28 = CARRY(!NB2_result_inc_805_nx24 # !BB2_data_out_59);


--NB2_forward_buffer_58 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_58
--operation mode is arithmetic

NB2_forward_buffer_58_carry_eqn = NB2_result_inc_805_nx28;
NB2_forward_buffer_58 = BB2_data_out_58 $ !NB2_forward_buffer_58_carry_eqn;

--NB2_result_inc_805_nx32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_805_nx32
--operation mode is arithmetic

NB2_result_inc_805_nx32 = CARRY(BB2_data_out_58 & !NB2_result_inc_805_nx28);


--NB2_forward_buffer_57 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_57
--operation mode is arithmetic

NB2_forward_buffer_57_carry_eqn = NB2_result_inc_805_nx32;
NB2_forward_buffer_57 = BB2_data_out_57 $ NB2_forward_buffer_57_carry_eqn;

--NB2_result_inc_805_nx36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_805_nx36
--operation mode is arithmetic

NB2_result_inc_805_nx36 = CARRY(!NB2_result_inc_805_nx32 # !BB2_data_out_57);


--NB2_forward_buffer_56 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_56
--operation mode is arithmetic

NB2_forward_buffer_56_carry_eqn = NB2_result_inc_805_nx36;
NB2_forward_buffer_56 = BB2_data_out_56 $ !NB2_forward_buffer_56_carry_eqn;

--NB2_result_inc_805_nx40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_805_nx40
--operation mode is arithmetic

NB2_result_inc_805_nx40 = CARRY(BB2_data_out_56 & !NB2_result_inc_805_nx36);


--NB2_forward_buffer_55 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_55
--operation mode is arithmetic

NB2_forward_buffer_55_carry_eqn = NB2_result_inc_805_nx40;
NB2_forward_buffer_55 = BB2_data_out_55 $ NB2_forward_buffer_55_carry_eqn;

--NB2_result_inc_805_nx44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_805_nx44
--operation mode is arithmetic

NB2_result_inc_805_nx44 = CARRY(!NB2_result_inc_805_nx40 # !BB2_data_out_55);


--NB2_forward_buffer_54 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_54
--operation mode is arithmetic

NB2_forward_buffer_54_carry_eqn = NB2_result_inc_805_nx44;
NB2_forward_buffer_54 = BB2_data_out_54 $ !NB2_forward_buffer_54_carry_eqn;

--NB2_result_inc_805_nx48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|result_inc_805_nx48
--operation mode is arithmetic

NB2_result_inc_805_nx48 = CARRY(BB2_data_out_54 & !NB2_result_inc_805_nx44);


--NB2_forward_buffer_53 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|forward_buffer_53
--operation mode is normal

NB2_forward_buffer_53_carry_eqn = NB2_result_inc_805_nx48;
NB2_forward_buffer_53 = BB2_data_out_53 $ NB2_forward_buffer_53_carry_eqn;


--FB4_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1|data_out_0
--operation mode is normal

FB4_data_out_0_lut_out = NB2_next_state_0;
FB4_data_out_0 = DFFEA(FB4_data_out_0_lut_out, U1__clk0, VCC, , , , );


--FB4_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1|data_out_1
--operation mode is normal

FB4_data_out_1_lut_out = NB2_next_state_1;
FB4_data_out_1 = DFFEA(FB4_data_out_1_lut_out, U1__clk0, VCC, , , , );


--FB4_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1|data_out_2
--operation mode is normal

FB4_data_out_2_lut_out = NB2_next_state_2;
FB4_data_out_2 = DFFEA(FB4_data_out_2_lut_out, U1__clk0, VCC, , , , );


--FB4_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl1|hamm_reg_4_0_1:h1|data_out_3
--operation mode is normal

FB4_data_out_3_lut_out = NB2_next_state_3;
FB4_data_out_3 = DFFEA(FB4_data_out_3_lut_out, U1__clk0, VCC, , , , );


--NB1_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|next_state_3
--operation mode is normal

NB1_next_state_3 = NB1_nx155 # !DB1_freeze_buffer & FB3_data_out_2 & NB1_nx182;


--NB1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|next_state_2
--operation mode is normal

NB1_next_state_2 = NB1_nx156 # NB1_nx160 # NB1_nx178 # NB1_nx179;


--NB1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|next_state_1
--operation mode is normal

NB1_next_state_1 = NB1_nx157 # NB1_nx145 & (W1_buf0_err # NB1_nx150);


--NB1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|next_state_0
--operation mode is normal

NB1_next_state_0 = NB1_nx163 # NB1_nx170 # NB1_nx164 & NB1_nx165;


--NB1_nx354 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx354
--operation mode is normal

NB1_nx354 = NB1_b_dirty & NB1_nx145 & (BB1_data_valid # W1_buf0_err) # !NB1_b_dirty & !BB1_data_valid & !W1_buf0_err;


--NB1_modgen_eq_717_nx24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|modgen_eq_717_nx24
--operation mode is normal

NB1_modgen_eq_717_nx24 = NB1_nx162 # !BB1_data_out_66 # !BB1_data_out_67 # !BB1_data_out_68;


--NB1_modgen_eq_718_nx0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|modgen_eq_718_nx0
--operation mode is normal

NB1_modgen_eq_718_nx0 = BB1_data_out_62 $ NB1_forward_buffer_54;


--NB1_nx143 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx143
--operation mode is normal

NB1_nx143 = !FB3_data_out_2 & FB3_data_out_0;


--NB1_nx144 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx144
--operation mode is normal

NB1_nx144 = !FB3_data_out_3 & !FB3_data_out_1;


--NB1_nx145 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx145
--operation mode is normal

NB1_nx145 = !FB3_data_out_3 & !FB3_data_out_2 & !FB3_data_out_1 & FB3_data_out_0;


--NB1_nx146 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx146
--operation mode is normal

NB1_nx146 = !FB3_data_out_2 & !FB3_data_out_0;


--NB1_nx147 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx147
--operation mode is normal

NB1_nx147 = !W1_buf0_err & NB1_modgen_eq_717_nx24 & NB1_nx143 & NB1_nx144;


--NB1_nx148 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx148
--operation mode is normal

NB1_nx148 = !FB3_data_out_2 & (FB3_data_out_0 # !X1_altered_frame0);


--NB1_nx149 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx149
--operation mode is normal

NB1_nx149 = !FB3_data_out_3 & FB3_data_out_1;


--NB1_nx150 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx150
--operation mode is normal

NB1_nx150 = NB1_forward_buffer_60 # NB1_forward_buffer_59;


--NB1_nx151 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx151
--operation mode is normal

NB1_nx151 = X1_altered_frame0 & !FB3_data_out_2 & !FB3_data_out_0;


--NB1_nx152 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx152
--operation mode is normal

NB1_nx152 = FB3_data_out_0 # !FB3_data_out_2;


--NB1_nx153 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx153
--operation mode is normal

NB1_nx153 = FB3_data_out_3 & !FB3_data_out_1;


--NB1_nx154 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx154
--operation mode is normal

NB1_nx154 = NB1_nx182 # NB1_nx144 & (BB1_data_valid # !BB1_buffer_half);


--NB1_nx155 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx155
--operation mode is normal

NB1_nx155 = !FB3_data_out_2 & NB1_nx153 & (DB1_freeze_buffer # !FB3_data_out_0);


--NB1_nx156 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx156
--operation mode is normal

NB1_nx156 = W1_buf0_err & !FB3_data_out_2 & FB3_data_out_0 & NB1_nx144;


--NB1_nx157 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx157
--operation mode is normal

NB1_nx157 = NB1_nx158 # NB1_nx159 # NB1_nx160 # NB1_nx161;


--NB1_nx158 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx158
--operation mode is normal

NB1_nx158 = NB1_nx149 & (DB1_freeze_buffer # !BB1_data_valid & !FB3_data_out_2);


--NB1_nx159 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx159
--operation mode is normal

NB1_nx159 = !FB3_data_out_0 & NB1_nx149 & (FB3_data_out_2 # !X1_reply0_valid);


--NB1_nx160 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx160
--operation mode is normal

NB1_nx160 = !BB1_data_valid & BB1_buffer_half & FB3_data_out_2 & NB1_nx144;


--NB1_nx161 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx161
--operation mode is normal

NB1_nx161 = NB1_nx145 & (NB1_forward_buffer_54 # NB1_forward_buffer_53 # NB1_nx177);


--NB1_nx162 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx162
--operation mode is normal

NB1_nx162 = !BB1_data_out_62 # !BB1_data_out_63 # !BB1_data_out_64 # !BB1_data_out_65;


--NB1_nx163 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx163
--operation mode is normal

NB1_nx163 = NB1_nx172 # NB1_nx144 & NB1_nx146 & NB1_nx173;


--NB1_nx164 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx164
--operation mode is normal

NB1_nx164 = NB1_nx175 # NB1_nx147 & (NB1_nx168 # NB1_nx169);


--NB1_nx165 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx165
--operation mode is normal

NB1_nx165 = NB1_forward_buffer_58 # NB1_forward_buffer_57 # NB1_nx150 # NB1_nx171;


--NB1_nx166 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx166
--operation mode is normal

NB1_nx166 = !X1_altered_frame0 & NB1_nx146 & (NB1_modgen_eq_717_nx24 # !X1_bridge);


--NB1_nx167 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx167
--operation mode is normal

NB1_nx167 = BB1_data_out_66 & (BB1_data_out_65 $ NB1_forward_buffer_57 # !NB1_forward_buffer_58) # !BB1_data_out_66 & (NB1_forward_buffer_58 # BB1_data_out_65 $ NB1_forward_buffer_57);


--NB1_nx168 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx168
--operation mode is normal

NB1_nx168 = BB1_data_out_64 & (BB1_data_out_63 $ NB1_forward_buffer_55 # !NB1_forward_buffer_56) # !BB1_data_out_64 & (NB1_forward_buffer_56 # BB1_data_out_63 $ NB1_forward_buffer_55);


--NB1_nx169 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx169
--operation mode is normal

NB1_nx169 = BB1_data_out_68 & (BB1_data_out_67 $ NB1_forward_buffer_59 # !NB1_forward_buffer_60) # !BB1_data_out_68 & (NB1_forward_buffer_60 # BB1_data_out_67 $ NB1_forward_buffer_59);


--NB1_nx170 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx170
--operation mode is normal

NB1_nx170 = DB1_freeze_buffer & (FB3_data_out_2 & NB1_nx154 # !FB3_data_out_2 & NB1_nx153);


--NB1_nx171 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx171
--operation mode is normal

NB1_nx171 = NB1_forward_buffer_56 # NB1_forward_buffer_55 # NB1_forward_buffer_54 # NB1_forward_buffer_53;


--NB1_nx172 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx172
--operation mode is normal

NB1_nx172 = NB1_nx149 & (NB1_nx174 # !X1_wait_for_bridge & !NB1_nx152);


--NB1_nx173 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx173
--operation mode is normal

NB1_nx173 = !X1_wait_for_bridge & NB1_b_dirty & (BB1_data_valid # W1_buf0_err);


--NB1_nx174 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx174
--operation mode is normal

NB1_nx174 = BB1_data_valid & DB1_freeze_buffer & !FB3_data_out_2 & FB3_data_out_0;


--NB1_nx175 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx175
--operation mode is normal

NB1_nx175 = NB1_nx176 # NB1_nx147 & (NB1_modgen_eq_718_nx0 # NB1_nx167);


--NB1_nx176 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx176
--operation mode is normal

NB1_nx176 = !BB1_data_out_61 & !W1_buf0_err & NB1_nx145;


--NB1_nx177 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx177
--operation mode is normal

NB1_nx177 = NB1_forward_buffer_58 # NB1_forward_buffer_57 # NB1_forward_buffer_56 # NB1_forward_buffer_55;


--NB1_nx178 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx178
--operation mode is normal

NB1_nx178 = !FB3_data_out_3 & FB3_data_out_1 & (NB1_nx180 # NB1_nx181);


--NB1_nx179 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx179
--operation mode is normal

NB1_nx179 = !FB3_data_out_3 & FB3_data_out_2 & (DB1_freeze_buffer # !FB3_data_out_0);


--NB1_nx180 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx180
--operation mode is normal

NB1_nx180 = !FB3_data_out_0 & (!DB1_freeze_buffer & X1_reply0_valid # !BB1_data_valid);


--NB1_nx181 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx181
--operation mode is normal

NB1_nx181 = !FB3_data_out_2 & FB3_data_out_0 & (!DB1_freeze_buffer # !BB1_data_valid);


--NB1_nx182 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|nx182
--operation mode is normal

NB1_nx182 = !FB3_data_out_3 & FB3_data_out_1 & FB3_data_out_0;


--NB1_d_to_dll_68 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_68
--operation mode is normal

NB1_d_to_dll_68 = BB1_data_out_68 & (NB1_nx148 # NB1_forward_buffer_60 & NB1_nx151) # !BB1_data_out_68 & NB1_forward_buffer_60 & NB1_nx151;


--NB1_d_to_dll_67 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_67
--operation mode is normal

NB1_d_to_dll_67 = BB1_data_out_67 & (NB1_nx148 # NB1_forward_buffer_59 & NB1_nx151) # !BB1_data_out_67 & NB1_forward_buffer_59 & NB1_nx151;


--NB1_d_to_dll_66 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_66
--operation mode is normal

NB1_d_to_dll_66 = BB1_data_out_66 & (NB1_nx148 # NB1_forward_buffer_58 & NB1_nx151) # !BB1_data_out_66 & NB1_forward_buffer_58 & NB1_nx151;


--NB1_d_to_dll_65 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_65
--operation mode is normal

NB1_d_to_dll_65 = BB1_data_out_65 & (NB1_nx148 # NB1_forward_buffer_57 & NB1_nx151) # !BB1_data_out_65 & NB1_forward_buffer_57 & NB1_nx151;


--NB1_d_to_dll_64 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_64
--operation mode is normal

NB1_d_to_dll_64 = BB1_data_out_64 & (NB1_nx148 # NB1_forward_buffer_56 & NB1_nx151) # !BB1_data_out_64 & NB1_forward_buffer_56 & NB1_nx151;


--NB1_d_to_dll_63 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_63
--operation mode is normal

NB1_d_to_dll_63 = BB1_data_out_63 & (NB1_nx148 # NB1_forward_buffer_55 & NB1_nx151) # !BB1_data_out_63 & NB1_forward_buffer_55 & NB1_nx151;


--NB1_d_to_dll_62 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_62
--operation mode is normal

NB1_d_to_dll_62 = BB1_data_out_62 & (NB1_nx148 # NB1_forward_buffer_54 & NB1_nx151) # !BB1_data_out_62 & NB1_forward_buffer_54 & NB1_nx151;


--NB1_d_to_dll_61 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_61
--operation mode is normal

NB1_d_to_dll_61 = NB1_nx166 # BB1_data_out_61 & !FB3_data_out_2 & FB3_data_out_0;


--NB1_d_to_dll_60 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_60
--operation mode is normal

NB1_d_to_dll_60 = !FB3_data_out_2 & NB1_forward_buffer_60 & (FB3_data_out_0 # !X1_altered_frame0);


--NB1_d_to_dll_59 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_59
--operation mode is normal

NB1_d_to_dll_59 = !FB3_data_out_2 & NB1_forward_buffer_59 & (FB3_data_out_0 # !X1_altered_frame0);


--NB1_d_to_dll_58 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_58
--operation mode is normal

NB1_d_to_dll_58 = !FB3_data_out_2 & NB1_forward_buffer_58 & (FB3_data_out_0 # !X1_altered_frame0);


--NB1_d_to_dll_57 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_57
--operation mode is normal

NB1_d_to_dll_57 = !FB3_data_out_2 & NB1_forward_buffer_57 & (FB3_data_out_0 # !X1_altered_frame0);


--NB1_d_to_dll_56 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_56
--operation mode is normal

NB1_d_to_dll_56 = !FB3_data_out_2 & NB1_forward_buffer_56 & (FB3_data_out_0 # !X1_altered_frame0);


--NB1_d_to_dll_55 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_55
--operation mode is normal

NB1_d_to_dll_55 = !FB3_data_out_2 & NB1_forward_buffer_55 & (FB3_data_out_0 # !X1_altered_frame0);


--NB1_d_to_dll_54 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_54
--operation mode is normal

NB1_d_to_dll_54 = !FB3_data_out_2 & NB1_forward_buffer_54 & (FB3_data_out_0 # !X1_altered_frame0);


--NB1_d_to_dll_53 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_53
--operation mode is normal

NB1_d_to_dll_53 = !FB3_data_out_2 & NB1_forward_buffer_53 & (FB3_data_out_0 # !X1_altered_frame0);


--NB1_d_to_dll_52 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_52
--operation mode is normal

NB1_d_to_dll_52 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_52 # !FB3_data_out_0 & V1_reply_52);


--NB1_d_to_dll_51 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_51
--operation mode is normal

NB1_d_to_dll_51 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_51 # !FB3_data_out_0 & V1_reply_51);


--NB1_d_to_dll_50 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_50
--operation mode is normal

NB1_d_to_dll_50 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_50 # !FB3_data_out_0 & V1_reply_50);


--NB1_d_to_dll_49 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_49
--operation mode is normal

NB1_d_to_dll_49 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_49 # !FB3_data_out_0 & V1_reply_49);


--NB1_d_to_dll_48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_48
--operation mode is normal

NB1_d_to_dll_48 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_48 # !FB3_data_out_0 & V1_reply_48);


--NB1_d_to_dll_47 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_47
--operation mode is normal

NB1_d_to_dll_47 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_47 # !FB3_data_out_0 & V1_reply_47);


--NB1_d_to_dll_46 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_46
--operation mode is normal

NB1_d_to_dll_46 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_46 # !FB3_data_out_0 & V1_reply_46);


--NB1_d_to_dll_45 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_45
--operation mode is normal

NB1_d_to_dll_45 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_45 # !FB3_data_out_0 & V1_reply_45);


--NB1_d_to_dll_44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_44
--operation mode is normal

NB1_d_to_dll_44 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_44 # !FB3_data_out_0 & V1_reply_44);


--NB1_d_to_dll_43 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_43
--operation mode is normal

NB1_d_to_dll_43 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_43 # !FB3_data_out_0 & V1_reply_43);


--NB1_d_to_dll_42 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_42
--operation mode is normal

NB1_d_to_dll_42 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_42 # !FB3_data_out_0 & V1_reply_42);


--NB1_d_to_dll_41 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_41
--operation mode is normal

NB1_d_to_dll_41 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_41 # !FB3_data_out_0 & V1_reply_41);


--NB1_d_to_dll_40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_40
--operation mode is normal

NB1_d_to_dll_40 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_40 # !FB3_data_out_0 & V1_reply_40);


--NB1_d_to_dll_39 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_39
--operation mode is normal

NB1_d_to_dll_39 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_39 # !FB3_data_out_0 & V1_reply_39);


--NB1_d_to_dll_38 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_38
--operation mode is normal

NB1_d_to_dll_38 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_38 # !FB3_data_out_0 & V1_reply_38);


--NB1_d_to_dll_37 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_37
--operation mode is normal

NB1_d_to_dll_37 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_37 # !FB3_data_out_0 & V1_reply_37);


--NB1_d_to_dll_36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_36
--operation mode is normal

NB1_d_to_dll_36 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_36 # !FB3_data_out_0 & V1_reply_36);


--NB1_d_to_dll_35 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_35
--operation mode is normal

NB1_d_to_dll_35 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_35 # !FB3_data_out_0 & V1_reply_35);


--NB1_d_to_dll_34 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_34
--operation mode is normal

NB1_d_to_dll_34 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_34 # !FB3_data_out_0 & V1_reply_34);


--NB1_d_to_dll_33 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_33
--operation mode is normal

NB1_d_to_dll_33 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_33 # !FB3_data_out_0 & V1_reply_33);


--NB1_d_to_dll_32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_32
--operation mode is normal

NB1_d_to_dll_32 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_32 # !FB3_data_out_0 & V1_reply_32);


--NB1_d_to_dll_31 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_31
--operation mode is normal

NB1_d_to_dll_31 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_31 # !FB3_data_out_0 & V1_reply_31);


--NB1_d_to_dll_30 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_30
--operation mode is normal

NB1_d_to_dll_30 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_30 # !FB3_data_out_0 & V1_reply_30);


--NB1_d_to_dll_29 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_29
--operation mode is normal

NB1_d_to_dll_29 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_29 # !FB3_data_out_0 & V1_reply_29);


--NB1_d_to_dll_28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_28
--operation mode is normal

NB1_d_to_dll_28 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_28 # !FB3_data_out_0 & V1_reply_28);


--NB1_d_to_dll_27 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_27
--operation mode is normal

NB1_d_to_dll_27 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_27 # !FB3_data_out_0 & V1_reply_27);


--NB1_d_to_dll_26 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_26
--operation mode is normal

NB1_d_to_dll_26 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_26 # !FB3_data_out_0 & V1_reply_26);


--NB1_d_to_dll_25 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_25
--operation mode is normal

NB1_d_to_dll_25 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_25 # !FB3_data_out_0 & V1_reply_25);


--NB1_d_to_dll_24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_24
--operation mode is normal

NB1_d_to_dll_24 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_24 # !FB3_data_out_0 & V1_reply_24);


--NB1_d_to_dll_23 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_23
--operation mode is normal

NB1_d_to_dll_23 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_23 # !FB3_data_out_0 & V1_reply_23);


--NB1_d_to_dll_22 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_22
--operation mode is normal

NB1_d_to_dll_22 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_22 # !FB3_data_out_0 & V1_reply_22);


--NB1_d_to_dll_21 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_21
--operation mode is normal

NB1_d_to_dll_21 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_21 # !FB3_data_out_0 & V1_reply_21);


--NB1_d_to_dll_20 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_20
--operation mode is normal

NB1_d_to_dll_20 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_20 # !FB3_data_out_0 & V1_reply_20);


--NB1_d_to_dll_19 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_19
--operation mode is normal

NB1_d_to_dll_19 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_19 # !FB3_data_out_0 & V1_reply_19);


--NB1_d_to_dll_18 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_18
--operation mode is normal

NB1_d_to_dll_18 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_18 # !FB3_data_out_0 & V1_reply_18);


--NB1_d_to_dll_17 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_17
--operation mode is normal

NB1_d_to_dll_17 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_17 # !FB3_data_out_0 & V1_reply_17);


--NB1_d_to_dll_16 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_16
--operation mode is normal

NB1_d_to_dll_16 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_16 # !FB3_data_out_0 & V1_reply_16);


--NB1_d_to_dll_15 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_15
--operation mode is normal

NB1_d_to_dll_15 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_15 # !FB3_data_out_0 & V1_reply_15);


--NB1_d_to_dll_14 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_14
--operation mode is normal

NB1_d_to_dll_14 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_14 # !FB3_data_out_0 & V1_reply_14);


--NB1_d_to_dll_13 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_13
--operation mode is normal

NB1_d_to_dll_13 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_13 # !FB3_data_out_0 & V1_reply_13);


--NB1_d_to_dll_12 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_12
--operation mode is normal

NB1_d_to_dll_12 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_12 # !FB3_data_out_0 & V1_reply_12);


--NB1_d_to_dll_11 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_11
--operation mode is normal

NB1_d_to_dll_11 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_11 # !FB3_data_out_0 & V1_reply_11);


--NB1_d_to_dll_10 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_10
--operation mode is normal

NB1_d_to_dll_10 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_10 # !FB3_data_out_0 & V1_reply_10);


--NB1_d_to_dll_9 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_9
--operation mode is normal

NB1_d_to_dll_9 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_9 # !FB3_data_out_0 & V1_reply_9);


--NB1_d_to_dll_8 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_8
--operation mode is normal

NB1_d_to_dll_8 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_8 # !FB3_data_out_0 & V1_reply_8);


--NB1_d_to_dll_7 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_7
--operation mode is normal

NB1_d_to_dll_7 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_7 # !FB3_data_out_0 & V1_reply_7);


--NB1_d_to_dll_6 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_6
--operation mode is normal

NB1_d_to_dll_6 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_6 # !FB3_data_out_0 & V1_reply_6);


--NB1_d_to_dll_5 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_5
--operation mode is normal

NB1_d_to_dll_5 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_5 # !FB3_data_out_0 & V1_reply_5);


--NB1_d_to_dll_4 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_4
--operation mode is normal

NB1_d_to_dll_4 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_4 # !FB3_data_out_0 & V1_reply_4);


--NB1_d_to_dll_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_3
--operation mode is normal

NB1_d_to_dll_3 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_3 # !FB3_data_out_0 & V1_reply_3);


--NB1_d_to_dll_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_2
--operation mode is normal

NB1_d_to_dll_2 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_2 # !FB3_data_out_0 & V1_reply_2);


--NB1_d_to_dll_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_1
--operation mode is normal

NB1_d_to_dll_1 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_1 # !FB3_data_out_0 & V1_reply_1);


--NB1_d_to_dll_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_to_dll_0
--operation mode is normal

NB1_d_to_dll_0 = !FB3_data_out_2 & (FB3_data_out_0 & BB1_data_out_0 # !FB3_data_out_0 & V1_reply_0);


--NB1_d_we is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_we
--operation mode is normal

NB1_d_we = !FB3_data_out_3 & FB3_data_out_1 & (FB3_data_out_0 # !FB3_data_out_2);


--NB1_d_initiate_send is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|d_initiate_send
--operation mode is normal

NB1_d_initiate_send = !FB3_data_out_1 & !FB3_data_out_0 & (FB3_data_out_3 $ FB3_data_out_2);


--NB1_request_valid is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|request_valid
--operation mode is normal

NB1_request_valid = !FB3_data_out_3 & !FB3_data_out_2 & FB3_data_out_1 & !FB3_data_out_0;


--NB1_b_dirty is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|b_dirty
--operation mode is normal

NB1_b_dirty_lut_out = !BB1_data_valid & !W1_buf0_err & !NB1_b_dirty;
NB1_b_dirty = DFFEA(NB1_b_dirty_lut_out, U1__clk0, VCC, , NB1_nx354, , );


--NB1_forward_buffer_60 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_60
--operation mode is normal

NB1_forward_buffer_60 = !BB1_data_out_60;


--NB1_result_inc_805_nx24 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_805_nx24
--operation mode is arithmetic

NB1_result_inc_805_nx24 = CARRY(BB1_data_out_60);


--NB1_forward_buffer_59 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_59
--operation mode is arithmetic

NB1_forward_buffer_59_carry_eqn = NB1_result_inc_805_nx24;
NB1_forward_buffer_59 = BB1_data_out_59 $ NB1_forward_buffer_59_carry_eqn;

--NB1_result_inc_805_nx28 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_805_nx28
--operation mode is arithmetic

NB1_result_inc_805_nx28 = CARRY(!NB1_result_inc_805_nx24 # !BB1_data_out_59);


--NB1_forward_buffer_58 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_58
--operation mode is arithmetic

NB1_forward_buffer_58_carry_eqn = NB1_result_inc_805_nx28;
NB1_forward_buffer_58 = BB1_data_out_58 $ !NB1_forward_buffer_58_carry_eqn;

--NB1_result_inc_805_nx32 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_805_nx32
--operation mode is arithmetic

NB1_result_inc_805_nx32 = CARRY(BB1_data_out_58 & !NB1_result_inc_805_nx28);


--NB1_forward_buffer_57 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_57
--operation mode is arithmetic

NB1_forward_buffer_57_carry_eqn = NB1_result_inc_805_nx32;
NB1_forward_buffer_57 = BB1_data_out_57 $ NB1_forward_buffer_57_carry_eqn;

--NB1_result_inc_805_nx36 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_805_nx36
--operation mode is arithmetic

NB1_result_inc_805_nx36 = CARRY(!NB1_result_inc_805_nx32 # !BB1_data_out_57);


--NB1_forward_buffer_56 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_56
--operation mode is arithmetic

NB1_forward_buffer_56_carry_eqn = NB1_result_inc_805_nx36;
NB1_forward_buffer_56 = BB1_data_out_56 $ !NB1_forward_buffer_56_carry_eqn;

--NB1_result_inc_805_nx40 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_805_nx40
--operation mode is arithmetic

NB1_result_inc_805_nx40 = CARRY(BB1_data_out_56 & !NB1_result_inc_805_nx36);


--NB1_forward_buffer_55 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_55
--operation mode is arithmetic

NB1_forward_buffer_55_carry_eqn = NB1_result_inc_805_nx40;
NB1_forward_buffer_55 = BB1_data_out_55 $ NB1_forward_buffer_55_carry_eqn;

--NB1_result_inc_805_nx44 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_805_nx44
--operation mode is arithmetic

NB1_result_inc_805_nx44 = CARRY(!NB1_result_inc_805_nx40 # !BB1_data_out_55);


--NB1_forward_buffer_54 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_54
--operation mode is arithmetic

NB1_forward_buffer_54_carry_eqn = NB1_result_inc_805_nx44;
NB1_forward_buffer_54 = BB1_data_out_54 $ !NB1_forward_buffer_54_carry_eqn;

--NB1_result_inc_805_nx48 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|result_inc_805_nx48
--operation mode is arithmetic

NB1_result_inc_805_nx48 = CARRY(BB1_data_out_54 & !NB1_result_inc_805_nx44);


--NB1_forward_buffer_53 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|forward_buffer_53
--operation mode is normal

NB1_forward_buffer_53_carry_eqn = NB1_result_inc_805_nx48;
NB1_forward_buffer_53 = BB1_data_out_53 $ NB1_forward_buffer_53_carry_eqn;


--FB3_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1|data_out_0
--operation mode is normal

FB3_data_out_0_lut_out = NB1_next_state_0;
FB3_data_out_0 = DFFEA(FB3_data_out_0_lut_out, U1__clk0, VCC, , , , );


--FB3_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1|data_out_1
--operation mode is normal

FB3_data_out_1_lut_out = NB1_next_state_1;
FB3_data_out_1 = DFFEA(FB3_data_out_1_lut_out, U1__clk0, VCC, , , , );


--FB3_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1|data_out_2
--operation mode is normal

FB3_data_out_2_lut_out = NB1_next_state_2;
FB3_data_out_2 = DFFEA(FB3_data_out_2_lut_out, U1__clk0, VCC, , , , );


--FB3_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|mcm_nw_nwsl:sl0|hamm_reg_4_0_1:h1|data_out_3
--operation mode is normal

FB3_data_out_3_lut_out = NB1_next_state_3;
FB3_data_out_3 = DFFEA(FB3_data_out_3_lut_out, U1__clk0, VCC, , , , );


--MB1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|hamm_reg_3_0_1_unfolded0:h1|data_out_0
--operation mode is normal

MB1_data_out_0_lut_out = X1_next_state_0;
MB1_data_out_0 = DFFEA(MB1_data_out_0_lut_out, U1__clk0, VCC, , , , );


--MB1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|hamm_reg_3_0_1_unfolded0:h1|data_out_1
--operation mode is normal

MB1_data_out_1_lut_out = X1_next_state_1;
MB1_data_out_1 = DFFEA(MB1_data_out_1_lut_out, U1__clk0, VCC, , , , );


--MB1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|hamm_reg_3_0_1_unfolded0:h1|data_out_2
--operation mode is normal

MB1_data_out_2_lut_out = X1_next_state_2;
MB1_data_out_2 = DFFEA(MB1_data_out_2_lut_out, U1__clk0, VCC, , , , );


--W1_d0_to_pl is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|d0_to_pl
--operation mode is normal

W1_d0_to_pl = X1_bridge & DB2_data_out_to_pl # !X1_bridge & DB1_data_out_to_pl;


--W1_d1_to_pl is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|d1_to_pl
--operation mode is normal

W1_d1_to_pl = X1_bridge & DB1_data_out_to_pl # !X1_bridge & DB2_data_out_to_pl;


--W1_buf0_err is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|buf0_err
--operation mode is normal

W1_buf0_err = BB1_buffer_full & !BB1_data_valid;


--W1_buf1_err is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|buf1_err
--operation mode is normal

W1_buf1_err = BB2_buffer_full & !BB2_data_valid;


--DB2_sleep_reset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|sleep_reset_n
--operation mode is normal

DB2_sleep_reset_n = HB2_data_out_2 & !HB2_data_out_1;


--DB2_request_data is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|request_data
--operation mode is normal

DB2_request_data = !HB2_data_out_2 & HB2_data_out_1 & HB2_data_out_0 & !KB2_stuff_bit_inserted;


--DB2_freeze_buffer is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|freeze_buffer
--operation mode is normal

DB2_freeze_buffer = HB2_data_out_1 # HB2_data_out_0;


--DB2_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|next_state_2
--operation mode is normal

DB2_next_state_2 = HB2_data_out_2 & !HB2_data_out_1 & !JB2_event # !HB2_data_out_2 & DB2_nx27;


--DB2_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|next_state_1
--operation mode is normal

DB2_next_state_1 = DB2_nx28 # !HB2_data_out_2 & HB2_data_out_0;


--DB2_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|next_state_0
--operation mode is normal

DB2_next_state_0 = DB2_nx29 # LB2_event_async & DB2_nx30;


--DB2_stuffing_strobe_in is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|stuffing_strobe_in
--operation mode is normal

DB2_stuffing_strobe_in = DB2_nx26 # !CB2_buffer_empty & LB2_event_async;


--DB2_stuffing_data_in is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|stuffing_data_in
--operation mode is normal

DB2_stuffing_data_in = CB2_data_out # !HB2_data_out_2 & !HB2_data_out_1 & HB2_data_out_0;


--DB2_stuffing_start_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|stuffing_start_n
--operation mode is normal

DB2_stuffing_start_n = HB2_data_out_1 # HB2_data_out_2 & HB2_data_out_0;


--DB2_timer_enable is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|timer_enable
--operation mode is normal

DB2_timer_enable = !HB2_data_out_2 & (HB2_data_out_1 # HB2_data_out_0);


--DB2_nx26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx26
--operation mode is normal

DB2_nx26 = !HB2_data_out_2 & !HB2_data_out_1 & HB2_data_out_0;


--DB2_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx27
--operation mode is normal

DB2_nx27 = CB2_buffer_empty & HB2_data_out_1 & !HB2_data_out_0 & LB2_event_async;


--DB2_nx28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx28
--operation mode is normal

DB2_nx28 = !HB2_data_out_2 & HB2_data_out_1 & (!LB2_event_async # !CB2_buffer_empty);


--DB2_nx29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx29
--operation mode is normal

DB2_nx29 = !HB2_data_out_1 & (HB2_data_out_0 & HB2_data_out_2 # !HB2_data_out_0 & NB2_d_initiate_send);


--DB2_nx30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|nx30
--operation mode is normal

DB2_nx30 = !CB2_buffer_empty & !HB2_data_out_2 & HB2_data_out_1 & !HB2_data_out_0;


--DB2_data_out_to_pl is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|data_out_to_pl
--operation mode is normal

DB2_data_out_to_pl_lut_out = KB2_stuffed_data_out & (HB2_data_out_1 # !HB2_data_out_2 & HB2_data_out_0);
DB2_data_out_to_pl = DFFEA(DB2_data_out_to_pl_lut_out, U1__clk0, VCC, , , , );


--LB2_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|nx18
--operation mode is normal

LB2_nx18 = LB2_state_0 # LB2_state_1 # !LB2_state_2;


--LB2_nx116 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|nx116
--operation mode is normal

LB2_nx116 = DB2_timer_enable # !DB2_freeze_buffer;


--LB2_event_async is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|event_async
--operation mode is normal

LB2_event_async = DB2_timer_enable & !LB2_state_2 & !LB2_state_0 & !LB2_state_1;


--LB2_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_0
--operation mode is normal

LB2_state_0_lut_out = DB2_timer_enable & DB2_freeze_buffer & LB2_b_0;
LB2_state_0 = DFFEA(LB2_state_0_lut_out, U1__clk0, VCC, , LB2_nx116, , );


--LB2_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_1
--operation mode is normal

LB2_state_1_lut_out = DB2_timer_enable & DB2_freeze_buffer & LB2_b_1_dup_60;
LB2_state_1 = DFFEA(LB2_state_1_lut_out, U1__clk0, VCC, , LB2_nx116, , );


--LB2_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_2
--operation mode is normal

LB2_state_2_lut_out = DB2_timer_enable & DB2_freeze_buffer & LB2_b_1;
LB2_state_2 = DFFEA(LB2_state_2_lut_out, U1__clk0, VCC, , LB2_nx116, , );


--LB2_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|b_0
--operation mode is normal

LB2_b_0 = !LB2_state_0 & LB2_nx18;


--LB2_state_inc_656_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_inc_656_nx14
--operation mode is arithmetic

LB2_state_inc_656_nx14 = CARRY(LB2_state_0);


--LB2_b_1_dup_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|b_1_dup_60
--operation mode is arithmetic

LB2_b_1_dup_60_carry_eqn = LB2_state_inc_656_nx14;
LB2_b_1_dup_60 = LB2_nx18 & (LB2_state_1 $ LB2_b_1_dup_60_carry_eqn);

--LB2_state_inc_656_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|state_inc_656_nx18
--operation mode is arithmetic

LB2_state_inc_656_nx18 = CARRY(!LB2_state_inc_656_nx14 # !LB2_state_1);


--LB2_b_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_4_0:timer_in|b_1
--operation mode is normal

LB2_b_1_carry_eqn = LB2_state_inc_656_nx18;
LB2_b_1 = LB2_nx18 & (LB2_state_2 $ !LB2_b_1_carry_eqn);


--KB2_nx120 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|nx120
--operation mode is normal

KB2_nx120 = DB2_stuffing_strobe_in # !DB2_stuffing_start_n;


--KB2_SCLEAR is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|SCLEAR
--operation mode is normal

KB2_SCLEAR = KB2_nx63 # DB2_stuffing_data_in $ KB2_data;


--KB2_nx63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|nx63
--operation mode is normal

KB2_nx63 = KB2_state_2 & KB2_state_1 & KB2_state_0 # !DB2_stuffing_start_n;


--KB2_data is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|data
--operation mode is normal

KB2_data_lut_out = DB2_stuffing_data_in & (!KB2_NOT_nx118 # !KB2_data) # !DB2_stuffing_data_in & !KB2_data & KB2_NOT_nx118;
KB2_data = DFFEA(KB2_data_lut_out, U1__clk0, VCC, , DB2_stuffing_strobe_in, , );


--KB2_stuffed_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|stuffed_data_out
--operation mode is normal

KB2_stuffed_data_out_lut_out = DB2_stuffing_strobe_in & (KB2_NOT_nx118 & !KB2_data # !KB2_NOT_nx118 & DB2_stuffing_data_in);
KB2_stuffed_data_out = DFFEA(KB2_stuffed_data_out_lut_out, U1__clk0, VCC, , KB2_nx120, , );


--KB2_NOT_nx118 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|NOT_nx118
--operation mode is normal

KB2_NOT_nx118 = DB2_stuffing_start_n & KB2_state_2 & KB2_state_1 & KB2_state_0;

--KB2_stuff_bit_inserted is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|stuff_bit_inserted
--operation mode is normal

KB2_stuff_bit_inserted = DFFEA(KB2_NOT_nx118, U1__clk0, VCC, , DB2_stuffing_strobe_in, , );


--KB2_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_0
--operation mode is arithmetic

KB2_state_0_lut_out = !KB2_state_0;
KB2_state_0_reg_input = !KB2_SCLEAR & KB2_state_0_lut_out;
KB2_state_0 = DFFEA(KB2_state_0_reg_input, U1__clk0, VCC, , DB2_stuffing_strobe_in, , );

--KB2_state_nx6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_nx6
--operation mode is arithmetic

KB2_state_nx6 = CARRY(KB2_state_0);


--KB2_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_2
--operation mode is normal

KB2_state_2_carry_eqn = KB2_state_nx12;
KB2_state_2_lut_out = KB2_state_2 $ !KB2_state_2_carry_eqn;
KB2_state_2_reg_input = !KB2_SCLEAR & KB2_state_2_lut_out;
KB2_state_2 = DFFEA(KB2_state_2_reg_input, U1__clk0, VCC, , DB2_stuffing_strobe_in, , );


--KB2_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_1
--operation mode is arithmetic

KB2_state_1_carry_eqn = KB2_state_nx6;
KB2_state_1_lut_out = KB2_state_1 $ KB2_state_1_carry_eqn;
KB2_state_1_reg_input = !KB2_SCLEAR & KB2_state_1_lut_out;
KB2_state_1 = DFFEA(KB2_state_1_reg_input, U1__clk0, VCC, , DB2_stuffing_strobe_in, , );

--KB2_state_nx12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_stuffing_7:stuff_in|state_nx12
--operation mode is arithmetic

KB2_state_nx12 = CARRY(!KB2_state_nx6 # !KB2_state_1);


--JB2_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx21
--operation mode is normal

JB2_nx21 = JB2_nx148 # !JB2_state_1 # !JB2_state_0;


--JB2_nx151 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx151
--operation mode is normal

JB2_nx151 = VCC;


--JB2_nx148 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx148
--operation mode is normal

JB2_nx148 = !JB2_state_5 # !JB2_state_4 # !JB2_state_3 # !JB2_state_2;


--JB2_nx149 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|nx149
--operation mode is normal

JB2_nx149 = DB2_sleep_reset_n;


--JB2_event is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|event
--operation mode is normal

JB2_event_lut_out = JB2_state_0 & JB2_state_1 & !JB2_nx148 & JB2_nx149;
JB2_event = DFFEA(JB2_event_lut_out, U1__clk0, VCC, , , , );


--JB2_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_0
--operation mode is normal

JB2_state_0_lut_out = JB2_b_0_dup_123 # !DB2_sleep_reset_n;
JB2_state_0 = DFFEA(JB2_state_0_lut_out, U1__clk0, VCC, , JB2_nx151, , );


--JB2_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_1
--operation mode is normal

JB2_state_1_lut_out = JB2_b_0_dup_119 # !DB2_sleep_reset_n;
JB2_state_1 = DFFEA(JB2_state_1_lut_out, U1__clk0, VCC, , JB2_nx151, , );


--JB2_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_2
--operation mode is normal

JB2_state_2_lut_out = JB2_b_0_dup_115 # !DB2_sleep_reset_n;
JB2_state_2 = DFFEA(JB2_state_2_lut_out, U1__clk0, VCC, , JB2_nx151, , );


--JB2_state_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_3
--operation mode is normal

JB2_state_3_lut_out = JB2_b_0_dup_111 # !DB2_sleep_reset_n;
JB2_state_3 = DFFEA(JB2_state_3_lut_out, U1__clk0, VCC, , JB2_nx151, , );


--JB2_state_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_4
--operation mode is normal

JB2_state_4_lut_out = JB2_b_0_dup_107 # !DB2_sleep_reset_n;
JB2_state_4 = DFFEA(JB2_state_4_lut_out, U1__clk0, VCC, , JB2_nx151, , );


--JB2_state_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_5
--operation mode is normal

JB2_state_5_lut_out = JB2_b_0 # !DB2_sleep_reset_n;
JB2_state_5 = DFFEA(JB2_state_5_lut_out, U1__clk0, VCC, , JB2_nx151, , );


--JB2_b_0_dup_123 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_123
--operation mode is normal

JB2_b_0_dup_123 = !JB2_state_0 & JB2_nx21;


--JB2_state_inc_670_nx20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx20
--operation mode is arithmetic

JB2_state_inc_670_nx20 = CARRY(JB2_state_0);


--JB2_b_0_dup_119 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_119
--operation mode is arithmetic

JB2_b_0_dup_119_carry_eqn = JB2_state_inc_670_nx20;
JB2_b_0_dup_119 = JB2_nx21 & (JB2_state_1 $ JB2_b_0_dup_119_carry_eqn);

--JB2_state_inc_670_nx24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx24
--operation mode is arithmetic

JB2_state_inc_670_nx24 = CARRY(!JB2_state_inc_670_nx20 # !JB2_state_1);


--JB2_b_0_dup_115 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_115
--operation mode is arithmetic

JB2_b_0_dup_115_carry_eqn = JB2_state_inc_670_nx24;
JB2_b_0_dup_115 = JB2_nx21 & (JB2_state_2 $ !JB2_b_0_dup_115_carry_eqn);

--JB2_state_inc_670_nx28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx28
--operation mode is arithmetic

JB2_state_inc_670_nx28 = CARRY(JB2_state_2 & !JB2_state_inc_670_nx24);


--JB2_b_0_dup_111 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_111
--operation mode is arithmetic

JB2_b_0_dup_111_carry_eqn = JB2_state_inc_670_nx28;
JB2_b_0_dup_111 = JB2_nx21 & (JB2_state_3 $ JB2_b_0_dup_111_carry_eqn);

--JB2_state_inc_670_nx32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx32
--operation mode is arithmetic

JB2_state_inc_670_nx32 = CARRY(!JB2_state_inc_670_nx28 # !JB2_state_3);


--JB2_b_0_dup_107 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0_dup_107
--operation mode is arithmetic

JB2_b_0_dup_107_carry_eqn = JB2_state_inc_670_nx32;
JB2_b_0_dup_107 = JB2_nx21 & (JB2_state_4 $ !JB2_b_0_dup_107_carry_eqn);

--JB2_state_inc_670_nx36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx36
--operation mode is arithmetic

JB2_state_inc_670_nx36 = CARRY(JB2_state_4 & !JB2_state_inc_670_nx32);


--JB2_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|mcm_nw_timer_63_63:sleeptimer|b_0
--operation mode is normal

JB2_b_0_carry_eqn = JB2_state_inc_670_nx36;
JB2_b_0 = JB2_nx21 & (JB2_state_5 $ JB2_b_0_carry_eqn);


--HB2_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|hamm_reg_3_0_1:h1|data_out_0
--operation mode is normal

HB2_data_out_0_lut_out = DB2_next_state_0;
HB2_data_out_0 = DFFEA(HB2_data_out_0_lut_out, U1__clk0, VCC, , , , );


--HB2_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|hamm_reg_3_0_1:h1|data_out_1
--operation mode is normal

HB2_data_out_1_lut_out = DB2_next_state_1;
HB2_data_out_1 = DFFEA(HB2_data_out_1_lut_out, U1__clk0, VCC, , , , );


--HB2_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st1|hamm_reg_3_0_1:h1|data_out_2
--operation mode is normal

HB2_data_out_2_lut_out = DB2_next_state_2;
HB2_data_out_2 = DFFEA(HB2_data_out_2_lut_out, U1__clk0, VCC, , , , );


--DB1_sleep_reset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|sleep_reset_n
--operation mode is normal

DB1_sleep_reset_n = HB1_data_out_2 & !HB1_data_out_1;


--DB1_request_data is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|request_data
--operation mode is normal

DB1_request_data = !HB1_data_out_2 & HB1_data_out_1 & HB1_data_out_0 & !KB1_stuff_bit_inserted;


--DB1_freeze_buffer is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|freeze_buffer
--operation mode is normal

DB1_freeze_buffer = HB1_data_out_1 # HB1_data_out_0;


--DB1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|next_state_2
--operation mode is normal

DB1_next_state_2 = HB1_data_out_2 & !HB1_data_out_1 & !JB1_event # !HB1_data_out_2 & DB1_nx27;


--DB1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|next_state_1
--operation mode is normal

DB1_next_state_1 = DB1_nx28 # !HB1_data_out_2 & HB1_data_out_0;


--DB1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|next_state_0
--operation mode is normal

DB1_next_state_0 = DB1_nx29 # LB1_event_async & DB1_nx30;


--DB1_stuffing_strobe_in is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|stuffing_strobe_in
--operation mode is normal

DB1_stuffing_strobe_in = DB1_nx26 # !CB1_buffer_empty & LB1_event_async;


--DB1_stuffing_data_in is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|stuffing_data_in
--operation mode is normal

DB1_stuffing_data_in = CB1_data_out # !HB1_data_out_2 & !HB1_data_out_1 & HB1_data_out_0;


--DB1_stuffing_start_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|stuffing_start_n
--operation mode is normal

DB1_stuffing_start_n = HB1_data_out_1 # HB1_data_out_2 & HB1_data_out_0;


--DB1_timer_enable is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|timer_enable
--operation mode is normal

DB1_timer_enable = !HB1_data_out_2 & (HB1_data_out_1 # HB1_data_out_0);


--DB1_nx26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx26
--operation mode is normal

DB1_nx26 = !HB1_data_out_2 & !HB1_data_out_1 & HB1_data_out_0;


--DB1_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx27
--operation mode is normal

DB1_nx27 = CB1_buffer_empty & HB1_data_out_1 & !HB1_data_out_0 & LB1_event_async;


--DB1_nx28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx28
--operation mode is normal

DB1_nx28 = !HB1_data_out_2 & HB1_data_out_1 & (!LB1_event_async # !CB1_buffer_empty);


--DB1_nx29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx29
--operation mode is normal

DB1_nx29 = !HB1_data_out_1 & (HB1_data_out_0 & HB1_data_out_2 # !HB1_data_out_0 & NB1_d_initiate_send);


--DB1_nx30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|nx30
--operation mode is normal

DB1_nx30 = !CB1_buffer_empty & !HB1_data_out_2 & HB1_data_out_1 & !HB1_data_out_0;


--DB1_data_out_to_pl is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|data_out_to_pl
--operation mode is normal

DB1_data_out_to_pl_lut_out = KB1_stuffed_data_out & (HB1_data_out_1 # !HB1_data_out_2 & HB1_data_out_0);
DB1_data_out_to_pl = DFFEA(DB1_data_out_to_pl_lut_out, U1__clk0, VCC, , , , );


--LB1_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|nx18
--operation mode is normal

LB1_nx18 = LB1_state_0 # LB1_state_1 # !LB1_state_2;


--LB1_nx116 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|nx116
--operation mode is normal

LB1_nx116 = DB1_timer_enable # !DB1_freeze_buffer;


--LB1_event_async is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|event_async
--operation mode is normal

LB1_event_async = DB1_timer_enable & !LB1_state_2 & !LB1_state_0 & !LB1_state_1;


--LB1_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_0
--operation mode is normal

LB1_state_0_lut_out = DB1_timer_enable & DB1_freeze_buffer & LB1_b_0;
LB1_state_0 = DFFEA(LB1_state_0_lut_out, U1__clk0, VCC, , LB1_nx116, , );


--LB1_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_1
--operation mode is normal

LB1_state_1_lut_out = DB1_timer_enable & DB1_freeze_buffer & LB1_b_1_dup_60;
LB1_state_1 = DFFEA(LB1_state_1_lut_out, U1__clk0, VCC, , LB1_nx116, , );


--LB1_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_2
--operation mode is normal

LB1_state_2_lut_out = DB1_timer_enable & DB1_freeze_buffer & LB1_b_1;
LB1_state_2 = DFFEA(LB1_state_2_lut_out, U1__clk0, VCC, , LB1_nx116, , );


--LB1_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|b_0
--operation mode is normal

LB1_b_0 = !LB1_state_0 & LB1_nx18;


--LB1_state_inc_656_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_inc_656_nx14
--operation mode is arithmetic

LB1_state_inc_656_nx14 = CARRY(LB1_state_0);


--LB1_b_1_dup_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|b_1_dup_60
--operation mode is arithmetic

LB1_b_1_dup_60_carry_eqn = LB1_state_inc_656_nx14;
LB1_b_1_dup_60 = LB1_nx18 & (LB1_state_1 $ LB1_b_1_dup_60_carry_eqn);

--LB1_state_inc_656_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|state_inc_656_nx18
--operation mode is arithmetic

LB1_state_inc_656_nx18 = CARRY(!LB1_state_inc_656_nx14 # !LB1_state_1);


--LB1_b_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_4_0:timer_in|b_1
--operation mode is normal

LB1_b_1_carry_eqn = LB1_state_inc_656_nx18;
LB1_b_1 = LB1_nx18 & (LB1_state_2 $ !LB1_b_1_carry_eqn);


--KB1_nx120 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|nx120
--operation mode is normal

KB1_nx120 = DB1_stuffing_strobe_in # !DB1_stuffing_start_n;


--KB1_SCLEAR is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|SCLEAR
--operation mode is normal

KB1_SCLEAR = KB1_nx63 # DB1_stuffing_data_in $ KB1_data;


--KB1_nx63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|nx63
--operation mode is normal

KB1_nx63 = KB1_state_2 & KB1_state_1 & KB1_state_0 # !DB1_stuffing_start_n;


--KB1_data is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|data
--operation mode is normal

KB1_data_lut_out = DB1_stuffing_data_in & (!KB1_NOT_nx118 # !KB1_data) # !DB1_stuffing_data_in & !KB1_data & KB1_NOT_nx118;
KB1_data = DFFEA(KB1_data_lut_out, U1__clk0, VCC, , DB1_stuffing_strobe_in, , );


--KB1_stuffed_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|stuffed_data_out
--operation mode is normal

KB1_stuffed_data_out_lut_out = DB1_stuffing_strobe_in & (KB1_NOT_nx118 & !KB1_data # !KB1_NOT_nx118 & DB1_stuffing_data_in);
KB1_stuffed_data_out = DFFEA(KB1_stuffed_data_out_lut_out, U1__clk0, VCC, , KB1_nx120, , );


--KB1_NOT_nx118 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|NOT_nx118
--operation mode is normal

KB1_NOT_nx118 = DB1_stuffing_start_n & KB1_state_2 & KB1_state_1 & KB1_state_0;

--KB1_stuff_bit_inserted is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|stuff_bit_inserted
--operation mode is normal

KB1_stuff_bit_inserted = DFFEA(KB1_NOT_nx118, U1__clk0, VCC, , DB1_stuffing_strobe_in, , );


--KB1_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_0
--operation mode is arithmetic

KB1_state_0_lut_out = !KB1_state_0;
KB1_state_0_reg_input = !KB1_SCLEAR & KB1_state_0_lut_out;
KB1_state_0 = DFFEA(KB1_state_0_reg_input, U1__clk0, VCC, , DB1_stuffing_strobe_in, , );

--KB1_state_nx6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_nx6
--operation mode is arithmetic

KB1_state_nx6 = CARRY(KB1_state_0);


--KB1_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_2
--operation mode is normal

KB1_state_2_carry_eqn = KB1_state_nx12;
KB1_state_2_lut_out = KB1_state_2 $ !KB1_state_2_carry_eqn;
KB1_state_2_reg_input = !KB1_SCLEAR & KB1_state_2_lut_out;
KB1_state_2 = DFFEA(KB1_state_2_reg_input, U1__clk0, VCC, , DB1_stuffing_strobe_in, , );


--KB1_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_1
--operation mode is arithmetic

KB1_state_1_carry_eqn = KB1_state_nx6;
KB1_state_1_lut_out = KB1_state_1 $ KB1_state_1_carry_eqn;
KB1_state_1_reg_input = !KB1_SCLEAR & KB1_state_1_lut_out;
KB1_state_1 = DFFEA(KB1_state_1_reg_input, U1__clk0, VCC, , DB1_stuffing_strobe_in, , );

--KB1_state_nx12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_stuffing_7:stuff_in|state_nx12
--operation mode is arithmetic

KB1_state_nx12 = CARRY(!KB1_state_nx6 # !KB1_state_1);


--JB1_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx21
--operation mode is normal

JB1_nx21 = JB1_nx148 # !JB1_state_1 # !JB1_state_0;


--JB1_nx151 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx151
--operation mode is normal

JB1_nx151 = VCC;


--JB1_nx148 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx148
--operation mode is normal

JB1_nx148 = !JB1_state_5 # !JB1_state_4 # !JB1_state_3 # !JB1_state_2;


--JB1_nx149 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|nx149
--operation mode is normal

JB1_nx149 = DB1_sleep_reset_n;


--JB1_event is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|event
--operation mode is normal

JB1_event_lut_out = JB1_state_0 & JB1_state_1 & !JB1_nx148 & JB1_nx149;
JB1_event = DFFEA(JB1_event_lut_out, U1__clk0, VCC, , , , );


--JB1_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_0
--operation mode is normal

JB1_state_0_lut_out = JB1_b_0_dup_123 # !DB1_sleep_reset_n;
JB1_state_0 = DFFEA(JB1_state_0_lut_out, U1__clk0, VCC, , JB1_nx151, , );


--JB1_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_1
--operation mode is normal

JB1_state_1_lut_out = JB1_b_0_dup_119 # !DB1_sleep_reset_n;
JB1_state_1 = DFFEA(JB1_state_1_lut_out, U1__clk0, VCC, , JB1_nx151, , );


--JB1_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_2
--operation mode is normal

JB1_state_2_lut_out = JB1_b_0_dup_115 # !DB1_sleep_reset_n;
JB1_state_2 = DFFEA(JB1_state_2_lut_out, U1__clk0, VCC, , JB1_nx151, , );


--JB1_state_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_3
--operation mode is normal

JB1_state_3_lut_out = JB1_b_0_dup_111 # !DB1_sleep_reset_n;
JB1_state_3 = DFFEA(JB1_state_3_lut_out, U1__clk0, VCC, , JB1_nx151, , );


--JB1_state_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_4
--operation mode is normal

JB1_state_4_lut_out = JB1_b_0_dup_107 # !DB1_sleep_reset_n;
JB1_state_4 = DFFEA(JB1_state_4_lut_out, U1__clk0, VCC, , JB1_nx151, , );


--JB1_state_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_5
--operation mode is normal

JB1_state_5_lut_out = JB1_b_0 # !DB1_sleep_reset_n;
JB1_state_5 = DFFEA(JB1_state_5_lut_out, U1__clk0, VCC, , JB1_nx151, , );


--JB1_b_0_dup_123 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_123
--operation mode is normal

JB1_b_0_dup_123 = !JB1_state_0 & JB1_nx21;


--JB1_state_inc_670_nx20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx20
--operation mode is arithmetic

JB1_state_inc_670_nx20 = CARRY(JB1_state_0);


--JB1_b_0_dup_119 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_119
--operation mode is arithmetic

JB1_b_0_dup_119_carry_eqn = JB1_state_inc_670_nx20;
JB1_b_0_dup_119 = JB1_nx21 & (JB1_state_1 $ JB1_b_0_dup_119_carry_eqn);

--JB1_state_inc_670_nx24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx24
--operation mode is arithmetic

JB1_state_inc_670_nx24 = CARRY(!JB1_state_inc_670_nx20 # !JB1_state_1);


--JB1_b_0_dup_115 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_115
--operation mode is arithmetic

JB1_b_0_dup_115_carry_eqn = JB1_state_inc_670_nx24;
JB1_b_0_dup_115 = JB1_nx21 & (JB1_state_2 $ !JB1_b_0_dup_115_carry_eqn);

--JB1_state_inc_670_nx28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx28
--operation mode is arithmetic

JB1_state_inc_670_nx28 = CARRY(JB1_state_2 & !JB1_state_inc_670_nx24);


--JB1_b_0_dup_111 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_111
--operation mode is arithmetic

JB1_b_0_dup_111_carry_eqn = JB1_state_inc_670_nx28;
JB1_b_0_dup_111 = JB1_nx21 & (JB1_state_3 $ JB1_b_0_dup_111_carry_eqn);

--JB1_state_inc_670_nx32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx32
--operation mode is arithmetic

JB1_state_inc_670_nx32 = CARRY(!JB1_state_inc_670_nx28 # !JB1_state_3);


--JB1_b_0_dup_107 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0_dup_107
--operation mode is arithmetic

JB1_b_0_dup_107_carry_eqn = JB1_state_inc_670_nx32;
JB1_b_0_dup_107 = JB1_nx21 & (JB1_state_4 $ !JB1_b_0_dup_107_carry_eqn);

--JB1_state_inc_670_nx36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|state_inc_670_nx36
--operation mode is arithmetic

JB1_state_inc_670_nx36 = CARRY(JB1_state_4 & !JB1_state_inc_670_nx32);


--JB1_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|mcm_nw_timer_63_63:sleeptimer|b_0
--operation mode is normal

JB1_b_0_carry_eqn = JB1_state_inc_670_nx36;
JB1_b_0 = JB1_nx21 & (JB1_state_5 $ JB1_b_0_carry_eqn);


--HB1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|hamm_reg_3_0_1:h1|data_out_0
--operation mode is normal

HB1_data_out_0_lut_out = DB1_next_state_0;
HB1_data_out_0 = DFFEA(HB1_data_out_0_lut_out, U1__clk0, VCC, , , , );


--HB1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|hamm_reg_3_0_1:h1|data_out_1
--operation mode is normal

HB1_data_out_1_lut_out = DB1_next_state_1;
HB1_data_out_1 = DFFEA(HB1_data_out_1_lut_out, U1__clk0, VCC, , , , );


--HB1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_sendtiming_4_7_63:st0|hamm_reg_3_0_1:h1|data_out_2
--operation mode is normal

HB1_data_out_2_lut_out = DB1_next_state_2;
HB1_data_out_2 = DFFEA(HB1_data_out_2_lut_out, U1__clk0, VCC, , , , );


--CB2_bitcounter_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_5
--operation mode is arithmetic

CB2_bitcounter_5_carry_eqn = CB2_bitcounter_nx33;
CB2_bitcounter_5_lut_out = CB2_bitcounter_5 $ CB2_bitcounter_5_carry_eqn;
CB2_bitcounter_5_reg_input = DB2_freeze_buffer & CB2_bitcounter_5_lut_out;
CB2_bitcounter_5 = DFFEA(CB2_bitcounter_5_reg_input, U1__clk0, VCC, , , , );

--CB2_bitcounter_nx37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx37
--operation mode is arithmetic

CB2_bitcounter_nx37 = CARRY(!CB2_bitcounter_nx33 # !CB2_bitcounter_5);


--CB2_bitcounter_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_4
--operation mode is arithmetic

CB2_bitcounter_4_carry_eqn = CB2_bitcounter_nx27;
CB2_bitcounter_4_lut_out = CB2_bitcounter_4 $ !CB2_bitcounter_4_carry_eqn;
CB2_bitcounter_4_reg_input = DB2_freeze_buffer & CB2_bitcounter_4_lut_out;
CB2_bitcounter_4 = DFFEA(CB2_bitcounter_4_reg_input, U1__clk0, VCC, , , , );

--CB2_bitcounter_nx33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx33
--operation mode is arithmetic

CB2_bitcounter_nx33 = CARRY(CB2_bitcounter_4 & !CB2_bitcounter_nx27);


--CB2_bitcounter_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_3
--operation mode is arithmetic

CB2_bitcounter_3_carry_eqn = CB2_bitcounter_nx21;
CB2_bitcounter_3_lut_out = CB2_bitcounter_3 $ CB2_bitcounter_3_carry_eqn;
CB2_bitcounter_3_reg_input = DB2_freeze_buffer & CB2_bitcounter_3_lut_out;
CB2_bitcounter_3 = DFFEA(CB2_bitcounter_3_reg_input, U1__clk0, VCC, , , , );

--CB2_bitcounter_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx27
--operation mode is arithmetic

CB2_bitcounter_nx27 = CARRY(!CB2_bitcounter_nx21 # !CB2_bitcounter_3);


--CB2_bitcounter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_2
--operation mode is arithmetic

CB2_bitcounter_2_carry_eqn = CB2_bitcounter_nx15;
CB2_bitcounter_2_lut_out = CB2_bitcounter_2 $ !CB2_bitcounter_2_carry_eqn;
CB2_bitcounter_2_reg_input = DB2_freeze_buffer & CB2_bitcounter_2_lut_out;
CB2_bitcounter_2 = DFFEA(CB2_bitcounter_2_reg_input, U1__clk0, VCC, , , , );

--CB2_bitcounter_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx21
--operation mode is arithmetic

CB2_bitcounter_nx21 = CARRY(CB2_bitcounter_2 & !CB2_bitcounter_nx15);


--CB2_bitcounter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_1
--operation mode is arithmetic

CB2_bitcounter_1_carry_eqn = CB2_bitcounter_nx9;
CB2_bitcounter_1_lut_out = CB2_bitcounter_1 $ CB2_bitcounter_1_carry_eqn;
CB2_bitcounter_1_reg_input = DB2_freeze_buffer & CB2_bitcounter_1_lut_out;
CB2_bitcounter_1 = DFFEA(CB2_bitcounter_1_reg_input, U1__clk0, VCC, , , , );

--CB2_bitcounter_nx15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx15
--operation mode is arithmetic

CB2_bitcounter_nx15 = CARRY(!CB2_bitcounter_nx9 # !CB2_bitcounter_1);


--CB2_bitcounter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_0
--operation mode is arithmetic

CB2_bitcounter_0_lut_out = CB2_bitcounter_0 $ CB2_nx1398;
CB2_bitcounter_0_reg_input = DB2_freeze_buffer & CB2_bitcounter_0_lut_out;
CB2_bitcounter_0 = DFFEA(CB2_bitcounter_0_reg_input, U1__clk0, VCC, , , , );

--CB2_bitcounter_nx9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_nx9
--operation mode is arithmetic

CB2_bitcounter_nx9 = CARRY(CB2_bitcounter_0 & CB2_nx1398);


--CB2_bitcounter_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|bitcounter_6
--operation mode is normal

CB2_bitcounter_6_carry_eqn = CB2_bitcounter_nx37;
CB2_bitcounter_6_lut_out = CB2_bitcounter_6 $ !CB2_bitcounter_6_carry_eqn;
CB2_bitcounter_6_reg_input = DB2_freeze_buffer & CB2_bitcounter_6_lut_out;
CB2_bitcounter_6 = DFFEA(CB2_bitcounter_6_reg_input, U1__clk0, VCC, , , , );


--CB2_NOT_nx714 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|NOT_nx714
--operation mode is normal

CB2_NOT_nx714 = DB2_freeze_buffer & DB2_request_data & CB2_nx119 # !DB2_freeze_buffer & NB2_d_we;


--CB2_nx1398 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|nx1398
--operation mode is normal

CB2_nx1398 = DB2_request_data & !CB2_buffer_empty;


--CB2_NOT_ob_empty is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|NOT_ob_empty
--operation mode is normal

CB2_NOT_ob_empty = !CB2_bitcounter_5 & CB2_modgen_gt_489_nx60 & !CB2_bitcounter_4 # !CB2_bitcounter_6;


--CB2_a_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|a_2
--operation mode is normal

CB2_a_2 = !DB2_freeze_buffer & NB2_d_we;


--CB2_modgen_gt_489_nx60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|modgen_gt_489_nx60
--operation mode is normal

CB2_modgen_gt_489_nx60 = !CB2_bitcounter_3 & (!CB2_bitcounter_1 & !CB2_bitcounter_0 # !CB2_bitcounter_2);


--CB2_nx119 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|nx119
--operation mode is normal

CB2_nx119 = CB2_nx120 # !CB2_bitcounter_5 & !CB2_bitcounter_3 & CB2_nx121;


--CB2_nx120 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|nx120
--operation mode is normal

CB2_nx120 = !CB2_bitcounter_5 & !CB2_bitcounter_4 # !CB2_bitcounter_6;


--CB2_nx121 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|nx121
--operation mode is normal

CB2_nx121 = !CB2_bitcounter_1 & !CB2_bitcounter_0 # !CB2_bitcounter_2;


--CB2_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|data_out
--operation mode is normal

CB2_data_out = CB2_ob_data_68 & (CB2_ob_crc_15 # CB2_NOT_ob_empty) # !CB2_ob_data_68 & CB2_ob_crc_15 & !CB2_NOT_ob_empty;


--CB2_buffer_empty is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|buffer_empty
--operation mode is normal

CB2_buffer_empty = CB2_bitcounter_6 & (CB2_bitcounter_5 # !CB2_modgen_gt_489_nx60 & CB2_bitcounter_4);


--CB2_ob_crc_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_0
--operation mode is normal

CB2_ob_crc_0_lut_out = CB2_ob_data_52 $ (CB2_ob_crc_15 & CB2_NOT_ob_empty);
CB2_ob_crc_0_sload_eqn = (CB2_a_2 & NB2_d_to_dll_53) # (!CB2_a_2 & CB2_ob_crc_0_lut_out);
CB2_ob_crc_0 = DFFEA(CB2_ob_crc_0_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_1
--operation mode is normal

CB2_ob_crc_1_lut_out = CB2_ob_crc_0;
CB2_ob_crc_1_sload_eqn = (CB2_a_2 & NB2_d_to_dll_54) # (!CB2_a_2 & CB2_ob_crc_1_lut_out);
CB2_ob_crc_1 = DFFEA(CB2_ob_crc_1_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_10
--operation mode is normal

CB2_ob_crc_10_lut_out = CB2_ob_crc_9;
CB2_ob_crc_10_sload_eqn = (CB2_a_2 & NB2_d_to_dll_63) # (!CB2_a_2 & CB2_ob_crc_10_lut_out);
CB2_ob_crc_10 = DFFEA(CB2_ob_crc_10_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_11
--operation mode is normal

CB2_ob_crc_11_lut_out = CB2_ob_crc_10;
CB2_ob_crc_11_sload_eqn = (CB2_a_2 & NB2_d_to_dll_64) # (!CB2_a_2 & CB2_ob_crc_11_lut_out);
CB2_ob_crc_11 = DFFEA(CB2_ob_crc_11_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_12
--operation mode is normal

CB2_ob_crc_12_lut_out = CB2_ob_crc_11;
CB2_ob_crc_12_sload_eqn = (CB2_a_2 & NB2_d_to_dll_65) # (!CB2_a_2 & CB2_ob_crc_12_lut_out);
CB2_ob_crc_12 = DFFEA(CB2_ob_crc_12_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_13
--operation mode is normal

CB2_ob_crc_13_lut_out = CB2_ob_crc_12;
CB2_ob_crc_13_sload_eqn = (CB2_a_2 & NB2_d_to_dll_66) # (!CB2_a_2 & CB2_ob_crc_13_lut_out);
CB2_ob_crc_13 = DFFEA(CB2_ob_crc_13_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_14
--operation mode is normal

CB2_ob_crc_14_lut_out = CB2_ob_crc_13;
CB2_ob_crc_14_sload_eqn = (CB2_a_2 & NB2_d_to_dll_67) # (!CB2_a_2 & CB2_ob_crc_14_lut_out);
CB2_ob_crc_14 = DFFEA(CB2_ob_crc_14_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_15
--operation mode is normal

CB2_ob_crc_15_lut_out = CB2_ob_crc_14 $ (CB2_ob_crc_15 & CB2_NOT_ob_empty);
CB2_ob_crc_15_sload_eqn = (CB2_a_2 & NB2_d_to_dll_68) # (!CB2_a_2 & CB2_ob_crc_15_lut_out);
CB2_ob_crc_15 = DFFEA(CB2_ob_crc_15_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_2
--operation mode is normal

CB2_ob_crc_2_lut_out = CB2_ob_crc_1 $ (CB2_ob_crc_15 & CB2_NOT_ob_empty);
CB2_ob_crc_2_sload_eqn = (CB2_a_2 & NB2_d_to_dll_55) # (!CB2_a_2 & CB2_ob_crc_2_lut_out);
CB2_ob_crc_2 = DFFEA(CB2_ob_crc_2_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_3
--operation mode is normal

CB2_ob_crc_3_lut_out = CB2_ob_crc_2;
CB2_ob_crc_3_sload_eqn = (CB2_a_2 & NB2_d_to_dll_56) # (!CB2_a_2 & CB2_ob_crc_3_lut_out);
CB2_ob_crc_3 = DFFEA(CB2_ob_crc_3_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_4
--operation mode is normal

CB2_ob_crc_4_lut_out = CB2_ob_crc_3;
CB2_ob_crc_4_sload_eqn = (CB2_a_2 & NB2_d_to_dll_57) # (!CB2_a_2 & CB2_ob_crc_4_lut_out);
CB2_ob_crc_4 = DFFEA(CB2_ob_crc_4_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_5
--operation mode is normal

CB2_ob_crc_5_lut_out = CB2_ob_crc_4;
CB2_ob_crc_5_sload_eqn = (CB2_a_2 & NB2_d_to_dll_58) # (!CB2_a_2 & CB2_ob_crc_5_lut_out);
CB2_ob_crc_5 = DFFEA(CB2_ob_crc_5_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_6
--operation mode is normal

CB2_ob_crc_6_lut_out = CB2_ob_crc_5;
CB2_ob_crc_6_sload_eqn = (CB2_a_2 & NB2_d_to_dll_59) # (!CB2_a_2 & CB2_ob_crc_6_lut_out);
CB2_ob_crc_6 = DFFEA(CB2_ob_crc_6_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_7
--operation mode is normal

CB2_ob_crc_7_lut_out = CB2_ob_crc_6;
CB2_ob_crc_7_sload_eqn = (CB2_a_2 & NB2_d_to_dll_60) # (!CB2_a_2 & CB2_ob_crc_7_lut_out);
CB2_ob_crc_7 = DFFEA(CB2_ob_crc_7_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_8
--operation mode is normal

CB2_ob_crc_8_lut_out = CB2_ob_crc_7;
CB2_ob_crc_8_sload_eqn = (CB2_a_2 & NB2_d_to_dll_61) # (!CB2_a_2 & CB2_ob_crc_8_lut_out);
CB2_ob_crc_8 = DFFEA(CB2_ob_crc_8_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_crc_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_crc_9
--operation mode is normal

CB2_ob_crc_9_lut_out = CB2_ob_crc_8;
CB2_ob_crc_9_sload_eqn = (CB2_a_2 & NB2_d_to_dll_62) # (!CB2_a_2 & CB2_ob_crc_9_lut_out);
CB2_ob_crc_9 = DFFEA(CB2_ob_crc_9_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_0
--operation mode is normal

CB2_ob_data_0_lut_out = !DB2_freeze_buffer & NB2_d_to_dll_0 & NB2_d_we;
CB2_ob_data_0 = DFFEA(CB2_ob_data_0_lut_out, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_1
--operation mode is normal

CB2_ob_data_1_lut_out = CB2_ob_data_0;
CB2_ob_data_1_sload_eqn = (CB2_a_2 & NB2_d_to_dll_1) # (!CB2_a_2 & CB2_ob_data_1_lut_out);
CB2_ob_data_1 = DFFEA(CB2_ob_data_1_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_10
--operation mode is normal

CB2_ob_data_10_lut_out = CB2_ob_data_9;
CB2_ob_data_10_sload_eqn = (CB2_a_2 & NB2_d_to_dll_10) # (!CB2_a_2 & CB2_ob_data_10_lut_out);
CB2_ob_data_10 = DFFEA(CB2_ob_data_10_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_11
--operation mode is normal

CB2_ob_data_11_lut_out = CB2_ob_data_10;
CB2_ob_data_11_sload_eqn = (CB2_a_2 & NB2_d_to_dll_11) # (!CB2_a_2 & CB2_ob_data_11_lut_out);
CB2_ob_data_11 = DFFEA(CB2_ob_data_11_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_12
--operation mode is normal

CB2_ob_data_12_lut_out = CB2_ob_data_11;
CB2_ob_data_12_sload_eqn = (CB2_a_2 & NB2_d_to_dll_12) # (!CB2_a_2 & CB2_ob_data_12_lut_out);
CB2_ob_data_12 = DFFEA(CB2_ob_data_12_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_13
--operation mode is normal

CB2_ob_data_13_lut_out = CB2_ob_data_12;
CB2_ob_data_13_sload_eqn = (CB2_a_2 & NB2_d_to_dll_13) # (!CB2_a_2 & CB2_ob_data_13_lut_out);
CB2_ob_data_13 = DFFEA(CB2_ob_data_13_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_14
--operation mode is normal

CB2_ob_data_14_lut_out = CB2_ob_data_13;
CB2_ob_data_14_sload_eqn = (CB2_a_2 & NB2_d_to_dll_14) # (!CB2_a_2 & CB2_ob_data_14_lut_out);
CB2_ob_data_14 = DFFEA(CB2_ob_data_14_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_15
--operation mode is normal

CB2_ob_data_15_lut_out = CB2_ob_data_14;
CB2_ob_data_15_sload_eqn = (CB2_a_2 & NB2_d_to_dll_15) # (!CB2_a_2 & CB2_ob_data_15_lut_out);
CB2_ob_data_15 = DFFEA(CB2_ob_data_15_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_16 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_16
--operation mode is normal

CB2_ob_data_16_lut_out = CB2_ob_data_15;
CB2_ob_data_16_sload_eqn = (CB2_a_2 & NB2_d_to_dll_16) # (!CB2_a_2 & CB2_ob_data_16_lut_out);
CB2_ob_data_16 = DFFEA(CB2_ob_data_16_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_17 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_17
--operation mode is normal

CB2_ob_data_17_lut_out = CB2_ob_data_16;
CB2_ob_data_17_sload_eqn = (CB2_a_2 & NB2_d_to_dll_17) # (!CB2_a_2 & CB2_ob_data_17_lut_out);
CB2_ob_data_17 = DFFEA(CB2_ob_data_17_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_18
--operation mode is normal

CB2_ob_data_18_lut_out = CB2_ob_data_17;
CB2_ob_data_18_sload_eqn = (CB2_a_2 & NB2_d_to_dll_18) # (!CB2_a_2 & CB2_ob_data_18_lut_out);
CB2_ob_data_18 = DFFEA(CB2_ob_data_18_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_19 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_19
--operation mode is normal

CB2_ob_data_19_lut_out = CB2_ob_data_18;
CB2_ob_data_19_sload_eqn = (CB2_a_2 & NB2_d_to_dll_19) # (!CB2_a_2 & CB2_ob_data_19_lut_out);
CB2_ob_data_19 = DFFEA(CB2_ob_data_19_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_2
--operation mode is normal

CB2_ob_data_2_lut_out = CB2_ob_data_1;
CB2_ob_data_2_sload_eqn = (CB2_a_2 & NB2_d_to_dll_2) # (!CB2_a_2 & CB2_ob_data_2_lut_out);
CB2_ob_data_2 = DFFEA(CB2_ob_data_2_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_20
--operation mode is normal

CB2_ob_data_20_lut_out = CB2_ob_data_19;
CB2_ob_data_20_sload_eqn = (CB2_a_2 & NB2_d_to_dll_20) # (!CB2_a_2 & CB2_ob_data_20_lut_out);
CB2_ob_data_20 = DFFEA(CB2_ob_data_20_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_21
--operation mode is normal

CB2_ob_data_21_lut_out = CB2_ob_data_20;
CB2_ob_data_21_sload_eqn = (CB2_a_2 & NB2_d_to_dll_21) # (!CB2_a_2 & CB2_ob_data_21_lut_out);
CB2_ob_data_21 = DFFEA(CB2_ob_data_21_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_22 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_22
--operation mode is normal

CB2_ob_data_22_lut_out = CB2_ob_data_21;
CB2_ob_data_22_sload_eqn = (CB2_a_2 & NB2_d_to_dll_22) # (!CB2_a_2 & CB2_ob_data_22_lut_out);
CB2_ob_data_22 = DFFEA(CB2_ob_data_22_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_23 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_23
--operation mode is normal

CB2_ob_data_23_lut_out = CB2_ob_data_22;
CB2_ob_data_23_sload_eqn = (CB2_a_2 & NB2_d_to_dll_23) # (!CB2_a_2 & CB2_ob_data_23_lut_out);
CB2_ob_data_23 = DFFEA(CB2_ob_data_23_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_24
--operation mode is normal

CB2_ob_data_24_lut_out = CB2_ob_data_23;
CB2_ob_data_24_sload_eqn = (CB2_a_2 & NB2_d_to_dll_24) # (!CB2_a_2 & CB2_ob_data_24_lut_out);
CB2_ob_data_24 = DFFEA(CB2_ob_data_24_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_25 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_25
--operation mode is normal

CB2_ob_data_25_lut_out = CB2_ob_data_24;
CB2_ob_data_25_sload_eqn = (CB2_a_2 & NB2_d_to_dll_25) # (!CB2_a_2 & CB2_ob_data_25_lut_out);
CB2_ob_data_25 = DFFEA(CB2_ob_data_25_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_26
--operation mode is normal

CB2_ob_data_26_lut_out = CB2_ob_data_25;
CB2_ob_data_26_sload_eqn = (CB2_a_2 & NB2_d_to_dll_26) # (!CB2_a_2 & CB2_ob_data_26_lut_out);
CB2_ob_data_26 = DFFEA(CB2_ob_data_26_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_27
--operation mode is normal

CB2_ob_data_27_lut_out = CB2_ob_data_26;
CB2_ob_data_27_sload_eqn = (CB2_a_2 & NB2_d_to_dll_27) # (!CB2_a_2 & CB2_ob_data_27_lut_out);
CB2_ob_data_27 = DFFEA(CB2_ob_data_27_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_28
--operation mode is normal

CB2_ob_data_28_lut_out = CB2_ob_data_27;
CB2_ob_data_28_sload_eqn = (CB2_a_2 & NB2_d_to_dll_28) # (!CB2_a_2 & CB2_ob_data_28_lut_out);
CB2_ob_data_28 = DFFEA(CB2_ob_data_28_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_29
--operation mode is normal

CB2_ob_data_29_lut_out = CB2_ob_data_28;
CB2_ob_data_29_sload_eqn = (CB2_a_2 & NB2_d_to_dll_29) # (!CB2_a_2 & CB2_ob_data_29_lut_out);
CB2_ob_data_29 = DFFEA(CB2_ob_data_29_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_3
--operation mode is normal

CB2_ob_data_3_lut_out = CB2_ob_data_2;
CB2_ob_data_3_sload_eqn = (CB2_a_2 & NB2_d_to_dll_3) # (!CB2_a_2 & CB2_ob_data_3_lut_out);
CB2_ob_data_3 = DFFEA(CB2_ob_data_3_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_30
--operation mode is normal

CB2_ob_data_30_lut_out = CB2_ob_data_29;
CB2_ob_data_30_sload_eqn = (CB2_a_2 & NB2_d_to_dll_30) # (!CB2_a_2 & CB2_ob_data_30_lut_out);
CB2_ob_data_30 = DFFEA(CB2_ob_data_30_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_31 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_31
--operation mode is normal

CB2_ob_data_31_lut_out = CB2_ob_data_30;
CB2_ob_data_31_sload_eqn = (CB2_a_2 & NB2_d_to_dll_31) # (!CB2_a_2 & CB2_ob_data_31_lut_out);
CB2_ob_data_31 = DFFEA(CB2_ob_data_31_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_32
--operation mode is normal

CB2_ob_data_32_lut_out = CB2_ob_data_31;
CB2_ob_data_32_sload_eqn = (CB2_a_2 & NB2_d_to_dll_32) # (!CB2_a_2 & CB2_ob_data_32_lut_out);
CB2_ob_data_32 = DFFEA(CB2_ob_data_32_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_33
--operation mode is normal

CB2_ob_data_33_lut_out = CB2_ob_data_32;
CB2_ob_data_33_sload_eqn = (CB2_a_2 & NB2_d_to_dll_33) # (!CB2_a_2 & CB2_ob_data_33_lut_out);
CB2_ob_data_33 = DFFEA(CB2_ob_data_33_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_34 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_34
--operation mode is normal

CB2_ob_data_34_lut_out = CB2_ob_data_33;
CB2_ob_data_34_sload_eqn = (CB2_a_2 & NB2_d_to_dll_34) # (!CB2_a_2 & CB2_ob_data_34_lut_out);
CB2_ob_data_34 = DFFEA(CB2_ob_data_34_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_35 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_35
--operation mode is normal

CB2_ob_data_35_lut_out = CB2_ob_data_34;
CB2_ob_data_35_sload_eqn = (CB2_a_2 & NB2_d_to_dll_35) # (!CB2_a_2 & CB2_ob_data_35_lut_out);
CB2_ob_data_35 = DFFEA(CB2_ob_data_35_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_36
--operation mode is normal

CB2_ob_data_36_lut_out = CB2_ob_data_35;
CB2_ob_data_36_sload_eqn = (CB2_a_2 & NB2_d_to_dll_36) # (!CB2_a_2 & CB2_ob_data_36_lut_out);
CB2_ob_data_36 = DFFEA(CB2_ob_data_36_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_37
--operation mode is normal

CB2_ob_data_37_lut_out = CB2_ob_data_36;
CB2_ob_data_37_sload_eqn = (CB2_a_2 & NB2_d_to_dll_37) # (!CB2_a_2 & CB2_ob_data_37_lut_out);
CB2_ob_data_37 = DFFEA(CB2_ob_data_37_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_38 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_38
--operation mode is normal

CB2_ob_data_38_lut_out = CB2_ob_data_37;
CB2_ob_data_38_sload_eqn = (CB2_a_2 & NB2_d_to_dll_38) # (!CB2_a_2 & CB2_ob_data_38_lut_out);
CB2_ob_data_38 = DFFEA(CB2_ob_data_38_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_39 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_39
--operation mode is normal

CB2_ob_data_39_lut_out = CB2_ob_data_38;
CB2_ob_data_39_sload_eqn = (CB2_a_2 & NB2_d_to_dll_39) # (!CB2_a_2 & CB2_ob_data_39_lut_out);
CB2_ob_data_39 = DFFEA(CB2_ob_data_39_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_4
--operation mode is normal

CB2_ob_data_4_lut_out = CB2_ob_data_3;
CB2_ob_data_4_sload_eqn = (CB2_a_2 & NB2_d_to_dll_4) # (!CB2_a_2 & CB2_ob_data_4_lut_out);
CB2_ob_data_4 = DFFEA(CB2_ob_data_4_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_40 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_40
--operation mode is normal

CB2_ob_data_40_lut_out = CB2_ob_data_39;
CB2_ob_data_40_sload_eqn = (CB2_a_2 & NB2_d_to_dll_40) # (!CB2_a_2 & CB2_ob_data_40_lut_out);
CB2_ob_data_40 = DFFEA(CB2_ob_data_40_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_41 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_41
--operation mode is normal

CB2_ob_data_41_lut_out = CB2_ob_data_40;
CB2_ob_data_41_sload_eqn = (CB2_a_2 & NB2_d_to_dll_41) # (!CB2_a_2 & CB2_ob_data_41_lut_out);
CB2_ob_data_41 = DFFEA(CB2_ob_data_41_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_42 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_42
--operation mode is normal

CB2_ob_data_42_lut_out = CB2_ob_data_41;
CB2_ob_data_42_sload_eqn = (CB2_a_2 & NB2_d_to_dll_42) # (!CB2_a_2 & CB2_ob_data_42_lut_out);
CB2_ob_data_42 = DFFEA(CB2_ob_data_42_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_43 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_43
--operation mode is normal

CB2_ob_data_43_lut_out = CB2_ob_data_42;
CB2_ob_data_43_sload_eqn = (CB2_a_2 & NB2_d_to_dll_43) # (!CB2_a_2 & CB2_ob_data_43_lut_out);
CB2_ob_data_43 = DFFEA(CB2_ob_data_43_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_44 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_44
--operation mode is normal

CB2_ob_data_44_lut_out = CB2_ob_data_43;
CB2_ob_data_44_sload_eqn = (CB2_a_2 & NB2_d_to_dll_44) # (!CB2_a_2 & CB2_ob_data_44_lut_out);
CB2_ob_data_44 = DFFEA(CB2_ob_data_44_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_45 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_45
--operation mode is normal

CB2_ob_data_45_lut_out = CB2_ob_data_44;
CB2_ob_data_45_sload_eqn = (CB2_a_2 & NB2_d_to_dll_45) # (!CB2_a_2 & CB2_ob_data_45_lut_out);
CB2_ob_data_45 = DFFEA(CB2_ob_data_45_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_46 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_46
--operation mode is normal

CB2_ob_data_46_lut_out = CB2_ob_data_45;
CB2_ob_data_46_sload_eqn = (CB2_a_2 & NB2_d_to_dll_46) # (!CB2_a_2 & CB2_ob_data_46_lut_out);
CB2_ob_data_46 = DFFEA(CB2_ob_data_46_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_47 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_47
--operation mode is normal

CB2_ob_data_47_lut_out = CB2_ob_data_46;
CB2_ob_data_47_sload_eqn = (CB2_a_2 & NB2_d_to_dll_47) # (!CB2_a_2 & CB2_ob_data_47_lut_out);
CB2_ob_data_47 = DFFEA(CB2_ob_data_47_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_48 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_48
--operation mode is normal

CB2_ob_data_48_lut_out = CB2_ob_data_47;
CB2_ob_data_48_sload_eqn = (CB2_a_2 & NB2_d_to_dll_48) # (!CB2_a_2 & CB2_ob_data_48_lut_out);
CB2_ob_data_48 = DFFEA(CB2_ob_data_48_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_49 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_49
--operation mode is normal

CB2_ob_data_49_lut_out = CB2_ob_data_48;
CB2_ob_data_49_sload_eqn = (CB2_a_2 & NB2_d_to_dll_49) # (!CB2_a_2 & CB2_ob_data_49_lut_out);
CB2_ob_data_49 = DFFEA(CB2_ob_data_49_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_5
--operation mode is normal

CB2_ob_data_5_lut_out = CB2_ob_data_4;
CB2_ob_data_5_sload_eqn = (CB2_a_2 & NB2_d_to_dll_5) # (!CB2_a_2 & CB2_ob_data_5_lut_out);
CB2_ob_data_5 = DFFEA(CB2_ob_data_5_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_50 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_50
--operation mode is normal

CB2_ob_data_50_lut_out = CB2_ob_data_49;
CB2_ob_data_50_sload_eqn = (CB2_a_2 & NB2_d_to_dll_50) # (!CB2_a_2 & CB2_ob_data_50_lut_out);
CB2_ob_data_50 = DFFEA(CB2_ob_data_50_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_51 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_51
--operation mode is normal

CB2_ob_data_51_lut_out = CB2_ob_data_50;
CB2_ob_data_51_sload_eqn = (CB2_a_2 & NB2_d_to_dll_51) # (!CB2_a_2 & CB2_ob_data_51_lut_out);
CB2_ob_data_51 = DFFEA(CB2_ob_data_51_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_52 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_52
--operation mode is normal

CB2_ob_data_52_lut_out = CB2_ob_data_51;
CB2_ob_data_52_sload_eqn = (CB2_a_2 & NB2_d_to_dll_52) # (!CB2_a_2 & CB2_ob_data_52_lut_out);
CB2_ob_data_52 = DFFEA(CB2_ob_data_52_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_53 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_53
--operation mode is normal

CB2_ob_data_53_lut_out = CB2_ob_data_52;
CB2_ob_data_53_sload_eqn = (CB2_a_2 & NB2_d_to_dll_53) # (!CB2_a_2 & CB2_ob_data_53_lut_out);
CB2_ob_data_53 = DFFEA(CB2_ob_data_53_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_54 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_54
--operation mode is normal

CB2_ob_data_54_lut_out = CB2_ob_data_53;
CB2_ob_data_54_sload_eqn = (CB2_a_2 & NB2_d_to_dll_54) # (!CB2_a_2 & CB2_ob_data_54_lut_out);
CB2_ob_data_54 = DFFEA(CB2_ob_data_54_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_55 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_55
--operation mode is normal

CB2_ob_data_55_lut_out = CB2_ob_data_54;
CB2_ob_data_55_sload_eqn = (CB2_a_2 & NB2_d_to_dll_55) # (!CB2_a_2 & CB2_ob_data_55_lut_out);
CB2_ob_data_55 = DFFEA(CB2_ob_data_55_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_56 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_56
--operation mode is normal

CB2_ob_data_56_lut_out = CB2_ob_data_55;
CB2_ob_data_56_sload_eqn = (CB2_a_2 & NB2_d_to_dll_56) # (!CB2_a_2 & CB2_ob_data_56_lut_out);
CB2_ob_data_56 = DFFEA(CB2_ob_data_56_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_57 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_57
--operation mode is normal

CB2_ob_data_57_lut_out = CB2_ob_data_56;
CB2_ob_data_57_sload_eqn = (CB2_a_2 & NB2_d_to_dll_57) # (!CB2_a_2 & CB2_ob_data_57_lut_out);
CB2_ob_data_57 = DFFEA(CB2_ob_data_57_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_58 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_58
--operation mode is normal

CB2_ob_data_58_lut_out = CB2_ob_data_57;
CB2_ob_data_58_sload_eqn = (CB2_a_2 & NB2_d_to_dll_58) # (!CB2_a_2 & CB2_ob_data_58_lut_out);
CB2_ob_data_58 = DFFEA(CB2_ob_data_58_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_59 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_59
--operation mode is normal

CB2_ob_data_59_lut_out = CB2_ob_data_58;
CB2_ob_data_59_sload_eqn = (CB2_a_2 & NB2_d_to_dll_59) # (!CB2_a_2 & CB2_ob_data_59_lut_out);
CB2_ob_data_59 = DFFEA(CB2_ob_data_59_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_6
--operation mode is normal

CB2_ob_data_6_lut_out = CB2_ob_data_5;
CB2_ob_data_6_sload_eqn = (CB2_a_2 & NB2_d_to_dll_6) # (!CB2_a_2 & CB2_ob_data_6_lut_out);
CB2_ob_data_6 = DFFEA(CB2_ob_data_6_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_60
--operation mode is normal

CB2_ob_data_60_lut_out = CB2_ob_data_59;
CB2_ob_data_60_sload_eqn = (CB2_a_2 & NB2_d_to_dll_60) # (!CB2_a_2 & CB2_ob_data_60_lut_out);
CB2_ob_data_60 = DFFEA(CB2_ob_data_60_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_61 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_61
--operation mode is normal

CB2_ob_data_61_lut_out = CB2_ob_data_60;
CB2_ob_data_61_sload_eqn = (CB2_a_2 & NB2_d_to_dll_61) # (!CB2_a_2 & CB2_ob_data_61_lut_out);
CB2_ob_data_61 = DFFEA(CB2_ob_data_61_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_62 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_62
--operation mode is normal

CB2_ob_data_62_lut_out = CB2_ob_data_61;
CB2_ob_data_62_sload_eqn = (CB2_a_2 & NB2_d_to_dll_62) # (!CB2_a_2 & CB2_ob_data_62_lut_out);
CB2_ob_data_62 = DFFEA(CB2_ob_data_62_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_63
--operation mode is normal

CB2_ob_data_63_lut_out = CB2_ob_data_62;
CB2_ob_data_63_sload_eqn = (CB2_a_2 & NB2_d_to_dll_63) # (!CB2_a_2 & CB2_ob_data_63_lut_out);
CB2_ob_data_63 = DFFEA(CB2_ob_data_63_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_64
--operation mode is normal

CB2_ob_data_64_lut_out = CB2_ob_data_63;
CB2_ob_data_64_sload_eqn = (CB2_a_2 & NB2_d_to_dll_64) # (!CB2_a_2 & CB2_ob_data_64_lut_out);
CB2_ob_data_64 = DFFEA(CB2_ob_data_64_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_65 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_65
--operation mode is normal

CB2_ob_data_65_lut_out = CB2_ob_data_64;
CB2_ob_data_65_sload_eqn = (CB2_a_2 & NB2_d_to_dll_65) # (!CB2_a_2 & CB2_ob_data_65_lut_out);
CB2_ob_data_65 = DFFEA(CB2_ob_data_65_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_66 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_66
--operation mode is normal

CB2_ob_data_66_lut_out = CB2_ob_data_65;
CB2_ob_data_66_sload_eqn = (CB2_a_2 & NB2_d_to_dll_66) # (!CB2_a_2 & CB2_ob_data_66_lut_out);
CB2_ob_data_66 = DFFEA(CB2_ob_data_66_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_67 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_67
--operation mode is normal

CB2_ob_data_67_lut_out = CB2_ob_data_66;
CB2_ob_data_67_sload_eqn = (CB2_a_2 & NB2_d_to_dll_67) # (!CB2_a_2 & CB2_ob_data_67_lut_out);
CB2_ob_data_67 = DFFEA(CB2_ob_data_67_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_68 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_68
--operation mode is normal

CB2_ob_data_68_lut_out = CB2_ob_data_67;
CB2_ob_data_68_sload_eqn = (CB2_a_2 & NB2_d_to_dll_68) # (!CB2_a_2 & CB2_ob_data_68_lut_out);
CB2_ob_data_68 = DFFEA(CB2_ob_data_68_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_7
--operation mode is normal

CB2_ob_data_7_lut_out = CB2_ob_data_6;
CB2_ob_data_7_sload_eqn = (CB2_a_2 & NB2_d_to_dll_7) # (!CB2_a_2 & CB2_ob_data_7_lut_out);
CB2_ob_data_7 = DFFEA(CB2_ob_data_7_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_8
--operation mode is normal

CB2_ob_data_8_lut_out = CB2_ob_data_7;
CB2_ob_data_8_sload_eqn = (CB2_a_2 & NB2_d_to_dll_8) # (!CB2_a_2 & CB2_ob_data_8_lut_out);
CB2_ob_data_8 = DFFEA(CB2_ob_data_8_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB2_ob_data_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob1|ob_data_9
--operation mode is normal

CB2_ob_data_9_lut_out = CB2_ob_data_8;
CB2_ob_data_9_sload_eqn = (CB2_a_2 & NB2_d_to_dll_9) # (!CB2_a_2 & CB2_ob_data_9_lut_out);
CB2_ob_data_9 = DFFEA(CB2_ob_data_9_sload_eqn, U1__clk0, VCC, , CB2_NOT_nx714, , );


--CB1_bitcounter_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_5
--operation mode is arithmetic

CB1_bitcounter_5_carry_eqn = CB1_bitcounter_nx33;
CB1_bitcounter_5_lut_out = CB1_bitcounter_5 $ CB1_bitcounter_5_carry_eqn;
CB1_bitcounter_5_reg_input = DB1_freeze_buffer & CB1_bitcounter_5_lut_out;
CB1_bitcounter_5 = DFFEA(CB1_bitcounter_5_reg_input, U1__clk0, VCC, , , , );

--CB1_bitcounter_nx37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx37
--operation mode is arithmetic

CB1_bitcounter_nx37 = CARRY(!CB1_bitcounter_nx33 # !CB1_bitcounter_5);


--CB1_bitcounter_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_4
--operation mode is arithmetic

CB1_bitcounter_4_carry_eqn = CB1_bitcounter_nx27;
CB1_bitcounter_4_lut_out = CB1_bitcounter_4 $ !CB1_bitcounter_4_carry_eqn;
CB1_bitcounter_4_reg_input = DB1_freeze_buffer & CB1_bitcounter_4_lut_out;
CB1_bitcounter_4 = DFFEA(CB1_bitcounter_4_reg_input, U1__clk0, VCC, , , , );

--CB1_bitcounter_nx33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx33
--operation mode is arithmetic

CB1_bitcounter_nx33 = CARRY(CB1_bitcounter_4 & !CB1_bitcounter_nx27);


--CB1_bitcounter_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_3
--operation mode is arithmetic

CB1_bitcounter_3_carry_eqn = CB1_bitcounter_nx21;
CB1_bitcounter_3_lut_out = CB1_bitcounter_3 $ CB1_bitcounter_3_carry_eqn;
CB1_bitcounter_3_reg_input = DB1_freeze_buffer & CB1_bitcounter_3_lut_out;
CB1_bitcounter_3 = DFFEA(CB1_bitcounter_3_reg_input, U1__clk0, VCC, , , , );

--CB1_bitcounter_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx27
--operation mode is arithmetic

CB1_bitcounter_nx27 = CARRY(!CB1_bitcounter_nx21 # !CB1_bitcounter_3);


--CB1_bitcounter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_2
--operation mode is arithmetic

CB1_bitcounter_2_carry_eqn = CB1_bitcounter_nx15;
CB1_bitcounter_2_lut_out = CB1_bitcounter_2 $ !CB1_bitcounter_2_carry_eqn;
CB1_bitcounter_2_reg_input = DB1_freeze_buffer & CB1_bitcounter_2_lut_out;
CB1_bitcounter_2 = DFFEA(CB1_bitcounter_2_reg_input, U1__clk0, VCC, , , , );

--CB1_bitcounter_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx21
--operation mode is arithmetic

CB1_bitcounter_nx21 = CARRY(CB1_bitcounter_2 & !CB1_bitcounter_nx15);


--CB1_bitcounter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_1
--operation mode is arithmetic

CB1_bitcounter_1_carry_eqn = CB1_bitcounter_nx9;
CB1_bitcounter_1_lut_out = CB1_bitcounter_1 $ CB1_bitcounter_1_carry_eqn;
CB1_bitcounter_1_reg_input = DB1_freeze_buffer & CB1_bitcounter_1_lut_out;
CB1_bitcounter_1 = DFFEA(CB1_bitcounter_1_reg_input, U1__clk0, VCC, , , , );

--CB1_bitcounter_nx15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx15
--operation mode is arithmetic

CB1_bitcounter_nx15 = CARRY(!CB1_bitcounter_nx9 # !CB1_bitcounter_1);


--CB1_bitcounter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_0
--operation mode is arithmetic

CB1_bitcounter_0_lut_out = CB1_bitcounter_0 $ CB1_nx1398;
CB1_bitcounter_0_reg_input = DB1_freeze_buffer & CB1_bitcounter_0_lut_out;
CB1_bitcounter_0 = DFFEA(CB1_bitcounter_0_reg_input, U1__clk0, VCC, , , , );

--CB1_bitcounter_nx9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_nx9
--operation mode is arithmetic

CB1_bitcounter_nx9 = CARRY(CB1_bitcounter_0 & CB1_nx1398);


--CB1_bitcounter_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|bitcounter_6
--operation mode is normal

CB1_bitcounter_6_carry_eqn = CB1_bitcounter_nx37;
CB1_bitcounter_6_lut_out = CB1_bitcounter_6 $ !CB1_bitcounter_6_carry_eqn;
CB1_bitcounter_6_reg_input = DB1_freeze_buffer & CB1_bitcounter_6_lut_out;
CB1_bitcounter_6 = DFFEA(CB1_bitcounter_6_reg_input, U1__clk0, VCC, , , , );


--CB1_NOT_nx714 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|NOT_nx714
--operation mode is normal

CB1_NOT_nx714 = DB1_freeze_buffer & DB1_request_data & CB1_nx119 # !DB1_freeze_buffer & NB1_d_we;


--CB1_nx1398 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|nx1398
--operation mode is normal

CB1_nx1398 = DB1_request_data & !CB1_buffer_empty;


--CB1_NOT_ob_empty is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|NOT_ob_empty
--operation mode is normal

CB1_NOT_ob_empty = !CB1_bitcounter_5 & CB1_modgen_gt_489_nx60 & !CB1_bitcounter_4 # !CB1_bitcounter_6;


--CB1_a_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|a_2
--operation mode is normal

CB1_a_2 = !DB1_freeze_buffer & NB1_d_we;


--CB1_modgen_gt_489_nx60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|modgen_gt_489_nx60
--operation mode is normal

CB1_modgen_gt_489_nx60 = !CB1_bitcounter_3 & (!CB1_bitcounter_1 & !CB1_bitcounter_0 # !CB1_bitcounter_2);


--CB1_nx119 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|nx119
--operation mode is normal

CB1_nx119 = CB1_nx120 # !CB1_bitcounter_5 & !CB1_bitcounter_3 & CB1_nx121;


--CB1_nx120 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|nx120
--operation mode is normal

CB1_nx120 = !CB1_bitcounter_5 & !CB1_bitcounter_4 # !CB1_bitcounter_6;


--CB1_nx121 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|nx121
--operation mode is normal

CB1_nx121 = !CB1_bitcounter_1 & !CB1_bitcounter_0 # !CB1_bitcounter_2;


--CB1_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|data_out
--operation mode is normal

CB1_data_out = CB1_ob_data_68 & (CB1_ob_crc_15 # CB1_NOT_ob_empty) # !CB1_ob_data_68 & CB1_ob_crc_15 & !CB1_NOT_ob_empty;


--CB1_buffer_empty is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|buffer_empty
--operation mode is normal

CB1_buffer_empty = CB1_bitcounter_6 & (CB1_bitcounter_5 # !CB1_modgen_gt_489_nx60 & CB1_bitcounter_4);


--CB1_ob_crc_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_0
--operation mode is normal

CB1_ob_crc_0_lut_out = CB1_ob_data_52 $ (CB1_ob_crc_15 & CB1_NOT_ob_empty);
CB1_ob_crc_0_sload_eqn = (CB1_a_2 & NB1_d_to_dll_53) # (!CB1_a_2 & CB1_ob_crc_0_lut_out);
CB1_ob_crc_0 = DFFEA(CB1_ob_crc_0_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_1
--operation mode is normal

CB1_ob_crc_1_lut_out = CB1_ob_crc_0;
CB1_ob_crc_1_sload_eqn = (CB1_a_2 & NB1_d_to_dll_54) # (!CB1_a_2 & CB1_ob_crc_1_lut_out);
CB1_ob_crc_1 = DFFEA(CB1_ob_crc_1_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_10
--operation mode is normal

CB1_ob_crc_10_lut_out = CB1_ob_crc_9;
CB1_ob_crc_10_sload_eqn = (CB1_a_2 & NB1_d_to_dll_63) # (!CB1_a_2 & CB1_ob_crc_10_lut_out);
CB1_ob_crc_10 = DFFEA(CB1_ob_crc_10_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_11
--operation mode is normal

CB1_ob_crc_11_lut_out = CB1_ob_crc_10;
CB1_ob_crc_11_sload_eqn = (CB1_a_2 & NB1_d_to_dll_64) # (!CB1_a_2 & CB1_ob_crc_11_lut_out);
CB1_ob_crc_11 = DFFEA(CB1_ob_crc_11_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_12
--operation mode is normal

CB1_ob_crc_12_lut_out = CB1_ob_crc_11;
CB1_ob_crc_12_sload_eqn = (CB1_a_2 & NB1_d_to_dll_65) # (!CB1_a_2 & CB1_ob_crc_12_lut_out);
CB1_ob_crc_12 = DFFEA(CB1_ob_crc_12_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_13
--operation mode is normal

CB1_ob_crc_13_lut_out = CB1_ob_crc_12;
CB1_ob_crc_13_sload_eqn = (CB1_a_2 & NB1_d_to_dll_66) # (!CB1_a_2 & CB1_ob_crc_13_lut_out);
CB1_ob_crc_13 = DFFEA(CB1_ob_crc_13_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_14
--operation mode is normal

CB1_ob_crc_14_lut_out = CB1_ob_crc_13;
CB1_ob_crc_14_sload_eqn = (CB1_a_2 & NB1_d_to_dll_67) # (!CB1_a_2 & CB1_ob_crc_14_lut_out);
CB1_ob_crc_14 = DFFEA(CB1_ob_crc_14_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_15
--operation mode is normal

CB1_ob_crc_15_lut_out = CB1_ob_crc_14 $ (CB1_ob_crc_15 & CB1_NOT_ob_empty);
CB1_ob_crc_15_sload_eqn = (CB1_a_2 & NB1_d_to_dll_68) # (!CB1_a_2 & CB1_ob_crc_15_lut_out);
CB1_ob_crc_15 = DFFEA(CB1_ob_crc_15_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_2
--operation mode is normal

CB1_ob_crc_2_lut_out = CB1_ob_crc_1 $ (CB1_ob_crc_15 & CB1_NOT_ob_empty);
CB1_ob_crc_2_sload_eqn = (CB1_a_2 & NB1_d_to_dll_55) # (!CB1_a_2 & CB1_ob_crc_2_lut_out);
CB1_ob_crc_2 = DFFEA(CB1_ob_crc_2_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_3
--operation mode is normal

CB1_ob_crc_3_lut_out = CB1_ob_crc_2;
CB1_ob_crc_3_sload_eqn = (CB1_a_2 & NB1_d_to_dll_56) # (!CB1_a_2 & CB1_ob_crc_3_lut_out);
CB1_ob_crc_3 = DFFEA(CB1_ob_crc_3_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_4
--operation mode is normal

CB1_ob_crc_4_lut_out = CB1_ob_crc_3;
CB1_ob_crc_4_sload_eqn = (CB1_a_2 & NB1_d_to_dll_57) # (!CB1_a_2 & CB1_ob_crc_4_lut_out);
CB1_ob_crc_4 = DFFEA(CB1_ob_crc_4_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_5
--operation mode is normal

CB1_ob_crc_5_lut_out = CB1_ob_crc_4;
CB1_ob_crc_5_sload_eqn = (CB1_a_2 & NB1_d_to_dll_58) # (!CB1_a_2 & CB1_ob_crc_5_lut_out);
CB1_ob_crc_5 = DFFEA(CB1_ob_crc_5_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_6
--operation mode is normal

CB1_ob_crc_6_lut_out = CB1_ob_crc_5;
CB1_ob_crc_6_sload_eqn = (CB1_a_2 & NB1_d_to_dll_59) # (!CB1_a_2 & CB1_ob_crc_6_lut_out);
CB1_ob_crc_6 = DFFEA(CB1_ob_crc_6_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_7
--operation mode is normal

CB1_ob_crc_7_lut_out = CB1_ob_crc_6;
CB1_ob_crc_7_sload_eqn = (CB1_a_2 & NB1_d_to_dll_60) # (!CB1_a_2 & CB1_ob_crc_7_lut_out);
CB1_ob_crc_7 = DFFEA(CB1_ob_crc_7_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_8
--operation mode is normal

CB1_ob_crc_8_lut_out = CB1_ob_crc_7;
CB1_ob_crc_8_sload_eqn = (CB1_a_2 & NB1_d_to_dll_61) # (!CB1_a_2 & CB1_ob_crc_8_lut_out);
CB1_ob_crc_8 = DFFEA(CB1_ob_crc_8_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_crc_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_crc_9
--operation mode is normal

CB1_ob_crc_9_lut_out = CB1_ob_crc_8;
CB1_ob_crc_9_sload_eqn = (CB1_a_2 & NB1_d_to_dll_62) # (!CB1_a_2 & CB1_ob_crc_9_lut_out);
CB1_ob_crc_9 = DFFEA(CB1_ob_crc_9_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_0
--operation mode is normal

CB1_ob_data_0_lut_out = !DB1_freeze_buffer & NB1_d_to_dll_0 & NB1_d_we;
CB1_ob_data_0 = DFFEA(CB1_ob_data_0_lut_out, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_1
--operation mode is normal

CB1_ob_data_1_lut_out = CB1_ob_data_0;
CB1_ob_data_1_sload_eqn = (CB1_a_2 & NB1_d_to_dll_1) # (!CB1_a_2 & CB1_ob_data_1_lut_out);
CB1_ob_data_1 = DFFEA(CB1_ob_data_1_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_10
--operation mode is normal

CB1_ob_data_10_lut_out = CB1_ob_data_9;
CB1_ob_data_10_sload_eqn = (CB1_a_2 & NB1_d_to_dll_10) # (!CB1_a_2 & CB1_ob_data_10_lut_out);
CB1_ob_data_10 = DFFEA(CB1_ob_data_10_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_11
--operation mode is normal

CB1_ob_data_11_lut_out = CB1_ob_data_10;
CB1_ob_data_11_sload_eqn = (CB1_a_2 & NB1_d_to_dll_11) # (!CB1_a_2 & CB1_ob_data_11_lut_out);
CB1_ob_data_11 = DFFEA(CB1_ob_data_11_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_12
--operation mode is normal

CB1_ob_data_12_lut_out = CB1_ob_data_11;
CB1_ob_data_12_sload_eqn = (CB1_a_2 & NB1_d_to_dll_12) # (!CB1_a_2 & CB1_ob_data_12_lut_out);
CB1_ob_data_12 = DFFEA(CB1_ob_data_12_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_13
--operation mode is normal

CB1_ob_data_13_lut_out = CB1_ob_data_12;
CB1_ob_data_13_sload_eqn = (CB1_a_2 & NB1_d_to_dll_13) # (!CB1_a_2 & CB1_ob_data_13_lut_out);
CB1_ob_data_13 = DFFEA(CB1_ob_data_13_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_14
--operation mode is normal

CB1_ob_data_14_lut_out = CB1_ob_data_13;
CB1_ob_data_14_sload_eqn = (CB1_a_2 & NB1_d_to_dll_14) # (!CB1_a_2 & CB1_ob_data_14_lut_out);
CB1_ob_data_14 = DFFEA(CB1_ob_data_14_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_15
--operation mode is normal

CB1_ob_data_15_lut_out = CB1_ob_data_14;
CB1_ob_data_15_sload_eqn = (CB1_a_2 & NB1_d_to_dll_15) # (!CB1_a_2 & CB1_ob_data_15_lut_out);
CB1_ob_data_15 = DFFEA(CB1_ob_data_15_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_16 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_16
--operation mode is normal

CB1_ob_data_16_lut_out = CB1_ob_data_15;
CB1_ob_data_16_sload_eqn = (CB1_a_2 & NB1_d_to_dll_16) # (!CB1_a_2 & CB1_ob_data_16_lut_out);
CB1_ob_data_16 = DFFEA(CB1_ob_data_16_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_17 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_17
--operation mode is normal

CB1_ob_data_17_lut_out = CB1_ob_data_16;
CB1_ob_data_17_sload_eqn = (CB1_a_2 & NB1_d_to_dll_17) # (!CB1_a_2 & CB1_ob_data_17_lut_out);
CB1_ob_data_17 = DFFEA(CB1_ob_data_17_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_18
--operation mode is normal

CB1_ob_data_18_lut_out = CB1_ob_data_17;
CB1_ob_data_18_sload_eqn = (CB1_a_2 & NB1_d_to_dll_18) # (!CB1_a_2 & CB1_ob_data_18_lut_out);
CB1_ob_data_18 = DFFEA(CB1_ob_data_18_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_19 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_19
--operation mode is normal

CB1_ob_data_19_lut_out = CB1_ob_data_18;
CB1_ob_data_19_sload_eqn = (CB1_a_2 & NB1_d_to_dll_19) # (!CB1_a_2 & CB1_ob_data_19_lut_out);
CB1_ob_data_19 = DFFEA(CB1_ob_data_19_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_2
--operation mode is normal

CB1_ob_data_2_lut_out = CB1_ob_data_1;
CB1_ob_data_2_sload_eqn = (CB1_a_2 & NB1_d_to_dll_2) # (!CB1_a_2 & CB1_ob_data_2_lut_out);
CB1_ob_data_2 = DFFEA(CB1_ob_data_2_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_20
--operation mode is normal

CB1_ob_data_20_lut_out = CB1_ob_data_19;
CB1_ob_data_20_sload_eqn = (CB1_a_2 & NB1_d_to_dll_20) # (!CB1_a_2 & CB1_ob_data_20_lut_out);
CB1_ob_data_20 = DFFEA(CB1_ob_data_20_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_21
--operation mode is normal

CB1_ob_data_21_lut_out = CB1_ob_data_20;
CB1_ob_data_21_sload_eqn = (CB1_a_2 & NB1_d_to_dll_21) # (!CB1_a_2 & CB1_ob_data_21_lut_out);
CB1_ob_data_21 = DFFEA(CB1_ob_data_21_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_22 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_22
--operation mode is normal

CB1_ob_data_22_lut_out = CB1_ob_data_21;
CB1_ob_data_22_sload_eqn = (CB1_a_2 & NB1_d_to_dll_22) # (!CB1_a_2 & CB1_ob_data_22_lut_out);
CB1_ob_data_22 = DFFEA(CB1_ob_data_22_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_23 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_23
--operation mode is normal

CB1_ob_data_23_lut_out = CB1_ob_data_22;
CB1_ob_data_23_sload_eqn = (CB1_a_2 & NB1_d_to_dll_23) # (!CB1_a_2 & CB1_ob_data_23_lut_out);
CB1_ob_data_23 = DFFEA(CB1_ob_data_23_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_24
--operation mode is normal

CB1_ob_data_24_lut_out = CB1_ob_data_23;
CB1_ob_data_24_sload_eqn = (CB1_a_2 & NB1_d_to_dll_24) # (!CB1_a_2 & CB1_ob_data_24_lut_out);
CB1_ob_data_24 = DFFEA(CB1_ob_data_24_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_25 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_25
--operation mode is normal

CB1_ob_data_25_lut_out = CB1_ob_data_24;
CB1_ob_data_25_sload_eqn = (CB1_a_2 & NB1_d_to_dll_25) # (!CB1_a_2 & CB1_ob_data_25_lut_out);
CB1_ob_data_25 = DFFEA(CB1_ob_data_25_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_26
--operation mode is normal

CB1_ob_data_26_lut_out = CB1_ob_data_25;
CB1_ob_data_26_sload_eqn = (CB1_a_2 & NB1_d_to_dll_26) # (!CB1_a_2 & CB1_ob_data_26_lut_out);
CB1_ob_data_26 = DFFEA(CB1_ob_data_26_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_27
--operation mode is normal

CB1_ob_data_27_lut_out = CB1_ob_data_26;
CB1_ob_data_27_sload_eqn = (CB1_a_2 & NB1_d_to_dll_27) # (!CB1_a_2 & CB1_ob_data_27_lut_out);
CB1_ob_data_27 = DFFEA(CB1_ob_data_27_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_28
--operation mode is normal

CB1_ob_data_28_lut_out = CB1_ob_data_27;
CB1_ob_data_28_sload_eqn = (CB1_a_2 & NB1_d_to_dll_28) # (!CB1_a_2 & CB1_ob_data_28_lut_out);
CB1_ob_data_28 = DFFEA(CB1_ob_data_28_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_29
--operation mode is normal

CB1_ob_data_29_lut_out = CB1_ob_data_28;
CB1_ob_data_29_sload_eqn = (CB1_a_2 & NB1_d_to_dll_29) # (!CB1_a_2 & CB1_ob_data_29_lut_out);
CB1_ob_data_29 = DFFEA(CB1_ob_data_29_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_3
--operation mode is normal

CB1_ob_data_3_lut_out = CB1_ob_data_2;
CB1_ob_data_3_sload_eqn = (CB1_a_2 & NB1_d_to_dll_3) # (!CB1_a_2 & CB1_ob_data_3_lut_out);
CB1_ob_data_3 = DFFEA(CB1_ob_data_3_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_30
--operation mode is normal

CB1_ob_data_30_lut_out = CB1_ob_data_29;
CB1_ob_data_30_sload_eqn = (CB1_a_2 & NB1_d_to_dll_30) # (!CB1_a_2 & CB1_ob_data_30_lut_out);
CB1_ob_data_30 = DFFEA(CB1_ob_data_30_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_31 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_31
--operation mode is normal

CB1_ob_data_31_lut_out = CB1_ob_data_30;
CB1_ob_data_31_sload_eqn = (CB1_a_2 & NB1_d_to_dll_31) # (!CB1_a_2 & CB1_ob_data_31_lut_out);
CB1_ob_data_31 = DFFEA(CB1_ob_data_31_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_32
--operation mode is normal

CB1_ob_data_32_lut_out = CB1_ob_data_31;
CB1_ob_data_32_sload_eqn = (CB1_a_2 & NB1_d_to_dll_32) # (!CB1_a_2 & CB1_ob_data_32_lut_out);
CB1_ob_data_32 = DFFEA(CB1_ob_data_32_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_33
--operation mode is normal

CB1_ob_data_33_lut_out = CB1_ob_data_32;
CB1_ob_data_33_sload_eqn = (CB1_a_2 & NB1_d_to_dll_33) # (!CB1_a_2 & CB1_ob_data_33_lut_out);
CB1_ob_data_33 = DFFEA(CB1_ob_data_33_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_34 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_34
--operation mode is normal

CB1_ob_data_34_lut_out = CB1_ob_data_33;
CB1_ob_data_34_sload_eqn = (CB1_a_2 & NB1_d_to_dll_34) # (!CB1_a_2 & CB1_ob_data_34_lut_out);
CB1_ob_data_34 = DFFEA(CB1_ob_data_34_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_35 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_35
--operation mode is normal

CB1_ob_data_35_lut_out = CB1_ob_data_34;
CB1_ob_data_35_sload_eqn = (CB1_a_2 & NB1_d_to_dll_35) # (!CB1_a_2 & CB1_ob_data_35_lut_out);
CB1_ob_data_35 = DFFEA(CB1_ob_data_35_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_36
--operation mode is normal

CB1_ob_data_36_lut_out = CB1_ob_data_35;
CB1_ob_data_36_sload_eqn = (CB1_a_2 & NB1_d_to_dll_36) # (!CB1_a_2 & CB1_ob_data_36_lut_out);
CB1_ob_data_36 = DFFEA(CB1_ob_data_36_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_37
--operation mode is normal

CB1_ob_data_37_lut_out = CB1_ob_data_36;
CB1_ob_data_37_sload_eqn = (CB1_a_2 & NB1_d_to_dll_37) # (!CB1_a_2 & CB1_ob_data_37_lut_out);
CB1_ob_data_37 = DFFEA(CB1_ob_data_37_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_38 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_38
--operation mode is normal

CB1_ob_data_38_lut_out = CB1_ob_data_37;
CB1_ob_data_38_sload_eqn = (CB1_a_2 & NB1_d_to_dll_38) # (!CB1_a_2 & CB1_ob_data_38_lut_out);
CB1_ob_data_38 = DFFEA(CB1_ob_data_38_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_39 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_39
--operation mode is normal

CB1_ob_data_39_lut_out = CB1_ob_data_38;
CB1_ob_data_39_sload_eqn = (CB1_a_2 & NB1_d_to_dll_39) # (!CB1_a_2 & CB1_ob_data_39_lut_out);
CB1_ob_data_39 = DFFEA(CB1_ob_data_39_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_4
--operation mode is normal

CB1_ob_data_4_lut_out = CB1_ob_data_3;
CB1_ob_data_4_sload_eqn = (CB1_a_2 & NB1_d_to_dll_4) # (!CB1_a_2 & CB1_ob_data_4_lut_out);
CB1_ob_data_4 = DFFEA(CB1_ob_data_4_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_40 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_40
--operation mode is normal

CB1_ob_data_40_lut_out = CB1_ob_data_39;
CB1_ob_data_40_sload_eqn = (CB1_a_2 & NB1_d_to_dll_40) # (!CB1_a_2 & CB1_ob_data_40_lut_out);
CB1_ob_data_40 = DFFEA(CB1_ob_data_40_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_41 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_41
--operation mode is normal

CB1_ob_data_41_lut_out = CB1_ob_data_40;
CB1_ob_data_41_sload_eqn = (CB1_a_2 & NB1_d_to_dll_41) # (!CB1_a_2 & CB1_ob_data_41_lut_out);
CB1_ob_data_41 = DFFEA(CB1_ob_data_41_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_42 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_42
--operation mode is normal

CB1_ob_data_42_lut_out = CB1_ob_data_41;
CB1_ob_data_42_sload_eqn = (CB1_a_2 & NB1_d_to_dll_42) # (!CB1_a_2 & CB1_ob_data_42_lut_out);
CB1_ob_data_42 = DFFEA(CB1_ob_data_42_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_43 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_43
--operation mode is normal

CB1_ob_data_43_lut_out = CB1_ob_data_42;
CB1_ob_data_43_sload_eqn = (CB1_a_2 & NB1_d_to_dll_43) # (!CB1_a_2 & CB1_ob_data_43_lut_out);
CB1_ob_data_43 = DFFEA(CB1_ob_data_43_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_44 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_44
--operation mode is normal

CB1_ob_data_44_lut_out = CB1_ob_data_43;
CB1_ob_data_44_sload_eqn = (CB1_a_2 & NB1_d_to_dll_44) # (!CB1_a_2 & CB1_ob_data_44_lut_out);
CB1_ob_data_44 = DFFEA(CB1_ob_data_44_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_45 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_45
--operation mode is normal

CB1_ob_data_45_lut_out = CB1_ob_data_44;
CB1_ob_data_45_sload_eqn = (CB1_a_2 & NB1_d_to_dll_45) # (!CB1_a_2 & CB1_ob_data_45_lut_out);
CB1_ob_data_45 = DFFEA(CB1_ob_data_45_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_46 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_46
--operation mode is normal

CB1_ob_data_46_lut_out = CB1_ob_data_45;
CB1_ob_data_46_sload_eqn = (CB1_a_2 & NB1_d_to_dll_46) # (!CB1_a_2 & CB1_ob_data_46_lut_out);
CB1_ob_data_46 = DFFEA(CB1_ob_data_46_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_47 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_47
--operation mode is normal

CB1_ob_data_47_lut_out = CB1_ob_data_46;
CB1_ob_data_47_sload_eqn = (CB1_a_2 & NB1_d_to_dll_47) # (!CB1_a_2 & CB1_ob_data_47_lut_out);
CB1_ob_data_47 = DFFEA(CB1_ob_data_47_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_48 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_48
--operation mode is normal

CB1_ob_data_48_lut_out = CB1_ob_data_47;
CB1_ob_data_48_sload_eqn = (CB1_a_2 & NB1_d_to_dll_48) # (!CB1_a_2 & CB1_ob_data_48_lut_out);
CB1_ob_data_48 = DFFEA(CB1_ob_data_48_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_49 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_49
--operation mode is normal

CB1_ob_data_49_lut_out = CB1_ob_data_48;
CB1_ob_data_49_sload_eqn = (CB1_a_2 & NB1_d_to_dll_49) # (!CB1_a_2 & CB1_ob_data_49_lut_out);
CB1_ob_data_49 = DFFEA(CB1_ob_data_49_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_5
--operation mode is normal

CB1_ob_data_5_lut_out = CB1_ob_data_4;
CB1_ob_data_5_sload_eqn = (CB1_a_2 & NB1_d_to_dll_5) # (!CB1_a_2 & CB1_ob_data_5_lut_out);
CB1_ob_data_5 = DFFEA(CB1_ob_data_5_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_50 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_50
--operation mode is normal

CB1_ob_data_50_lut_out = CB1_ob_data_49;
CB1_ob_data_50_sload_eqn = (CB1_a_2 & NB1_d_to_dll_50) # (!CB1_a_2 & CB1_ob_data_50_lut_out);
CB1_ob_data_50 = DFFEA(CB1_ob_data_50_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_51 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_51
--operation mode is normal

CB1_ob_data_51_lut_out = CB1_ob_data_50;
CB1_ob_data_51_sload_eqn = (CB1_a_2 & NB1_d_to_dll_51) # (!CB1_a_2 & CB1_ob_data_51_lut_out);
CB1_ob_data_51 = DFFEA(CB1_ob_data_51_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_52 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_52
--operation mode is normal

CB1_ob_data_52_lut_out = CB1_ob_data_51;
CB1_ob_data_52_sload_eqn = (CB1_a_2 & NB1_d_to_dll_52) # (!CB1_a_2 & CB1_ob_data_52_lut_out);
CB1_ob_data_52 = DFFEA(CB1_ob_data_52_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_53 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_53
--operation mode is normal

CB1_ob_data_53_lut_out = CB1_ob_data_52;
CB1_ob_data_53_sload_eqn = (CB1_a_2 & NB1_d_to_dll_53) # (!CB1_a_2 & CB1_ob_data_53_lut_out);
CB1_ob_data_53 = DFFEA(CB1_ob_data_53_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_54 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_54
--operation mode is normal

CB1_ob_data_54_lut_out = CB1_ob_data_53;
CB1_ob_data_54_sload_eqn = (CB1_a_2 & NB1_d_to_dll_54) # (!CB1_a_2 & CB1_ob_data_54_lut_out);
CB1_ob_data_54 = DFFEA(CB1_ob_data_54_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_55 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_55
--operation mode is normal

CB1_ob_data_55_lut_out = CB1_ob_data_54;
CB1_ob_data_55_sload_eqn = (CB1_a_2 & NB1_d_to_dll_55) # (!CB1_a_2 & CB1_ob_data_55_lut_out);
CB1_ob_data_55 = DFFEA(CB1_ob_data_55_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_56 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_56
--operation mode is normal

CB1_ob_data_56_lut_out = CB1_ob_data_55;
CB1_ob_data_56_sload_eqn = (CB1_a_2 & NB1_d_to_dll_56) # (!CB1_a_2 & CB1_ob_data_56_lut_out);
CB1_ob_data_56 = DFFEA(CB1_ob_data_56_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_57 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_57
--operation mode is normal

CB1_ob_data_57_lut_out = CB1_ob_data_56;
CB1_ob_data_57_sload_eqn = (CB1_a_2 & NB1_d_to_dll_57) # (!CB1_a_2 & CB1_ob_data_57_lut_out);
CB1_ob_data_57 = DFFEA(CB1_ob_data_57_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_58 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_58
--operation mode is normal

CB1_ob_data_58_lut_out = CB1_ob_data_57;
CB1_ob_data_58_sload_eqn = (CB1_a_2 & NB1_d_to_dll_58) # (!CB1_a_2 & CB1_ob_data_58_lut_out);
CB1_ob_data_58 = DFFEA(CB1_ob_data_58_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_59 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_59
--operation mode is normal

CB1_ob_data_59_lut_out = CB1_ob_data_58;
CB1_ob_data_59_sload_eqn = (CB1_a_2 & NB1_d_to_dll_59) # (!CB1_a_2 & CB1_ob_data_59_lut_out);
CB1_ob_data_59 = DFFEA(CB1_ob_data_59_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_6
--operation mode is normal

CB1_ob_data_6_lut_out = CB1_ob_data_5;
CB1_ob_data_6_sload_eqn = (CB1_a_2 & NB1_d_to_dll_6) # (!CB1_a_2 & CB1_ob_data_6_lut_out);
CB1_ob_data_6 = DFFEA(CB1_ob_data_6_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_60
--operation mode is normal

CB1_ob_data_60_lut_out = CB1_ob_data_59;
CB1_ob_data_60_sload_eqn = (CB1_a_2 & NB1_d_to_dll_60) # (!CB1_a_2 & CB1_ob_data_60_lut_out);
CB1_ob_data_60 = DFFEA(CB1_ob_data_60_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_61 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_61
--operation mode is normal

CB1_ob_data_61_lut_out = CB1_ob_data_60;
CB1_ob_data_61_sload_eqn = (CB1_a_2 & NB1_d_to_dll_61) # (!CB1_a_2 & CB1_ob_data_61_lut_out);
CB1_ob_data_61 = DFFEA(CB1_ob_data_61_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_62 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_62
--operation mode is normal

CB1_ob_data_62_lut_out = CB1_ob_data_61;
CB1_ob_data_62_sload_eqn = (CB1_a_2 & NB1_d_to_dll_62) # (!CB1_a_2 & CB1_ob_data_62_lut_out);
CB1_ob_data_62 = DFFEA(CB1_ob_data_62_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_63
--operation mode is normal

CB1_ob_data_63_lut_out = CB1_ob_data_62;
CB1_ob_data_63_sload_eqn = (CB1_a_2 & NB1_d_to_dll_63) # (!CB1_a_2 & CB1_ob_data_63_lut_out);
CB1_ob_data_63 = DFFEA(CB1_ob_data_63_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_64
--operation mode is normal

CB1_ob_data_64_lut_out = CB1_ob_data_63;
CB1_ob_data_64_sload_eqn = (CB1_a_2 & NB1_d_to_dll_64) # (!CB1_a_2 & CB1_ob_data_64_lut_out);
CB1_ob_data_64 = DFFEA(CB1_ob_data_64_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_65 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_65
--operation mode is normal

CB1_ob_data_65_lut_out = CB1_ob_data_64;
CB1_ob_data_65_sload_eqn = (CB1_a_2 & NB1_d_to_dll_65) # (!CB1_a_2 & CB1_ob_data_65_lut_out);
CB1_ob_data_65 = DFFEA(CB1_ob_data_65_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_66 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_66
--operation mode is normal

CB1_ob_data_66_lut_out = CB1_ob_data_65;
CB1_ob_data_66_sload_eqn = (CB1_a_2 & NB1_d_to_dll_66) # (!CB1_a_2 & CB1_ob_data_66_lut_out);
CB1_ob_data_66 = DFFEA(CB1_ob_data_66_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_67 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_67
--operation mode is normal

CB1_ob_data_67_lut_out = CB1_ob_data_66;
CB1_ob_data_67_sload_eqn = (CB1_a_2 & NB1_d_to_dll_67) # (!CB1_a_2 & CB1_ob_data_67_lut_out);
CB1_ob_data_67 = DFFEA(CB1_ob_data_67_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_68 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_68
--operation mode is normal

CB1_ob_data_68_lut_out = CB1_ob_data_67;
CB1_ob_data_68_sload_eqn = (CB1_a_2 & NB1_d_to_dll_68) # (!CB1_a_2 & CB1_ob_data_68_lut_out);
CB1_ob_data_68 = DFFEA(CB1_ob_data_68_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_7
--operation mode is normal

CB1_ob_data_7_lut_out = CB1_ob_data_6;
CB1_ob_data_7_sload_eqn = (CB1_a_2 & NB1_d_to_dll_7) # (!CB1_a_2 & CB1_ob_data_7_lut_out);
CB1_ob_data_7 = DFFEA(CB1_ob_data_7_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_8
--operation mode is normal

CB1_ob_data_8_lut_out = CB1_ob_data_7;
CB1_ob_data_8_sload_eqn = (CB1_a_2 & NB1_d_to_dll_8) # (!CB1_a_2 & CB1_ob_data_8_lut_out);
CB1_ob_data_8 = DFFEA(CB1_ob_data_8_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--CB1_ob_data_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_outbuf_69_7:ob0|ob_data_9
--operation mode is normal

CB1_ob_data_9_lut_out = CB1_ob_data_8;
CB1_ob_data_9_sload_eqn = (CB1_a_2 & NB1_d_to_dll_9) # (!CB1_a_2 & CB1_ob_data_9_lut_out);
CB1_ob_data_9 = DFFEA(CB1_ob_data_9_sload_eqn, U1__clk0, VCC, , CB1_NOT_nx714, , );


--BB2_bitcounter_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_5
--operation mode is arithmetic

BB2_bitcounter_5_carry_eqn = BB2_bitcounter_nx33;
BB2_bitcounter_5_lut_out = BB2_bitcounter_5 $ BB2_bitcounter_5_carry_eqn;
BB2_bitcounter_5_reg_input = AB2_buffer_flush_n & BB2_bitcounter_5_lut_out;
BB2_bitcounter_5 = DFFEA(BB2_bitcounter_5_reg_input, U1__clk0, VCC, , , , );

--BB2_bitcounter_nx37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx37
--operation mode is arithmetic

BB2_bitcounter_nx37 = CARRY(!BB2_bitcounter_nx33 # !BB2_bitcounter_5);


--BB2_bitcounter_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_4
--operation mode is arithmetic

BB2_bitcounter_4_carry_eqn = BB2_bitcounter_nx27;
BB2_bitcounter_4_lut_out = BB2_bitcounter_4 $ !BB2_bitcounter_4_carry_eqn;
BB2_bitcounter_4_reg_input = AB2_buffer_flush_n & BB2_bitcounter_4_lut_out;
BB2_bitcounter_4 = DFFEA(BB2_bitcounter_4_reg_input, U1__clk0, VCC, , , , );

--BB2_bitcounter_nx33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx33
--operation mode is arithmetic

BB2_bitcounter_nx33 = CARRY(BB2_bitcounter_4 & !BB2_bitcounter_nx27);


--BB2_bitcounter_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_3
--operation mode is arithmetic

BB2_bitcounter_3_carry_eqn = BB2_bitcounter_nx21;
BB2_bitcounter_3_lut_out = BB2_bitcounter_3 $ BB2_bitcounter_3_carry_eqn;
BB2_bitcounter_3_reg_input = AB2_buffer_flush_n & BB2_bitcounter_3_lut_out;
BB2_bitcounter_3 = DFFEA(BB2_bitcounter_3_reg_input, U1__clk0, VCC, , , , );

--BB2_bitcounter_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx27
--operation mode is arithmetic

BB2_bitcounter_nx27 = CARRY(!BB2_bitcounter_nx21 # !BB2_bitcounter_3);


--BB2_bitcounter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_2
--operation mode is arithmetic

BB2_bitcounter_2_carry_eqn = BB2_bitcounter_nx15;
BB2_bitcounter_2_lut_out = BB2_bitcounter_2 $ !BB2_bitcounter_2_carry_eqn;
BB2_bitcounter_2_reg_input = AB2_buffer_flush_n & BB2_bitcounter_2_lut_out;
BB2_bitcounter_2 = DFFEA(BB2_bitcounter_2_reg_input, U1__clk0, VCC, , , , );

--BB2_bitcounter_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx21
--operation mode is arithmetic

BB2_bitcounter_nx21 = CARRY(BB2_bitcounter_2 & !BB2_bitcounter_nx15);


--BB2_bitcounter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_1
--operation mode is arithmetic

BB2_bitcounter_1_carry_eqn = BB2_bitcounter_nx9;
BB2_bitcounter_1_lut_out = BB2_bitcounter_1 $ BB2_bitcounter_1_carry_eqn;
BB2_bitcounter_1_reg_input = AB2_buffer_flush_n & BB2_bitcounter_1_lut_out;
BB2_bitcounter_1 = DFFEA(BB2_bitcounter_1_reg_input, U1__clk0, VCC, , , , );

--BB2_bitcounter_nx15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx15
--operation mode is arithmetic

BB2_bitcounter_nx15 = CARRY(!BB2_bitcounter_nx9 # !BB2_bitcounter_1);


--BB2_bitcounter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_0
--operation mode is arithmetic

BB2_bitcounter_0_lut_out = BB2_bitcounter_0 $ EB2_strobe_out;
BB2_bitcounter_0_reg_input = AB2_buffer_flush_n & BB2_bitcounter_0_lut_out;
BB2_bitcounter_0 = DFFEA(BB2_bitcounter_0_reg_input, U1__clk0, VCC, , , , );

--BB2_bitcounter_nx9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_nx9
--operation mode is arithmetic

BB2_bitcounter_nx9 = CARRY(BB2_bitcounter_0 & EB2_strobe_out);


--BB2_bitcounter_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|bitcounter_6
--operation mode is normal

BB2_bitcounter_6_carry_eqn = BB2_bitcounter_nx37;
BB2_bitcounter_6_lut_out = BB2_bitcounter_6 $ !BB2_bitcounter_6_carry_eqn;
BB2_bitcounter_6_reg_input = AB2_buffer_flush_n & BB2_bitcounter_6_lut_out;
BB2_bitcounter_6 = DFFEA(BB2_bitcounter_6_reg_input, U1__clk0, VCC, , , , );


--BB2_NOT_nx676 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|NOT_nx676
--operation mode is normal

BB2_NOT_nx676 = BB2_nx285 # BB2_nx277 & !BB2_nx286 # !AB2_buffer_flush_n;


--BB2_nx1520 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx1520
--operation mode is normal

BB2_nx1520 = EB2_strobe_out & !BB2_buffer_full # !AB2_buffer_flush_n;


--BB2_nx277 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx277
--operation mode is normal

BB2_nx277 = EB2_strobe_out & !BB2_bitcounter_5 & !BB2_bitcounter_3 & !BB2_bitcounter_4;


--BB2_nx278 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx278
--operation mode is normal

BB2_nx278 = !BB2_b_crc_11 & !BB2_b_crc_10 & !BB2_b_crc_9 & !BB2_b_crc_8;


--BB2_nx279 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx279
--operation mode is normal

BB2_nx279 = !BB2_b_crc_7 & !BB2_b_crc_6 & !BB2_b_crc_5 & !BB2_b_crc_4;


--BB2_nx280 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx280
--operation mode is normal

BB2_nx280 = BB2_bitcounter_3 # BB2_bitcounter_2 & (BB2_bitcounter_1 # BB2_bitcounter_0);


--BB2_nx281 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx281
--operation mode is normal

BB2_nx281 = BB2_bitcounter_3 # BB2_bitcounter_1 # BB2_bitcounter_0 # BB2_bitcounter_2;


--BB2_nx282 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx282
--operation mode is normal

BB2_nx282 = !BB2_b_crc_15 & !BB2_b_crc_14 & !BB2_b_crc_13 & !BB2_b_crc_12;


--BB2_nx283 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx283
--operation mode is normal

BB2_nx283 = !BB2_b_crc_1 & !BB2_b_crc_0 & BB2_nx279 & BB2_nx284;


--BB2_nx284 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx284
--operation mode is normal

BB2_nx284 = !BB2_b_crc_3 & !BB2_b_crc_2;


--BB2_nx285 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx285
--operation mode is normal

BB2_nx285 = EB2_strobe_out & !BB2_bitcounter_6;


--BB2_nx286 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|nx286
--operation mode is normal

BB2_nx286 = BB2_bitcounter_2 & (BB2_bitcounter_1 # BB2_bitcounter_0);


--BB2_buffer_half is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|buffer_half
--operation mode is normal

BB2_buffer_half = BB2_bitcounter_6 & (BB2_bitcounter_5 # BB2_bitcounter_4 & BB2_nx281);


--BB2_buffer_full is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|buffer_full
--operation mode is normal

BB2_buffer_full = BB2_bitcounter_6 & (BB2_bitcounter_5 # BB2_bitcounter_4 & BB2_nx280);


--BB2_data_valid is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_valid
--operation mode is normal

BB2_data_valid = BB2_buffer_full & BB2_nx278 & BB2_nx282 & BB2_nx283;


--BB2_b_crc_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_0
--operation mode is normal

BB2_b_crc_0_lut_out = EB2_data_out $ BB2_b_crc_15;
BB2_b_crc_0_reg_input = AB2_buffer_flush_n & BB2_b_crc_0_lut_out;
BB2_b_crc_0 = DFFEA(BB2_b_crc_0_reg_input, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_1
--operation mode is normal

BB2_b_crc_1_lut_out = AB2_buffer_flush_n & BB2_b_crc_0;
BB2_b_crc_1 = DFFEA(BB2_b_crc_1_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_10
--operation mode is normal

BB2_b_crc_10_lut_out = AB2_buffer_flush_n & BB2_b_crc_9;
BB2_b_crc_10 = DFFEA(BB2_b_crc_10_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_11
--operation mode is normal

BB2_b_crc_11_lut_out = AB2_buffer_flush_n & BB2_b_crc_10;
BB2_b_crc_11 = DFFEA(BB2_b_crc_11_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_12
--operation mode is normal

BB2_b_crc_12_lut_out = AB2_buffer_flush_n & BB2_b_crc_11;
BB2_b_crc_12 = DFFEA(BB2_b_crc_12_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_13
--operation mode is normal

BB2_b_crc_13_lut_out = AB2_buffer_flush_n & BB2_b_crc_12;
BB2_b_crc_13 = DFFEA(BB2_b_crc_13_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_14
--operation mode is normal

BB2_b_crc_14_lut_out = AB2_buffer_flush_n & BB2_b_crc_13;
BB2_b_crc_14 = DFFEA(BB2_b_crc_14_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_15
--operation mode is normal

BB2_b_crc_15_lut_out = BB2_b_crc_15 $ BB2_b_crc_14;
BB2_b_crc_15_reg_input = AB2_buffer_flush_n & BB2_b_crc_15_lut_out;
BB2_b_crc_15 = DFFEA(BB2_b_crc_15_reg_input, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_2
--operation mode is normal

BB2_b_crc_2_lut_out = BB2_b_crc_15 $ BB2_b_crc_1;
BB2_b_crc_2_reg_input = AB2_buffer_flush_n & BB2_b_crc_2_lut_out;
BB2_b_crc_2 = DFFEA(BB2_b_crc_2_reg_input, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_3
--operation mode is normal

BB2_b_crc_3_lut_out = AB2_buffer_flush_n & BB2_b_crc_2;
BB2_b_crc_3 = DFFEA(BB2_b_crc_3_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_4
--operation mode is normal

BB2_b_crc_4_lut_out = AB2_buffer_flush_n & BB2_b_crc_3;
BB2_b_crc_4 = DFFEA(BB2_b_crc_4_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_5
--operation mode is normal

BB2_b_crc_5_lut_out = AB2_buffer_flush_n & BB2_b_crc_4;
BB2_b_crc_5 = DFFEA(BB2_b_crc_5_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_6
--operation mode is normal

BB2_b_crc_6_lut_out = AB2_buffer_flush_n & BB2_b_crc_5;
BB2_b_crc_6 = DFFEA(BB2_b_crc_6_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_7
--operation mode is normal

BB2_b_crc_7_lut_out = AB2_buffer_flush_n & BB2_b_crc_6;
BB2_b_crc_7 = DFFEA(BB2_b_crc_7_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_8
--operation mode is normal

BB2_b_crc_8_lut_out = AB2_buffer_flush_n & BB2_b_crc_7;
BB2_b_crc_8 = DFFEA(BB2_b_crc_8_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_b_crc_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|b_crc_9
--operation mode is normal

BB2_b_crc_9_lut_out = AB2_buffer_flush_n & BB2_b_crc_8;
BB2_b_crc_9 = DFFEA(BB2_b_crc_9_lut_out, U1__clk0, VCC, , BB2_nx1520, , );


--BB2_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_0
--operation mode is normal

BB2_data_out_0_lut_out = EB2_data_out;
BB2_data_out_0_reg_input = AB2_buffer_flush_n & BB2_data_out_0_lut_out;
BB2_data_out_0 = DFFEA(BB2_data_out_0_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_1
--operation mode is normal

BB2_data_out_1_lut_out = BB2_data_out_0;
BB2_data_out_1_reg_input = AB2_buffer_flush_n & BB2_data_out_1_lut_out;
BB2_data_out_1 = DFFEA(BB2_data_out_1_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_10
--operation mode is normal

BB2_data_out_10_lut_out = BB2_data_out_9;
BB2_data_out_10_reg_input = AB2_buffer_flush_n & BB2_data_out_10_lut_out;
BB2_data_out_10 = DFFEA(BB2_data_out_10_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_11
--operation mode is normal

BB2_data_out_11_lut_out = BB2_data_out_10;
BB2_data_out_11_reg_input = AB2_buffer_flush_n & BB2_data_out_11_lut_out;
BB2_data_out_11 = DFFEA(BB2_data_out_11_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_12
--operation mode is normal

BB2_data_out_12_lut_out = BB2_data_out_11;
BB2_data_out_12_reg_input = AB2_buffer_flush_n & BB2_data_out_12_lut_out;
BB2_data_out_12 = DFFEA(BB2_data_out_12_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_13
--operation mode is normal

BB2_data_out_13_lut_out = BB2_data_out_12;
BB2_data_out_13_reg_input = AB2_buffer_flush_n & BB2_data_out_13_lut_out;
BB2_data_out_13 = DFFEA(BB2_data_out_13_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_14
--operation mode is normal

BB2_data_out_14_lut_out = BB2_data_out_13;
BB2_data_out_14_reg_input = AB2_buffer_flush_n & BB2_data_out_14_lut_out;
BB2_data_out_14 = DFFEA(BB2_data_out_14_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_15
--operation mode is normal

BB2_data_out_15_lut_out = BB2_data_out_14;
BB2_data_out_15_reg_input = AB2_buffer_flush_n & BB2_data_out_15_lut_out;
BB2_data_out_15 = DFFEA(BB2_data_out_15_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_16 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_16
--operation mode is normal

BB2_data_out_16_lut_out = BB2_data_out_15;
BB2_data_out_16_reg_input = AB2_buffer_flush_n & BB2_data_out_16_lut_out;
BB2_data_out_16 = DFFEA(BB2_data_out_16_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_17 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_17
--operation mode is normal

BB2_data_out_17_lut_out = BB2_data_out_16;
BB2_data_out_17_reg_input = AB2_buffer_flush_n & BB2_data_out_17_lut_out;
BB2_data_out_17 = DFFEA(BB2_data_out_17_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_18
--operation mode is normal

BB2_data_out_18_lut_out = BB2_data_out_17;
BB2_data_out_18_reg_input = AB2_buffer_flush_n & BB2_data_out_18_lut_out;
BB2_data_out_18 = DFFEA(BB2_data_out_18_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_19 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_19
--operation mode is normal

BB2_data_out_19_lut_out = BB2_data_out_18;
BB2_data_out_19_reg_input = AB2_buffer_flush_n & BB2_data_out_19_lut_out;
BB2_data_out_19 = DFFEA(BB2_data_out_19_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_2
--operation mode is normal

BB2_data_out_2_lut_out = BB2_data_out_1;
BB2_data_out_2_reg_input = AB2_buffer_flush_n & BB2_data_out_2_lut_out;
BB2_data_out_2 = DFFEA(BB2_data_out_2_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_20
--operation mode is normal

BB2_data_out_20_lut_out = BB2_data_out_19;
BB2_data_out_20_reg_input = AB2_buffer_flush_n & BB2_data_out_20_lut_out;
BB2_data_out_20 = DFFEA(BB2_data_out_20_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_21
--operation mode is normal

BB2_data_out_21_lut_out = BB2_data_out_20;
BB2_data_out_21_reg_input = AB2_buffer_flush_n & BB2_data_out_21_lut_out;
BB2_data_out_21 = DFFEA(BB2_data_out_21_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_22 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_22
--operation mode is normal

BB2_data_out_22_lut_out = BB2_data_out_21;
BB2_data_out_22_reg_input = AB2_buffer_flush_n & BB2_data_out_22_lut_out;
BB2_data_out_22 = DFFEA(BB2_data_out_22_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_23 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_23
--operation mode is normal

BB2_data_out_23_lut_out = BB2_data_out_22;
BB2_data_out_23_reg_input = AB2_buffer_flush_n & BB2_data_out_23_lut_out;
BB2_data_out_23 = DFFEA(BB2_data_out_23_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_24
--operation mode is normal

BB2_data_out_24_lut_out = BB2_data_out_23;
BB2_data_out_24_reg_input = AB2_buffer_flush_n & BB2_data_out_24_lut_out;
BB2_data_out_24 = DFFEA(BB2_data_out_24_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_25 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_25
--operation mode is normal

BB2_data_out_25_lut_out = BB2_data_out_24;
BB2_data_out_25_reg_input = AB2_buffer_flush_n & BB2_data_out_25_lut_out;
BB2_data_out_25 = DFFEA(BB2_data_out_25_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_26
--operation mode is normal

BB2_data_out_26_lut_out = BB2_data_out_25;
BB2_data_out_26_reg_input = AB2_buffer_flush_n & BB2_data_out_26_lut_out;
BB2_data_out_26 = DFFEA(BB2_data_out_26_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_27
--operation mode is normal

BB2_data_out_27_lut_out = BB2_data_out_26;
BB2_data_out_27_reg_input = AB2_buffer_flush_n & BB2_data_out_27_lut_out;
BB2_data_out_27 = DFFEA(BB2_data_out_27_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_28
--operation mode is normal

BB2_data_out_28_lut_out = BB2_data_out_27;
BB2_data_out_28_reg_input = AB2_buffer_flush_n & BB2_data_out_28_lut_out;
BB2_data_out_28 = DFFEA(BB2_data_out_28_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_29
--operation mode is normal

BB2_data_out_29_lut_out = BB2_data_out_28;
BB2_data_out_29_reg_input = AB2_buffer_flush_n & BB2_data_out_29_lut_out;
BB2_data_out_29 = DFFEA(BB2_data_out_29_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_3
--operation mode is normal

BB2_data_out_3_lut_out = BB2_data_out_2;
BB2_data_out_3_reg_input = AB2_buffer_flush_n & BB2_data_out_3_lut_out;
BB2_data_out_3 = DFFEA(BB2_data_out_3_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_30
--operation mode is normal

BB2_data_out_30_lut_out = BB2_data_out_29;
BB2_data_out_30_reg_input = AB2_buffer_flush_n & BB2_data_out_30_lut_out;
BB2_data_out_30 = DFFEA(BB2_data_out_30_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_31 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_31
--operation mode is normal

BB2_data_out_31_lut_out = BB2_data_out_30;
BB2_data_out_31_reg_input = AB2_buffer_flush_n & BB2_data_out_31_lut_out;
BB2_data_out_31 = DFFEA(BB2_data_out_31_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_32
--operation mode is normal

BB2_data_out_32_lut_out = BB2_data_out_31;
BB2_data_out_32_reg_input = AB2_buffer_flush_n & BB2_data_out_32_lut_out;
BB2_data_out_32 = DFFEA(BB2_data_out_32_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_33
--operation mode is normal

BB2_data_out_33_lut_out = BB2_data_out_32;
BB2_data_out_33_reg_input = AB2_buffer_flush_n & BB2_data_out_33_lut_out;
BB2_data_out_33 = DFFEA(BB2_data_out_33_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_34 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_34
--operation mode is normal

BB2_data_out_34_lut_out = BB2_data_out_33;
BB2_data_out_34_reg_input = AB2_buffer_flush_n & BB2_data_out_34_lut_out;
BB2_data_out_34 = DFFEA(BB2_data_out_34_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_35 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_35
--operation mode is normal

BB2_data_out_35_lut_out = BB2_data_out_34;
BB2_data_out_35_reg_input = AB2_buffer_flush_n & BB2_data_out_35_lut_out;
BB2_data_out_35 = DFFEA(BB2_data_out_35_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_36
--operation mode is normal

BB2_data_out_36_lut_out = BB2_data_out_35;
BB2_data_out_36_reg_input = AB2_buffer_flush_n & BB2_data_out_36_lut_out;
BB2_data_out_36 = DFFEA(BB2_data_out_36_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_37
--operation mode is normal

BB2_data_out_37_lut_out = BB2_data_out_36;
BB2_data_out_37_reg_input = AB2_buffer_flush_n & BB2_data_out_37_lut_out;
BB2_data_out_37 = DFFEA(BB2_data_out_37_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_38 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_38
--operation mode is normal

BB2_data_out_38_lut_out = BB2_data_out_37;
BB2_data_out_38_reg_input = AB2_buffer_flush_n & BB2_data_out_38_lut_out;
BB2_data_out_38 = DFFEA(BB2_data_out_38_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_39 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_39
--operation mode is normal

BB2_data_out_39_lut_out = BB2_data_out_38;
BB2_data_out_39_reg_input = AB2_buffer_flush_n & BB2_data_out_39_lut_out;
BB2_data_out_39 = DFFEA(BB2_data_out_39_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_4
--operation mode is normal

BB2_data_out_4_lut_out = BB2_data_out_3;
BB2_data_out_4_reg_input = AB2_buffer_flush_n & BB2_data_out_4_lut_out;
BB2_data_out_4 = DFFEA(BB2_data_out_4_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_40 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_40
--operation mode is normal

BB2_data_out_40_lut_out = BB2_data_out_39;
BB2_data_out_40_reg_input = AB2_buffer_flush_n & BB2_data_out_40_lut_out;
BB2_data_out_40 = DFFEA(BB2_data_out_40_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_41 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_41
--operation mode is normal

BB2_data_out_41_lut_out = BB2_data_out_40;
BB2_data_out_41_reg_input = AB2_buffer_flush_n & BB2_data_out_41_lut_out;
BB2_data_out_41 = DFFEA(BB2_data_out_41_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_42 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_42
--operation mode is normal

BB2_data_out_42_lut_out = BB2_data_out_41;
BB2_data_out_42_reg_input = AB2_buffer_flush_n & BB2_data_out_42_lut_out;
BB2_data_out_42 = DFFEA(BB2_data_out_42_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_43 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_43
--operation mode is normal

BB2_data_out_43_lut_out = BB2_data_out_42;
BB2_data_out_43_reg_input = AB2_buffer_flush_n & BB2_data_out_43_lut_out;
BB2_data_out_43 = DFFEA(BB2_data_out_43_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_44 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_44
--operation mode is normal

BB2_data_out_44_lut_out = BB2_data_out_43;
BB2_data_out_44_reg_input = AB2_buffer_flush_n & BB2_data_out_44_lut_out;
BB2_data_out_44 = DFFEA(BB2_data_out_44_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_45 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_45
--operation mode is normal

BB2_data_out_45_lut_out = BB2_data_out_44;
BB2_data_out_45_reg_input = AB2_buffer_flush_n & BB2_data_out_45_lut_out;
BB2_data_out_45 = DFFEA(BB2_data_out_45_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_46 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_46
--operation mode is normal

BB2_data_out_46_lut_out = BB2_data_out_45;
BB2_data_out_46_reg_input = AB2_buffer_flush_n & BB2_data_out_46_lut_out;
BB2_data_out_46 = DFFEA(BB2_data_out_46_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_47 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_47
--operation mode is normal

BB2_data_out_47_lut_out = BB2_data_out_46;
BB2_data_out_47_reg_input = AB2_buffer_flush_n & BB2_data_out_47_lut_out;
BB2_data_out_47 = DFFEA(BB2_data_out_47_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_48 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_48
--operation mode is normal

BB2_data_out_48_lut_out = BB2_data_out_47;
BB2_data_out_48_reg_input = AB2_buffer_flush_n & BB2_data_out_48_lut_out;
BB2_data_out_48 = DFFEA(BB2_data_out_48_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_49 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_49
--operation mode is normal

BB2_data_out_49_lut_out = BB2_data_out_48;
BB2_data_out_49_reg_input = AB2_buffer_flush_n & BB2_data_out_49_lut_out;
BB2_data_out_49 = DFFEA(BB2_data_out_49_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_5
--operation mode is normal

BB2_data_out_5_lut_out = BB2_data_out_4;
BB2_data_out_5_reg_input = AB2_buffer_flush_n & BB2_data_out_5_lut_out;
BB2_data_out_5 = DFFEA(BB2_data_out_5_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_50 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_50
--operation mode is normal

BB2_data_out_50_lut_out = BB2_data_out_49;
BB2_data_out_50_reg_input = AB2_buffer_flush_n & BB2_data_out_50_lut_out;
BB2_data_out_50 = DFFEA(BB2_data_out_50_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_51 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_51
--operation mode is normal

BB2_data_out_51_lut_out = BB2_data_out_50;
BB2_data_out_51_reg_input = AB2_buffer_flush_n & BB2_data_out_51_lut_out;
BB2_data_out_51 = DFFEA(BB2_data_out_51_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_52 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_52
--operation mode is normal

BB2_data_out_52_lut_out = BB2_data_out_51;
BB2_data_out_52_reg_input = AB2_buffer_flush_n & BB2_data_out_52_lut_out;
BB2_data_out_52 = DFFEA(BB2_data_out_52_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_53 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_53
--operation mode is normal

BB2_data_out_53_lut_out = BB2_data_out_52;
BB2_data_out_53_reg_input = AB2_buffer_flush_n & BB2_data_out_53_lut_out;
BB2_data_out_53 = DFFEA(BB2_data_out_53_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_54 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_54
--operation mode is normal

BB2_data_out_54_lut_out = BB2_data_out_53;
BB2_data_out_54_reg_input = AB2_buffer_flush_n & BB2_data_out_54_lut_out;
BB2_data_out_54 = DFFEA(BB2_data_out_54_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_55 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_55
--operation mode is normal

BB2_data_out_55_lut_out = BB2_data_out_54;
BB2_data_out_55_reg_input = AB2_buffer_flush_n & BB2_data_out_55_lut_out;
BB2_data_out_55 = DFFEA(BB2_data_out_55_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_56 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_56
--operation mode is normal

BB2_data_out_56_lut_out = BB2_data_out_55;
BB2_data_out_56_reg_input = AB2_buffer_flush_n & BB2_data_out_56_lut_out;
BB2_data_out_56 = DFFEA(BB2_data_out_56_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_57 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_57
--operation mode is normal

BB2_data_out_57_lut_out = BB2_data_out_56;
BB2_data_out_57_reg_input = AB2_buffer_flush_n & BB2_data_out_57_lut_out;
BB2_data_out_57 = DFFEA(BB2_data_out_57_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_58 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_58
--operation mode is normal

BB2_data_out_58_lut_out = BB2_data_out_57;
BB2_data_out_58_reg_input = AB2_buffer_flush_n & BB2_data_out_58_lut_out;
BB2_data_out_58 = DFFEA(BB2_data_out_58_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_59 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_59
--operation mode is normal

BB2_data_out_59_lut_out = BB2_data_out_58;
BB2_data_out_59_reg_input = AB2_buffer_flush_n & BB2_data_out_59_lut_out;
BB2_data_out_59 = DFFEA(BB2_data_out_59_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_6
--operation mode is normal

BB2_data_out_6_lut_out = BB2_data_out_5;
BB2_data_out_6_reg_input = AB2_buffer_flush_n & BB2_data_out_6_lut_out;
BB2_data_out_6 = DFFEA(BB2_data_out_6_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_60
--operation mode is normal

BB2_data_out_60_lut_out = BB2_data_out_59;
BB2_data_out_60_reg_input = AB2_buffer_flush_n & BB2_data_out_60_lut_out;
BB2_data_out_60 = DFFEA(BB2_data_out_60_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_61 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_61
--operation mode is normal

BB2_data_out_61_lut_out = BB2_data_out_60;
BB2_data_out_61_reg_input = AB2_buffer_flush_n & BB2_data_out_61_lut_out;
BB2_data_out_61 = DFFEA(BB2_data_out_61_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_62 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_62
--operation mode is normal

BB2_data_out_62_lut_out = BB2_data_out_61;
BB2_data_out_62_reg_input = AB2_buffer_flush_n & BB2_data_out_62_lut_out;
BB2_data_out_62 = DFFEA(BB2_data_out_62_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_63
--operation mode is normal

BB2_data_out_63_lut_out = BB2_data_out_62;
BB2_data_out_63_reg_input = AB2_buffer_flush_n & BB2_data_out_63_lut_out;
BB2_data_out_63 = DFFEA(BB2_data_out_63_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_64
--operation mode is normal

BB2_data_out_64_lut_out = BB2_data_out_63;
BB2_data_out_64_reg_input = AB2_buffer_flush_n & BB2_data_out_64_lut_out;
BB2_data_out_64 = DFFEA(BB2_data_out_64_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_65 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_65
--operation mode is normal

BB2_data_out_65_lut_out = BB2_data_out_64;
BB2_data_out_65_reg_input = AB2_buffer_flush_n & BB2_data_out_65_lut_out;
BB2_data_out_65 = DFFEA(BB2_data_out_65_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_66 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_66
--operation mode is normal

BB2_data_out_66_lut_out = BB2_data_out_65;
BB2_data_out_66_reg_input = AB2_buffer_flush_n & BB2_data_out_66_lut_out;
BB2_data_out_66 = DFFEA(BB2_data_out_66_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_67 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_67
--operation mode is normal

BB2_data_out_67_lut_out = BB2_data_out_66;
BB2_data_out_67_reg_input = AB2_buffer_flush_n & BB2_data_out_67_lut_out;
BB2_data_out_67 = DFFEA(BB2_data_out_67_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_68 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_68
--operation mode is normal

BB2_data_out_68_lut_out = BB2_data_out_67;
BB2_data_out_68_reg_input = AB2_buffer_flush_n & BB2_data_out_68_lut_out;
BB2_data_out_68 = DFFEA(BB2_data_out_68_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_7
--operation mode is normal

BB2_data_out_7_lut_out = BB2_data_out_6;
BB2_data_out_7_reg_input = AB2_buffer_flush_n & BB2_data_out_7_lut_out;
BB2_data_out_7 = DFFEA(BB2_data_out_7_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_8
--operation mode is normal

BB2_data_out_8_lut_out = BB2_data_out_7;
BB2_data_out_8_reg_input = AB2_buffer_flush_n & BB2_data_out_8_lut_out;
BB2_data_out_8 = DFFEA(BB2_data_out_8_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB2_data_out_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib1|data_out_9
--operation mode is normal

BB2_data_out_9_lut_out = BB2_data_out_8;
BB2_data_out_9_reg_input = AB2_buffer_flush_n & BB2_data_out_9_lut_out;
BB2_data_out_9 = DFFEA(BB2_data_out_9_reg_input, U1__clk0, VCC, , BB2_NOT_nx676, , );


--BB1_bitcounter_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_5
--operation mode is arithmetic

BB1_bitcounter_5_carry_eqn = BB1_bitcounter_nx33;
BB1_bitcounter_5_lut_out = BB1_bitcounter_5 $ BB1_bitcounter_5_carry_eqn;
BB1_bitcounter_5_reg_input = AB1_buffer_flush_n & BB1_bitcounter_5_lut_out;
BB1_bitcounter_5 = DFFEA(BB1_bitcounter_5_reg_input, U1__clk0, VCC, , , , );

--BB1_bitcounter_nx37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx37
--operation mode is arithmetic

BB1_bitcounter_nx37 = CARRY(!BB1_bitcounter_nx33 # !BB1_bitcounter_5);


--BB1_bitcounter_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_4
--operation mode is arithmetic

BB1_bitcounter_4_carry_eqn = BB1_bitcounter_nx27;
BB1_bitcounter_4_lut_out = BB1_bitcounter_4 $ !BB1_bitcounter_4_carry_eqn;
BB1_bitcounter_4_reg_input = AB1_buffer_flush_n & BB1_bitcounter_4_lut_out;
BB1_bitcounter_4 = DFFEA(BB1_bitcounter_4_reg_input, U1__clk0, VCC, , , , );

--BB1_bitcounter_nx33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx33
--operation mode is arithmetic

BB1_bitcounter_nx33 = CARRY(BB1_bitcounter_4 & !BB1_bitcounter_nx27);


--BB1_bitcounter_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_3
--operation mode is arithmetic

BB1_bitcounter_3_carry_eqn = BB1_bitcounter_nx21;
BB1_bitcounter_3_lut_out = BB1_bitcounter_3 $ BB1_bitcounter_3_carry_eqn;
BB1_bitcounter_3_reg_input = AB1_buffer_flush_n & BB1_bitcounter_3_lut_out;
BB1_bitcounter_3 = DFFEA(BB1_bitcounter_3_reg_input, U1__clk0, VCC, , , , );

--BB1_bitcounter_nx27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx27
--operation mode is arithmetic

BB1_bitcounter_nx27 = CARRY(!BB1_bitcounter_nx21 # !BB1_bitcounter_3);


--BB1_bitcounter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_2
--operation mode is arithmetic

BB1_bitcounter_2_carry_eqn = BB1_bitcounter_nx15;
BB1_bitcounter_2_lut_out = BB1_bitcounter_2 $ !BB1_bitcounter_2_carry_eqn;
BB1_bitcounter_2_reg_input = AB1_buffer_flush_n & BB1_bitcounter_2_lut_out;
BB1_bitcounter_2 = DFFEA(BB1_bitcounter_2_reg_input, U1__clk0, VCC, , , , );

--BB1_bitcounter_nx21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx21
--operation mode is arithmetic

BB1_bitcounter_nx21 = CARRY(BB1_bitcounter_2 & !BB1_bitcounter_nx15);


--BB1_bitcounter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_1
--operation mode is arithmetic

BB1_bitcounter_1_carry_eqn = BB1_bitcounter_nx9;
BB1_bitcounter_1_lut_out = BB1_bitcounter_1 $ BB1_bitcounter_1_carry_eqn;
BB1_bitcounter_1_reg_input = AB1_buffer_flush_n & BB1_bitcounter_1_lut_out;
BB1_bitcounter_1 = DFFEA(BB1_bitcounter_1_reg_input, U1__clk0, VCC, , , , );

--BB1_bitcounter_nx15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx15
--operation mode is arithmetic

BB1_bitcounter_nx15 = CARRY(!BB1_bitcounter_nx9 # !BB1_bitcounter_1);


--BB1_bitcounter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_0
--operation mode is arithmetic

BB1_bitcounter_0_lut_out = BB1_bitcounter_0 $ EB1_strobe_out;
BB1_bitcounter_0_reg_input = AB1_buffer_flush_n & BB1_bitcounter_0_lut_out;
BB1_bitcounter_0 = DFFEA(BB1_bitcounter_0_reg_input, U1__clk0, VCC, , , , );

--BB1_bitcounter_nx9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_nx9
--operation mode is arithmetic

BB1_bitcounter_nx9 = CARRY(BB1_bitcounter_0 & EB1_strobe_out);


--BB1_bitcounter_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|bitcounter_6
--operation mode is normal

BB1_bitcounter_6_carry_eqn = BB1_bitcounter_nx37;
BB1_bitcounter_6_lut_out = BB1_bitcounter_6 $ !BB1_bitcounter_6_carry_eqn;
BB1_bitcounter_6_reg_input = AB1_buffer_flush_n & BB1_bitcounter_6_lut_out;
BB1_bitcounter_6 = DFFEA(BB1_bitcounter_6_reg_input, U1__clk0, VCC, , , , );


--BB1_NOT_nx676 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|NOT_nx676
--operation mode is normal

BB1_NOT_nx676 = BB1_nx285 # BB1_nx277 & !BB1_nx286 # !AB1_buffer_flush_n;


--BB1_nx1520 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx1520
--operation mode is normal

BB1_nx1520 = EB1_strobe_out & !BB1_buffer_full # !AB1_buffer_flush_n;


--BB1_nx277 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx277
--operation mode is normal

BB1_nx277 = EB1_strobe_out & !BB1_bitcounter_5 & !BB1_bitcounter_3 & !BB1_bitcounter_4;


--BB1_nx278 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx278
--operation mode is normal

BB1_nx278 = !BB1_b_crc_11 & !BB1_b_crc_10 & !BB1_b_crc_9 & !BB1_b_crc_8;


--BB1_nx279 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx279
--operation mode is normal

BB1_nx279 = !BB1_b_crc_7 & !BB1_b_crc_6 & !BB1_b_crc_5 & !BB1_b_crc_4;


--BB1_nx280 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx280
--operation mode is normal

BB1_nx280 = BB1_bitcounter_3 # BB1_bitcounter_2 & (BB1_bitcounter_1 # BB1_bitcounter_0);


--BB1_nx281 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx281
--operation mode is normal

BB1_nx281 = BB1_bitcounter_3 # BB1_bitcounter_1 # BB1_bitcounter_0 # BB1_bitcounter_2;


--BB1_nx282 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx282
--operation mode is normal

BB1_nx282 = !BB1_b_crc_15 & !BB1_b_crc_14 & !BB1_b_crc_13 & !BB1_b_crc_12;


--BB1_nx283 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx283
--operation mode is normal

BB1_nx283 = !BB1_b_crc_1 & !BB1_b_crc_0 & BB1_nx279 & BB1_nx284;


--BB1_nx284 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx284
--operation mode is normal

BB1_nx284 = !BB1_b_crc_3 & !BB1_b_crc_2;


--BB1_nx285 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx285
--operation mode is normal

BB1_nx285 = EB1_strobe_out & !BB1_bitcounter_6;


--BB1_nx286 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|nx286
--operation mode is normal

BB1_nx286 = BB1_bitcounter_2 & (BB1_bitcounter_1 # BB1_bitcounter_0);


--BB1_buffer_half is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|buffer_half
--operation mode is normal

BB1_buffer_half = BB1_bitcounter_6 & (BB1_bitcounter_5 # BB1_bitcounter_4 & BB1_nx281);


--BB1_buffer_full is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|buffer_full
--operation mode is normal

BB1_buffer_full = BB1_bitcounter_6 & (BB1_bitcounter_5 # BB1_bitcounter_4 & BB1_nx280);


--BB1_data_valid is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_valid
--operation mode is normal

BB1_data_valid = BB1_buffer_full & BB1_nx278 & BB1_nx282 & BB1_nx283;


--BB1_b_crc_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_0
--operation mode is normal

BB1_b_crc_0_lut_out = EB1_data_out $ BB1_b_crc_15;
BB1_b_crc_0_reg_input = AB1_buffer_flush_n & BB1_b_crc_0_lut_out;
BB1_b_crc_0 = DFFEA(BB1_b_crc_0_reg_input, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_1
--operation mode is normal

BB1_b_crc_1_lut_out = AB1_buffer_flush_n & BB1_b_crc_0;
BB1_b_crc_1 = DFFEA(BB1_b_crc_1_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_10
--operation mode is normal

BB1_b_crc_10_lut_out = AB1_buffer_flush_n & BB1_b_crc_9;
BB1_b_crc_10 = DFFEA(BB1_b_crc_10_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_11
--operation mode is normal

BB1_b_crc_11_lut_out = AB1_buffer_flush_n & BB1_b_crc_10;
BB1_b_crc_11 = DFFEA(BB1_b_crc_11_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_12
--operation mode is normal

BB1_b_crc_12_lut_out = AB1_buffer_flush_n & BB1_b_crc_11;
BB1_b_crc_12 = DFFEA(BB1_b_crc_12_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_13
--operation mode is normal

BB1_b_crc_13_lut_out = AB1_buffer_flush_n & BB1_b_crc_12;
BB1_b_crc_13 = DFFEA(BB1_b_crc_13_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_14
--operation mode is normal

BB1_b_crc_14_lut_out = AB1_buffer_flush_n & BB1_b_crc_13;
BB1_b_crc_14 = DFFEA(BB1_b_crc_14_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_15
--operation mode is normal

BB1_b_crc_15_lut_out = BB1_b_crc_15 $ BB1_b_crc_14;
BB1_b_crc_15_reg_input = AB1_buffer_flush_n & BB1_b_crc_15_lut_out;
BB1_b_crc_15 = DFFEA(BB1_b_crc_15_reg_input, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_2
--operation mode is normal

BB1_b_crc_2_lut_out = BB1_b_crc_15 $ BB1_b_crc_1;
BB1_b_crc_2_reg_input = AB1_buffer_flush_n & BB1_b_crc_2_lut_out;
BB1_b_crc_2 = DFFEA(BB1_b_crc_2_reg_input, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_3
--operation mode is normal

BB1_b_crc_3_lut_out = AB1_buffer_flush_n & BB1_b_crc_2;
BB1_b_crc_3 = DFFEA(BB1_b_crc_3_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_4
--operation mode is normal

BB1_b_crc_4_lut_out = AB1_buffer_flush_n & BB1_b_crc_3;
BB1_b_crc_4 = DFFEA(BB1_b_crc_4_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_5
--operation mode is normal

BB1_b_crc_5_lut_out = AB1_buffer_flush_n & BB1_b_crc_4;
BB1_b_crc_5 = DFFEA(BB1_b_crc_5_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_6
--operation mode is normal

BB1_b_crc_6_lut_out = AB1_buffer_flush_n & BB1_b_crc_5;
BB1_b_crc_6 = DFFEA(BB1_b_crc_6_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_7
--operation mode is normal

BB1_b_crc_7_lut_out = AB1_buffer_flush_n & BB1_b_crc_6;
BB1_b_crc_7 = DFFEA(BB1_b_crc_7_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_8
--operation mode is normal

BB1_b_crc_8_lut_out = AB1_buffer_flush_n & BB1_b_crc_7;
BB1_b_crc_8 = DFFEA(BB1_b_crc_8_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_b_crc_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|b_crc_9
--operation mode is normal

BB1_b_crc_9_lut_out = AB1_buffer_flush_n & BB1_b_crc_8;
BB1_b_crc_9 = DFFEA(BB1_b_crc_9_lut_out, U1__clk0, VCC, , BB1_nx1520, , );


--BB1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_0
--operation mode is normal

BB1_data_out_0_lut_out = EB1_data_out;
BB1_data_out_0_reg_input = AB1_buffer_flush_n & BB1_data_out_0_lut_out;
BB1_data_out_0 = DFFEA(BB1_data_out_0_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_1
--operation mode is normal

BB1_data_out_1_lut_out = BB1_data_out_0;
BB1_data_out_1_reg_input = AB1_buffer_flush_n & BB1_data_out_1_lut_out;
BB1_data_out_1 = DFFEA(BB1_data_out_1_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_10
--operation mode is normal

BB1_data_out_10_lut_out = BB1_data_out_9;
BB1_data_out_10_reg_input = AB1_buffer_flush_n & BB1_data_out_10_lut_out;
BB1_data_out_10 = DFFEA(BB1_data_out_10_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_11 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_11
--operation mode is normal

BB1_data_out_11_lut_out = BB1_data_out_10;
BB1_data_out_11_reg_input = AB1_buffer_flush_n & BB1_data_out_11_lut_out;
BB1_data_out_11 = DFFEA(BB1_data_out_11_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_12
--operation mode is normal

BB1_data_out_12_lut_out = BB1_data_out_11;
BB1_data_out_12_reg_input = AB1_buffer_flush_n & BB1_data_out_12_lut_out;
BB1_data_out_12 = DFFEA(BB1_data_out_12_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_13 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_13
--operation mode is normal

BB1_data_out_13_lut_out = BB1_data_out_12;
BB1_data_out_13_reg_input = AB1_buffer_flush_n & BB1_data_out_13_lut_out;
BB1_data_out_13 = DFFEA(BB1_data_out_13_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_14
--operation mode is normal

BB1_data_out_14_lut_out = BB1_data_out_13;
BB1_data_out_14_reg_input = AB1_buffer_flush_n & BB1_data_out_14_lut_out;
BB1_data_out_14 = DFFEA(BB1_data_out_14_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_15 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_15
--operation mode is normal

BB1_data_out_15_lut_out = BB1_data_out_14;
BB1_data_out_15_reg_input = AB1_buffer_flush_n & BB1_data_out_15_lut_out;
BB1_data_out_15 = DFFEA(BB1_data_out_15_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_16 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_16
--operation mode is normal

BB1_data_out_16_lut_out = BB1_data_out_15;
BB1_data_out_16_reg_input = AB1_buffer_flush_n & BB1_data_out_16_lut_out;
BB1_data_out_16 = DFFEA(BB1_data_out_16_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_17 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_17
--operation mode is normal

BB1_data_out_17_lut_out = BB1_data_out_16;
BB1_data_out_17_reg_input = AB1_buffer_flush_n & BB1_data_out_17_lut_out;
BB1_data_out_17 = DFFEA(BB1_data_out_17_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_18
--operation mode is normal

BB1_data_out_18_lut_out = BB1_data_out_17;
BB1_data_out_18_reg_input = AB1_buffer_flush_n & BB1_data_out_18_lut_out;
BB1_data_out_18 = DFFEA(BB1_data_out_18_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_19 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_19
--operation mode is normal

BB1_data_out_19_lut_out = BB1_data_out_18;
BB1_data_out_19_reg_input = AB1_buffer_flush_n & BB1_data_out_19_lut_out;
BB1_data_out_19 = DFFEA(BB1_data_out_19_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_2
--operation mode is normal

BB1_data_out_2_lut_out = BB1_data_out_1;
BB1_data_out_2_reg_input = AB1_buffer_flush_n & BB1_data_out_2_lut_out;
BB1_data_out_2 = DFFEA(BB1_data_out_2_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_20 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_20
--operation mode is normal

BB1_data_out_20_lut_out = BB1_data_out_19;
BB1_data_out_20_reg_input = AB1_buffer_flush_n & BB1_data_out_20_lut_out;
BB1_data_out_20 = DFFEA(BB1_data_out_20_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_21 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_21
--operation mode is normal

BB1_data_out_21_lut_out = BB1_data_out_20;
BB1_data_out_21_reg_input = AB1_buffer_flush_n & BB1_data_out_21_lut_out;
BB1_data_out_21 = DFFEA(BB1_data_out_21_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_22 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_22
--operation mode is normal

BB1_data_out_22_lut_out = BB1_data_out_21;
BB1_data_out_22_reg_input = AB1_buffer_flush_n & BB1_data_out_22_lut_out;
BB1_data_out_22 = DFFEA(BB1_data_out_22_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_23 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_23
--operation mode is normal

BB1_data_out_23_lut_out = BB1_data_out_22;
BB1_data_out_23_reg_input = AB1_buffer_flush_n & BB1_data_out_23_lut_out;
BB1_data_out_23 = DFFEA(BB1_data_out_23_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_24 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_24
--operation mode is normal

BB1_data_out_24_lut_out = BB1_data_out_23;
BB1_data_out_24_reg_input = AB1_buffer_flush_n & BB1_data_out_24_lut_out;
BB1_data_out_24 = DFFEA(BB1_data_out_24_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_25 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_25
--operation mode is normal

BB1_data_out_25_lut_out = BB1_data_out_24;
BB1_data_out_25_reg_input = AB1_buffer_flush_n & BB1_data_out_25_lut_out;
BB1_data_out_25 = DFFEA(BB1_data_out_25_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_26 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_26
--operation mode is normal

BB1_data_out_26_lut_out = BB1_data_out_25;
BB1_data_out_26_reg_input = AB1_buffer_flush_n & BB1_data_out_26_lut_out;
BB1_data_out_26 = DFFEA(BB1_data_out_26_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_27 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_27
--operation mode is normal

BB1_data_out_27_lut_out = BB1_data_out_26;
BB1_data_out_27_reg_input = AB1_buffer_flush_n & BB1_data_out_27_lut_out;
BB1_data_out_27 = DFFEA(BB1_data_out_27_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_28 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_28
--operation mode is normal

BB1_data_out_28_lut_out = BB1_data_out_27;
BB1_data_out_28_reg_input = AB1_buffer_flush_n & BB1_data_out_28_lut_out;
BB1_data_out_28 = DFFEA(BB1_data_out_28_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_29 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_29
--operation mode is normal

BB1_data_out_29_lut_out = BB1_data_out_28;
BB1_data_out_29_reg_input = AB1_buffer_flush_n & BB1_data_out_29_lut_out;
BB1_data_out_29 = DFFEA(BB1_data_out_29_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_3
--operation mode is normal

BB1_data_out_3_lut_out = BB1_data_out_2;
BB1_data_out_3_reg_input = AB1_buffer_flush_n & BB1_data_out_3_lut_out;
BB1_data_out_3 = DFFEA(BB1_data_out_3_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_30 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_30
--operation mode is normal

BB1_data_out_30_lut_out = BB1_data_out_29;
BB1_data_out_30_reg_input = AB1_buffer_flush_n & BB1_data_out_30_lut_out;
BB1_data_out_30 = DFFEA(BB1_data_out_30_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_31 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_31
--operation mode is normal

BB1_data_out_31_lut_out = BB1_data_out_30;
BB1_data_out_31_reg_input = AB1_buffer_flush_n & BB1_data_out_31_lut_out;
BB1_data_out_31 = DFFEA(BB1_data_out_31_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_32 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_32
--operation mode is normal

BB1_data_out_32_lut_out = BB1_data_out_31;
BB1_data_out_32_reg_input = AB1_buffer_flush_n & BB1_data_out_32_lut_out;
BB1_data_out_32 = DFFEA(BB1_data_out_32_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_33 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_33
--operation mode is normal

BB1_data_out_33_lut_out = BB1_data_out_32;
BB1_data_out_33_reg_input = AB1_buffer_flush_n & BB1_data_out_33_lut_out;
BB1_data_out_33 = DFFEA(BB1_data_out_33_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_34 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_34
--operation mode is normal

BB1_data_out_34_lut_out = BB1_data_out_33;
BB1_data_out_34_reg_input = AB1_buffer_flush_n & BB1_data_out_34_lut_out;
BB1_data_out_34 = DFFEA(BB1_data_out_34_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_35 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_35
--operation mode is normal

BB1_data_out_35_lut_out = BB1_data_out_34;
BB1_data_out_35_reg_input = AB1_buffer_flush_n & BB1_data_out_35_lut_out;
BB1_data_out_35 = DFFEA(BB1_data_out_35_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_36 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_36
--operation mode is normal

BB1_data_out_36_lut_out = BB1_data_out_35;
BB1_data_out_36_reg_input = AB1_buffer_flush_n & BB1_data_out_36_lut_out;
BB1_data_out_36 = DFFEA(BB1_data_out_36_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_37 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_37
--operation mode is normal

BB1_data_out_37_lut_out = BB1_data_out_36;
BB1_data_out_37_reg_input = AB1_buffer_flush_n & BB1_data_out_37_lut_out;
BB1_data_out_37 = DFFEA(BB1_data_out_37_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_38 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_38
--operation mode is normal

BB1_data_out_38_lut_out = BB1_data_out_37;
BB1_data_out_38_reg_input = AB1_buffer_flush_n & BB1_data_out_38_lut_out;
BB1_data_out_38 = DFFEA(BB1_data_out_38_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_39 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_39
--operation mode is normal

BB1_data_out_39_lut_out = BB1_data_out_38;
BB1_data_out_39_reg_input = AB1_buffer_flush_n & BB1_data_out_39_lut_out;
BB1_data_out_39 = DFFEA(BB1_data_out_39_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_4 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_4
--operation mode is normal

BB1_data_out_4_lut_out = BB1_data_out_3;
BB1_data_out_4_reg_input = AB1_buffer_flush_n & BB1_data_out_4_lut_out;
BB1_data_out_4 = DFFEA(BB1_data_out_4_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_40 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_40
--operation mode is normal

BB1_data_out_40_lut_out = BB1_data_out_39;
BB1_data_out_40_reg_input = AB1_buffer_flush_n & BB1_data_out_40_lut_out;
BB1_data_out_40 = DFFEA(BB1_data_out_40_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_41 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_41
--operation mode is normal

BB1_data_out_41_lut_out = BB1_data_out_40;
BB1_data_out_41_reg_input = AB1_buffer_flush_n & BB1_data_out_41_lut_out;
BB1_data_out_41 = DFFEA(BB1_data_out_41_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_42 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_42
--operation mode is normal

BB1_data_out_42_lut_out = BB1_data_out_41;
BB1_data_out_42_reg_input = AB1_buffer_flush_n & BB1_data_out_42_lut_out;
BB1_data_out_42 = DFFEA(BB1_data_out_42_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_43 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_43
--operation mode is normal

BB1_data_out_43_lut_out = BB1_data_out_42;
BB1_data_out_43_reg_input = AB1_buffer_flush_n & BB1_data_out_43_lut_out;
BB1_data_out_43 = DFFEA(BB1_data_out_43_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_44 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_44
--operation mode is normal

BB1_data_out_44_lut_out = BB1_data_out_43;
BB1_data_out_44_reg_input = AB1_buffer_flush_n & BB1_data_out_44_lut_out;
BB1_data_out_44 = DFFEA(BB1_data_out_44_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_45 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_45
--operation mode is normal

BB1_data_out_45_lut_out = BB1_data_out_44;
BB1_data_out_45_reg_input = AB1_buffer_flush_n & BB1_data_out_45_lut_out;
BB1_data_out_45 = DFFEA(BB1_data_out_45_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_46 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_46
--operation mode is normal

BB1_data_out_46_lut_out = BB1_data_out_45;
BB1_data_out_46_reg_input = AB1_buffer_flush_n & BB1_data_out_46_lut_out;
BB1_data_out_46 = DFFEA(BB1_data_out_46_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_47 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_47
--operation mode is normal

BB1_data_out_47_lut_out = BB1_data_out_46;
BB1_data_out_47_reg_input = AB1_buffer_flush_n & BB1_data_out_47_lut_out;
BB1_data_out_47 = DFFEA(BB1_data_out_47_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_48 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_48
--operation mode is normal

BB1_data_out_48_lut_out = BB1_data_out_47;
BB1_data_out_48_reg_input = AB1_buffer_flush_n & BB1_data_out_48_lut_out;
BB1_data_out_48 = DFFEA(BB1_data_out_48_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_49 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_49
--operation mode is normal

BB1_data_out_49_lut_out = BB1_data_out_48;
BB1_data_out_49_reg_input = AB1_buffer_flush_n & BB1_data_out_49_lut_out;
BB1_data_out_49 = DFFEA(BB1_data_out_49_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_5 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_5
--operation mode is normal

BB1_data_out_5_lut_out = BB1_data_out_4;
BB1_data_out_5_reg_input = AB1_buffer_flush_n & BB1_data_out_5_lut_out;
BB1_data_out_5 = DFFEA(BB1_data_out_5_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_50 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_50
--operation mode is normal

BB1_data_out_50_lut_out = BB1_data_out_49;
BB1_data_out_50_reg_input = AB1_buffer_flush_n & BB1_data_out_50_lut_out;
BB1_data_out_50 = DFFEA(BB1_data_out_50_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_51 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_51
--operation mode is normal

BB1_data_out_51_lut_out = BB1_data_out_50;
BB1_data_out_51_reg_input = AB1_buffer_flush_n & BB1_data_out_51_lut_out;
BB1_data_out_51 = DFFEA(BB1_data_out_51_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_52 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_52
--operation mode is normal

BB1_data_out_52_lut_out = BB1_data_out_51;
BB1_data_out_52_reg_input = AB1_buffer_flush_n & BB1_data_out_52_lut_out;
BB1_data_out_52 = DFFEA(BB1_data_out_52_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_53 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_53
--operation mode is normal

BB1_data_out_53_lut_out = BB1_data_out_52;
BB1_data_out_53_reg_input = AB1_buffer_flush_n & BB1_data_out_53_lut_out;
BB1_data_out_53 = DFFEA(BB1_data_out_53_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_54 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_54
--operation mode is normal

BB1_data_out_54_lut_out = BB1_data_out_53;
BB1_data_out_54_reg_input = AB1_buffer_flush_n & BB1_data_out_54_lut_out;
BB1_data_out_54 = DFFEA(BB1_data_out_54_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_55 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_55
--operation mode is normal

BB1_data_out_55_lut_out = BB1_data_out_54;
BB1_data_out_55_reg_input = AB1_buffer_flush_n & BB1_data_out_55_lut_out;
BB1_data_out_55 = DFFEA(BB1_data_out_55_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_56 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_56
--operation mode is normal

BB1_data_out_56_lut_out = BB1_data_out_55;
BB1_data_out_56_reg_input = AB1_buffer_flush_n & BB1_data_out_56_lut_out;
BB1_data_out_56 = DFFEA(BB1_data_out_56_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_57 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_57
--operation mode is normal

BB1_data_out_57_lut_out = BB1_data_out_56;
BB1_data_out_57_reg_input = AB1_buffer_flush_n & BB1_data_out_57_lut_out;
BB1_data_out_57 = DFFEA(BB1_data_out_57_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_58 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_58
--operation mode is normal

BB1_data_out_58_lut_out = BB1_data_out_57;
BB1_data_out_58_reg_input = AB1_buffer_flush_n & BB1_data_out_58_lut_out;
BB1_data_out_58 = DFFEA(BB1_data_out_58_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_59 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_59
--operation mode is normal

BB1_data_out_59_lut_out = BB1_data_out_58;
BB1_data_out_59_reg_input = AB1_buffer_flush_n & BB1_data_out_59_lut_out;
BB1_data_out_59 = DFFEA(BB1_data_out_59_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_6
--operation mode is normal

BB1_data_out_6_lut_out = BB1_data_out_5;
BB1_data_out_6_reg_input = AB1_buffer_flush_n & BB1_data_out_6_lut_out;
BB1_data_out_6 = DFFEA(BB1_data_out_6_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_60 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_60
--operation mode is normal

BB1_data_out_60_lut_out = BB1_data_out_59;
BB1_data_out_60_reg_input = AB1_buffer_flush_n & BB1_data_out_60_lut_out;
BB1_data_out_60 = DFFEA(BB1_data_out_60_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_61 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_61
--operation mode is normal

BB1_data_out_61_lut_out = BB1_data_out_60;
BB1_data_out_61_reg_input = AB1_buffer_flush_n & BB1_data_out_61_lut_out;
BB1_data_out_61 = DFFEA(BB1_data_out_61_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_62 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_62
--operation mode is normal

BB1_data_out_62_lut_out = BB1_data_out_61;
BB1_data_out_62_reg_input = AB1_buffer_flush_n & BB1_data_out_62_lut_out;
BB1_data_out_62 = DFFEA(BB1_data_out_62_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_63 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_63
--operation mode is normal

BB1_data_out_63_lut_out = BB1_data_out_62;
BB1_data_out_63_reg_input = AB1_buffer_flush_n & BB1_data_out_63_lut_out;
BB1_data_out_63 = DFFEA(BB1_data_out_63_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_64
--operation mode is normal

BB1_data_out_64_lut_out = BB1_data_out_63;
BB1_data_out_64_reg_input = AB1_buffer_flush_n & BB1_data_out_64_lut_out;
BB1_data_out_64 = DFFEA(BB1_data_out_64_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_65 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_65
--operation mode is normal

BB1_data_out_65_lut_out = BB1_data_out_64;
BB1_data_out_65_reg_input = AB1_buffer_flush_n & BB1_data_out_65_lut_out;
BB1_data_out_65 = DFFEA(BB1_data_out_65_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_66 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_66
--operation mode is normal

BB1_data_out_66_lut_out = BB1_data_out_65;
BB1_data_out_66_reg_input = AB1_buffer_flush_n & BB1_data_out_66_lut_out;
BB1_data_out_66 = DFFEA(BB1_data_out_66_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_67 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_67
--operation mode is normal

BB1_data_out_67_lut_out = BB1_data_out_66;
BB1_data_out_67_reg_input = AB1_buffer_flush_n & BB1_data_out_67_lut_out;
BB1_data_out_67 = DFFEA(BB1_data_out_67_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_68 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_68
--operation mode is normal

BB1_data_out_68_lut_out = BB1_data_out_67;
BB1_data_out_68_reg_input = AB1_buffer_flush_n & BB1_data_out_68_lut_out;
BB1_data_out_68 = DFFEA(BB1_data_out_68_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_7 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_7
--operation mode is normal

BB1_data_out_7_lut_out = BB1_data_out_6;
BB1_data_out_7_reg_input = AB1_buffer_flush_n & BB1_data_out_7_lut_out;
BB1_data_out_7 = DFFEA(BB1_data_out_7_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_8 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_8
--operation mode is normal

BB1_data_out_8_lut_out = BB1_data_out_7;
BB1_data_out_8_reg_input = AB1_buffer_flush_n & BB1_data_out_8_lut_out;
BB1_data_out_8 = DFFEA(BB1_data_out_8_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--BB1_data_out_9 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_inbuf_69_4_7:ib0|data_out_9
--operation mode is normal

BB1_data_out_9_lut_out = BB1_data_out_8;
BB1_data_out_9_reg_input = AB1_buffer_flush_n & BB1_data_out_9_lut_out;
BB1_data_out_9 = DFFEA(BB1_data_out_9_reg_input, U1__clk0, VCC, , BB1_NOT_nx676, , );


--AB2_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|next_state_2
--operation mode is normal

AB2_next_state_2 = AB2_nx92 # AB2_nx93 # AB2_nx107 # AB2_nx108;


--AB2_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|next_state_1
--operation mode is normal

AB2_next_state_1 = AB2_nx94 # AB2_nx95 # AB2_nx97 # AB2_nx106;


--AB2_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|next_state_0
--operation mode is normal

AB2_next_state_0 = AB2_nx99 # AB2_nx100 # AB2_nx104 # AB2_nx105;


--AB2_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|next_state_3
--operation mode is normal

AB2_next_state_3 = !AB2_nx83 & AB2_nx89 & AB2_nx109 & AB2_nx110;


--AB2_NOT_nx210 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|NOT_nx210
--operation mode is normal

AB2_NOT_nx210 = AB2_nx87 # AB2_nx101 # AB2_nx85 & AB2_nx103;


--AB2_time_in_hotreset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|time_in_hotreset_n
--operation mode is normal

AB2_time_in_hotreset_n = FB2_data_out_3 # FB2_data_out_2 & (FB2_data_out_0 # !FB2_data_out_1) # !FB2_data_out_2 & (FB2_data_out_1 # !FB2_data_out_0);


--AB2_time_in_enable is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|time_in_enable
--operation mode is normal

AB2_time_in_enable = FB2_data_out_3 & !FB2_data_out_2 & !FB2_data_out_1 & !FB2_data_out_0 # !FB2_data_out_3 & (FB2_data_out_1 # FB2_data_out_2 & FB2_data_out_0);


--AB2_s_to_ds is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|s_to_ds
--operation mode is normal

AB2_s_to_ds = !FB2_data_out_1 & (FB2_data_out_3 & !FB2_data_out_2 & !FB2_data_out_0 # !FB2_data_out_3 & FB2_data_out_2 & FB2_data_out_0);


--AB2_time_in_reset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|time_in_reset_n
--operation mode is normal

AB2_time_in_reset_n = FB2_data_out_3 # FB2_data_out_2 # FB2_data_out_1 # FB2_data_out_0;


--AB2_nx80 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx80
--operation mode is normal

AB2_nx80 = BB2_buffer_full # EB2_stuff_err;


--AB2_nx81 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx81
--operation mode is normal

AB2_nx81 = AB2_sync_counter_2 # AB2_sync_counter_1;


--AB2_nx82 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx82
--operation mode is normal

AB2_nx82 = !FB2_data_out_3 & FB2_data_out_2;


--AB2_nx83 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx83
--operation mode is normal

AB2_nx83 = AB2_sync_counter_0 # Y1_d1_to_dll $ !AB2_d_buff;


--AB2_nx84 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx84
--operation mode is normal

AB2_nx84 = !FB2_data_out_3 & FB2_data_out_1;


--AB2_nx85 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx85
--operation mode is normal

AB2_nx85 = !FB2_data_out_3 & FB2_data_out_2 & !FB2_data_out_1;


--AB2_nx86 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx86
--operation mode is normal

AB2_nx86 = FB2_data_out_2 # FB2_data_out_1 & FB2_data_out_0;


--AB2_nx87 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx87
--operation mode is normal

AB2_nx87 = !FB2_data_out_2 & !FB2_data_out_1 & !FB2_data_out_0;


--AB2_nx88 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx88
--operation mode is normal

AB2_nx88 = !BB2_buffer_full & !EB2_stuff_err # !FB2_data_out_0;


--AB2_nx89 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx89
--operation mode is normal

AB2_nx89 = !FB2_data_out_3 & FB2_data_out_1 & !GB2_event_async;


--AB2_time_in_twofwd_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|time_in_twofwd_n
--operation mode is normal

AB2_time_in_twofwd_n = FB2_data_out_2 # FB2_data_out_1 # FB2_data_out_0 # !FB2_data_out_3;


--AB2_nx90 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx90
--operation mode is normal

AB2_nx90 = FB2_data_out_3 # FB2_data_out_2;


--AB2_nx91 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx91
--operation mode is normal

AB2_nx91 = !FB2_data_out_3 & FB2_data_out_2 & FB2_data_out_1 & !GB2_event_async;


--AB2_nx92 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx92
--operation mode is normal

AB2_nx92 = FB2_data_out_0 & !AB2_nx81 & !AB2_nx83 & AB2_nx85;


--AB2_nx93 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx93
--operation mode is normal

AB2_nx93 = GB2_event_async & AB2_nx84 & (!FB2_data_out_0 # !FB2_data_out_2);


--AB2_nx94 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx94
--operation mode is normal

AB2_nx94 = Y1_d1_to_dll & !FB2_data_out_1 & FB2_data_out_0 & !AB2_nx90;


--AB2_nx95 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx95
--operation mode is normal

AB2_nx95 = !FB2_data_out_2 & AB2_nx84 & !AB2_nx88 # !AB2_time_in_twofwd_n;


--AB2_nx96 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx96
--operation mode is normal

AB2_nx96 = AB2_nx83 & (AB2_nx85 # AB2_nx89) # !AB2_nx83 & !FB2_data_out_0 & AB2_nx89;


--AB2_nx97 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx97
--operation mode is normal

AB2_nx97 = AB2_nx81 & (AB2_nx85 # AB2_nx89) # !AB2_nx81 & AB2_nx80 & AB2_nx85;


--AB2_nx98 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx98
--operation mode is normal

AB2_nx98 = !Y1_d1_to_dll & !FB2_data_out_2 & !FB2_data_out_1 & FB2_data_out_0;


--AB2_nx99 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx99
--operation mode is normal

AB2_nx99 = FB2_data_out_1 & (AB2_nx90 # GB2_event_async & AB2_nx88);


--AB2_nx100 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx100
--operation mode is normal

AB2_nx100 = !AB2_nx80 & AB2_nx86 & (AB2_nx81 # AB2_nx83);


--AB2_nx101 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx101
--operation mode is normal

AB2_nx101 = !FB2_data_out_3 & !FB2_data_out_0 & (!FB2_data_out_1 # !FB2_data_out_2);


--AB2_nx103 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx103
--operation mode is normal

AB2_nx103 = AB2_sync_counter_2 # AB2_sync_counter_1 # AB2_sync_counter_0;


--AB2_nx104 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx104
--operation mode is normal

AB2_nx104 = FB2_data_out_3 & (FB2_data_out_2 # FB2_data_out_0) # !FB2_data_out_3 & !FB2_data_out_2 & !FB2_data_out_1 & !FB2_data_out_0;


--AB2_nx105 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx105
--operation mode is normal

AB2_nx105 = AB2_nx98 # !FB2_data_out_1 & !FB2_data_out_0 & !AB2_nx80;


--AB2_nx106 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx106
--operation mode is normal

AB2_nx106 = AB2_nx91 # AB2_nx96 # !FB2_data_out_0 & AB2_nx82;


--AB2_nx107 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx107
--operation mode is normal

AB2_nx107 = BB2_buffer_full & (AB2_nx85 # !AB2_time_in_twofwd_n) # !BB2_buffer_full & EB2_stuff_err & (AB2_nx85 # !AB2_time_in_twofwd_n);


--AB2_nx108 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx108
--operation mode is normal

AB2_nx108 = AB2_nx91 # FB2_data_out_0 & AB2_nx80 & AB2_nx89;


--AB2_nx109 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx109
--operation mode is normal

AB2_nx109 = !FB2_data_out_2 & FB2_data_out_0;


--AB2_nx110 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx110
--operation mode is normal

AB2_nx110 = !BB2_buffer_full & !EB2_stuff_err & !AB2_sync_counter_2 & !AB2_sync_counter_1;


--AB2_buffer_flush_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|buffer_flush_n
--operation mode is normal

AB2_buffer_flush_n = FB2_data_out_3 # FB2_data_out_2 # FB2_data_out_0;


--AB2_d_buff is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|d_buff
--operation mode is normal

AB2_d_buff_lut_out = Y1_d1_to_dll;
AB2_d_buff = DFFEA(AB2_d_buff_lut_out, U1__clk0, VCC, , , , );


--AB2_sync_counter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|sync_counter_0
--operation mode is normal

AB2_sync_counter_0_lut_out = FB2_data_out_3 & !FB2_data_out_2 & !FB2_data_out_0 # !FB2_data_out_3 & FB2_data_out_2 & (AB2_nx142 # !FB2_data_out_0);
AB2_sync_counter_0 = DFFEA(AB2_sync_counter_0_lut_out, U1__clk0, VCC, , AB2_NOT_nx210, , );


--AB2_sync_counter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|sync_counter_1
--operation mode is normal

AB2_sync_counter_1_lut_out = FB2_data_out_3 & !FB2_data_out_2 & !FB2_data_out_0 # !FB2_data_out_3 & FB2_data_out_2 & (AB2_nx141 # !FB2_data_out_0);
AB2_sync_counter_1 = DFFEA(AB2_sync_counter_1_lut_out, U1__clk0, VCC, , AB2_NOT_nx210, , );


--AB2_sync_counter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|sync_counter_2
--operation mode is normal

AB2_sync_counter_2_lut_out = FB2_data_out_3 & !FB2_data_out_2 & !FB2_data_out_0 # !FB2_data_out_3 & FB2_data_out_2 & (AB2_nx140 # !FB2_data_out_0);
AB2_sync_counter_2 = DFFEA(AB2_sync_counter_2_lut_out, U1__clk0, VCC, , AB2_NOT_nx210, , );


--AB2_nx142 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx142
--operation mode is normal

AB2_nx142 = !AB2_sync_counter_0;


--AB2_result_dec_623_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|result_dec_623_nx14
--operation mode is arithmetic

AB2_result_dec_623_nx14 = CARRY(AB2_sync_counter_0);


--AB2_nx141 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx141
--operation mode is arithmetic

AB2_nx141_carry_eqn = AB2_result_dec_623_nx14;
AB2_nx141 = AB2_sync_counter_1 $ !AB2_nx141_carry_eqn;

--AB2_result_dec_623_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|result_dec_623_nx18
--operation mode is arithmetic

AB2_result_dec_623_nx18 = CARRY(!AB2_sync_counter_1 & !AB2_result_dec_623_nx14);


--AB2_nx140 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|nx140
--operation mode is normal

AB2_nx140_carry_eqn = AB2_result_dec_623_nx18;
AB2_nx140 = AB2_sync_counter_2 $ AB2_nx140_carry_eqn;


--GB2_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx18
--operation mode is normal

GB2_nx18 = GB2_state_0 # GB2_state_1 # !GB2_state_2;


--GB2_nx116 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx116
--operation mode is normal

GB2_nx116 = AB2_time_in_enable # !AB2_time_in_twofwd_n # !AB2_time_in_hotreset_n # !AB2_time_in_reset_n;


--GB2_nx92 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx92
--operation mode is normal

GB2_nx92 = !AB2_time_in_hotreset_n # !AB2_time_in_reset_n;


--GB2_nx93 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx93
--operation mode is normal

GB2_nx93 = AB2_time_in_enable & AB2_time_in_twofwd_n;


--GB2_nx94 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx94
--operation mode is normal

GB2_nx94 = !AB2_time_in_twofwd_n & !GB2_state_2 & !GB2_state_0 & GB2_state_1;


--GB2_nx95 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx95
--operation mode is normal

GB2_nx95 = AB2_time_in_enable & AB2_time_in_twofwd_n & GB2_b_0 # !AB2_time_in_hotreset_n;


--GB2_nx96 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx96
--operation mode is normal

GB2_nx96 = !GB2_state_1 & (GB2_state_2 $ GB2_state_0);


--GB2_nx97 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|nx97
--operation mode is normal

GB2_nx97 = !AB2_time_in_twofwd_n & !GB2_state_2 & !GB2_state_1;


--GB2_event_async is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|event_async
--operation mode is normal

GB2_event_async = AB2_time_in_enable & !GB2_state_2 & !GB2_state_0 & GB2_state_1;


--GB2_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_0
--operation mode is normal

GB2_state_0_lut_out = AB2_time_in_reset_n & (GB2_nx95 # !AB2_time_in_twofwd_n & GB2_nx96);
GB2_state_0 = DFFEA(GB2_state_0_lut_out, U1__clk0, VCC, , GB2_nx116, , );


--GB2_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_1
--operation mode is normal

GB2_state_1_lut_out = GB2_nx92 # GB2_nx97 # GB2_b_1_dup_64 & GB2_nx93;
GB2_state_1 = DFFEA(GB2_state_1_lut_out, U1__clk0, VCC, , GB2_nx116, , );


--GB2_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_2
--operation mode is normal

GB2_state_2_lut_out = !GB2_nx92 & (GB2_nx94 # GB2_b_1 & GB2_nx93);
GB2_state_2 = DFFEA(GB2_state_2_lut_out, U1__clk0, VCC, , GB2_nx116, , );


--GB2_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|b_0
--operation mode is normal

GB2_b_0 = !GB2_state_0 & GB2_nx18;


--GB2_state_inc_587_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_inc_587_nx14
--operation mode is arithmetic

GB2_state_inc_587_nx14 = CARRY(GB2_state_0);


--GB2_b_1_dup_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|b_1_dup_64
--operation mode is arithmetic

GB2_b_1_dup_64_carry_eqn = GB2_state_inc_587_nx14;
GB2_b_1_dup_64 = GB2_nx18 & (GB2_state_1 $ GB2_b_1_dup_64_carry_eqn);

--GB2_state_inc_587_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|state_inc_587_nx18
--operation mode is arithmetic

GB2_state_inc_587_nx18 = CARRY(!GB2_state_inc_587_nx14 # !GB2_state_1);


--GB2_b_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_timer_4_2:timer_in|b_1
--operation mode is normal

GB2_b_1_carry_eqn = GB2_state_inc_587_nx18;
GB2_b_1 = GB2_nx18 & (GB2_state_2 $ !GB2_b_1_carry_eqn);


--FB2_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1|data_out_0
--operation mode is normal

FB2_data_out_0_lut_out = AB2_next_state_0;
FB2_data_out_0 = DFFEA(FB2_data_out_0_lut_out, U1__clk0, VCC, , , , );


--FB2_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1|data_out_1
--operation mode is normal

FB2_data_out_1_lut_out = AB2_next_state_1;
FB2_data_out_1 = DFFEA(FB2_data_out_1_lut_out, U1__clk0, VCC, , , , );


--FB2_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1|data_out_2
--operation mode is normal

FB2_data_out_2_lut_out = AB2_next_state_2;
FB2_data_out_2 = DFFEA(FB2_data_out_2_lut_out, U1__clk0, VCC, , , , );


--FB2_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|hamm_reg_4_0_1:h1|data_out_3
--operation mode is normal

FB2_data_out_3_lut_out = AB2_next_state_3;
FB2_data_out_3 = DFFEA(FB2_data_out_3_lut_out, U1__clk0, VCC, , , , );


--EB2_counter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_0
--operation mode is arithmetic

EB2_counter_0_lut_out = !EB2_counter_0;
EB2_counter_0_reg_input = !EB2_SCLEAR & EB2_counter_0_lut_out;
EB2_counter_0 = DFFEA(EB2_counter_0_reg_input, U1__clk0, VCC, , EB2_nx90, , );

--EB2_counter_nx6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_nx6
--operation mode is arithmetic

EB2_counter_nx6 = CARRY(EB2_counter_0);


--EB2_counter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_2
--operation mode is normal

EB2_counter_2_carry_eqn = EB2_counter_nx12;
EB2_counter_2_lut_out = EB2_counter_2 $ !EB2_counter_2_carry_eqn;
EB2_counter_2_reg_input = !EB2_SCLEAR & EB2_counter_2_lut_out;
EB2_counter_2 = DFFEA(EB2_counter_2_reg_input, U1__clk0, VCC, , EB2_nx90, , );


--EB2_counter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_1
--operation mode is arithmetic

EB2_counter_1_carry_eqn = EB2_counter_nx6;
EB2_counter_1_lut_out = EB2_counter_1 $ EB2_counter_1_carry_eqn;
EB2_counter_1_reg_input = !EB2_SCLEAR & EB2_counter_1_lut_out;
EB2_counter_1 = DFFEA(EB2_counter_1_reg_input, U1__clk0, VCC, , EB2_nx90, , );

--EB2_counter_nx12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|counter_nx12
--operation mode is arithmetic

EB2_counter_nx12 = CARRY(!EB2_counter_nx6 # !EB2_counter_1);


--EB2_nx10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|nx10
--operation mode is normal

EB2_nx10 = !EB2_counter_0 # !EB2_counter_1 # !EB2_counter_2;


--EB2_nx90 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|nx90
--operation mode is normal

EB2_nx90 = AB2_s_to_ds # !AB2_buffer_flush_n;


--EB2_SCLEAR is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|SCLEAR
--operation mode is normal

EB2_SCLEAR = Y1_d1_to_dll $ EB2_data_out # !EB2_nx10 # !AB2_buffer_flush_n;


--EB2_nx233 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|nx233
--operation mode is normal

EB2_nx233 = AB2_s_to_ds & AB2_buffer_flush_n;


--EB2_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|data_out
--operation mode is normal

EB2_data_out_lut_out = Y1_d1_to_dll # !AB2_buffer_flush_n;
EB2_data_out = DFFEA(EB2_data_out_lut_out, U1__clk0, VCC, , EB2_nx90, , );


--EB2_stuff_err is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|stuff_err
--operation mode is normal

EB2_stuff_err_lut_out = !EB2_nx10 & EB2_nx233 & (Y1_d1_to_dll $ !EB2_data_out);
EB2_stuff_err = DFFEA(EB2_stuff_err_lut_out, U1__clk0, VCC, , , , );


--EB2_strobe_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt1|mcm_nw_destuffing_7:destuff_in|strobe_out
--operation mode is normal

EB2_strobe_out_lut_out = AB2_s_to_ds & AB2_buffer_flush_n & EB2_nx10;
EB2_strobe_out = DFFEA(EB2_strobe_out_lut_out, U1__clk0, VCC, , , , );


--AB1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|next_state_2
--operation mode is normal

AB1_next_state_2 = AB1_nx92 # AB1_nx93 # AB1_nx107 # AB1_nx108;


--AB1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|next_state_1
--operation mode is normal

AB1_next_state_1 = AB1_nx94 # AB1_nx95 # AB1_nx97 # AB1_nx106;


--AB1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|next_state_0
--operation mode is normal

AB1_next_state_0 = AB1_nx99 # AB1_nx100 # AB1_nx104 # AB1_nx105;


--AB1_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|next_state_3
--operation mode is normal

AB1_next_state_3 = !AB1_nx83 & AB1_nx89 & AB1_nx109 & AB1_nx110;


--AB1_NOT_nx210 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|NOT_nx210
--operation mode is normal

AB1_NOT_nx210 = AB1_nx87 # AB1_nx101 # AB1_nx85 & AB1_nx103;


--AB1_time_in_hotreset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|time_in_hotreset_n
--operation mode is normal

AB1_time_in_hotreset_n = FB1_data_out_3 # FB1_data_out_2 & (FB1_data_out_0 # !FB1_data_out_1) # !FB1_data_out_2 & (FB1_data_out_1 # !FB1_data_out_0);


--AB1_time_in_enable is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|time_in_enable
--operation mode is normal

AB1_time_in_enable = FB1_data_out_3 & !FB1_data_out_2 & !FB1_data_out_1 & !FB1_data_out_0 # !FB1_data_out_3 & (FB1_data_out_1 # FB1_data_out_2 & FB1_data_out_0);


--AB1_s_to_ds is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|s_to_ds
--operation mode is normal

AB1_s_to_ds = !FB1_data_out_1 & (FB1_data_out_3 & !FB1_data_out_2 & !FB1_data_out_0 # !FB1_data_out_3 & FB1_data_out_2 & FB1_data_out_0);


--AB1_time_in_reset_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|time_in_reset_n
--operation mode is normal

AB1_time_in_reset_n = FB1_data_out_3 # FB1_data_out_2 # FB1_data_out_1 # FB1_data_out_0;


--AB1_nx80 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx80
--operation mode is normal

AB1_nx80 = BB1_buffer_full # EB1_stuff_err;


--AB1_nx81 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx81
--operation mode is normal

AB1_nx81 = AB1_sync_counter_2 # AB1_sync_counter_1;


--AB1_nx82 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx82
--operation mode is normal

AB1_nx82 = !FB1_data_out_3 & FB1_data_out_2;


--AB1_nx83 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx83
--operation mode is normal

AB1_nx83 = AB1_sync_counter_0 # Y1_d0_to_dll $ !AB1_d_buff;


--AB1_nx84 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx84
--operation mode is normal

AB1_nx84 = !FB1_data_out_3 & FB1_data_out_1;


--AB1_nx85 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx85
--operation mode is normal

AB1_nx85 = !FB1_data_out_3 & FB1_data_out_2 & !FB1_data_out_1;


--AB1_nx86 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx86
--operation mode is normal

AB1_nx86 = FB1_data_out_2 # FB1_data_out_1 & FB1_data_out_0;


--AB1_nx87 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx87
--operation mode is normal

AB1_nx87 = !FB1_data_out_2 & !FB1_data_out_1 & !FB1_data_out_0;


--AB1_nx88 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx88
--operation mode is normal

AB1_nx88 = !BB1_buffer_full & !EB1_stuff_err # !FB1_data_out_0;


--AB1_nx89 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx89
--operation mode is normal

AB1_nx89 = !FB1_data_out_3 & FB1_data_out_1 & !GB1_event_async;


--AB1_time_in_twofwd_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|time_in_twofwd_n
--operation mode is normal

AB1_time_in_twofwd_n = FB1_data_out_2 # FB1_data_out_1 # FB1_data_out_0 # !FB1_data_out_3;


--AB1_nx90 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx90
--operation mode is normal

AB1_nx90 = FB1_data_out_3 # FB1_data_out_2;


--AB1_nx91 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx91
--operation mode is normal

AB1_nx91 = !FB1_data_out_3 & FB1_data_out_2 & FB1_data_out_1 & !GB1_event_async;


--AB1_nx92 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx92
--operation mode is normal

AB1_nx92 = FB1_data_out_0 & !AB1_nx81 & !AB1_nx83 & AB1_nx85;


--AB1_nx93 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx93
--operation mode is normal

AB1_nx93 = GB1_event_async & AB1_nx84 & (!FB1_data_out_0 # !FB1_data_out_2);


--AB1_nx94 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx94
--operation mode is normal

AB1_nx94 = Y1_d0_to_dll & !FB1_data_out_1 & FB1_data_out_0 & !AB1_nx90;


--AB1_nx95 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx95
--operation mode is normal

AB1_nx95 = !FB1_data_out_2 & AB1_nx84 & !AB1_nx88 # !AB1_time_in_twofwd_n;


--AB1_nx96 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx96
--operation mode is normal

AB1_nx96 = AB1_nx83 & (AB1_nx85 # AB1_nx89) # !AB1_nx83 & !FB1_data_out_0 & AB1_nx89;


--AB1_nx97 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx97
--operation mode is normal

AB1_nx97 = AB1_nx81 & (AB1_nx85 # AB1_nx89) # !AB1_nx81 & AB1_nx80 & AB1_nx85;


--AB1_nx98 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx98
--operation mode is normal

AB1_nx98 = !Y1_d0_to_dll & !FB1_data_out_2 & !FB1_data_out_1 & FB1_data_out_0;


--AB1_nx99 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx99
--operation mode is normal

AB1_nx99 = FB1_data_out_1 & (AB1_nx90 # GB1_event_async & AB1_nx88);


--AB1_nx100 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx100
--operation mode is normal

AB1_nx100 = !AB1_nx80 & AB1_nx86 & (AB1_nx81 # AB1_nx83);


--AB1_nx101 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx101
--operation mode is normal

AB1_nx101 = !FB1_data_out_3 & !FB1_data_out_0 & (!FB1_data_out_1 # !FB1_data_out_2);


--AB1_nx103 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx103
--operation mode is normal

AB1_nx103 = AB1_sync_counter_2 # AB1_sync_counter_1 # AB1_sync_counter_0;


--AB1_nx104 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx104
--operation mode is normal

AB1_nx104 = FB1_data_out_3 & (FB1_data_out_2 # FB1_data_out_0) # !FB1_data_out_3 & !FB1_data_out_2 & !FB1_data_out_1 & !FB1_data_out_0;


--AB1_nx105 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx105
--operation mode is normal

AB1_nx105 = AB1_nx98 # !FB1_data_out_1 & !FB1_data_out_0 & !AB1_nx80;


--AB1_nx106 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx106
--operation mode is normal

AB1_nx106 = AB1_nx91 # AB1_nx96 # !FB1_data_out_0 & AB1_nx82;


--AB1_nx107 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx107
--operation mode is normal

AB1_nx107 = BB1_buffer_full & (AB1_nx85 # !AB1_time_in_twofwd_n) # !BB1_buffer_full & EB1_stuff_err & (AB1_nx85 # !AB1_time_in_twofwd_n);


--AB1_nx108 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx108
--operation mode is normal

AB1_nx108 = AB1_nx91 # FB1_data_out_0 & AB1_nx80 & AB1_nx89;


--AB1_nx109 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx109
--operation mode is normal

AB1_nx109 = !FB1_data_out_2 & FB1_data_out_0;


--AB1_nx110 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx110
--operation mode is normal

AB1_nx110 = !BB1_buffer_full & !EB1_stuff_err & !AB1_sync_counter_2 & !AB1_sync_counter_1;


--AB1_buffer_flush_n is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|buffer_flush_n
--operation mode is normal

AB1_buffer_flush_n = FB1_data_out_3 # FB1_data_out_2 # FB1_data_out_0;


--AB1_d_buff is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|d_buff
--operation mode is normal

AB1_d_buff_lut_out = Y1_d0_to_dll;
AB1_d_buff = DFFEA(AB1_d_buff_lut_out, U1__clk0, VCC, , , , );


--AB1_sync_counter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|sync_counter_0
--operation mode is normal

AB1_sync_counter_0_lut_out = FB1_data_out_3 & !FB1_data_out_2 & !FB1_data_out_0 # !FB1_data_out_3 & FB1_data_out_2 & (AB1_nx142 # !FB1_data_out_0);
AB1_sync_counter_0 = DFFEA(AB1_sync_counter_0_lut_out, U1__clk0, VCC, , AB1_NOT_nx210, , );


--AB1_sync_counter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|sync_counter_1
--operation mode is normal

AB1_sync_counter_1_lut_out = FB1_data_out_3 & !FB1_data_out_2 & !FB1_data_out_0 # !FB1_data_out_3 & FB1_data_out_2 & (AB1_nx141 # !FB1_data_out_0);
AB1_sync_counter_1 = DFFEA(AB1_sync_counter_1_lut_out, U1__clk0, VCC, , AB1_NOT_nx210, , );


--AB1_sync_counter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|sync_counter_2
--operation mode is normal

AB1_sync_counter_2_lut_out = FB1_data_out_3 & !FB1_data_out_2 & !FB1_data_out_0 # !FB1_data_out_3 & FB1_data_out_2 & (AB1_nx140 # !FB1_data_out_0);
AB1_sync_counter_2 = DFFEA(AB1_sync_counter_2_lut_out, U1__clk0, VCC, , AB1_NOT_nx210, , );


--AB1_nx142 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx142
--operation mode is normal

AB1_nx142 = !AB1_sync_counter_0;


--AB1_result_dec_623_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|result_dec_623_nx14
--operation mode is arithmetic

AB1_result_dec_623_nx14 = CARRY(AB1_sync_counter_0);


--AB1_nx141 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx141
--operation mode is arithmetic

AB1_nx141_carry_eqn = AB1_result_dec_623_nx14;
AB1_nx141 = AB1_sync_counter_1 $ !AB1_nx141_carry_eqn;

--AB1_result_dec_623_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|result_dec_623_nx18
--operation mode is arithmetic

AB1_result_dec_623_nx18 = CARRY(!AB1_sync_counter_1 & !AB1_result_dec_623_nx14);


--AB1_nx140 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|nx140
--operation mode is normal

AB1_nx140_carry_eqn = AB1_result_dec_623_nx18;
AB1_nx140 = AB1_sync_counter_2 $ AB1_nx140_carry_eqn;


--GB1_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx18
--operation mode is normal

GB1_nx18 = GB1_state_0 # GB1_state_1 # !GB1_state_2;


--GB1_nx116 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx116
--operation mode is normal

GB1_nx116 = AB1_time_in_enable # !AB1_time_in_twofwd_n # !AB1_time_in_hotreset_n # !AB1_time_in_reset_n;


--GB1_nx92 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx92
--operation mode is normal

GB1_nx92 = !AB1_time_in_hotreset_n # !AB1_time_in_reset_n;


--GB1_nx93 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx93
--operation mode is normal

GB1_nx93 = AB1_time_in_enable & AB1_time_in_twofwd_n;


--GB1_nx94 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx94
--operation mode is normal

GB1_nx94 = !AB1_time_in_twofwd_n & !GB1_state_2 & !GB1_state_0 & GB1_state_1;


--GB1_nx95 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx95
--operation mode is normal

GB1_nx95 = AB1_time_in_enable & AB1_time_in_twofwd_n & GB1_b_0 # !AB1_time_in_hotreset_n;


--GB1_nx96 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx96
--operation mode is normal

GB1_nx96 = !GB1_state_1 & (GB1_state_2 $ GB1_state_0);


--GB1_nx97 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|nx97
--operation mode is normal

GB1_nx97 = !AB1_time_in_twofwd_n & !GB1_state_2 & !GB1_state_1;


--GB1_event_async is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|event_async
--operation mode is normal

GB1_event_async = AB1_time_in_enable & !GB1_state_2 & !GB1_state_0 & GB1_state_1;


--GB1_state_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_0
--operation mode is normal

GB1_state_0_lut_out = AB1_time_in_reset_n & (GB1_nx95 # !AB1_time_in_twofwd_n & GB1_nx96);
GB1_state_0 = DFFEA(GB1_state_0_lut_out, U1__clk0, VCC, , GB1_nx116, , );


--GB1_state_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_1
--operation mode is normal

GB1_state_1_lut_out = GB1_nx92 # GB1_nx97 # GB1_b_1_dup_64 & GB1_nx93;
GB1_state_1 = DFFEA(GB1_state_1_lut_out, U1__clk0, VCC, , GB1_nx116, , );


--GB1_state_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_2
--operation mode is normal

GB1_state_2_lut_out = !GB1_nx92 & (GB1_nx94 # GB1_b_1 & GB1_nx93);
GB1_state_2 = DFFEA(GB1_state_2_lut_out, U1__clk0, VCC, , GB1_nx116, , );


--GB1_b_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|b_0
--operation mode is normal

GB1_b_0 = !GB1_state_0 & GB1_nx18;


--GB1_state_inc_587_nx14 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_inc_587_nx14
--operation mode is arithmetic

GB1_state_inc_587_nx14 = CARRY(GB1_state_0);


--GB1_b_1_dup_64 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|b_1_dup_64
--operation mode is arithmetic

GB1_b_1_dup_64_carry_eqn = GB1_state_inc_587_nx14;
GB1_b_1_dup_64 = GB1_nx18 & (GB1_state_1 $ GB1_b_1_dup_64_carry_eqn);

--GB1_state_inc_587_nx18 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|state_inc_587_nx18
--operation mode is arithmetic

GB1_state_inc_587_nx18 = CARRY(!GB1_state_inc_587_nx14 # !GB1_state_1);


--GB1_b_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_timer_4_2:timer_in|b_1
--operation mode is normal

GB1_b_1_carry_eqn = GB1_state_inc_587_nx18;
GB1_b_1 = GB1_nx18 & (GB1_state_2 $ !GB1_b_1_carry_eqn);


--FB1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1|data_out_0
--operation mode is normal

FB1_data_out_0_lut_out = AB1_next_state_0;
FB1_data_out_0 = DFFEA(FB1_data_out_0_lut_out, U1__clk0, VCC, , , , );


--FB1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1|data_out_1
--operation mode is normal

FB1_data_out_1_lut_out = AB1_next_state_1;
FB1_data_out_1 = DFFEA(FB1_data_out_1_lut_out, U1__clk0, VCC, , , , );


--FB1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1|data_out_2
--operation mode is normal

FB1_data_out_2_lut_out = AB1_next_state_2;
FB1_data_out_2 = DFFEA(FB1_data_out_2_lut_out, U1__clk0, VCC, , , , );


--FB1_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|hamm_reg_4_0_1:h1|data_out_3
--operation mode is normal

FB1_data_out_3_lut_out = AB1_next_state_3;
FB1_data_out_3 = DFFEA(FB1_data_out_3_lut_out, U1__clk0, VCC, , , , );


--EB1_counter_0 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_0
--operation mode is arithmetic

EB1_counter_0_lut_out = !EB1_counter_0;
EB1_counter_0_reg_input = !EB1_SCLEAR & EB1_counter_0_lut_out;
EB1_counter_0 = DFFEA(EB1_counter_0_reg_input, U1__clk0, VCC, , EB1_nx90, , );

--EB1_counter_nx6 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_nx6
--operation mode is arithmetic

EB1_counter_nx6 = CARRY(EB1_counter_0);


--EB1_counter_2 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_2
--operation mode is normal

EB1_counter_2_carry_eqn = EB1_counter_nx12;
EB1_counter_2_lut_out = EB1_counter_2 $ !EB1_counter_2_carry_eqn;
EB1_counter_2_reg_input = !EB1_SCLEAR & EB1_counter_2_lut_out;
EB1_counter_2 = DFFEA(EB1_counter_2_reg_input, U1__clk0, VCC, , EB1_nx90, , );


--EB1_counter_1 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_1
--operation mode is arithmetic

EB1_counter_1_carry_eqn = EB1_counter_nx6;
EB1_counter_1_lut_out = EB1_counter_1 $ EB1_counter_1_carry_eqn;
EB1_counter_1_reg_input = !EB1_SCLEAR & EB1_counter_1_lut_out;
EB1_counter_1 = DFFEA(EB1_counter_1_reg_input, U1__clk0, VCC, , EB1_nx90, , );

--EB1_counter_nx12 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|counter_nx12
--operation mode is arithmetic

EB1_counter_nx12 = CARRY(!EB1_counter_nx6 # !EB1_counter_1);


--EB1_nx10 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|nx10
--operation mode is normal

EB1_nx10 = !EB1_counter_0 # !EB1_counter_1 # !EB1_counter_2;


--EB1_nx90 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|nx90
--operation mode is normal

EB1_nx90 = AB1_s_to_ds # !AB1_buffer_flush_n;


--EB1_SCLEAR is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|SCLEAR
--operation mode is normal

EB1_SCLEAR = Y1_d0_to_dll $ EB1_data_out # !EB1_nx10 # !AB1_buffer_flush_n;


--EB1_nx233 is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|nx233
--operation mode is normal

EB1_nx233 = AB1_s_to_ds & AB1_buffer_flush_n;


--EB1_data_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|data_out
--operation mode is normal

EB1_data_out_lut_out = Y1_d0_to_dll # !AB1_buffer_flush_n;
EB1_data_out = DFFEA(EB1_data_out_lut_out, U1__clk0, VCC, , EB1_nx90, , );


--EB1_stuff_err is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|stuff_err
--operation mode is normal

EB1_stuff_err_lut_out = !EB1_nx10 & EB1_nx233 & (Y1_d0_to_dll $ !EB1_data_out);
EB1_stuff_err = DFFEA(EB1_stuff_err_lut_out, U1__clk0, VCC, , , , );


--EB1_strobe_out is mcm_network_interface:scsn_slave|mcm_nw_dll_4_2_7_63_69_4_7:nw_dll|mcm_nw_bittiming_4_2_7_7_2:bt0|mcm_nw_destuffing_7:destuff_in|strobe_out
--operation mode is normal

EB1_strobe_out_lut_out = AB1_s_to_ds & AB1_buffer_flush_n & EB1_nx10;
EB1_strobe_out = DFFEA(EB1_strobe_out_lut_out, U1__clk0, VCC, , , , );


--V1_next_state_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|next_state_3
--operation mode is normal

V1_next_state_3 = V1_nx412 # V1_nx437 # V1_nx414 & V1_nx424;


--V1_next_state_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|next_state_2
--operation mode is normal

V1_next_state_2 = V1_nx415 # V1_nx417 # V1_nx431 # V1_nx435;


--V1_next_state_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|next_state_1
--operation mode is normal

V1_next_state_1 = V1_nx419 # V1_nx420 # V1_nx421 # V1_nx430;


--V1_next_state_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|next_state_0
--operation mode is normal

V1_next_state_0 = V1_nx422 # V1_nx427 # V1_nx407 & V1_nx429;


--V1_nx241 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx241
--operation mode is normal

V1_nx241 = Z1_data_out_3 & !Z1_data_out_2 & !Z1_data_out_1 & Z1_data_out_0;


--V1_nx383 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx383
--operation mode is normal

V1_nx383 = V1_long_transaction & V1_nx407;


--V1_nx397 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx397
--operation mode is normal

V1_nx397 = !Z1_data_out_3 & Z1_data_out_1 & Z1_data_out_0;


--V1_nx402 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx402
--operation mode is normal

V1_nx402 = V1_waitcount_5 # V1_waitcount_4 # V1_nx411;


--V1_nx403 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx403
--operation mode is normal

V1_nx403 = V1_nx425 & (V1_waitcount_5 # V1_waitcount_4 # V1_nx411);


--V1_a_0_dup_53 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|a_0_dup_53
--operation mode is normal

V1_a_0_dup_53 = !Z1_data_out_3 & Z1_data_out_1 & !Z1_data_out_0;


--V1_a_2_dup_231 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|a_2_dup_231
--operation mode is normal

V1_a_2_dup_231 = V1_long_transaction & (V1_waitcount_5 # V1_waitcount_4 # V1_nx411);


--V1_nx1105 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx1105
--operation mode is normal

V1_nx1105 = !Z1_data_out_3 & (Z1_data_out_2 & !Z1_data_out_0 # !Z1_data_out_2 & !Z1_data_out_1);


--V1_ix34_ix22_nx10 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|ix34_ix22_nx10
--operation mode is normal

V1_ix34_ix22_nx10 = Z1_data_out_2 # !Z1_data_out_3;


--V1_ix34_ix30_nx12 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|ix34_ix30_nx12
--operation mode is normal

V1_ix34_ix30_nx12 = Z1_data_out_3 # Z1_data_out_1 # Z1_data_out_0 # !Z1_data_out_2;


--V1_nx399 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx399
--operation mode is normal

V1_nx399 = Z1_data_out_2 # Z1_data_out_1;


--V1_nx400 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx400
--operation mode is normal

V1_nx400 = X1_request_50 # !X1_request_52 & !X1_request_51;


--V1_nx401 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx401
--operation mode is normal

V1_nx401 = X1_request_valid & !Z1_data_out_3;


--V1_ix34_ix32_nx8 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|ix34_ix32_nx8
--operation mode is normal

V1_ix34_ix32_nx8 = !Z1_data_out_0 # !Z1_data_out_1;


--V1_nx404 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx404
--operation mode is normal

V1_nx404 = !Z1_data_out_3 & Z1_data_out_0;


--V1_nx405 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx405
--operation mode is normal

V1_nx405 = !X1_request_49 & X1_request_valid & !Z1_data_out_3 & !Z1_data_out_0;


--V1_nx406 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx406
--operation mode is normal

V1_nx406 = X1_request_51 # !X1_request_52 & X1_request_50;


--V1_ix34_ix34_nx8 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|ix34_ix34_nx8
--operation mode is normal

V1_ix34_ix34_nx8 = Z1_data_out_0 # !Z1_data_out_1;


--V1_nx407 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx407
--operation mode is normal

V1_nx407 = Z1_data_out_3 & Z1_data_out_2 & Z1_data_out_1 & Z1_data_out_0;


--V1_nx408 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx408
--operation mode is normal

V1_nx408 = !Z1_data_out_3 & Z1_data_out_2 & Z1_data_out_0;


--V1_nx410 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx410
--operation mode is normal

V1_nx410 = G1_bus_ack # V1_current_state_dp_2 # V1_current_state_dp_0;


--V1_nx411 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx411
--operation mode is normal

V1_nx411 = V1_waitcount_3 # V1_waitcount_2 # V1_waitcount_1 # V1_waitcount_0;


--V1_nx412 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx412
--operation mode is normal

V1_nx412 = V1_nx413 # V1_nx439 # V1_nx407 & !V1_nx429;


--V1_nx413 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx413
--operation mode is normal

V1_nx413 = !Z1_data_out_1 & V1_long_transaction & !V1_nx402 & V1_nx408;


--V1_nx414 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx414
--operation mode is normal

V1_nx414 = !X1_request_49 & X1_request_valid & !Z1_data_out_0 & !V1_nx399;


--V1_nx415 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx415
--operation mode is normal

V1_nx415 = X1_request_52 & X1_request_51 & !Z1_data_out_1 & V1_nx405;


--V1_nx416 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx416
--operation mode is normal

V1_nx416 = X1_request_51 & !X1_request_50 & X1_request_valid & Z1_data_out_2;


--V1_nx417 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx417
--operation mode is normal

V1_nx417 = Z1_data_out_2 & V1_nx401 # !Z1_data_out_2 & !V1_a_2_dup_231 & !V1_ix34_ix32_nx8;


--V1_nx418 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx418
--operation mode is normal

V1_nx418 = V1_nx408 # !Z1_data_out_1 & !V1_nx400 & V1_nx405;


--V1_nx419 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx419
--operation mode is normal

V1_nx419 = V1_nx431 # !Z1_data_out_3 & V1_a_2_dup_231 & !V1_ix34_ix32_nx8;


--V1_nx420 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx420
--operation mode is normal

V1_nx420 = V1_nx436 # Z1_data_out_1 & !Z1_data_out_0 & V1_nx401;


--V1_nx421 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx421
--operation mode is normal

V1_nx421 = !V1_a_2_dup_231 & V1_nx408 & (!Z1_data_out_1 # !G1_bus_dout_0);


--V1_nx422 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx422
--operation mode is normal

V1_nx422 = !Z1_data_out_3 & Z1_data_out_0 & V1_a_2_dup_231 & V1_nx399;


--V1_nx423 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx423
--operation mode is normal

V1_nx423 = !V1_nx399 & V1_nx401 & (Z1_data_out_0 # !V1_nx400);


--V1_nx424 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx424
--operation mode is normal

V1_nx424 = X1_request_52 $ X1_request_51 # !X1_request_50;


--V1_nx425 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx425
--operation mode is normal

V1_nx425 = !Z1_data_out_3 & Z1_data_out_0 & (Z1_data_out_2 # Z1_data_out_1);


--V1_nx426 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx426
--operation mode is normal

V1_nx426 = !V1_req_reg & V1_cfg_req & !V1_bus_req;


--V1_nx427 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx427
--operation mode is normal

V1_nx427 = V1_nx423 # !X1_request_49 & !V1_nx399 & V1_nx428;


--V1_nx428 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx428
--operation mode is normal

V1_nx428 = X1_request_valid & !Z1_data_out_3 & (X1_request_52 $ X1_request_51);


--V1_nx429 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx429
--operation mode is normal

V1_nx429 = !X1_request_50 & X1_request_valid & (X1_request_52 # X1_request_51);


--V1_nx430 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx430
--operation mode is normal

V1_nx430 = V1_nx432 & (V1_nx433 # V1_nx434) # !V1_nx432 & V1_nx406 & V1_nx434;


--V1_nx431 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx431
--operation mode is normal

V1_nx431 = Z1_data_out_3 & (Z1_data_out_2 & Z1_data_out_1 & !Z1_data_out_0 # !Z1_data_out_2 & Z1_data_out_0);


--V1_nx432 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx432
--operation mode is normal

V1_nx432 = X1_request_52 & !X1_request_50;


--V1_nx433 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx433
--operation mode is normal

V1_nx433 = X1_request_valid & Z1_data_out_3 & Z1_data_out_1 & Z1_data_out_0;


--V1_nx434 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx434
--operation mode is normal

V1_nx434 = !Z1_data_out_2 & V1_nx405;


--V1_nx435 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx435
--operation mode is normal

V1_nx435 = V1_nx418 # V1_nx436 # !V1_ix34_ix32_nx8 & V1_nx416;


--V1_nx436 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx436
--operation mode is normal

V1_nx436 = X1_request_valid & G1_bus_ack & Z1_data_out_0 & !V1_nx399;


--V1_nx437 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx437
--operation mode is normal

V1_nx437 = V1_nx438 & (Z1_data_out_3 # X1_request_49 & V1_nx400);


--V1_nx438 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx438
--operation mode is normal

V1_nx438 = X1_request_valid & !Z1_data_out_2 & !Z1_data_out_1 & !Z1_data_out_0;


--V1_nx439 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|nx439
--operation mode is normal

V1_nx439 = !V1_nx399 & V1_nx404 & (G1_bus_ack # !X1_request_valid);


--V1_reply_52 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_52
--operation mode is normal

V1_reply_52 = X1_request_52 # !Z1_data_out_1 & !Z1_data_out_0 & !V1_ix34_ix22_nx10;


--V1_reply_51 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_51
--operation mode is normal

V1_reply_51 = X1_request_51 # !Z1_data_out_1 & !Z1_data_out_0 & !V1_ix34_ix22_nx10;


--V1_reply_50 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_50
--operation mode is normal

V1_reply_50 = X1_request_50 # !Z1_data_out_1 & !Z1_data_out_0 & !V1_ix34_ix22_nx10;


--V1_reply_49 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_49
--operation mode is normal

V1_reply_49 = X1_request_49 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_48 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_48
--operation mode is normal

V1_reply_48 = X1_request_48 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_47 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_47
--operation mode is normal

V1_reply_47 = X1_request_47 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_46 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_46
--operation mode is normal

V1_reply_46 = X1_request_46 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_45 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_45
--operation mode is normal

V1_reply_45 = X1_request_45 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_44 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_44
--operation mode is normal

V1_reply_44 = X1_request_44 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_43 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_43
--operation mode is normal

V1_reply_43 = X1_request_43 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_42 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_42
--operation mode is normal

V1_reply_42 = X1_request_42 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_41 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_41
--operation mode is normal

V1_reply_41 = X1_request_41 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_40 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_40
--operation mode is normal

V1_reply_40 = X1_request_40 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_39 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_39
--operation mode is normal

V1_reply_39 = X1_request_39 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_38 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_38
--operation mode is normal

V1_reply_38 = X1_request_38 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_37 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_37
--operation mode is normal

V1_reply_37 = X1_request_37 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_36 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_36
--operation mode is normal

V1_reply_36 = X1_request_36 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_35 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_35
--operation mode is normal

V1_reply_35 = X1_request_35 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_34 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_34
--operation mode is normal

V1_reply_34 = X1_request_34 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_33 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_33
--operation mode is normal

V1_reply_33 = X1_request_33 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_32 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_32
--operation mode is normal

V1_reply_32 = X1_request_32 & (Z1_data_out_1 # Z1_data_out_0 # V1_ix34_ix22_nx10);


--V1_reply_31 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_31
--operation mode is normal

V1_reply_31 = X1_request_31 & (V1_a_0_dup_53 # V1_read_data_0 & !V1_ix34_ix30_nx12) # !X1_request_31 & V1_read_data_0 & !V1_ix34_ix30_nx12;


--V1_reply_30 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_30
--operation mode is normal

V1_reply_30 = X1_request_30 & (V1_a_0_dup_53 # V1_read_data_1 & !V1_ix34_ix30_nx12) # !X1_request_30 & V1_read_data_1 & !V1_ix34_ix30_nx12;


--V1_reply_29 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_29
--operation mode is normal

V1_reply_29 = X1_request_29 & (V1_a_0_dup_53 # V1_read_data_2 & !V1_ix34_ix30_nx12) # !X1_request_29 & V1_read_data_2 & !V1_ix34_ix30_nx12;


--V1_reply_28 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_28
--operation mode is normal

V1_reply_28 = X1_request_28 & (V1_a_0_dup_53 # V1_read_data_3 & !V1_ix34_ix30_nx12) # !X1_request_28 & V1_read_data_3 & !V1_ix34_ix30_nx12;


--V1_reply_27 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_27
--operation mode is normal

V1_reply_27 = X1_request_27 & (V1_a_0_dup_53 # V1_read_data_4 & !V1_ix34_ix30_nx12) # !X1_request_27 & V1_read_data_4 & !V1_ix34_ix30_nx12;


--V1_reply_26 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_26
--operation mode is normal

V1_reply_26 = X1_request_26 & (V1_a_0_dup_53 # V1_read_data_5 & !V1_ix34_ix30_nx12) # !X1_request_26 & V1_read_data_5 & !V1_ix34_ix30_nx12;


--V1_reply_25 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_25
--operation mode is normal

V1_reply_25 = X1_request_25 & (V1_a_0_dup_53 # V1_read_data_6 & !V1_ix34_ix30_nx12) # !X1_request_25 & V1_read_data_6 & !V1_ix34_ix30_nx12;


--V1_reply_24 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_24
--operation mode is normal

V1_reply_24 = X1_request_24 & (V1_a_0_dup_53 # V1_read_data_7 & !V1_ix34_ix30_nx12) # !X1_request_24 & V1_read_data_7 & !V1_ix34_ix30_nx12;


--V1_reply_23 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_23
--operation mode is normal

V1_reply_23 = X1_request_23 & (V1_a_0_dup_53 # V1_read_data_8 & !V1_ix34_ix30_nx12) # !X1_request_23 & V1_read_data_8 & !V1_ix34_ix30_nx12;


--V1_reply_22 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_22
--operation mode is normal

V1_reply_22 = X1_request_22 & (V1_a_0_dup_53 # V1_read_data_9 & !V1_ix34_ix30_nx12) # !X1_request_22 & V1_read_data_9 & !V1_ix34_ix30_nx12;


--V1_reply_21 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_21
--operation mode is normal

V1_reply_21 = X1_request_21 & (V1_a_0_dup_53 # V1_read_data_10 & !V1_ix34_ix30_nx12) # !X1_request_21 & V1_read_data_10 & !V1_ix34_ix30_nx12;


--V1_reply_20 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_20
--operation mode is normal

V1_reply_20 = X1_request_20 & (V1_a_0_dup_53 # V1_read_data_11 & !V1_ix34_ix30_nx12) # !X1_request_20 & V1_read_data_11 & !V1_ix34_ix30_nx12;


--V1_reply_19 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_19
--operation mode is normal

V1_reply_19 = X1_request_19 & (V1_a_0_dup_53 # V1_read_data_12 & !V1_ix34_ix30_nx12) # !X1_request_19 & V1_read_data_12 & !V1_ix34_ix30_nx12;


--V1_reply_18 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_18
--operation mode is normal

V1_reply_18 = X1_request_18 & (V1_a_0_dup_53 # V1_read_data_13 & !V1_ix34_ix30_nx12) # !X1_request_18 & V1_read_data_13 & !V1_ix34_ix30_nx12;


--V1_reply_17 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_17
--operation mode is normal

V1_reply_17 = X1_request_17 & (V1_a_0_dup_53 # V1_read_data_14 & !V1_ix34_ix30_nx12) # !X1_request_17 & V1_read_data_14 & !V1_ix34_ix30_nx12;


--V1_reply_16 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_16
--operation mode is normal

V1_reply_16 = X1_request_16 & (V1_a_0_dup_53 # V1_read_data_15 & !V1_ix34_ix30_nx12) # !X1_request_16 & V1_read_data_15 & !V1_ix34_ix30_nx12;


--V1_reply_15 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_15
--operation mode is normal

V1_reply_15 = X1_request_15 & (V1_a_0_dup_53 # V1_read_data_16 & !V1_ix34_ix30_nx12) # !X1_request_15 & V1_read_data_16 & !V1_ix34_ix30_nx12;


--V1_reply_14 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_14
--operation mode is normal

V1_reply_14 = X1_request_14 & (V1_a_0_dup_53 # V1_read_data_17 & !V1_ix34_ix30_nx12) # !X1_request_14 & V1_read_data_17 & !V1_ix34_ix30_nx12;


--V1_reply_13 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_13
--operation mode is normal

V1_reply_13 = X1_request_13 & (V1_a_0_dup_53 # V1_read_data_18 & !V1_ix34_ix30_nx12) # !X1_request_13 & V1_read_data_18 & !V1_ix34_ix30_nx12;


--V1_reply_12 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_12
--operation mode is normal

V1_reply_12 = X1_request_12 & (V1_a_0_dup_53 # V1_read_data_19 & !V1_ix34_ix30_nx12) # !X1_request_12 & V1_read_data_19 & !V1_ix34_ix30_nx12;


--V1_reply_11 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_11
--operation mode is normal

V1_reply_11 = X1_request_11 & (V1_a_0_dup_53 # V1_read_data_20 & !V1_ix34_ix30_nx12) # !X1_request_11 & V1_read_data_20 & !V1_ix34_ix30_nx12;


--V1_reply_10 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_10
--operation mode is normal

V1_reply_10 = X1_request_10 & (V1_a_0_dup_53 # V1_read_data_21 & !V1_ix34_ix30_nx12) # !X1_request_10 & V1_read_data_21 & !V1_ix34_ix30_nx12;


--V1_reply_9 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_9
--operation mode is normal

V1_reply_9 = X1_request_9 & (V1_a_0_dup_53 # V1_read_data_22 & !V1_ix34_ix30_nx12) # !X1_request_9 & V1_read_data_22 & !V1_ix34_ix30_nx12;


--V1_reply_8 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_8
--operation mode is normal

V1_reply_8 = X1_request_8 & (V1_a_0_dup_53 # V1_read_data_23 & !V1_ix34_ix30_nx12) # !X1_request_8 & V1_read_data_23 & !V1_ix34_ix30_nx12;


--V1_reply_7 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_7
--operation mode is normal

V1_reply_7 = X1_request_7 & (V1_a_0_dup_53 # V1_read_data_24 & !V1_ix34_ix30_nx12) # !X1_request_7 & V1_read_data_24 & !V1_ix34_ix30_nx12;


--V1_reply_6 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_6
--operation mode is normal

V1_reply_6 = X1_request_6 & (V1_a_0_dup_53 # V1_read_data_25 & !V1_ix34_ix30_nx12) # !X1_request_6 & V1_read_data_25 & !V1_ix34_ix30_nx12;


--V1_reply_5 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_5
--operation mode is normal

V1_reply_5 = X1_request_5 & (V1_a_0_dup_53 # V1_read_data_26 & !V1_ix34_ix30_nx12) # !X1_request_5 & V1_read_data_26 & !V1_ix34_ix30_nx12;


--V1_reply_4 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_4
--operation mode is normal

V1_reply_4 = X1_request_4 & (V1_a_0_dup_53 # V1_read_data_27 & !V1_ix34_ix30_nx12) # !X1_request_4 & V1_read_data_27 & !V1_ix34_ix30_nx12;


--V1_reply_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_3
--operation mode is normal

V1_reply_3 = X1_request_3 & (V1_a_0_dup_53 # V1_read_data_28 & !V1_ix34_ix30_nx12) # !X1_request_3 & V1_read_data_28 & !V1_ix34_ix30_nx12;


--V1_reply_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_2
--operation mode is normal

V1_reply_2 = X1_request_2 & (V1_a_0_dup_53 # V1_read_data_29 & !V1_ix34_ix30_nx12) # !X1_request_2 & V1_read_data_29 & !V1_ix34_ix30_nx12;


--V1_reply_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_1
--operation mode is normal

V1_reply_1 = X1_request_1 & (V1_a_0_dup_53 # V1_read_data_30 & !V1_ix34_ix30_nx12) # !X1_request_1 & V1_read_data_30 & !V1_ix34_ix30_nx12;


--V1_reply_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_0
--operation mode is normal

V1_reply_0 = X1_request_0 & (V1_a_0_dup_53 # V1_read_data_31 & !V1_ix34_ix30_nx12) # !X1_request_0 & V1_read_data_31 & !V1_ix34_ix30_nx12;


--V1_reply_valid is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|reply_valid
--operation mode is normal

V1_reply_valid = !Z1_data_out_0 & (Z1_data_out_3 $ (Z1_data_out_2 # Z1_data_out_1));


--V1_altered_frame is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|altered_frame
--operation mode is normal

V1_altered_frame = !Z1_data_out_0 & (Z1_data_out_3 & !Z1_data_out_2 & !Z1_data_out_1 # !Z1_data_out_3 & (Z1_data_out_2 $ Z1_data_out_1));


--V1_bridge_alter is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|bridge_alter
--operation mode is normal

V1_bridge_alter = X1_request_valid & !Z1_data_out_3 & !Z1_data_out_2 & !V1_ix34_ix34_nx8;


--V1_cfg_req is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|cfg_req
--operation mode is normal

V1_cfg_req_lut_out = Z1_data_out_3 # Z1_data_out_0 # !Z1_data_out_2 & Z1_data_out_1;
V1_cfg_req = DFFEA(V1_cfg_req_lut_out, U1__clk0, VCC, , V1_nx1105, , );


--V1_chipRST_n is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|chipRST_n
--operation mode is normal

V1_chipRST_n_lut_out = Z1_data_out_2 # !Z1_data_out_0 # !Z1_data_out_1 # !Z1_data_out_3;
V1_chipRST_n = DFFEA(V1_chipRST_n_lut_out, U1__clk0, VCC, , , , );


--V1_current_state_dp_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|current_state_dp_0
--operation mode is normal

V1_current_state_dp_0_lut_out = V1_current_state_dp_2 # V1_current_state_dp_0 & !V1_nx426 # !V1_current_state_dp_0 & !V1_bus_req;
V1_current_state_dp_0 = DFFEA(V1_current_state_dp_0_lut_out, U1__clk0, VCC, , , , );


--V1_bus_req is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|bus_req
--operation mode is normal

V1_bus_req_lut_out = !V1_current_state_dp_2 & V1_current_state_dp_0 & V1_nx426;
V1_bus_req = DFFEA(V1_bus_req_lut_out, U1__clk0, VCC, , V1_nx410, , );


--V1_current_state_dp_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|current_state_dp_2
--operation mode is normal

V1_current_state_dp_2_lut_out = G1_bus_ack & !V1_current_state_dp_2 & !V1_current_state_dp_0 & V1_bus_req;
V1_current_state_dp_2 = DFFEA(V1_current_state_dp_2_lut_out, U1__clk0, VCC, , , , );


--V1_long_transaction is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|long_transaction
--operation mode is normal

V1_long_transaction_lut_out = X1_request_31;
V1_long_transaction = DFFEA(V1_long_transaction_lut_out, U1__clk0, VCC, , V1_nx241, , );


--V1_rd_wr_oase is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|rd_wr_oase
--operation mode is normal

V1_rd_wr_oase_lut_out = X1_request_52 # X1_request_50 # !X1_request_49 # !X1_request_51;
V1_rd_wr_oase = DFFEA(V1_rd_wr_oase_lut_out, U1__clk0, VCC, , , , );


--V1_read_data_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_0
--operation mode is normal

V1_read_data_0_lut_out = G1_bus_dout_0;
V1_read_data_0 = DFFEA(V1_read_data_0_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_1
--operation mode is normal

V1_read_data_1_lut_out = G1_bus_dout_1;
V1_read_data_1 = DFFEA(V1_read_data_1_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_10 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_10
--operation mode is normal

V1_read_data_10_lut_out = G1_bus_dout_10;
V1_read_data_10 = DFFEA(V1_read_data_10_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_11 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_11
--operation mode is normal

V1_read_data_11_lut_out = G1_bus_dout_11;
V1_read_data_11 = DFFEA(V1_read_data_11_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_12 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_12
--operation mode is normal

V1_read_data_12_lut_out = G1_bus_dout_12;
V1_read_data_12 = DFFEA(V1_read_data_12_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_13 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_13
--operation mode is normal

V1_read_data_13_lut_out = G1_bus_dout_13;
V1_read_data_13 = DFFEA(V1_read_data_13_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_14 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_14
--operation mode is normal

V1_read_data_14_lut_out = G1_bus_dout_14;
V1_read_data_14 = DFFEA(V1_read_data_14_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_15 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_15
--operation mode is normal

V1_read_data_15_lut_out = G1_bus_dout_15;
V1_read_data_15 = DFFEA(V1_read_data_15_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_16 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_16
--operation mode is normal

V1_read_data_16_lut_out = G1_bus_dout_16;
V1_read_data_16 = DFFEA(V1_read_data_16_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_17 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_17
--operation mode is normal

V1_read_data_17_lut_out = G1_bus_dout_17;
V1_read_data_17 = DFFEA(V1_read_data_17_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_18 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_18
--operation mode is normal

V1_read_data_18_lut_out = G1_bus_dout_18;
V1_read_data_18 = DFFEA(V1_read_data_18_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_19 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_19
--operation mode is normal

V1_read_data_19_lut_out = G1_bus_dout_19;
V1_read_data_19 = DFFEA(V1_read_data_19_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_2
--operation mode is normal

V1_read_data_2_lut_out = G1_bus_dout_2;
V1_read_data_2 = DFFEA(V1_read_data_2_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_20 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_20
--operation mode is normal

V1_read_data_20_lut_out = G1_bus_dout_20;
V1_read_data_20 = DFFEA(V1_read_data_20_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_21 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_21
--operation mode is normal

V1_read_data_21_lut_out = G1_bus_dout_21;
V1_read_data_21 = DFFEA(V1_read_data_21_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_22 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_22
--operation mode is normal

V1_read_data_22_lut_out = G1_bus_dout_22;
V1_read_data_22 = DFFEA(V1_read_data_22_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_23 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_23
--operation mode is normal

V1_read_data_23_lut_out = G1_bus_dout_23;
V1_read_data_23 = DFFEA(V1_read_data_23_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_24 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_24
--operation mode is normal

V1_read_data_24_lut_out = G1_bus_dout_24;
V1_read_data_24 = DFFEA(V1_read_data_24_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_25 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_25
--operation mode is normal

V1_read_data_25_lut_out = G1_bus_dout_25;
V1_read_data_25 = DFFEA(V1_read_data_25_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_26 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_26
--operation mode is normal

V1_read_data_26_lut_out = G1_bus_dout_26;
V1_read_data_26 = DFFEA(V1_read_data_26_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_27 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_27
--operation mode is normal

V1_read_data_27_lut_out = G1_bus_dout_27;
V1_read_data_27 = DFFEA(V1_read_data_27_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_28 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_28
--operation mode is normal

V1_read_data_28_lut_out = G1_bus_dout_28;
V1_read_data_28 = DFFEA(V1_read_data_28_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_29 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_29
--operation mode is normal

V1_read_data_29_lut_out = G1_bus_dout_29;
V1_read_data_29 = DFFEA(V1_read_data_29_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_3
--operation mode is normal

V1_read_data_3_lut_out = G1_bus_dout_3;
V1_read_data_3 = DFFEA(V1_read_data_3_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_30 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_30
--operation mode is normal

V1_read_data_30_lut_out = G1_bus_dout_30;
V1_read_data_30 = DFFEA(V1_read_data_30_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_31 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_31
--operation mode is normal

V1_read_data_31_lut_out = G1_bus_dout_31;
V1_read_data_31 = DFFEA(V1_read_data_31_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_4 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_4
--operation mode is normal

V1_read_data_4_lut_out = G1_bus_dout_4;
V1_read_data_4 = DFFEA(V1_read_data_4_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_5 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_5
--operation mode is normal

V1_read_data_5_lut_out = G1_bus_dout_5;
V1_read_data_5 = DFFEA(V1_read_data_5_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_6 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_6
--operation mode is normal

V1_read_data_6_lut_out = G1_bus_dout_6;
V1_read_data_6 = DFFEA(V1_read_data_6_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_7 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_7
--operation mode is normal

V1_read_data_7_lut_out = G1_bus_dout_7;
V1_read_data_7 = DFFEA(V1_read_data_7_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_8 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_8
--operation mode is normal

V1_read_data_8_lut_out = G1_bus_dout_8;
V1_read_data_8 = DFFEA(V1_read_data_8_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_read_data_9 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|read_data_9
--operation mode is normal

V1_read_data_9_lut_out = G1_bus_dout_9;
V1_read_data_9 = DFFEA(V1_read_data_9_lut_out, U1__clk0, VCC, , V1_nx397, , );


--V1_req_reg is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|req_reg
--operation mode is normal

V1_req_reg_lut_out = V1_cfg_req;
V1_req_reg = DFFEA(V1_req_reg_lut_out, U1__clk0, VCC, , , , );


--V1_waitcount_4 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_4
--operation mode is arithmetic

V1_waitcount_4_carry_eqn = V1_waitcount_nx33;
V1_waitcount_4_lut_out = V1_waitcount_4 $ V1_waitcount_4_carry_eqn;
V1_waitcount_4_sload_eqn = (V1_nx383 & ~GND) # (!V1_nx383 & V1_waitcount_4_lut_out);
V1_waitcount_4 = DFFEA(V1_waitcount_4_sload_eqn, U1__clk0, VCC, , , , );

--V1_waitcount_nx37 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx37
--operation mode is arithmetic

V1_waitcount_nx37 = CARRY(V1_waitcount_4 # !V1_waitcount_nx33);


--V1_waitcount_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_3
--operation mode is arithmetic

V1_waitcount_3_carry_eqn = V1_waitcount_nx28;
V1_waitcount_3_lut_out = V1_waitcount_3 $ !V1_waitcount_3_carry_eqn;
V1_waitcount_3_sload_eqn = (V1_nx383 & VCC) # (!V1_nx383 & V1_waitcount_3_lut_out);
V1_waitcount_3 = DFFEA(V1_waitcount_3_sload_eqn, U1__clk0, VCC, , , , );

--V1_waitcount_nx33 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx33
--operation mode is arithmetic

V1_waitcount_nx33 = CARRY(!V1_waitcount_3 & !V1_waitcount_nx28);


--V1_waitcount_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_2
--operation mode is arithmetic

V1_waitcount_2_carry_eqn = V1_waitcount_nx21;
V1_waitcount_2_lut_out = V1_waitcount_2 $ V1_waitcount_2_carry_eqn;
V1_waitcount_2_sload_eqn = (V1_nx383 & ~GND) # (!V1_nx383 & V1_waitcount_2_lut_out);
V1_waitcount_2 = DFFEA(V1_waitcount_2_sload_eqn, U1__clk0, VCC, , , , );

--V1_waitcount_nx28 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx28
--operation mode is arithmetic

V1_waitcount_nx28 = CARRY(V1_waitcount_2 # !V1_waitcount_nx21);


--V1_waitcount_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_1
--operation mode is arithmetic

V1_waitcount_1_carry_eqn = V1_waitcount_nx15;
V1_waitcount_1_lut_out = V1_waitcount_1 $ !V1_waitcount_1_carry_eqn;
V1_waitcount_1_sload_eqn = (V1_nx383 & ~GND) # (!V1_nx383 & V1_waitcount_1_lut_out);
V1_waitcount_1 = DFFEA(V1_waitcount_1_sload_eqn, U1__clk0, VCC, , , , );

--V1_waitcount_nx21 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx21
--operation mode is arithmetic

V1_waitcount_nx21 = CARRY(!V1_waitcount_1 & !V1_waitcount_nx15);


--V1_waitcount_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_0
--operation mode is arithmetic

V1_waitcount_0_lut_out = V1_waitcount_0 $ V1_nx403;
V1_waitcount_0_sload_eqn = (V1_nx383 & ~GND) # (!V1_nx383 & V1_waitcount_0_lut_out);
V1_waitcount_0 = DFFEA(V1_waitcount_0_sload_eqn, U1__clk0, VCC, , , , );

--V1_waitcount_nx15 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_nx15
--operation mode is arithmetic

V1_waitcount_nx15 = CARRY(V1_waitcount_0 # !V1_nx403);


--V1_waitcount_5 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|waitcount_5
--operation mode is normal

V1_waitcount_5_carry_eqn = V1_waitcount_nx37;
V1_waitcount_5_lut_out = V1_waitcount_5 $ !V1_waitcount_5_carry_eqn;
V1_waitcount_5_sload_eqn = (V1_nx383 & ~GND) # (!V1_nx383 & V1_waitcount_5_lut_out);
V1_waitcount_5 = DFFEA(V1_waitcount_5_sload_eqn, U1__clk0, VCC, , , , );


--Z1_data_out_0 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1|data_out_0
--operation mode is normal

Z1_data_out_0_lut_out = V1_next_state_0;
Z1_data_out_0 = DFFEA(Z1_data_out_0_lut_out, U1__clk0, VCC, , , , );


--Z1_data_out_1 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1|data_out_1
--operation mode is normal

Z1_data_out_1_lut_out = V1_next_state_1;
Z1_data_out_1 = DFFEA(Z1_data_out_1_lut_out, U1__clk0, VCC, , , , );


--Z1_data_out_2 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1|data_out_2
--operation mode is normal

Z1_data_out_2_lut_out = V1_next_state_2;
Z1_data_out_2 = DFFEA(Z1_data_out_2_lut_out, U1__clk0, VCC, , , , );


--Z1_data_out_3 is mcm_network_interface:scsn_slave|mcm_nw_apl:nw_apl|hamm_reg_4_0_1_unfolded0:h1|data_out_3
--operation mode is normal

Z1_data_out_3_lut_out = V1_next_state_3;
Z1_data_out_3 = DFFEA(Z1_data_out_3_lut_out, U1__clk0, VCC, , , , );


--U1__clk0 is pll120:PLL|altpll:altpll_component|_clk0
U1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(GND), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(CLK_gen), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--U1__clk1 is pll120:PLL|altpll:altpll_component|_clk1
U1__clk1 = PLL.CLK1(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(GND), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(CLK_gen), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--B1_nx884 is ADC_DAC_0:adcdac|nx884
--operation mode is normal

B1_nx884 = K1_cl_1 # K1_cl_0 # !V1_rd_wr_oase & G1_ce_shutdn;


--B1_nx886 is ADC_DAC_0:adcdac|nx886
--operation mode is normal

B1_nx886 = K1_cl_1 # !V1_rd_wr_oase & G1_ce_shutdn;


--B1_SlowDAC_Din is ADC_DAC_0:adcdac|SlowDAC_Din
--operation mode is normal

B1_SlowDAC_Din = M1_SDAT # M2_SDAT;


--B1_AD_SYNC_OUT_0 is ADC_DAC_0:adcdac|AD_SYNC_OUT_0
--operation mode is normal

B1_AD_SYNC_OUT_0_lut_out = AD_SYNC_IN[0];
B1_AD_SYNC_OUT_0 = DFFEA(B1_AD_SYNC_OUT_0_lut_out, U1__clk1, VCC, , , , );


--B1_AD_SYNC_OUT_1 is ADC_DAC_0:adcdac|AD_SYNC_OUT_1
--operation mode is normal

B1_AD_SYNC_OUT_1_lut_out = AD_SYNC_IN[1];
B1_AD_SYNC_OUT_1 = DFFEA(B1_AD_SYNC_OUT_1_lut_out, U1__clk1, VCC, , , , );


--B1_VMCM_Shdwn_a is ADC_DAC_0:adcdac|VMCM_Shdwn_a
--operation mode is normal

B1_VMCM_Shdwn_a_lut_out = X1_request_31 & !K1_cl_1 & !K1_cl_0;
B1_VMCM_Shdwn_a = DFFEA(B1_VMCM_Shdwn_a_lut_out, U1__clk1, V1_chipRST_n, , B1_nx884, , );


--B1_VMCM_Shdwn_d is ADC_DAC_0:adcdac|VMCM_Shdwn_d
--operation mode is normal

B1_VMCM_Shdwn_d_lut_out = X1_request_30 & !K1_cl_1;
B1_VMCM_Shdwn_d = DFFEA(B1_VMCM_Shdwn_d_lut_out, U1__clk1, V1_chipRST_n, , B1_nx886, , );


--M2_CNT_FF_2 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|CNT_FF_2
--operation mode is arithmetic

M2_CNT_FF_2_carry_eqn = M2_CNT_FF_nx16;
M2_CNT_FF_2_lut_out = M2_CNT_FF_2 $ M2_CNT_FF_2_carry_eqn;
M2_CNT_FF_2_reg_input = M2_SERREG_2 & M2_CNT_FF_2_lut_out;
M2_CNT_FF_2 = DFFEA(M2_CNT_FF_2_reg_input, U1__clk1, V1_chipRST_n, , M2_NOT_nx413, , );

--M2_CNT_FF_nx21 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|CNT_FF_nx21
--operation mode is arithmetic

M2_CNT_FF_nx21 = CARRY(M2_CNT_FF_2 # !M2_CNT_FF_nx16);


--M2_CNT_FF_1 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|CNT_FF_1
--operation mode is arithmetic

M2_CNT_FF_1_carry_eqn = M2_CNT_FF_nx10;
M2_CNT_FF_1_lut_out = M2_CNT_FF_1 $ !M2_CNT_FF_1_carry_eqn;
M2_CNT_FF_1_reg_input = M2_SERREG_2 & M2_CNT_FF_1_lut_out;
M2_CNT_FF_1 = DFFEA(M2_CNT_FF_1_reg_input, U1__clk1, V1_chipRST_n, , M2_NOT_nx413, , );

--M2_CNT_FF_nx16 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|CNT_FF_nx16
--operation mode is arithmetic

M2_CNT_FF_nx16 = CARRY(!M2_CNT_FF_1 & !M2_CNT_FF_nx10);


--M2_CNT_FF_0 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|CNT_FF_0
--operation mode is arithmetic

M2_CNT_FF_0_lut_out = !M2_CNT_FF_0;
M2_CNT_FF_0_reg_input = M2_SERREG_2 & M2_CNT_FF_0_lut_out;
M2_CNT_FF_0 = DFFEA(M2_CNT_FF_0_reg_input, U1__clk1, V1_chipRST_n, , M2_NOT_nx413, , );

--M2_CNT_FF_nx10 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|CNT_FF_nx10
--operation mode is arithmetic

M2_CNT_FF_nx10 = CARRY(M2_CNT_FF_0);


--M2_CNT_FF_3 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|CNT_FF_3
--operation mode is normal

M2_CNT_FF_3_carry_eqn = M2_CNT_FF_nx21;
M2_CNT_FF_3_lut_out = M2_CNT_FF_3 $ !M2_CNT_FF_3_carry_eqn;
M2_CNT_FF_3_reg_input = M2_SERREG_2 & M2_CNT_FF_3_lut_out;
M2_CNT_FF_3 = DFFEA(M2_CNT_FF_3_reg_input, U1__clk1, V1_chipRST_n, , M2_NOT_nx413, , );


--M2_dcounter_nx38 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|dcounter_nx38
--operation mode is arithmetic

M2_dcounter_nx38_carry_eqn = M2_dcounter_nx9;
M2_dcounter_nx38_lut_out = M2_dcounter_nx38 $ !M2_dcounter_nx38_carry_eqn;
M2_dcounter_nx38_sload_eqn = (M2_LOAD & ~GND) # (!M2_LOAD & M2_dcounter_nx38_lut_out);
M2_dcounter_nx38 = DFFEA(M2_dcounter_nx38_sload_eqn, U1__clk1, V1_chipRST_n, , , , );

--M2_dcounter_nx15 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|dcounter_nx15
--operation mode is arithmetic

M2_dcounter_nx15 = CARRY(M2_dcounter_nx38 & !M2_dcounter_nx9);


--M2_dcounter_nx45 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|dcounter_nx45
--operation mode is arithmetic

M2_dcounter_nx45_lut_out = !M2_dcounter_nx45;
M2_dcounter_nx45_sload_eqn = (M2_LOAD & ~GND) # (!M2_LOAD & M2_dcounter_nx45_lut_out);
M2_dcounter_nx45 = DFFEA(M2_dcounter_nx45_sload_eqn, U1__clk1, V1_chipRST_n, , , , );

--M2_dcounter_nx9 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|dcounter_nx9
--operation mode is arithmetic

M2_dcounter_nx9 = CARRY(!M2_dcounter_nx45);


--M2_dcounter_nx23 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|dcounter_nx23
--operation mode is normal

M2_dcounter_nx23_carry_eqn = M2_dcounter_nx20;
M2_dcounter_nx23_lut_out = M2_dcounter_nx23 $ !M2_dcounter_nx23_carry_eqn;
M2_dcounter_nx23_sload_eqn = (M2_LOAD & ~GND) # (!M2_LOAD & M2_dcounter_nx23_lut_out);
M2_dcounter_nx23 = DFFEA(M2_dcounter_nx23_sload_eqn, U1__clk1, V1_chipRST_n, , , , );


--M2_dcounter_nx30 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|dcounter_nx30
--operation mode is arithmetic

M2_dcounter_nx30_carry_eqn = M2_dcounter_nx15;
M2_dcounter_nx30_lut_out = M2_dcounter_nx30 $ M2_dcounter_nx30_carry_eqn;
M2_dcounter_nx30_sload_eqn = (M2_LOAD & ~GND) # (!M2_LOAD & M2_dcounter_nx30_lut_out);
M2_dcounter_nx30 = DFFEA(M2_dcounter_nx30_sload_eqn, U1__clk1, V1_chipRST_n, , , , );

--M2_dcounter_nx20 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|dcounter_nx20
--operation mode is arithmetic

M2_dcounter_nx20 = CARRY(!M2_dcounter_nx15 # !M2_dcounter_nx30);


--M2_NOT_nx154 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|NOT_nx154
--operation mode is normal

M2_NOT_nx154 = G1_ce_2sdac & !V1_rd_wr_oase & !M2_SERREG_1 & !M2_nx116;


--M2_NOT_nx150 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|NOT_nx150
--operation mode is normal

M2_NOT_nx150 = M2_SERREG_1 & M2_cnt_div # !M2_SERREG_1 & M2_nx52 & !M2_nx116;


--M2_LOAD is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|LOAD
--operation mode is normal

M2_LOAD = !M2_SL & !M2_nx116;


--M2_NOT_nx413 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|NOT_nx413
--operation mode is normal

M2_NOT_nx413 = M2_cnt_div & (M2_SERREG_2 # !M2_nx116);


--M2_nx521 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|nx521
--operation mode is normal

M2_nx521 = M2_nx116 # G1_ce_2sdac & !V1_rd_wr_oase;


--M2_nx142 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|nx142
--operation mode is normal

M2_nx142 = !M2_CNT_FF_3 & !M2_CNT_FF_2 & !M2_CNT_FF_1 & !M2_CNT_FF_0;


--M2_nx143 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|nx143
--operation mode is normal

M2_nx143 = M2_SERREG_1 & (M2_CNT_FF_2 # M2_CNT_FF_1 # M2_CNT_FF_0);


--M2_nx144 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|nx144
--operation mode is normal

M2_nx144 = M2_SL & (M2_SERREG_1 & !M2_NOT_CNT_FF_4 # !M2_nx116) # !M2_SL & M2_SERREG_1 & !M2_NOT_CNT_FF_4;


--M2_SDAT is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|SDAT
--operation mode is normal

M2_SDAT = M2_PQ_15 & M2_nx116;


--M2_cnt_div is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|cnt_div
--operation mode is normal

M2_cnt_div_lut_out = M2_dcounter_nx23 & M2_dcounter_nx30 & M2_dcounter_nx38 & M2_dcounter_nx45;
M2_cnt_div = DFFEA(M2_cnt_div_lut_out, U1__clk1, V1_chipRST_n, , , , );


--M2_NOT_CNT_FF_4 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|NOT_CNT_FF_4
--operation mode is normal

M2_NOT_CNT_FF_4_lut_out = M2_nx116;
M2_NOT_CNT_FF_4 = DFFEA(M2_NOT_CNT_FF_4_lut_out, U1__clk1, V1_chipRST_n, , M2_NOT_nx413, , );


--M2_PQ_dup0_0 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_dup0_0
--operation mode is normal

M2_PQ_dup0_0_lut_out = X1_request_31;
M2_PQ_dup0_0_sload_eqn = (M2_SERREG_1 & M2_PQ_15) # (!M2_SERREG_1 & M2_PQ_dup0_0_lut_out);
M2_PQ_dup0_0 = DFFEA(M2_PQ_dup0_0_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_1 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_1
--operation mode is normal

M2_PQ_1_lut_out = X1_request_30;
M2_PQ_1_sload_eqn = (M2_SERREG_1 & M2_PQ_dup0_0) # (!M2_SERREG_1 & M2_PQ_1_lut_out);
M2_PQ_1 = DFFEA(M2_PQ_1_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_10 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_10
--operation mode is normal

M2_PQ_10_lut_out = X1_request_21;
M2_PQ_10_sload_eqn = (M2_SERREG_1 & M2_PQ_9) # (!M2_SERREG_1 & M2_PQ_10_lut_out);
M2_PQ_10 = DFFEA(M2_PQ_10_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_11 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_11
--operation mode is normal

M2_PQ_11_lut_out = X1_request_20;
M2_PQ_11_sload_eqn = (M2_SERREG_1 & M2_PQ_10) # (!M2_SERREG_1 & M2_PQ_11_lut_out);
M2_PQ_11 = DFFEA(M2_PQ_11_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_12 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_12
--operation mode is normal

M2_PQ_12_lut_out = X1_request_19;
M2_PQ_12_sload_eqn = (M2_SERREG_1 & M2_PQ_11) # (!M2_SERREG_1 & M2_PQ_12_lut_out);
M2_PQ_12 = DFFEA(M2_PQ_12_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_13 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_13
--operation mode is normal

M2_PQ_13_lut_out = X1_request_18;
M2_PQ_13_sload_eqn = (M2_SERREG_1 & M2_PQ_12) # (!M2_SERREG_1 & M2_PQ_13_lut_out);
M2_PQ_13 = DFFEA(M2_PQ_13_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_14 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_14
--operation mode is normal

M2_PQ_14_lut_out = X1_request_17;
M2_PQ_14_sload_eqn = (M2_SERREG_1 & M2_PQ_13) # (!M2_SERREG_1 & M2_PQ_14_lut_out);
M2_PQ_14 = DFFEA(M2_PQ_14_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_15 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_15
--operation mode is normal

M2_PQ_15_lut_out = X1_request_16;
M2_PQ_15_sload_eqn = (M2_SERREG_1 & M2_PQ_14) # (!M2_SERREG_1 & M2_PQ_15_lut_out);
M2_PQ_15 = DFFEA(M2_PQ_15_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_2 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_2
--operation mode is normal

M2_PQ_2_lut_out = X1_request_29;
M2_PQ_2_sload_eqn = (M2_SERREG_1 & M2_PQ_1) # (!M2_SERREG_1 & M2_PQ_2_lut_out);
M2_PQ_2 = DFFEA(M2_PQ_2_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_3 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_3
--operation mode is normal

M2_PQ_3_lut_out = X1_request_28;
M2_PQ_3_sload_eqn = (M2_SERREG_1 & M2_PQ_2) # (!M2_SERREG_1 & M2_PQ_3_lut_out);
M2_PQ_3 = DFFEA(M2_PQ_3_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_4 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_4
--operation mode is normal

M2_PQ_4_lut_out = X1_request_27;
M2_PQ_4_sload_eqn = (M2_SERREG_1 & M2_PQ_3) # (!M2_SERREG_1 & M2_PQ_4_lut_out);
M2_PQ_4 = DFFEA(M2_PQ_4_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_5 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_5
--operation mode is normal

M2_PQ_5_lut_out = X1_request_26;
M2_PQ_5_sload_eqn = (M2_SERREG_1 & M2_PQ_4) # (!M2_SERREG_1 & M2_PQ_5_lut_out);
M2_PQ_5 = DFFEA(M2_PQ_5_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_6 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_6
--operation mode is normal

M2_PQ_6_lut_out = X1_request_25;
M2_PQ_6_sload_eqn = (M2_SERREG_1 & M2_PQ_5) # (!M2_SERREG_1 & M2_PQ_6_lut_out);
M2_PQ_6 = DFFEA(M2_PQ_6_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_7 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_7
--operation mode is normal

M2_PQ_7_lut_out = X1_request_24;
M2_PQ_7_sload_eqn = (M2_SERREG_1 & M2_PQ_6) # (!M2_SERREG_1 & M2_PQ_7_lut_out);
M2_PQ_7 = DFFEA(M2_PQ_7_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_8 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_8
--operation mode is normal

M2_PQ_8_lut_out = X1_request_23;
M2_PQ_8_sload_eqn = (M2_SERREG_1 & M2_PQ_7) # (!M2_SERREG_1 & M2_PQ_8_lut_out);
M2_PQ_8 = DFFEA(M2_PQ_8_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_9 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_9
--operation mode is normal

M2_PQ_9_lut_out = X1_request_22;
M2_PQ_9_sload_eqn = (M2_SERREG_1 & M2_PQ_8) # (!M2_SERREG_1 & M2_PQ_9_lut_out);
M2_PQ_9 = DFFEA(M2_PQ_9_sload_eqn, U1__clk1, VCC, , M2_NOT_nx150, , );


--M2_PQ_16 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|PQ_16
--operation mode is normal

M2_PQ_16_lut_out = X1_request_15;
M2_PQ_16 = DFFEA(M2_PQ_16_lut_out, U1__clk1, VCC, , M2_NOT_nx154, , );


--M2_NOT_LDACn is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|NOT_LDACn
--operation mode is normal

M2_NOT_LDACn_lut_out = M2_PQ_16 & (M2_SERREG_5 & M2_SL # !M2_SERREG_5 & M2_SERREG_4);
M2_NOT_LDACn = DFFEA(M2_NOT_LDACn_lut_out, U1__clk1, V1_chipRST_n, , M2_cnt_div, , );


--M2_SCLK is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|SCLK
--operation mode is normal

M2_SCLK_lut_out = !M2_SERREG_3 & !M2_SERREG_2;
M2_SCLK = DFFEA(M2_SCLK_lut_out, U1__clk1, V1_chipRST_n, , M2_cnt_div, , );


--M2_nx116 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|nx116
--operation mode is normal

M2_nx116_lut_out = M2_SL # !M2_SERREG_5 & M2_nx116;
M2_nx116 = DFFEA(M2_nx116_lut_out, U1__clk1, V1_chipRST_n, , M2_cnt_div, , );


--M2_SERREG_1 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|SERREG_1
--operation mode is normal

M2_SERREG_1_lut_out = M2_SERREG_2;
M2_SERREG_1 = DFFEA(M2_SERREG_1_lut_out, U1__clk1, V1_chipRST_n, , M2_cnt_div, , );


--M2_SERREG_2 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|SERREG_2
--operation mode is normal

M2_SERREG_2_lut_out = M2_nx143 # M2_nx144 # M2_CNT_FF_3 & M2_SERREG_1;
M2_SERREG_2 = DFFEA(M2_SERREG_2_lut_out, U1__clk1, V1_chipRST_n, , M2_cnt_div, , );


--M2_SERREG_3 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|SERREG_3
--operation mode is normal

M2_SERREG_3_lut_out = M2_SERREG_1 & M2_NOT_CNT_FF_4 & M2_nx142;
M2_SERREG_3 = DFFEA(M2_SERREG_3_lut_out, U1__clk1, V1_chipRST_n, , M2_cnt_div, , );


--M2_SERREG_4 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|SERREG_4
--operation mode is normal

M2_SERREG_4_lut_out = M2_SERREG_3;
M2_SERREG_4 = DFFEA(M2_SERREG_4_lut_out, U1__clk1, V1_chipRST_n, , M2_cnt_div, , );


--M2_SERREG_5 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|SERREG_5
--operation mode is normal

M2_SERREG_5_lut_out = M2_SERREG_4 # M2_SL & M2_SERREG_5;
M2_SERREG_5 = DFFEA(M2_SERREG_5_lut_out, U1__clk1, V1_chipRST_n, , M2_cnt_div, , );


--M2_nx52 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|nx52
--operation mode is normal

M2_nx52 = G1_ce_2sdac & !V1_rd_wr_oase;

--M2_SL is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|SL
--operation mode is normal

M2_SL = DFFEA(M2_nx52, U1__clk1, VCC, , M2_nx521, , );


--M2_SSTR is ADC_DAC_0:adcdac|TLV5630_16:slow_dac2|SSTR
--operation mode is normal

M2_SSTR_lut_out = M2_SERREG_3 # M2_SERREG_1 & M2_NOT_CNT_FF_4 & M2_nx142;
M2_SSTR = DFFEA(M2_SSTR_lut_out, U1__clk1, V1_chipRST_n, , M2_cnt_div, , );


--M1_CNT_FF_2 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|CNT_FF_2
--operation mode is arithmetic

M1_CNT_FF_2_carry_eqn = M1_CNT_FF_nx16;
M1_CNT_FF_2_lut_out = M1_CNT_FF_2 $ M1_CNT_FF_2_carry_eqn;
M1_CNT_FF_2_reg_input = M1_SERREG_2 & M1_CNT_FF_2_lut_out;
M1_CNT_FF_2 = DFFEA(M1_CNT_FF_2_reg_input, U1__clk1, V1_chipRST_n, , M1_NOT_nx413, , );

--M1_CNT_FF_nx21 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|CNT_FF_nx21
--operation mode is arithmetic

M1_CNT_FF_nx21 = CARRY(M1_CNT_FF_2 # !M1_CNT_FF_nx16);


--M1_CNT_FF_1 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|CNT_FF_1
--operation mode is arithmetic

M1_CNT_FF_1_carry_eqn = M1_CNT_FF_nx10;
M1_CNT_FF_1_lut_out = M1_CNT_FF_1 $ !M1_CNT_FF_1_carry_eqn;
M1_CNT_FF_1_reg_input = M1_SERREG_2 & M1_CNT_FF_1_lut_out;
M1_CNT_FF_1 = DFFEA(M1_CNT_FF_1_reg_input, U1__clk1, V1_chipRST_n, , M1_NOT_nx413, , );

--M1_CNT_FF_nx16 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|CNT_FF_nx16
--operation mode is arithmetic

M1_CNT_FF_nx16 = CARRY(!M1_CNT_FF_1 & !M1_CNT_FF_nx10);


--M1_CNT_FF_0 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|CNT_FF_0
--operation mode is arithmetic

M1_CNT_FF_0_lut_out = !M1_CNT_FF_0;
M1_CNT_FF_0_reg_input = M1_SERREG_2 & M1_CNT_FF_0_lut_out;
M1_CNT_FF_0 = DFFEA(M1_CNT_FF_0_reg_input, U1__clk1, V1_chipRST_n, , M1_NOT_nx413, , );

--M1_CNT_FF_nx10 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|CNT_FF_nx10
--operation mode is arithmetic

M1_CNT_FF_nx10 = CARRY(M1_CNT_FF_0);


--M1_CNT_FF_3 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|CNT_FF_3
--operation mode is normal

M1_CNT_FF_3_carry_eqn = M1_CNT_FF_nx21;
M1_CNT_FF_3_lut_out = M1_CNT_FF_3 $ !M1_CNT_FF_3_carry_eqn;
M1_CNT_FF_3_reg_input = M1_SERREG_2 & M1_CNT_FF_3_lut_out;
M1_CNT_FF_3 = DFFEA(M1_CNT_FF_3_reg_input, U1__clk1, V1_chipRST_n, , M1_NOT_nx413, , );


--M1_dcounter_nx38 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|dcounter_nx38
--operation mode is arithmetic

M1_dcounter_nx38_carry_eqn = M1_dcounter_nx9;
M1_dcounter_nx38_lut_out = M1_dcounter_nx38 $ !M1_dcounter_nx38_carry_eqn;
M1_dcounter_nx38_sload_eqn = (M1_LOAD & ~GND) # (!M1_LOAD & M1_dcounter_nx38_lut_out);
M1_dcounter_nx38 = DFFEA(M1_dcounter_nx38_sload_eqn, U1__clk1, V1_chipRST_n, , , , );

--M1_dcounter_nx15 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|dcounter_nx15
--operation mode is arithmetic

M1_dcounter_nx15 = CARRY(M1_dcounter_nx38 & !M1_dcounter_nx9);


--M1_dcounter_nx45 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|dcounter_nx45
--operation mode is arithmetic

M1_dcounter_nx45_lut_out = !M1_dcounter_nx45;
M1_dcounter_nx45_sload_eqn = (M1_LOAD & ~GND) # (!M1_LOAD & M1_dcounter_nx45_lut_out);
M1_dcounter_nx45 = DFFEA(M1_dcounter_nx45_sload_eqn, U1__clk1, V1_chipRST_n, , , , );

--M1_dcounter_nx9 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|dcounter_nx9
--operation mode is arithmetic

M1_dcounter_nx9 = CARRY(!M1_dcounter_nx45);


--M1_dcounter_nx23 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|dcounter_nx23
--operation mode is normal

M1_dcounter_nx23_carry_eqn = M1_dcounter_nx20;
M1_dcounter_nx23_lut_out = M1_dcounter_nx23 $ !M1_dcounter_nx23_carry_eqn;
M1_dcounter_nx23_sload_eqn = (M1_LOAD & ~GND) # (!M1_LOAD & M1_dcounter_nx23_lut_out);
M1_dcounter_nx23 = DFFEA(M1_dcounter_nx23_sload_eqn, U1__clk1, V1_chipRST_n, , , , );


--M1_dcounter_nx30 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|dcounter_nx30
--operation mode is arithmetic

M1_dcounter_nx30_carry_eqn = M1_dcounter_nx15;
M1_dcounter_nx30_lut_out = M1_dcounter_nx30 $ M1_dcounter_nx30_carry_eqn;
M1_dcounter_nx30_sload_eqn = (M1_LOAD & ~GND) # (!M1_LOAD & M1_dcounter_nx30_lut_out);
M1_dcounter_nx30 = DFFEA(M1_dcounter_nx30_sload_eqn, U1__clk1, V1_chipRST_n, , , , );

--M1_dcounter_nx20 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|dcounter_nx20
--operation mode is arithmetic

M1_dcounter_nx20 = CARRY(!M1_dcounter_nx15 # !M1_dcounter_nx30);


--M1_NOT_nx154 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|NOT_nx154
--operation mode is normal

M1_NOT_nx154 = G1_ce_1sdac & !V1_rd_wr_oase & !M1_SERREG_1 & !M1_nx116;


--M1_NOT_nx150 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|NOT_nx150
--operation mode is normal

M1_NOT_nx150 = M1_SERREG_1 & M1_cnt_div # !M1_SERREG_1 & M1_nx52 & !M1_nx116;


--M1_LOAD is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|LOAD
--operation mode is normal

M1_LOAD = !M1_SL & !M1_nx116;


--M1_NOT_nx413 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|NOT_nx413
--operation mode is normal

M1_NOT_nx413 = M1_cnt_div & (M1_SERREG_2 # !M1_nx116);


--M1_nx521 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|nx521
--operation mode is normal

M1_nx521 = M1_nx116 # G1_ce_1sdac & !V1_rd_wr_oase;


--M1_nx142 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|nx142
--operation mode is normal

M1_nx142 = !M1_CNT_FF_3 & !M1_CNT_FF_2 & !M1_CNT_FF_1 & !M1_CNT_FF_0;


--M1_nx143 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|nx143
--operation mode is normal

M1_nx143 = M1_SERREG_1 & (M1_CNT_FF_2 # M1_CNT_FF_1 # M1_CNT_FF_0);


--M1_nx144 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|nx144
--operation mode is normal

M1_nx144 = M1_SL & (M1_SERREG_1 & !M1_NOT_CNT_FF_4 # !M1_nx116) # !M1_SL & M1_SERREG_1 & !M1_NOT_CNT_FF_4;


--M1_SDAT is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|SDAT
--operation mode is normal

M1_SDAT = M1_PQ_15 & M1_nx116;


--M1_cnt_div is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|cnt_div
--operation mode is normal

M1_cnt_div_lut_out = M1_dcounter_nx23 & M1_dcounter_nx30 & M1_dcounter_nx38 & M1_dcounter_nx45;
M1_cnt_div = DFFEA(M1_cnt_div_lut_out, U1__clk1, V1_chipRST_n, , , , );


--M1_NOT_CNT_FF_4 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|NOT_CNT_FF_4
--operation mode is normal

M1_NOT_CNT_FF_4_lut_out = M1_nx116;
M1_NOT_CNT_FF_4 = DFFEA(M1_NOT_CNT_FF_4_lut_out, U1__clk1, V1_chipRST_n, , M1_NOT_nx413, , );


--M1_PQ_dup0_0 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_dup0_0
--operation mode is normal

M1_PQ_dup0_0_lut_out = X1_request_31;
M1_PQ_dup0_0_sload_eqn = (M1_SERREG_1 & M1_PQ_15) # (!M1_SERREG_1 & M1_PQ_dup0_0_lut_out);
M1_PQ_dup0_0 = DFFEA(M1_PQ_dup0_0_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_1 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_1
--operation mode is normal

M1_PQ_1_lut_out = X1_request_30;
M1_PQ_1_sload_eqn = (M1_SERREG_1 & M1_PQ_dup0_0) # (!M1_SERREG_1 & M1_PQ_1_lut_out);
M1_PQ_1 = DFFEA(M1_PQ_1_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_10 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_10
--operation mode is normal

M1_PQ_10_lut_out = X1_request_21;
M1_PQ_10_sload_eqn = (M1_SERREG_1 & M1_PQ_9) # (!M1_SERREG_1 & M1_PQ_10_lut_out);
M1_PQ_10 = DFFEA(M1_PQ_10_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_11 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_11
--operation mode is normal

M1_PQ_11_lut_out = X1_request_20;
M1_PQ_11_sload_eqn = (M1_SERREG_1 & M1_PQ_10) # (!M1_SERREG_1 & M1_PQ_11_lut_out);
M1_PQ_11 = DFFEA(M1_PQ_11_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_12 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_12
--operation mode is normal

M1_PQ_12_lut_out = X1_request_19;
M1_PQ_12_sload_eqn = (M1_SERREG_1 & M1_PQ_11) # (!M1_SERREG_1 & M1_PQ_12_lut_out);
M1_PQ_12 = DFFEA(M1_PQ_12_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_13 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_13
--operation mode is normal

M1_PQ_13_lut_out = X1_request_18;
M1_PQ_13_sload_eqn = (M1_SERREG_1 & M1_PQ_12) # (!M1_SERREG_1 & M1_PQ_13_lut_out);
M1_PQ_13 = DFFEA(M1_PQ_13_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_14 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_14
--operation mode is normal

M1_PQ_14_lut_out = X1_request_17;
M1_PQ_14_sload_eqn = (M1_SERREG_1 & M1_PQ_13) # (!M1_SERREG_1 & M1_PQ_14_lut_out);
M1_PQ_14 = DFFEA(M1_PQ_14_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_15 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_15
--operation mode is normal

M1_PQ_15_lut_out = X1_request_16;
M1_PQ_15_sload_eqn = (M1_SERREG_1 & M1_PQ_14) # (!M1_SERREG_1 & M1_PQ_15_lut_out);
M1_PQ_15 = DFFEA(M1_PQ_15_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_2 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_2
--operation mode is normal

M1_PQ_2_lut_out = X1_request_29;
M1_PQ_2_sload_eqn = (M1_SERREG_1 & M1_PQ_1) # (!M1_SERREG_1 & M1_PQ_2_lut_out);
M1_PQ_2 = DFFEA(M1_PQ_2_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_3 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_3
--operation mode is normal

M1_PQ_3_lut_out = X1_request_28;
M1_PQ_3_sload_eqn = (M1_SERREG_1 & M1_PQ_2) # (!M1_SERREG_1 & M1_PQ_3_lut_out);
M1_PQ_3 = DFFEA(M1_PQ_3_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_4 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_4
--operation mode is normal

M1_PQ_4_lut_out = X1_request_27;
M1_PQ_4_sload_eqn = (M1_SERREG_1 & M1_PQ_3) # (!M1_SERREG_1 & M1_PQ_4_lut_out);
M1_PQ_4 = DFFEA(M1_PQ_4_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_5 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_5
--operation mode is normal

M1_PQ_5_lut_out = X1_request_26;
M1_PQ_5_sload_eqn = (M1_SERREG_1 & M1_PQ_4) # (!M1_SERREG_1 & M1_PQ_5_lut_out);
M1_PQ_5 = DFFEA(M1_PQ_5_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_6 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_6
--operation mode is normal

M1_PQ_6_lut_out = X1_request_25;
M1_PQ_6_sload_eqn = (M1_SERREG_1 & M1_PQ_5) # (!M1_SERREG_1 & M1_PQ_6_lut_out);
M1_PQ_6 = DFFEA(M1_PQ_6_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_7 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_7
--operation mode is normal

M1_PQ_7_lut_out = X1_request_24;
M1_PQ_7_sload_eqn = (M1_SERREG_1 & M1_PQ_6) # (!M1_SERREG_1 & M1_PQ_7_lut_out);
M1_PQ_7 = DFFEA(M1_PQ_7_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_8 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_8
--operation mode is normal

M1_PQ_8_lut_out = X1_request_23;
M1_PQ_8_sload_eqn = (M1_SERREG_1 & M1_PQ_7) # (!M1_SERREG_1 & M1_PQ_8_lut_out);
M1_PQ_8 = DFFEA(M1_PQ_8_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_9 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_9
--operation mode is normal

M1_PQ_9_lut_out = X1_request_22;
M1_PQ_9_sload_eqn = (M1_SERREG_1 & M1_PQ_8) # (!M1_SERREG_1 & M1_PQ_9_lut_out);
M1_PQ_9 = DFFEA(M1_PQ_9_sload_eqn, U1__clk1, VCC, , M1_NOT_nx150, , );


--M1_PQ_16 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|PQ_16
--operation mode is normal

M1_PQ_16_lut_out = X1_request_15;
M1_PQ_16 = DFFEA(M1_PQ_16_lut_out, U1__clk1, VCC, , M1_NOT_nx154, , );


--M1_NOT_LDACn is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|NOT_LDACn
--operation mode is normal

M1_NOT_LDACn_lut_out = M1_PQ_16 & (M1_SERREG_5 & M1_SL # !M1_SERREG_5 & M1_SERREG_4);
M1_NOT_LDACn = DFFEA(M1_NOT_LDACn_lut_out, U1__clk1, V1_chipRST_n, , M1_cnt_div, , );


--M1_SCLK is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|SCLK
--operation mode is normal

M1_SCLK_lut_out = !M1_SERREG_3 & !M1_SERREG_2;
M1_SCLK = DFFEA(M1_SCLK_lut_out, U1__clk1, V1_chipRST_n, , M1_cnt_div, , );


--M1_nx116 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|nx116
--operation mode is normal

M1_nx116_lut_out = M1_SL # !M1_SERREG_5 & M1_nx116;
M1_nx116 = DFFEA(M1_nx116_lut_out, U1__clk1, V1_chipRST_n, , M1_cnt_div, , );


--M1_SERREG_1 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|SERREG_1
--operation mode is normal

M1_SERREG_1_lut_out = M1_SERREG_2;
M1_SERREG_1 = DFFEA(M1_SERREG_1_lut_out, U1__clk1, V1_chipRST_n, , M1_cnt_div, , );


--M1_SERREG_2 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|SERREG_2
--operation mode is normal

M1_SERREG_2_lut_out = M1_nx143 # M1_nx144 # M1_CNT_FF_3 & M1_SERREG_1;
M1_SERREG_2 = DFFEA(M1_SERREG_2_lut_out, U1__clk1, V1_chipRST_n, , M1_cnt_div, , );


--M1_SERREG_3 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|SERREG_3
--operation mode is normal

M1_SERREG_3_lut_out = M1_SERREG_1 & M1_NOT_CNT_FF_4 & M1_nx142;
M1_SERREG_3 = DFFEA(M1_SERREG_3_lut_out, U1__clk1, V1_chipRST_n, , M1_cnt_div, , );


--M1_SERREG_4 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|SERREG_4
--operation mode is normal

M1_SERREG_4_lut_out = M1_SERREG_3;
M1_SERREG_4 = DFFEA(M1_SERREG_4_lut_out, U1__clk1, V1_chipRST_n, , M1_cnt_div, , );


--M1_SERREG_5 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|SERREG_5
--operation mode is normal

M1_SERREG_5_lut_out = M1_SERREG_4 # M1_SL & M1_SERREG_5;
M1_SERREG_5 = DFFEA(M1_SERREG_5_lut_out, U1__clk1, V1_chipRST_n, , M1_cnt_div, , );


--M1_nx52 is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|nx52
--operation mode is normal

M1_nx52 = G1_ce_1sdac & !V1_rd_wr_oase;

--M1_SL is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|SL
--operation mode is normal

M1_SL = DFFEA(M1_nx52, U1__clk1, VCC, , M1_nx521, , );


--M1_SSTR is ADC_DAC_0:adcdac|TLV5630_16:slow_dac1|SSTR
--operation mode is normal

M1_SSTR_lut_out = M1_SERREG_3 # M1_SERREG_1 & M1_NOT_CNT_FF_4 & M1_nx142;
M1_SSTR = DFFEA(M1_SSTR_lut_out, U1__clk1, V1_chipRST_n, , M1_cnt_div, , );


--L1_counter_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|counter_2
--operation mode is normal

L1_counter_2_carry_eqn = L1_counter_nx16;
L1_counter_2_lut_out = L1_counter_2 $ !L1_counter_2_carry_eqn;
L1_counter_2_reg_input = !L1_nx1346 & L1_counter_2_lut_out;
L1_counter_2 = DFFEA(L1_counter_2_reg_input, U1__clk1, V1_chipRST_n, , L1_NOT_nx1355, , );


--L1_counter_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|counter_1
--operation mode is arithmetic

L1_counter_1_carry_eqn = L1_counter_nx9;
L1_counter_1_lut_out = L1_counter_1 $ L1_counter_1_carry_eqn;
L1_counter_1_reg_input = !L1_nx1346 & L1_counter_1_lut_out;
L1_counter_1 = DFFEA(L1_counter_1_reg_input, U1__clk1, V1_chipRST_n, , L1_NOT_nx1355, , );

--L1_counter_nx16 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|counter_nx16
--operation mode is arithmetic

L1_counter_nx16 = CARRY(!L1_counter_nx9 # !L1_counter_1);


--L1_counter_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|counter_0
--operation mode is arithmetic

L1_counter_0_lut_out = L1_counter_0 $ L1_nx5;
L1_counter_0_reg_input = !L1_nx1346 & L1_counter_0_lut_out;
L1_counter_0 = DFFEA(L1_counter_0_reg_input, U1__clk1, V1_chipRST_n, , L1_NOT_nx1355, , );

--L1_counter_nx9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|counter_nx9
--operation mode is arithmetic

L1_counter_nx9 = CARRY(L1_counter_0 & L1_nx5);


--L1_nx10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx10
--operation mode is normal

L1_nx10 = G1_ce_sc_adc & !V1_rd_wr_oase;


--L1_NOT_nx462 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx462
--operation mode is normal

L1_NOT_nx462 = G1_ce_sc_adc & !V1_rd_wr_oase & X1_request_48 & !L1_nx910;


--L1_NOT_nx510 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx510
--operation mode is normal

L1_NOT_nx510 = G1_ce_sc_adc & !V1_rd_wr_oase & !X1_request_48 & !L1_nx910;


--L1_nx1346 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx1346
--operation mode is normal

L1_nx1346 = L1_sm_6 # !L1_nx637;


--L1_NOT_nx1369 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx1369
--operation mode is normal

L1_NOT_nx1369 = L1_nx906 # L1_nx637 & (L1_sm_5 # L1_sm_2);


--L1_NOT_nx1355 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx1355
--operation mode is normal

L1_NOT_nx1355 = !L1_modgen_select_123_nx2 & L1_nx909 & (L1_b_3 # !L1_sm_2);


--L1_NOT_nx2189 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx2189
--operation mode is normal

L1_NOT_nx2189 = L1_sm_4 & !L1_counter_2 & !L1_counter_1 & !L1_counter_0;


--L1_NOT_nx2213 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx2213
--operation mode is normal

L1_NOT_nx2213 = L1_sm_4 & !L1_counter_2 & !L1_counter_1 & L1_counter_0;


--L1_NOT_nx2237 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx2237
--operation mode is normal

L1_NOT_nx2237 = L1_sm_4 & !L1_counter_2 & L1_counter_1 & !L1_counter_0;


--L1_NOT_nx2261 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx2261
--operation mode is normal

L1_NOT_nx2261 = L1_sm_4 & !L1_counter_2 & L1_counter_1 & L1_counter_0;


--L1_NOT_nx2285 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx2285
--operation mode is normal

L1_NOT_nx2285 = L1_sm_4 & L1_counter_2 & !L1_counter_1 & !L1_counter_0;


--L1_NOT_nx2309 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx2309
--operation mode is normal

L1_NOT_nx2309 = L1_sm_4 & L1_counter_2 & !L1_counter_1 & L1_counter_0;


--L1_NOT_nx2333 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_nx2333
--operation mode is normal

L1_NOT_nx2333 = L1_sm_4 & L1_counter_2 & L1_counter_1 & !L1_counter_0;


--L1_nx5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx5
--operation mode is normal

L1_nx5 = L1_sm_4 # L1_sm_2;


--L1_b_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|b_3
--operation mode is normal

L1_b_3 = !L1_timer_6 & !L1_timer_5 & !L1_timer_4 & !L1_nx818;


--L1_modgen_select_123_nx2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|modgen_select_123_nx2
--operation mode is normal

L1_modgen_select_123_nx2 = L1_sm_4 & L1_counter_2 & L1_counter_1 & L1_counter_0;


--L1_modgen_select_136_nx2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|modgen_select_136_nx2
--operation mode is normal

L1_modgen_select_136_nx2 = L1_sm_4 & (!L1_counter_0 # !L1_counter_1 # !L1_counter_2);


--L1_NOT_ix37_ix7_nx8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_ix37_ix7_nx8
--operation mode is normal

L1_NOT_ix37_ix7_nx8 = X1_request_46 & X1_request_47 & X1_request_48;


--L1_NOT_ix37_ix9_nx8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_ix37_ix9_nx8
--operation mode is normal

L1_NOT_ix37_ix9_nx8 = X1_request_46 & X1_request_47 & !X1_request_48;


--L1_ix38_ix21_nx8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|ix38_ix21_nx8
--operation mode is normal

L1_ix38_ix21_nx8 = L1_counter_2 # L1_counter_1 # L1_counter_0;


--L1_nx814 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx814
--operation mode is normal

L1_nx814 = L1_sm_2 # L1_sm_5 & !L1_b_3;


--L1_nx815 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx815
--operation mode is normal

L1_nx815 = L1_b_3 & (L1_sm_2 # L1_sm_5 & L1_ix38_ix21_nx8);


--L1_nx816 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx816
--operation mode is normal

L1_nx816 = L1_send_cfr # L1_nx637;


--L1_nx817 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx817
--operation mode is normal

L1_nx817 = L1_ce_adc # !T2_RDY;


--L1_nx818 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx818
--operation mode is normal

L1_nx818 = L1_timer_3 # L1_timer_2 # L1_timer_1 # L1_timer_0;


--L1_nx819 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx819
--operation mode is normal

L1_nx819 = !L1_sm_7 & !L1_sm_5 & !L1_sm_3 & !L1_sm_1;


--L1_nx820 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx820
--operation mode is normal

L1_nx820 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_11 # !X1_request_48 & L1_adc_last_1_11);


--L1_nx821 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx821
--operation mode is normal

L1_nx821 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_11 # !X1_request_48 & L1_adc_last_5_11);


--L1_nx822 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx822
--operation mode is normal

L1_nx822 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_23 # !X1_request_48 & !L1_NOT_climits_a_23);


--L1_nx823 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx823
--operation mode is normal

L1_nx823 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_10 # !X1_request_48 & L1_adc_last_1_10);


--L1_nx824 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx824
--operation mode is normal

L1_nx824 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_10 # !X1_request_48 & L1_adc_last_5_10);


--L1_nx825 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx825
--operation mode is normal

L1_nx825 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_22 # !X1_request_48 & !L1_NOT_climits_a_22);


--L1_nx826 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx826
--operation mode is normal

L1_nx826 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_9 # !X1_request_48 & L1_adc_last_1_9);


--L1_nx827 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx827
--operation mode is normal

L1_nx827 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_9 # !X1_request_48 & L1_adc_last_5_9);


--L1_nx828 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx828
--operation mode is normal

L1_nx828 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_21 # !X1_request_48 & !L1_NOT_climits_a_21);


--L1_nx829 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx829
--operation mode is normal

L1_nx829 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_8 # !X1_request_48 & L1_adc_last_1_8);


--L1_nx830 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx830
--operation mode is normal

L1_nx830 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_8 # !X1_request_48 & L1_adc_last_5_8);


--L1_nx831 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx831
--operation mode is normal

L1_nx831 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_20 # !X1_request_48 & !L1_NOT_climits_a_20);


--L1_nx832 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx832
--operation mode is normal

L1_nx832 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_7 # !X1_request_48 & L1_adc_last_1_7);


--L1_nx833 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx833
--operation mode is normal

L1_nx833 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_7 # !X1_request_48 & L1_adc_last_5_7);


--L1_nx834 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx834
--operation mode is normal

L1_nx834 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_19 # !X1_request_48 & !L1_NOT_climits_a_19);


--L1_nx835 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx835
--operation mode is normal

L1_nx835 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_6 # !X1_request_48 & L1_adc_last_1_6);


--L1_nx836 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx836
--operation mode is normal

L1_nx836 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_6 # !X1_request_48 & L1_adc_last_5_6);


--L1_nx837 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx837
--operation mode is normal

L1_nx837 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_18 # !X1_request_48 & !L1_NOT_climits_a_18);


--L1_nx838 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx838
--operation mode is normal

L1_nx838 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_5 # !X1_request_48 & L1_adc_last_1_5);


--L1_nx839 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx839
--operation mode is normal

L1_nx839 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_5 # !X1_request_48 & L1_adc_last_5_5);


--L1_nx840 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx840
--operation mode is normal

L1_nx840 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_17 # !X1_request_48 & !L1_NOT_climits_a_17);


--L1_nx841 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx841
--operation mode is normal

L1_nx841 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_4 # !X1_request_48 & L1_adc_last_1_4);


--L1_nx842 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx842
--operation mode is normal

L1_nx842 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_4 # !X1_request_48 & L1_adc_last_5_4);


--L1_nx843 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx843
--operation mode is normal

L1_nx843 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_16 # !X1_request_48 & !L1_NOT_climits_a_16);


--L1_nx844 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx844
--operation mode is normal

L1_nx844 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_3 # !X1_request_48 & L1_adc_last_1_3);


--L1_nx845 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx845
--operation mode is normal

L1_nx845 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_3 # !X1_request_48 & L1_adc_last_5_3);


--L1_nx846 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx846
--operation mode is normal

L1_nx846 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_15 # !X1_request_48 & !L1_NOT_climits_a_15);


--L1_nx847 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx847
--operation mode is normal

L1_nx847 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_2 # !X1_request_48 & L1_adc_last_1_2);


--L1_nx848 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx848
--operation mode is normal

L1_nx848 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_2 # !X1_request_48 & L1_adc_last_5_2);


--L1_nx849 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx849
--operation mode is normal

L1_nx849 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_14 # !X1_request_48 & !L1_NOT_climits_a_14);


--L1_nx850 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx850
--operation mode is normal

L1_nx850 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_1 # !X1_request_48 & L1_adc_last_1_1);


--L1_nx851 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx851
--operation mode is normal

L1_nx851 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_1 # !X1_request_48 & L1_adc_last_5_1);


--L1_nx852 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx852
--operation mode is normal

L1_nx852 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_13 # !X1_request_48 & !L1_NOT_climits_a_13);


--L1_nx853 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx853
--operation mode is normal

L1_nx853 = !L1_nx908 & (X1_request_48 & L1_adc_last_3_0 # !X1_request_48 & L1_adc_last_1_0);


--L1_nx854 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx854
--operation mode is normal

L1_nx854 = !L1_nx907 & (X1_request_48 & L1_adc_last_7_0 # !X1_request_48 & L1_adc_last_5_0);


--L1_nx855 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx855
--operation mode is normal

L1_nx855 = X1_request_46 & !X1_request_47 & L1_cfr_12;


--L1_nx856 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx856
--operation mode is normal

L1_nx856 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_12 # !X1_request_48 & !L1_NOT_climits_a_12);


--L1_nx857 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx857
--operation mode is normal

L1_nx857 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_11 # !X1_request_48 & L1_adc_last_0_11);


--L1_nx858 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx858
--operation mode is normal

L1_nx858 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_11 # !X1_request_48 & L1_adc_last_4_11);


--L1_nx859 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx859
--operation mode is normal

L1_nx859 = X1_request_46 & !X1_request_47 & L1_cfr_11;


--L1_nx860 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx860
--operation mode is normal

L1_nx860 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_11 # !X1_request_48 & !L1_NOT_climits_a_11);


--L1_nx861 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx861
--operation mode is normal

L1_nx861 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_10 # !X1_request_48 & L1_adc_last_0_10);


--L1_nx862 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx862
--operation mode is normal

L1_nx862 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_10 # !X1_request_48 & L1_adc_last_4_10);


--L1_nx863 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx863
--operation mode is normal

L1_nx863 = X1_request_46 & !X1_request_47 & L1_cfr_10;


--L1_nx864 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx864
--operation mode is normal

L1_nx864 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_10 # !X1_request_48 & !L1_NOT_climits_a_10);


--L1_nx865 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx865
--operation mode is normal

L1_nx865 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_9 # !X1_request_48 & L1_adc_last_0_9);


--L1_nx866 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx866
--operation mode is normal

L1_nx866 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_9 # !X1_request_48 & L1_adc_last_4_9);


--L1_nx867 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx867
--operation mode is normal

L1_nx867 = X1_request_46 & !X1_request_47 & L1_cfr_9;


--L1_nx868 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx868
--operation mode is normal

L1_nx868 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_9 # !X1_request_48 & !L1_NOT_climits_a_9);


--L1_nx869 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx869
--operation mode is normal

L1_nx869 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_8 # !X1_request_48 & L1_adc_last_0_8);


--L1_nx870 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx870
--operation mode is normal

L1_nx870 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_8 # !X1_request_48 & L1_adc_last_4_8);


--L1_nx871 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx871
--operation mode is normal

L1_nx871 = X1_request_46 & !X1_request_47 & L1_cfr_8;


--L1_nx872 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx872
--operation mode is normal

L1_nx872 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_8 # !X1_request_48 & !L1_NOT_climits_a_8);


--L1_nx873 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx873
--operation mode is normal

L1_nx873 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_7 # !X1_request_48 & L1_adc_last_0_7);


--L1_nx874 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx874
--operation mode is normal

L1_nx874 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_7 # !X1_request_48 & L1_adc_last_4_7);


--L1_nx875 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx875
--operation mode is normal

L1_nx875 = X1_request_46 & !X1_request_47 & L1_cfr_7;


--L1_nx876 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx876
--operation mode is normal

L1_nx876 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_7 # !X1_request_48 & !L1_NOT_climits_a_7);


--L1_nx877 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx877
--operation mode is normal

L1_nx877 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_6 # !X1_request_48 & L1_adc_last_0_6);


--L1_nx878 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx878
--operation mode is normal

L1_nx878 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_6 # !X1_request_48 & L1_adc_last_4_6);


--L1_nx879 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx879
--operation mode is normal

L1_nx879 = X1_request_46 & !X1_request_47 & L1_cfr_6;


--L1_nx880 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx880
--operation mode is normal

L1_nx880 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_6 # !X1_request_48 & !L1_NOT_climits_a_6);


--L1_nx881 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx881
--operation mode is normal

L1_nx881 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_5 # !X1_request_48 & L1_adc_last_0_5);


--L1_nx882 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx882
--operation mode is normal

L1_nx882 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_5 # !X1_request_48 & L1_adc_last_4_5);


--L1_nx883 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx883
--operation mode is normal

L1_nx883 = X1_request_46 & !X1_request_47 & L1_cfr_5;


--L1_nx884 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx884
--operation mode is normal

L1_nx884 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_5 # !X1_request_48 & !L1_NOT_climits_a_5);


--L1_nx885 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx885
--operation mode is normal

L1_nx885 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_4 # !X1_request_48 & L1_adc_last_0_4);


--L1_nx886 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx886
--operation mode is normal

L1_nx886 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_4 # !X1_request_48 & L1_adc_last_4_4);


--L1_nx887 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx887
--operation mode is normal

L1_nx887 = X1_request_46 & !X1_request_47 & L1_cfr_4;


--L1_nx888 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx888
--operation mode is normal

L1_nx888 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_4 # !X1_request_48 & !L1_NOT_climits_a_4);


--L1_nx889 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx889
--operation mode is normal

L1_nx889 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_3 # !X1_request_48 & L1_adc_last_0_3);


--L1_nx890 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx890
--operation mode is normal

L1_nx890 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_3 # !X1_request_48 & L1_adc_last_4_3);


--L1_nx891 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx891
--operation mode is normal

L1_nx891 = X1_request_46 & !X1_request_47 & L1_cfr_3;


--L1_nx892 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx892
--operation mode is normal

L1_nx892 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_3 # !X1_request_48 & !L1_NOT_climits_a_3);


--L1_nx893 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx893
--operation mode is normal

L1_nx893 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_2 # !X1_request_48 & L1_adc_last_0_2);


--L1_nx894 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx894
--operation mode is normal

L1_nx894 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_2 # !X1_request_48 & L1_adc_last_4_2);


--L1_nx895 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx895
--operation mode is normal

L1_nx895 = X1_request_46 & !X1_request_47 & L1_cfr_2;


--L1_nx896 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx896
--operation mode is normal

L1_nx896 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_2 # !X1_request_48 & !L1_NOT_climits_a_2);


--L1_nx897 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx897
--operation mode is normal

L1_nx897 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_1 # !X1_request_48 & L1_adc_last_0_1);


--L1_nx898 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx898
--operation mode is normal

L1_nx898 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_1 # !X1_request_48 & L1_adc_last_4_1);


--L1_nx899 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx899
--operation mode is normal

L1_nx899 = X1_request_46 & !X1_request_47 & L1_cfr_1;


--L1_nx900 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx900
--operation mode is normal

L1_nx900 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_1 # !X1_request_48 & !L1_NOT_climits_a_1);


--L1_nx901 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx901
--operation mode is normal

L1_nx901 = !L1_nx908 & (X1_request_48 & L1_adc_last_2_0 # !X1_request_48 & L1_adc_last_0_0);


--L1_nx902 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx902
--operation mode is normal

L1_nx902 = !L1_nx907 & (X1_request_48 & L1_adc_last_6_0 # !X1_request_48 & L1_adc_last_4_0);


--L1_nx903 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx903
--operation mode is normal

L1_nx903 = X1_request_46 & !X1_request_47 & L1_cfr_0;


--L1_nx904 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx904
--operation mode is normal

L1_nx904 = !L1_nx910 & (X1_request_48 & !L1_NOT_climits_d_0 # !X1_request_48 & !L1_NOT_climits_a_0);


--L1_nx905 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx905
--operation mode is normal

L1_nx905 = L1_b_3 & L1_sm_5 & L1_ix38_ix21_nx8 # !L1_b_3 & L1_sm_2;


--L1_nx906 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx906
--operation mode is normal

L1_nx906 = !L1_send_cfr & L1_start_cyc & !L1_nx637;


--L1_nx907 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx907
--operation mode is normal

L1_nx907 = X1_request_46 # !X1_request_47;


--L1_nx908 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx908
--operation mode is normal

L1_nx908 = X1_request_46 # X1_request_47;


--L1_nx909 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx909
--operation mode is normal

L1_nx909 = L1_nx819 & (L1_nx637 # !L1_send_cfr & L1_start_cyc);


--L1_nx910 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx910
--operation mode is normal

L1_nx910 = !X1_request_47 # !X1_request_46;


--L1_RDATA_23 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_23
--operation mode is normal

L1_RDATA_23 = L1_nx820 # L1_nx821 # L1_nx822;


--L1_RDATA_22 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_22
--operation mode is normal

L1_RDATA_22 = L1_nx823 # L1_nx824 # L1_nx825;


--L1_RDATA_21 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_21
--operation mode is normal

L1_RDATA_21 = L1_nx826 # L1_nx827 # L1_nx828;


--L1_RDATA_20 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_20
--operation mode is normal

L1_RDATA_20 = L1_nx829 # L1_nx830 # L1_nx831;


--L1_RDATA_19 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_19
--operation mode is normal

L1_RDATA_19 = L1_nx832 # L1_nx833 # L1_nx834;


--L1_RDATA_18 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_18
--operation mode is normal

L1_RDATA_18 = L1_nx835 # L1_nx836 # L1_nx837;


--L1_RDATA_17 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_17
--operation mode is normal

L1_RDATA_17 = L1_nx838 # L1_nx839 # L1_nx840;


--L1_RDATA_16 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_16
--operation mode is normal

L1_RDATA_16 = L1_nx841 # L1_nx842 # L1_nx843;


--L1_RDATA_15 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_15
--operation mode is normal

L1_RDATA_15 = L1_nx844 # L1_nx845 # L1_nx846;


--L1_RDATA_14 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_14
--operation mode is normal

L1_RDATA_14 = L1_nx847 # L1_nx848 # L1_nx849;


--L1_RDATA_13 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_13
--operation mode is normal

L1_RDATA_13 = L1_nx850 # L1_nx851 # L1_nx852;


--L1_RDATA_12 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_12
--operation mode is normal

L1_RDATA_12 = L1_nx853 # L1_nx854 # L1_nx855 # L1_nx856;


--L1_RDATA_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_11
--operation mode is normal

L1_RDATA_11 = L1_nx857 # L1_nx858 # L1_nx859 # L1_nx860;


--L1_RDATA_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_10
--operation mode is normal

L1_RDATA_10 = L1_nx861 # L1_nx862 # L1_nx863 # L1_nx864;


--L1_RDATA_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_9
--operation mode is normal

L1_RDATA_9 = L1_nx865 # L1_nx866 # L1_nx867 # L1_nx868;


--L1_RDATA_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_8
--operation mode is normal

L1_RDATA_8 = L1_nx869 # L1_nx870 # L1_nx871 # L1_nx872;


--L1_RDATA_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_7
--operation mode is normal

L1_RDATA_7 = L1_nx873 # L1_nx874 # L1_nx875 # L1_nx876;


--L1_RDATA_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_6
--operation mode is normal

L1_RDATA_6 = L1_nx877 # L1_nx878 # L1_nx879 # L1_nx880;


--L1_RDATA_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_5
--operation mode is normal

L1_RDATA_5 = L1_nx881 # L1_nx882 # L1_nx883 # L1_nx884;


--L1_RDATA_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_4
--operation mode is normal

L1_RDATA_4 = L1_nx885 # L1_nx886 # L1_nx887 # L1_nx888;


--L1_RDATA_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_3
--operation mode is normal

L1_RDATA_3 = L1_nx889 # L1_nx890 # L1_nx891 # L1_nx892;


--L1_RDATA_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_2
--operation mode is normal

L1_RDATA_2 = L1_nx893 # L1_nx894 # L1_nx895 # L1_nx896;


--L1_RDATA_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_1
--operation mode is normal

L1_RDATA_1 = L1_nx897 # L1_nx898 # L1_nx899 # L1_nx900;


--L1_RDATA_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|RDATA_0
--operation mode is normal

L1_RDATA_0 = L1_nx901 # L1_nx902 # L1_nx903 # L1_nx904;


--L1_adc_last_0_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_0
--operation mode is normal

L1_adc_last_0_0_lut_out = T2_RDATA_0;
L1_adc_last_0_0 = DFFEA(L1_adc_last_0_0_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_1
--operation mode is normal

L1_adc_last_0_1_lut_out = T2_RDATA_1;
L1_adc_last_0_1 = DFFEA(L1_adc_last_0_1_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_10
--operation mode is normal

L1_adc_last_0_10_lut_out = T2_RDATA_10;
L1_adc_last_0_10 = DFFEA(L1_adc_last_0_10_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_11
--operation mode is normal

L1_adc_last_0_11_lut_out = T2_RDATA_11;
L1_adc_last_0_11 = DFFEA(L1_adc_last_0_11_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_2
--operation mode is normal

L1_adc_last_0_2_lut_out = T2_RDATA_2;
L1_adc_last_0_2 = DFFEA(L1_adc_last_0_2_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_3
--operation mode is normal

L1_adc_last_0_3_lut_out = T2_RDATA_3;
L1_adc_last_0_3 = DFFEA(L1_adc_last_0_3_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_4
--operation mode is normal

L1_adc_last_0_4_lut_out = T2_RDATA_4;
L1_adc_last_0_4 = DFFEA(L1_adc_last_0_4_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_5
--operation mode is normal

L1_adc_last_0_5_lut_out = T2_RDATA_5;
L1_adc_last_0_5 = DFFEA(L1_adc_last_0_5_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_6
--operation mode is normal

L1_adc_last_0_6_lut_out = T2_RDATA_6;
L1_adc_last_0_6 = DFFEA(L1_adc_last_0_6_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_7
--operation mode is normal

L1_adc_last_0_7_lut_out = T2_RDATA_7;
L1_adc_last_0_7 = DFFEA(L1_adc_last_0_7_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_8
--operation mode is normal

L1_adc_last_0_8_lut_out = T2_RDATA_8;
L1_adc_last_0_8 = DFFEA(L1_adc_last_0_8_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_0_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_0_9
--operation mode is normal

L1_adc_last_0_9_lut_out = T2_RDATA_9;
L1_adc_last_0_9 = DFFEA(L1_adc_last_0_9_lut_out, U1__clk1, VCC, , L1_NOT_nx2189, , );


--L1_adc_last_1_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_0
--operation mode is normal

L1_adc_last_1_0_lut_out = T2_RDATA_0;
L1_adc_last_1_0 = DFFEA(L1_adc_last_1_0_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_1
--operation mode is normal

L1_adc_last_1_1_lut_out = T2_RDATA_1;
L1_adc_last_1_1 = DFFEA(L1_adc_last_1_1_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_10
--operation mode is normal

L1_adc_last_1_10_lut_out = T2_RDATA_10;
L1_adc_last_1_10 = DFFEA(L1_adc_last_1_10_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_11
--operation mode is normal

L1_adc_last_1_11_lut_out = T2_RDATA_11;
L1_adc_last_1_11 = DFFEA(L1_adc_last_1_11_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_2
--operation mode is normal

L1_adc_last_1_2_lut_out = T2_RDATA_2;
L1_adc_last_1_2 = DFFEA(L1_adc_last_1_2_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_3
--operation mode is normal

L1_adc_last_1_3_lut_out = T2_RDATA_3;
L1_adc_last_1_3 = DFFEA(L1_adc_last_1_3_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_4
--operation mode is normal

L1_adc_last_1_4_lut_out = T2_RDATA_4;
L1_adc_last_1_4 = DFFEA(L1_adc_last_1_4_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_5
--operation mode is normal

L1_adc_last_1_5_lut_out = T2_RDATA_5;
L1_adc_last_1_5 = DFFEA(L1_adc_last_1_5_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_6
--operation mode is normal

L1_adc_last_1_6_lut_out = T2_RDATA_6;
L1_adc_last_1_6 = DFFEA(L1_adc_last_1_6_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_7
--operation mode is normal

L1_adc_last_1_7_lut_out = T2_RDATA_7;
L1_adc_last_1_7 = DFFEA(L1_adc_last_1_7_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_8
--operation mode is normal

L1_adc_last_1_8_lut_out = T2_RDATA_8;
L1_adc_last_1_8 = DFFEA(L1_adc_last_1_8_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_1_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_1_9
--operation mode is normal

L1_adc_last_1_9_lut_out = T2_RDATA_9;
L1_adc_last_1_9 = DFFEA(L1_adc_last_1_9_lut_out, U1__clk1, VCC, , L1_NOT_nx2213, , );


--L1_adc_last_2_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_0
--operation mode is normal

L1_adc_last_2_0_lut_out = T2_RDATA_0;
L1_adc_last_2_0 = DFFEA(L1_adc_last_2_0_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_1
--operation mode is normal

L1_adc_last_2_1_lut_out = T2_RDATA_1;
L1_adc_last_2_1 = DFFEA(L1_adc_last_2_1_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_10
--operation mode is normal

L1_adc_last_2_10_lut_out = T2_RDATA_10;
L1_adc_last_2_10 = DFFEA(L1_adc_last_2_10_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_11
--operation mode is normal

L1_adc_last_2_11_lut_out = T2_RDATA_11;
L1_adc_last_2_11 = DFFEA(L1_adc_last_2_11_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_2
--operation mode is normal

L1_adc_last_2_2_lut_out = T2_RDATA_2;
L1_adc_last_2_2 = DFFEA(L1_adc_last_2_2_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_3
--operation mode is normal

L1_adc_last_2_3_lut_out = T2_RDATA_3;
L1_adc_last_2_3 = DFFEA(L1_adc_last_2_3_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_4
--operation mode is normal

L1_adc_last_2_4_lut_out = T2_RDATA_4;
L1_adc_last_2_4 = DFFEA(L1_adc_last_2_4_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_5
--operation mode is normal

L1_adc_last_2_5_lut_out = T2_RDATA_5;
L1_adc_last_2_5 = DFFEA(L1_adc_last_2_5_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_6
--operation mode is normal

L1_adc_last_2_6_lut_out = T2_RDATA_6;
L1_adc_last_2_6 = DFFEA(L1_adc_last_2_6_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_7
--operation mode is normal

L1_adc_last_2_7_lut_out = T2_RDATA_7;
L1_adc_last_2_7 = DFFEA(L1_adc_last_2_7_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_8
--operation mode is normal

L1_adc_last_2_8_lut_out = T2_RDATA_8;
L1_adc_last_2_8 = DFFEA(L1_adc_last_2_8_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_2_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_2_9
--operation mode is normal

L1_adc_last_2_9_lut_out = T2_RDATA_9;
L1_adc_last_2_9 = DFFEA(L1_adc_last_2_9_lut_out, U1__clk1, VCC, , L1_NOT_nx2237, , );


--L1_adc_last_3_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_0
--operation mode is normal

L1_adc_last_3_0_lut_out = T2_RDATA_0;
L1_adc_last_3_0 = DFFEA(L1_adc_last_3_0_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_1
--operation mode is normal

L1_adc_last_3_1_lut_out = T2_RDATA_1;
L1_adc_last_3_1 = DFFEA(L1_adc_last_3_1_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_10
--operation mode is normal

L1_adc_last_3_10_lut_out = T2_RDATA_10;
L1_adc_last_3_10 = DFFEA(L1_adc_last_3_10_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_11
--operation mode is normal

L1_adc_last_3_11_lut_out = T2_RDATA_11;
L1_adc_last_3_11 = DFFEA(L1_adc_last_3_11_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_2
--operation mode is normal

L1_adc_last_3_2_lut_out = T2_RDATA_2;
L1_adc_last_3_2 = DFFEA(L1_adc_last_3_2_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_3
--operation mode is normal

L1_adc_last_3_3_lut_out = T2_RDATA_3;
L1_adc_last_3_3 = DFFEA(L1_adc_last_3_3_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_4
--operation mode is normal

L1_adc_last_3_4_lut_out = T2_RDATA_4;
L1_adc_last_3_4 = DFFEA(L1_adc_last_3_4_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_5
--operation mode is normal

L1_adc_last_3_5_lut_out = T2_RDATA_5;
L1_adc_last_3_5 = DFFEA(L1_adc_last_3_5_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_6
--operation mode is normal

L1_adc_last_3_6_lut_out = T2_RDATA_6;
L1_adc_last_3_6 = DFFEA(L1_adc_last_3_6_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_7
--operation mode is normal

L1_adc_last_3_7_lut_out = T2_RDATA_7;
L1_adc_last_3_7 = DFFEA(L1_adc_last_3_7_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_8
--operation mode is normal

L1_adc_last_3_8_lut_out = T2_RDATA_8;
L1_adc_last_3_8 = DFFEA(L1_adc_last_3_8_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_3_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_3_9
--operation mode is normal

L1_adc_last_3_9_lut_out = T2_RDATA_9;
L1_adc_last_3_9 = DFFEA(L1_adc_last_3_9_lut_out, U1__clk1, VCC, , L1_NOT_nx2261, , );


--L1_adc_last_4_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_0
--operation mode is normal

L1_adc_last_4_0_lut_out = T2_RDATA_0;
L1_adc_last_4_0 = DFFEA(L1_adc_last_4_0_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_1
--operation mode is normal

L1_adc_last_4_1_lut_out = T2_RDATA_1;
L1_adc_last_4_1 = DFFEA(L1_adc_last_4_1_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_10
--operation mode is normal

L1_adc_last_4_10_lut_out = T2_RDATA_10;
L1_adc_last_4_10 = DFFEA(L1_adc_last_4_10_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_11
--operation mode is normal

L1_adc_last_4_11_lut_out = T2_RDATA_11;
L1_adc_last_4_11 = DFFEA(L1_adc_last_4_11_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_2
--operation mode is normal

L1_adc_last_4_2_lut_out = T2_RDATA_2;
L1_adc_last_4_2 = DFFEA(L1_adc_last_4_2_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_3
--operation mode is normal

L1_adc_last_4_3_lut_out = T2_RDATA_3;
L1_adc_last_4_3 = DFFEA(L1_adc_last_4_3_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_4
--operation mode is normal

L1_adc_last_4_4_lut_out = T2_RDATA_4;
L1_adc_last_4_4 = DFFEA(L1_adc_last_4_4_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_5
--operation mode is normal

L1_adc_last_4_5_lut_out = T2_RDATA_5;
L1_adc_last_4_5 = DFFEA(L1_adc_last_4_5_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_6
--operation mode is normal

L1_adc_last_4_6_lut_out = T2_RDATA_6;
L1_adc_last_4_6 = DFFEA(L1_adc_last_4_6_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_7
--operation mode is normal

L1_adc_last_4_7_lut_out = T2_RDATA_7;
L1_adc_last_4_7 = DFFEA(L1_adc_last_4_7_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_8
--operation mode is normal

L1_adc_last_4_8_lut_out = T2_RDATA_8;
L1_adc_last_4_8 = DFFEA(L1_adc_last_4_8_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_4_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_4_9
--operation mode is normal

L1_adc_last_4_9_lut_out = T2_RDATA_9;
L1_adc_last_4_9 = DFFEA(L1_adc_last_4_9_lut_out, U1__clk1, VCC, , L1_NOT_nx2285, , );


--L1_adc_last_5_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_0
--operation mode is normal

L1_adc_last_5_0_lut_out = T2_RDATA_0;
L1_adc_last_5_0 = DFFEA(L1_adc_last_5_0_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_1
--operation mode is normal

L1_adc_last_5_1_lut_out = T2_RDATA_1;
L1_adc_last_5_1 = DFFEA(L1_adc_last_5_1_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_10
--operation mode is normal

L1_adc_last_5_10_lut_out = T2_RDATA_10;
L1_adc_last_5_10 = DFFEA(L1_adc_last_5_10_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_11
--operation mode is normal

L1_adc_last_5_11_lut_out = T2_RDATA_11;
L1_adc_last_5_11 = DFFEA(L1_adc_last_5_11_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_2
--operation mode is normal

L1_adc_last_5_2_lut_out = T2_RDATA_2;
L1_adc_last_5_2 = DFFEA(L1_adc_last_5_2_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_3
--operation mode is normal

L1_adc_last_5_3_lut_out = T2_RDATA_3;
L1_adc_last_5_3 = DFFEA(L1_adc_last_5_3_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_4
--operation mode is normal

L1_adc_last_5_4_lut_out = T2_RDATA_4;
L1_adc_last_5_4 = DFFEA(L1_adc_last_5_4_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_5
--operation mode is normal

L1_adc_last_5_5_lut_out = T2_RDATA_5;
L1_adc_last_5_5 = DFFEA(L1_adc_last_5_5_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_6
--operation mode is normal

L1_adc_last_5_6_lut_out = T2_RDATA_6;
L1_adc_last_5_6 = DFFEA(L1_adc_last_5_6_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_7
--operation mode is normal

L1_adc_last_5_7_lut_out = T2_RDATA_7;
L1_adc_last_5_7 = DFFEA(L1_adc_last_5_7_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_8
--operation mode is normal

L1_adc_last_5_8_lut_out = T2_RDATA_8;
L1_adc_last_5_8 = DFFEA(L1_adc_last_5_8_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_5_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_5_9
--operation mode is normal

L1_adc_last_5_9_lut_out = T2_RDATA_9;
L1_adc_last_5_9 = DFFEA(L1_adc_last_5_9_lut_out, U1__clk1, VCC, , L1_NOT_nx2309, , );


--L1_adc_last_6_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_0
--operation mode is normal

L1_adc_last_6_0_lut_out = T2_RDATA_0;
L1_adc_last_6_0 = DFFEA(L1_adc_last_6_0_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_1
--operation mode is normal

L1_adc_last_6_1_lut_out = T2_RDATA_1;
L1_adc_last_6_1 = DFFEA(L1_adc_last_6_1_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_10
--operation mode is normal

L1_adc_last_6_10_lut_out = T2_RDATA_10;
L1_adc_last_6_10 = DFFEA(L1_adc_last_6_10_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_11
--operation mode is normal

L1_adc_last_6_11_lut_out = T2_RDATA_11;
L1_adc_last_6_11 = DFFEA(L1_adc_last_6_11_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_2
--operation mode is normal

L1_adc_last_6_2_lut_out = T2_RDATA_2;
L1_adc_last_6_2 = DFFEA(L1_adc_last_6_2_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_3
--operation mode is normal

L1_adc_last_6_3_lut_out = T2_RDATA_3;
L1_adc_last_6_3 = DFFEA(L1_adc_last_6_3_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_4
--operation mode is normal

L1_adc_last_6_4_lut_out = T2_RDATA_4;
L1_adc_last_6_4 = DFFEA(L1_adc_last_6_4_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_5
--operation mode is normal

L1_adc_last_6_5_lut_out = T2_RDATA_5;
L1_adc_last_6_5 = DFFEA(L1_adc_last_6_5_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_6
--operation mode is normal

L1_adc_last_6_6_lut_out = T2_RDATA_6;
L1_adc_last_6_6 = DFFEA(L1_adc_last_6_6_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_7
--operation mode is normal

L1_adc_last_6_7_lut_out = T2_RDATA_7;
L1_adc_last_6_7 = DFFEA(L1_adc_last_6_7_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_8
--operation mode is normal

L1_adc_last_6_8_lut_out = T2_RDATA_8;
L1_adc_last_6_8 = DFFEA(L1_adc_last_6_8_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_6_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_6_9
--operation mode is normal

L1_adc_last_6_9_lut_out = T2_RDATA_9;
L1_adc_last_6_9 = DFFEA(L1_adc_last_6_9_lut_out, U1__clk1, VCC, , L1_NOT_nx2333, , );


--L1_adc_last_7_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_0
--operation mode is normal

L1_adc_last_7_0_lut_out = T2_RDATA_0;
L1_adc_last_7_0 = DFFEA(L1_adc_last_7_0_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_1
--operation mode is normal

L1_adc_last_7_1_lut_out = T2_RDATA_1;
L1_adc_last_7_1 = DFFEA(L1_adc_last_7_1_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_10
--operation mode is normal

L1_adc_last_7_10_lut_out = T2_RDATA_10;
L1_adc_last_7_10 = DFFEA(L1_adc_last_7_10_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_11
--operation mode is normal

L1_adc_last_7_11_lut_out = T2_RDATA_11;
L1_adc_last_7_11 = DFFEA(L1_adc_last_7_11_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_2
--operation mode is normal

L1_adc_last_7_2_lut_out = T2_RDATA_2;
L1_adc_last_7_2 = DFFEA(L1_adc_last_7_2_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_3
--operation mode is normal

L1_adc_last_7_3_lut_out = T2_RDATA_3;
L1_adc_last_7_3 = DFFEA(L1_adc_last_7_3_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_4
--operation mode is normal

L1_adc_last_7_4_lut_out = T2_RDATA_4;
L1_adc_last_7_4 = DFFEA(L1_adc_last_7_4_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_5
--operation mode is normal

L1_adc_last_7_5_lut_out = T2_RDATA_5;
L1_adc_last_7_5 = DFFEA(L1_adc_last_7_5_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_6
--operation mode is normal

L1_adc_last_7_6_lut_out = T2_RDATA_6;
L1_adc_last_7_6 = DFFEA(L1_adc_last_7_6_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_7
--operation mode is normal

L1_adc_last_7_7_lut_out = T2_RDATA_7;
L1_adc_last_7_7 = DFFEA(L1_adc_last_7_7_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_8
--operation mode is normal

L1_adc_last_7_8_lut_out = T2_RDATA_8;
L1_adc_last_7_8 = DFFEA(L1_adc_last_7_8_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_adc_last_7_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|adc_last_7_9
--operation mode is normal

L1_adc_last_7_9_lut_out = T2_RDATA_9;
L1_adc_last_7_9 = DFFEA(L1_adc_last_7_9_lut_out, U1__clk1, VCC, , L1_modgen_select_123_nx2, , );


--L1_NOT_ADC_nCSStrt is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_ADC_nCSStrt
--operation mode is normal

L1_NOT_ADC_nCSStrt_lut_out = L1_sm_2;
L1_NOT_ADC_nCSStrt = DFFEA(L1_NOT_ADC_nCSStrt_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_ce_adc is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|ce_adc
--operation mode is normal

L1_ce_adc_lut_out = L1_sm_6 # L1_modgen_select_136_nx2 # L1_send_cfr & !L1_nx637;
L1_ce_adc = DFFEA(L1_ce_adc_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_cfr_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_0
--operation mode is normal

L1_cfr_0_lut_out = X1_request_31;
L1_cfr_0 = DFFEA(L1_cfr_0_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_1
--operation mode is normal

L1_cfr_1_lut_out = X1_request_30;
L1_cfr_1 = DFFEA(L1_cfr_1_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_10
--operation mode is normal

L1_cfr_10_lut_out = X1_request_21;
L1_cfr_10 = DFFEA(L1_cfr_10_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_11
--operation mode is normal

L1_cfr_11_lut_out = X1_request_20;
L1_cfr_11 = DFFEA(L1_cfr_11_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_12 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_12
--operation mode is normal

L1_cfr_12_lut_out = X1_request_19;
L1_cfr_12 = DFFEA(L1_cfr_12_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_2
--operation mode is normal

L1_cfr_2_lut_out = X1_request_29;
L1_cfr_2 = DFFEA(L1_cfr_2_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_3
--operation mode is normal

L1_cfr_3_lut_out = X1_request_28;
L1_cfr_3 = DFFEA(L1_cfr_3_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_4
--operation mode is normal

L1_cfr_4_lut_out = X1_request_27;
L1_cfr_4 = DFFEA(L1_cfr_4_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_5
--operation mode is normal

L1_cfr_5_lut_out = X1_request_26;
L1_cfr_5 = DFFEA(L1_cfr_5_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_6
--operation mode is normal

L1_cfr_6_lut_out = X1_request_25;
L1_cfr_6 = DFFEA(L1_cfr_6_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_7
--operation mode is normal

L1_cfr_7_lut_out = X1_request_24;
L1_cfr_7 = DFFEA(L1_cfr_7_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_8
--operation mode is normal

L1_cfr_8_lut_out = X1_request_23;
L1_cfr_8 = DFFEA(L1_cfr_8_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_cfr_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cfr_9
--operation mode is normal

L1_cfr_9_lut_out = X1_request_22;
L1_cfr_9 = DFFEA(L1_cfr_9_lut_out, U1__clk1, V1_chipRST_n, , L1_nx538, , );


--L1_NOT_climits_a_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_0
--operation mode is normal

L1_NOT_climits_a_0_lut_out = !X1_request_31;
L1_NOT_climits_a_0 = DFFEA(L1_NOT_climits_a_0_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_1
--operation mode is normal

L1_NOT_climits_a_1_lut_out = !X1_request_30;
L1_NOT_climits_a_1 = DFFEA(L1_NOT_climits_a_1_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_10
--operation mode is normal

L1_NOT_climits_a_10_lut_out = !X1_request_21;
L1_NOT_climits_a_10 = DFFEA(L1_NOT_climits_a_10_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_11
--operation mode is normal

L1_NOT_climits_a_11_lut_out = !X1_request_20;
L1_NOT_climits_a_11 = DFFEA(L1_NOT_climits_a_11_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_12 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_12
--operation mode is normal

L1_NOT_climits_a_12_lut_out = !X1_request_19;
L1_NOT_climits_a_12 = DFFEA(L1_NOT_climits_a_12_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_13 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_13
--operation mode is normal

L1_NOT_climits_a_13_lut_out = L1_NOT_climits_a_13;
L1_NOT_climits_a_13_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L931) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_13_lut_out);
L1_NOT_climits_a_13 = DFFEA(L1_NOT_climits_a_13_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_14 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_14
--operation mode is normal

L1_NOT_climits_a_14_lut_out = L1_NOT_climits_a_14;
L1_NOT_climits_a_14_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L731) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_14_lut_out);
L1_NOT_climits_a_14 = DFFEA(L1_NOT_climits_a_14_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_15 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_15
--operation mode is normal

L1_NOT_climits_a_15_lut_out = L1_NOT_climits_a_15;
L1_NOT_climits_a_15_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L531) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_15_lut_out);
L1_NOT_climits_a_15 = DFFEA(L1_NOT_climits_a_15_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_16 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_16
--operation mode is normal

L1_NOT_climits_a_16_lut_out = L1_NOT_climits_a_16;
L1_NOT_climits_a_16_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L331) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_16_lut_out);
L1_NOT_climits_a_16 = DFFEA(L1_NOT_climits_a_16_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_17 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_17
--operation mode is normal

L1_NOT_climits_a_17_lut_out = L1_NOT_climits_a_17;
L1_NOT_climits_a_17_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L131) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_17_lut_out);
L1_NOT_climits_a_17 = DFFEA(L1_NOT_climits_a_17_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_18 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_18
--operation mode is normal

L1_NOT_climits_a_18_lut_out = L1_NOT_climits_a_18;
L1_NOT_climits_a_18_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L921) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_18_lut_out);
L1_NOT_climits_a_18 = DFFEA(L1_NOT_climits_a_18_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_19 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_19
--operation mode is normal

L1_NOT_climits_a_19_lut_out = L1_NOT_climits_a_19;
L1_NOT_climits_a_19_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L721) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_19_lut_out);
L1_NOT_climits_a_19 = DFFEA(L1_NOT_climits_a_19_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_2
--operation mode is normal

L1_NOT_climits_a_2_lut_out = !X1_request_29;
L1_NOT_climits_a_2 = DFFEA(L1_NOT_climits_a_2_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_20 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_20
--operation mode is normal

L1_NOT_climits_a_20_lut_out = L1_NOT_climits_a_20;
L1_NOT_climits_a_20_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L521) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_20_lut_out);
L1_NOT_climits_a_20 = DFFEA(L1_NOT_climits_a_20_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_21 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_21
--operation mode is normal

L1_NOT_climits_a_21_lut_out = L1_NOT_climits_a_21;
L1_NOT_climits_a_21_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L321) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_21_lut_out);
L1_NOT_climits_a_21 = DFFEA(L1_NOT_climits_a_21_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_22 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_22
--operation mode is normal

L1_NOT_climits_a_22_lut_out = L1_NOT_climits_a_22;
L1_NOT_climits_a_22_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L121) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_22_lut_out);
L1_NOT_climits_a_22 = DFFEA(L1_NOT_climits_a_22_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_23 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_23
--operation mode is normal

L1_NOT_climits_a_23_lut_out = L1_NOT_climits_a_23;
L1_NOT_climits_a_23_sload_eqn = (L1_NOT_ix37_ix9_nx8 & X1L911) # (!L1_NOT_ix37_ix9_nx8 & L1_NOT_climits_a_23_lut_out);
L1_NOT_climits_a_23 = DFFEA(L1_NOT_climits_a_23_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_a_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_3
--operation mode is normal

L1_NOT_climits_a_3_lut_out = !X1_request_28;
L1_NOT_climits_a_3 = DFFEA(L1_NOT_climits_a_3_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_4
--operation mode is normal

L1_NOT_climits_a_4_lut_out = !X1_request_27;
L1_NOT_climits_a_4 = DFFEA(L1_NOT_climits_a_4_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_5
--operation mode is normal

L1_NOT_climits_a_5_lut_out = !X1_request_26;
L1_NOT_climits_a_5 = DFFEA(L1_NOT_climits_a_5_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_6
--operation mode is normal

L1_NOT_climits_a_6_lut_out = !X1_request_25;
L1_NOT_climits_a_6 = DFFEA(L1_NOT_climits_a_6_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_7
--operation mode is normal

L1_NOT_climits_a_7_lut_out = !X1_request_24;
L1_NOT_climits_a_7 = DFFEA(L1_NOT_climits_a_7_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_8
--operation mode is normal

L1_NOT_climits_a_8_lut_out = !X1_request_23;
L1_NOT_climits_a_8 = DFFEA(L1_NOT_climits_a_8_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_a_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_a_9
--operation mode is normal

L1_NOT_climits_a_9_lut_out = !X1_request_22;
L1_NOT_climits_a_9 = DFFEA(L1_NOT_climits_a_9_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx510, , );


--L1_NOT_climits_d_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_0
--operation mode is normal

L1_NOT_climits_d_0_lut_out = !X1_request_31;
L1_NOT_climits_d_0 = DFFEA(L1_NOT_climits_d_0_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_1
--operation mode is normal

L1_NOT_climits_d_1_lut_out = !X1_request_30;
L1_NOT_climits_d_1 = DFFEA(L1_NOT_climits_d_1_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_10
--operation mode is normal

L1_NOT_climits_d_10_lut_out = !X1_request_21;
L1_NOT_climits_d_10 = DFFEA(L1_NOT_climits_d_10_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_11
--operation mode is normal

L1_NOT_climits_d_11_lut_out = !X1_request_20;
L1_NOT_climits_d_11 = DFFEA(L1_NOT_climits_d_11_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_12 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_12
--operation mode is normal

L1_NOT_climits_d_12_lut_out = !X1_request_19;
L1_NOT_climits_d_12 = DFFEA(L1_NOT_climits_d_12_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_13 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_13
--operation mode is normal

L1_NOT_climits_d_13_lut_out = L1_NOT_climits_d_13;
L1_NOT_climits_d_13_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L931) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_13_lut_out);
L1_NOT_climits_d_13 = DFFEA(L1_NOT_climits_d_13_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_14 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_14
--operation mode is normal

L1_NOT_climits_d_14_lut_out = L1_NOT_climits_d_14;
L1_NOT_climits_d_14_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L731) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_14_lut_out);
L1_NOT_climits_d_14 = DFFEA(L1_NOT_climits_d_14_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_15 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_15
--operation mode is normal

L1_NOT_climits_d_15_lut_out = L1_NOT_climits_d_15;
L1_NOT_climits_d_15_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L531) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_15_lut_out);
L1_NOT_climits_d_15 = DFFEA(L1_NOT_climits_d_15_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_16 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_16
--operation mode is normal

L1_NOT_climits_d_16_lut_out = L1_NOT_climits_d_16;
L1_NOT_climits_d_16_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L331) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_16_lut_out);
L1_NOT_climits_d_16 = DFFEA(L1_NOT_climits_d_16_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_17 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_17
--operation mode is normal

L1_NOT_climits_d_17_lut_out = L1_NOT_climits_d_17;
L1_NOT_climits_d_17_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L131) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_17_lut_out);
L1_NOT_climits_d_17 = DFFEA(L1_NOT_climits_d_17_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_18 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_18
--operation mode is normal

L1_NOT_climits_d_18_lut_out = L1_NOT_climits_d_18;
L1_NOT_climits_d_18_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L921) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_18_lut_out);
L1_NOT_climits_d_18 = DFFEA(L1_NOT_climits_d_18_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_19 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_19
--operation mode is normal

L1_NOT_climits_d_19_lut_out = L1_NOT_climits_d_19;
L1_NOT_climits_d_19_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L721) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_19_lut_out);
L1_NOT_climits_d_19 = DFFEA(L1_NOT_climits_d_19_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_2
--operation mode is normal

L1_NOT_climits_d_2_lut_out = !X1_request_29;
L1_NOT_climits_d_2 = DFFEA(L1_NOT_climits_d_2_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_20 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_20
--operation mode is normal

L1_NOT_climits_d_20_lut_out = L1_NOT_climits_d_20;
L1_NOT_climits_d_20_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L521) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_20_lut_out);
L1_NOT_climits_d_20 = DFFEA(L1_NOT_climits_d_20_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_21 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_21
--operation mode is normal

L1_NOT_climits_d_21_lut_out = L1_NOT_climits_d_21;
L1_NOT_climits_d_21_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L321) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_21_lut_out);
L1_NOT_climits_d_21 = DFFEA(L1_NOT_climits_d_21_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_22 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_22
--operation mode is normal

L1_NOT_climits_d_22_lut_out = L1_NOT_climits_d_22;
L1_NOT_climits_d_22_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L121) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_22_lut_out);
L1_NOT_climits_d_22 = DFFEA(L1_NOT_climits_d_22_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_23 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_23
--operation mode is normal

L1_NOT_climits_d_23_lut_out = L1_NOT_climits_d_23;
L1_NOT_climits_d_23_sload_eqn = (L1_NOT_ix37_ix7_nx8 & X1L911) # (!L1_NOT_ix37_ix7_nx8 & L1_NOT_climits_d_23_lut_out);
L1_NOT_climits_d_23 = DFFEA(L1_NOT_climits_d_23_sload_eqn, U1__clk1, V1_chipRST_n, , L1_nx10, , );


--L1_NOT_climits_d_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_3
--operation mode is normal

L1_NOT_climits_d_3_lut_out = !X1_request_28;
L1_NOT_climits_d_3 = DFFEA(L1_NOT_climits_d_3_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_4
--operation mode is normal

L1_NOT_climits_d_4_lut_out = !X1_request_27;
L1_NOT_climits_d_4 = DFFEA(L1_NOT_climits_d_4_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_5
--operation mode is normal

L1_NOT_climits_d_5_lut_out = !X1_request_26;
L1_NOT_climits_d_5 = DFFEA(L1_NOT_climits_d_5_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_6
--operation mode is normal

L1_NOT_climits_d_6_lut_out = !X1_request_25;
L1_NOT_climits_d_6 = DFFEA(L1_NOT_climits_d_6_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_7
--operation mode is normal

L1_NOT_climits_d_7_lut_out = !X1_request_24;
L1_NOT_climits_d_7 = DFFEA(L1_NOT_climits_d_7_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_8
--operation mode is normal

L1_NOT_climits_d_8_lut_out = !X1_request_23;
L1_NOT_climits_d_8 = DFFEA(L1_NOT_climits_d_8_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_NOT_climits_d_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|NOT_climits_d_9
--operation mode is normal

L1_NOT_climits_d_9_lut_out = !X1_request_22;
L1_NOT_climits_d_9 = DFFEA(L1_NOT_climits_d_9_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx462, , );


--L1_cmd_adc_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cmd_adc_1
--operation mode is normal

L1_cmd_adc_1_lut_out = VCC;
L1_cmd_adc_1 = DFFEA(L1_cmd_adc_1_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_cmd_adc_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|cmd_adc_2
--operation mode is normal

L1_cmd_adc_2_lut_out = L1_nx637;
L1_cmd_adc_2 = DFFEA(L1_cmd_adc_2_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_nx538 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx538
--operation mode is normal

L1_nx538 = G1_ce_sc_adc & !V1_rd_wr_oase & X1_request_46 & !X1_request_47;

--L1_send_cfr is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|send_cfr
--operation mode is normal

L1_send_cfr = DFFEA(L1_nx538, U1__clk1, V1_chipRST_n, , , , );


--L1_nx637 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx637
--operation mode is normal

L1_nx637_lut_out = L1_sm_7 & !T2_RDY & (L1_start_cyc # L1_nx816) # !L1_sm_7 & (L1_start_cyc # L1_nx816);
L1_nx637 = DFFEA(L1_nx637_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_sm_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|sm_1
--operation mode is normal

L1_sm_1_lut_out = L1_send_cfr & !L1_nx637;
L1_sm_1 = DFFEA(L1_sm_1_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_sm_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|sm_2
--operation mode is normal

L1_sm_2_lut_out = L1_nx905 # !L1_send_cfr & L1_start_cyc & !L1_nx637;
L1_sm_2 = DFFEA(L1_sm_2_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_sm_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|sm_3
--operation mode is normal

L1_sm_3_lut_out = L1_sm_6 # L1_modgen_select_136_nx2 # L1_sm_3 & L1_nx817;
L1_sm_3 = DFFEA(L1_sm_3_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_sm_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|sm_4
--operation mode is normal

L1_sm_4_lut_out = L1_sm_3 & !L1_ce_adc & T2_RDY;
L1_sm_4 = DFFEA(L1_sm_4_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_sm_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|sm_5
--operation mode is normal

L1_sm_5_lut_out = L1_sm_2;
L1_sm_5 = DFFEA(L1_sm_5_lut_out, U1__clk1, V1_chipRST_n, , L1_b_3, , );


--L1_sm_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|sm_6
--operation mode is normal

L1_sm_6_lut_out = L1_sm_5 & L1_b_3 & !L1_ix38_ix21_nx8;
L1_sm_6 = DFFEA(L1_sm_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_sm_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|sm_7
--operation mode is normal

L1_sm_7_lut_out = L1_sm_1 # L1_modgen_select_123_nx2 # L1_sm_7 & !T2_RDY;
L1_sm_7 = DFFEA(L1_sm_7_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_start_cyc is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|start_cyc
--operation mode is normal

L1_start_cyc_lut_out = L1_cfr_12 # G1_ce_sc_adc & !V1_rd_wr_oase & !X1_request_46;
L1_start_cyc = DFFEA(L1_start_cyc_lut_out, U1__clk1, V1_chipRST_n, , , , );


--L1_timer_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_0
--operation mode is normal

L1_timer_0_lut_out = L1_nx815 # L1_nx1229 & L1_nx814 # !L1_nx637;
L1_timer_0 = DFFEA(L1_timer_0_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx1369, , );


--L1_timer_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_1
--operation mode is normal

L1_timer_1_lut_out = L1_nx815 # L1_nx1228 & L1_nx814 # !L1_nx637;
L1_timer_1 = DFFEA(L1_timer_1_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx1369, , );


--L1_timer_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_2
--operation mode is normal

L1_timer_2_lut_out = L1_nx815 # L1_nx1227 & L1_nx814 # !L1_nx637;
L1_timer_2 = DFFEA(L1_timer_2_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx1369, , );


--L1_timer_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_3
--operation mode is normal

L1_timer_3_lut_out = L1_nx815 # L1_nx1226 & L1_nx814 # !L1_nx637;
L1_timer_3 = DFFEA(L1_timer_3_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx1369, , );


--L1_timer_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_4
--operation mode is normal

L1_timer_4_lut_out = L1_nx815 # L1_nx1225 & L1_nx814 # !L1_nx637;
L1_timer_4 = DFFEA(L1_timer_4_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx1369, , );


--L1_timer_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_5
--operation mode is normal

L1_timer_5_lut_out = L1_nx815 # L1_nx1224 & L1_nx814 # !L1_nx637;
L1_timer_5 = DFFEA(L1_timer_5_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx1369, , );


--L1_timer_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_6
--operation mode is normal

L1_timer_6_lut_out = L1_nx815 # L1_nx1223 & L1_nx814 # !L1_nx637;
L1_timer_6 = DFFEA(L1_timer_6_lut_out, U1__clk1, V1_chipRST_n, , L1_NOT_nx1369, , );


--L1_nx1229 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx1229
--operation mode is normal

L1_nx1229 = !L1_timer_0;


--L1_timer_dec_115_nx22 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_dec_115_nx22
--operation mode is arithmetic

L1_timer_dec_115_nx22 = CARRY(L1_timer_0);


--L1_nx1228 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx1228
--operation mode is arithmetic

L1_nx1228_carry_eqn = L1_timer_dec_115_nx22;
L1_nx1228 = L1_timer_1 $ !L1_nx1228_carry_eqn;

--L1_timer_dec_115_nx26 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_dec_115_nx26
--operation mode is arithmetic

L1_timer_dec_115_nx26 = CARRY(!L1_timer_1 & !L1_timer_dec_115_nx22);


--L1_nx1227 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx1227
--operation mode is arithmetic

L1_nx1227_carry_eqn = L1_timer_dec_115_nx26;
L1_nx1227 = L1_timer_2 $ L1_nx1227_carry_eqn;

--L1_timer_dec_115_nx30 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_dec_115_nx30
--operation mode is arithmetic

L1_timer_dec_115_nx30 = CARRY(L1_timer_2 # !L1_timer_dec_115_nx26);


--L1_nx1226 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx1226
--operation mode is arithmetic

L1_nx1226_carry_eqn = L1_timer_dec_115_nx30;
L1_nx1226 = L1_timer_3 $ !L1_nx1226_carry_eqn;

--L1_timer_dec_115_nx34 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_dec_115_nx34
--operation mode is arithmetic

L1_timer_dec_115_nx34 = CARRY(!L1_timer_3 & !L1_timer_dec_115_nx30);


--L1_nx1225 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx1225
--operation mode is arithmetic

L1_nx1225_carry_eqn = L1_timer_dec_115_nx34;
L1_nx1225 = L1_timer_4 $ L1_nx1225_carry_eqn;

--L1_timer_dec_115_nx38 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_dec_115_nx38
--operation mode is arithmetic

L1_timer_dec_115_nx38 = CARRY(L1_timer_4 # !L1_timer_dec_115_nx34);


--L1_nx1224 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx1224
--operation mode is arithmetic

L1_nx1224_carry_eqn = L1_timer_dec_115_nx38;
L1_nx1224 = L1_timer_5 $ !L1_nx1224_carry_eqn;

--L1_timer_dec_115_nx42 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|timer_dec_115_nx42
--operation mode is arithmetic

L1_timer_dec_115_nx42 = CARRY(!L1_timer_5 & !L1_timer_dec_115_nx38);


--L1_nx1223 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|nx1223
--operation mode is normal

L1_nx1223_carry_eqn = L1_timer_dec_115_nx42;
L1_nx1223 = L1_timer_6 $ L1_nx1223_carry_eqn;


--T2_counter_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_2
--operation mode is arithmetic

T2_counter_2_carry_eqn = T2_counter_nx16;
T2_counter_2_lut_out = T2_counter_2 $ T2_counter_2_carry_eqn;
T2_counter_2_reg_input = T2_sm_2 & T2_counter_2_lut_out;
T2_counter_2 = DFFEA(T2_counter_2_reg_input, U1__clk1, V1_chipRST_n, , T2_NOT_nx499, , );

--T2_counter_nx21 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_nx21
--operation mode is arithmetic

T2_counter_nx21 = CARRY(T2_counter_2 # !T2_counter_nx16);


--T2_counter_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_1
--operation mode is arithmetic

T2_counter_1_carry_eqn = T2_counter_nx10;
T2_counter_1_lut_out = T2_counter_1 $ !T2_counter_1_carry_eqn;
T2_counter_1_reg_input = T2_sm_2 & T2_counter_1_lut_out;
T2_counter_1 = DFFEA(T2_counter_1_reg_input, U1__clk1, V1_chipRST_n, , T2_NOT_nx499, , );

--T2_counter_nx16 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_nx16
--operation mode is arithmetic

T2_counter_nx16 = CARRY(!T2_counter_1 & !T2_counter_nx10);


--T2_counter_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_0
--operation mode is arithmetic

T2_counter_0_lut_out = !T2_counter_0;
T2_counter_0_reg_input = T2_sm_2 & T2_counter_0_lut_out;
T2_counter_0 = DFFEA(T2_counter_0_reg_input, U1__clk1, V1_chipRST_n, , T2_NOT_nx499, , );

--T2_counter_nx10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_nx10
--operation mode is arithmetic

T2_counter_nx10 = CARRY(T2_counter_0);


--T2_counter_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|counter_3
--operation mode is normal

T2_counter_3_carry_eqn = T2_counter_nx21;
T2_counter_3_lut_out = T2_counter_3 $ !T2_counter_3_carry_eqn;
T2_counter_3_reg_input = T2_sm_2 & T2_counter_3_lut_out;
T2_counter_3 = DFFEA(T2_counter_3_reg_input, U1__clk1, V1_chipRST_n, , T2_NOT_nx499, , );


--T2_NOT_nx295 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|NOT_nx295
--operation mode is normal

T2_NOT_nx295 = T2_ADC_SCLK & (T2_counter_3 # T2_counter_2 # !T2_fifo_rd);


--T2_NOT_nx214 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|NOT_nx214
--operation mode is normal

T2_NOT_nx214 = L1_ce_adc & (T2_ADC_SCLK # !T2_nx60) # !L1_ce_adc & T2_nx60 & T2_ADC_SCLK;


--T2_NOT_nx499 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|NOT_nx499
--operation mode is normal

T2_NOT_nx499 = !T2_sm_4 & !T2_ADC_SCLK;


--T2_nx94 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|nx94
--operation mode is normal

T2_nx94 = L1_cmd_adc_1 & !L1_cmd_adc_2 & !T2_nx60;


--T2_nx95 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|nx95
--operation mode is normal

T2_nx95 = T2_counter_3 # T2_counter_2;


--T2_nx96 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|nx96
--operation mode is normal

T2_nx96 = T2_counter_1 # T2_counter_0;


--T2_RDATA_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_0
--operation mode is normal

T2_RDATA_0_lut_out = SC_ADC_SDO;
T2_RDATA_0 = DFFEA(T2_RDATA_0_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_1
--operation mode is normal

T2_RDATA_1_lut_out = T2_RDATA_0;
T2_RDATA_1 = DFFEA(T2_RDATA_1_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_10
--operation mode is normal

T2_RDATA_10_lut_out = T2_RDATA_9;
T2_RDATA_10 = DFFEA(T2_RDATA_10_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_11
--operation mode is normal

T2_RDATA_11_lut_out = T2_RDATA_10;
T2_RDATA_11 = DFFEA(T2_RDATA_11_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_2
--operation mode is normal

T2_RDATA_2_lut_out = T2_RDATA_1;
T2_RDATA_2 = DFFEA(T2_RDATA_2_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_3
--operation mode is normal

T2_RDATA_3_lut_out = T2_RDATA_2;
T2_RDATA_3 = DFFEA(T2_RDATA_3_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_4
--operation mode is normal

T2_RDATA_4_lut_out = T2_RDATA_3;
T2_RDATA_4 = DFFEA(T2_RDATA_4_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_5
--operation mode is normal

T2_RDATA_5_lut_out = T2_RDATA_4;
T2_RDATA_5 = DFFEA(T2_RDATA_5_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_6
--operation mode is normal

T2_RDATA_6_lut_out = T2_RDATA_5;
T2_RDATA_6 = DFFEA(T2_RDATA_6_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_7
--operation mode is normal

T2_RDATA_7_lut_out = T2_RDATA_6;
T2_RDATA_7 = DFFEA(T2_RDATA_7_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_8
--operation mode is normal

T2_RDATA_8_lut_out = T2_RDATA_7;
T2_RDATA_8 = DFFEA(T2_RDATA_8_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_RDATA_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDATA_9
--operation mode is normal

T2_RDATA_9_lut_out = T2_RDATA_8;
T2_RDATA_9 = DFFEA(T2_RDATA_9_lut_out, U1__clk1, VCC, , T2_NOT_nx295, , );


--T2_datasr_0 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_0
--operation mode is normal

T2_datasr_0_lut_out = L1_cfr_0 & T2_nx94;
T2_datasr_0 = DFFEA(T2_datasr_0_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_1
--operation mode is normal

T2_datasr_1_lut_out = L1_cfr_1 & (T2_nx94 # T2_datasr_0 & T2_ADC_SCLK) # !L1_cfr_1 & T2_datasr_0 & T2_ADC_SCLK;
T2_datasr_1 = DFFEA(T2_datasr_1_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_10 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_10
--operation mode is normal

T2_datasr_10_lut_out = L1_cfr_10 & (T2_nx94 # T2_datasr_9 & T2_ADC_SCLK) # !L1_cfr_10 & T2_datasr_9 & T2_ADC_SCLK;
T2_datasr_10 = DFFEA(T2_datasr_10_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_11 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_11
--operation mode is normal

T2_datasr_11_lut_out = L1_cfr_11 & (T2_nx94 # T2_datasr_10 & T2_ADC_SCLK) # !L1_cfr_11 & T2_datasr_10 & T2_ADC_SCLK;
T2_datasr_11 = DFFEA(T2_datasr_11_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_12 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_12
--operation mode is normal

T2_datasr_12_lut_out = T2_datasr_11 & T2_ADC_SCLK;
T2_datasr_12 = DFFEA(T2_datasr_12_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_13 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_13
--operation mode is normal

T2_datasr_13_lut_out = L1_cmd_adc_1 & (T2_datasr_12 & T2_ADC_SCLK # !T2_nx60) # !L1_cmd_adc_1 & T2_datasr_12 & T2_ADC_SCLK;
T2_datasr_13 = DFFEA(T2_datasr_13_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_14 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_14
--operation mode is normal

T2_datasr_14_lut_out = L1_cmd_adc_2 & (T2_datasr_13 & T2_ADC_SCLK # !T2_nx60) # !L1_cmd_adc_2 & T2_datasr_13 & T2_ADC_SCLK;
T2_datasr_14 = DFFEA(T2_datasr_14_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_ADC_SDI is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|ADC_SDI
--operation mode is normal

T2_ADC_SDI_lut_out = L1_cmd_adc_1 & (T2_datasr_14 & T2_ADC_SCLK # !T2_nx60) # !L1_cmd_adc_1 & T2_datasr_14 & T2_ADC_SCLK;
T2_ADC_SDI = DFFEA(T2_ADC_SDI_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_2
--operation mode is normal

T2_datasr_2_lut_out = L1_cfr_2 & (T2_nx94 # T2_datasr_1 & T2_ADC_SCLK) # !L1_cfr_2 & T2_datasr_1 & T2_ADC_SCLK;
T2_datasr_2 = DFFEA(T2_datasr_2_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_3 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_3
--operation mode is normal

T2_datasr_3_lut_out = L1_cfr_3 & (T2_nx94 # T2_datasr_2 & T2_ADC_SCLK) # !L1_cfr_3 & T2_datasr_2 & T2_ADC_SCLK;
T2_datasr_3 = DFFEA(T2_datasr_3_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_4
--operation mode is normal

T2_datasr_4_lut_out = L1_cfr_4 & (T2_nx94 # T2_datasr_3 & T2_ADC_SCLK) # !L1_cfr_4 & T2_datasr_3 & T2_ADC_SCLK;
T2_datasr_4 = DFFEA(T2_datasr_4_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_5 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_5
--operation mode is normal

T2_datasr_5_lut_out = L1_cfr_5 & (T2_nx94 # T2_datasr_4 & T2_ADC_SCLK) # !L1_cfr_5 & T2_datasr_4 & T2_ADC_SCLK;
T2_datasr_5 = DFFEA(T2_datasr_5_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_6 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_6
--operation mode is normal

T2_datasr_6_lut_out = L1_cfr_6 & (T2_nx94 # T2_datasr_5 & T2_ADC_SCLK) # !L1_cfr_6 & T2_datasr_5 & T2_ADC_SCLK;
T2_datasr_6 = DFFEA(T2_datasr_6_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_7 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_7
--operation mode is normal

T2_datasr_7_lut_out = L1_cfr_7 & (T2_nx94 # T2_datasr_6 & T2_ADC_SCLK) # !L1_cfr_7 & T2_datasr_6 & T2_ADC_SCLK;
T2_datasr_7 = DFFEA(T2_datasr_7_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_8 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_8
--operation mode is normal

T2_datasr_8_lut_out = L1_cfr_8 & (T2_nx94 # T2_datasr_7 & T2_ADC_SCLK) # !L1_cfr_8 & T2_datasr_7 & T2_ADC_SCLK;
T2_datasr_8 = DFFEA(T2_datasr_8_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_datasr_9 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|datasr_9
--operation mode is normal

T2_datasr_9_lut_out = L1_cfr_9 & (T2_nx94 # T2_datasr_8 & T2_ADC_SCLK) # !L1_cfr_9 & T2_datasr_8 & T2_ADC_SCLK;
T2_datasr_9 = DFFEA(T2_datasr_9_lut_out, U1__clk1, VCC, , T2_NOT_nx214, , );


--T2_fifo_rd is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|fifo_rd
--operation mode is normal

T2_fifo_rd_lut_out = L1_cmd_adc_1 & L1_cmd_adc_2;
T2_fifo_rd = DFFEA(T2_fifo_rd_lut_out, U1__clk1, VCC, , T2_modgen_select_108_nx4, , );


--T2_RDY is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|RDY
--operation mode is normal

T2_RDY_lut_out = !L1_ce_adc & !T2_nx60;
T2_RDY = DFFEA(T2_RDY_lut_out, U1__clk1, V1_chipRST_n, , , , );


--T2_nx60 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|nx60
--operation mode is normal

T2_nx60_lut_out = !T2_sm_4 & (L1_ce_adc # T2_nx60);
T2_nx60 = DFFEA(T2_nx60_lut_out, U1__clk1, V1_chipRST_n, , , , );


--T2_modgen_select_108_nx4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|modgen_select_108_nx4
--operation mode is normal

T2_modgen_select_108_nx4 = L1_ce_adc & !T2_nx60;

--T2_sm_1 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|sm_1
--operation mode is normal

T2_sm_1 = DFFEA(T2_modgen_select_108_nx4, U1__clk1, V1_chipRST_n, , , , );


--T2_sm_2 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|sm_2
--operation mode is normal

T2_sm_2_lut_out = T2_sm_1 # T2_ADC_SCLK & (T2_nx95 # T2_nx96);
T2_sm_2 = DFFEA(T2_sm_2_lut_out, U1__clk1, V1_chipRST_n, , , , );


--T2_ADC_SCLK is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|ADC_SCLK
--operation mode is normal

T2_ADC_SCLK_lut_out = T2_sm_2;
T2_ADC_SCLK = DFFEA(T2_ADC_SCLK_lut_out, U1__clk1, V1_chipRST_n, , , , );


--T2_sm_4 is ADC_DAC_0:adcdac|seradc_auto_unfolded0:sc_adc|TLV2548:adc|sm_4
--operation mode is normal

T2_sm_4_lut_out = !T2_counter_1 & !T2_counter_0 & T2_ADC_SCLK & !T2_nx95;
T2_sm_4 = DFFEA(T2_sm_4_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_counter_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|counter_2
--operation mode is normal

K1_counter_2_carry_eqn = K1_counter_nx16;
K1_counter_2_lut_out = K1_counter_2 $ !K1_counter_2_carry_eqn;
K1_counter_2_reg_input = !K1_nx1346 & K1_counter_2_lut_out;
K1_counter_2 = DFFEA(K1_counter_2_reg_input, U1__clk1, V1_chipRST_n, , K1_NOT_nx1355, , );


--K1_counter_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|counter_1
--operation mode is arithmetic

K1_counter_1_carry_eqn = K1_counter_nx9;
K1_counter_1_lut_out = K1_counter_1 $ K1_counter_1_carry_eqn;
K1_counter_1_reg_input = !K1_nx1346 & K1_counter_1_lut_out;
K1_counter_1 = DFFEA(K1_counter_1_reg_input, U1__clk1, V1_chipRST_n, , K1_NOT_nx1355, , );

--K1_counter_nx16 is ADC_DAC_0:adcdac|seradc_auto:power_adc|counter_nx16
--operation mode is arithmetic

K1_counter_nx16 = CARRY(!K1_counter_nx9 # !K1_counter_1);


--K1_counter_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|counter_0
--operation mode is arithmetic

K1_counter_0_lut_out = K1_counter_0 $ K1_nx5;
K1_counter_0_reg_input = !K1_nx1346 & K1_counter_0_lut_out;
K1_counter_0 = DFFEA(K1_counter_0_reg_input, U1__clk1, V1_chipRST_n, , K1_NOT_nx1355, , );

--K1_counter_nx9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|counter_nx9
--operation mode is arithmetic

K1_counter_nx9 = CARRY(K1_counter_0 & K1_nx5);


--K1_nx10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx10
--operation mode is normal

K1_nx10 = G1_ce_psply_adc & !V1_rd_wr_oase;


--K1_NOT_nx462 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx462
--operation mode is normal

K1_NOT_nx462 = G1_ce_psply_adc & !V1_rd_wr_oase & X1_request_48 & !K1_nx993;


--K1_NOT_nx510 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx510
--operation mode is normal

K1_NOT_nx510 = G1_ce_psply_adc & !V1_rd_wr_oase & !X1_request_48 & !K1_nx993;


--K1_nx1346 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx1346
--operation mode is normal

K1_nx1346 = K1_sm_6 # !K1_nx692;


--K1_NOT_nx1369 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx1369
--operation mode is normal

K1_NOT_nx1369 = K1_nx989 # K1_nx692 & (K1_sm_5 # K1_sm_2);


--K1_NOT_nx1355 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx1355
--operation mode is normal

K1_NOT_nx1355 = !K1_modgen_select_123_nx2 & K1_nx992 & (K1_b_3 # !K1_sm_2);


--K1_NOT_nx2189 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx2189
--operation mode is normal

K1_NOT_nx2189 = K1_sm_4 & !K1_counter_2 & !K1_counter_1 & !K1_counter_0;


--K1_NOT_nx2213 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx2213
--operation mode is normal

K1_NOT_nx2213 = K1_sm_4 & !K1_counter_2 & !K1_counter_1 & K1_counter_0;


--K1_NOT_nx2237 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx2237
--operation mode is normal

K1_NOT_nx2237 = K1_sm_4 & !K1_counter_2 & K1_counter_1 & !K1_counter_0;


--K1_NOT_nx2261 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx2261
--operation mode is normal

K1_NOT_nx2261 = K1_sm_4 & !K1_counter_2 & K1_counter_1 & K1_counter_0;


--K1_NOT_nx2285 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx2285
--operation mode is normal

K1_NOT_nx2285 = K1_sm_4 & K1_counter_2 & !K1_counter_1 & !K1_counter_0;


--K1_NOT_nx2309 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx2309
--operation mode is normal

K1_NOT_nx2309 = K1_sm_4 & K1_counter_2 & !K1_counter_1 & K1_counter_0;


--K1_NOT_nx2333 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_nx2333
--operation mode is normal

K1_NOT_nx2333 = K1_sm_4 & K1_counter_2 & K1_counter_1 & !K1_counter_0;


--K1_nx5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx5
--operation mode is normal

K1_nx5 = K1_sm_4 # K1_sm_2;


--K1_b_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|b_3
--operation mode is normal

K1_b_3 = !K1_timer_6 & !K1_timer_5 & !K1_timer_4 & !K1_nx901;


--K1_modgen_select_123_nx2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_select_123_nx2
--operation mode is normal

K1_modgen_select_123_nx2 = K1_sm_4 & K1_counter_2 & K1_counter_1 & K1_counter_0;


--K1_modgen_select_136_nx2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_select_136_nx2
--operation mode is normal

K1_modgen_select_136_nx2 = K1_sm_4 & (!K1_counter_0 # !K1_counter_1 # !K1_counter_2);


--K1_NOT_ix37_ix7_nx8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_ix37_ix7_nx8
--operation mode is normal

K1_NOT_ix37_ix7_nx8 = X1_request_46 & X1_request_47 & X1_request_48;


--K1_NOT_ix37_ix9_nx8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_ix37_ix9_nx8
--operation mode is normal

K1_NOT_ix37_ix9_nx8 = X1_request_46 & X1_request_47 & !X1_request_48;


--K1_ix38_ix21_nx8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|ix38_ix21_nx8
--operation mode is normal

K1_ix38_ix21_nx8 = K1_counter_2 # K1_counter_1 # K1_counter_0;


--K1_nx897 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx897
--operation mode is normal

K1_nx897 = K1_sm_2 # K1_sm_5 & !K1_b_3;


--K1_nx898 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx898
--operation mode is normal

K1_nx898 = K1_b_3 & (K1_sm_2 # K1_sm_5 & K1_ix38_ix21_nx8);


--K1_nx899 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx899
--operation mode is normal

K1_nx899 = K1_send_cfr # K1_nx692;


--K1_nx900 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx900
--operation mode is normal

K1_nx900 = K1_ce_adc # !T1_RDY;


--K1_nx901 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx901
--operation mode is normal

K1_nx901 = K1_timer_3 # K1_timer_2 # K1_timer_1 # K1_timer_0;


--K1_nx902 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx902
--operation mode is normal

K1_nx902 = !K1_sm_7 & !K1_sm_5 & !K1_sm_3 & !K1_sm_1;


--K1_nx903 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx903
--operation mode is normal

K1_nx903 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_11 # !X1_request_48 & K1_adc_last_1_11);


--K1_nx904 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx904
--operation mode is normal

K1_nx904 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_11 # !X1_request_48 & K1_adc_last_5_11);


--K1_nx905 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx905
--operation mode is normal

K1_nx905 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_23 # !X1_request_48 & !K1_NOT_climits_a_23);


--K1_nx906 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx906
--operation mode is normal

K1_nx906 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_10 # !X1_request_48 & K1_adc_last_1_10);


--K1_nx907 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx907
--operation mode is normal

K1_nx907 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_10 # !X1_request_48 & K1_adc_last_5_10);


--K1_nx908 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx908
--operation mode is normal

K1_nx908 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_22 # !X1_request_48 & !K1_NOT_climits_a_22);


--K1_nx909 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx909
--operation mode is normal

K1_nx909 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_9 # !X1_request_48 & K1_adc_last_1_9);


--K1_nx910 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx910
--operation mode is normal

K1_nx910 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_9 # !X1_request_48 & K1_adc_last_5_9);


--K1_nx911 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx911
--operation mode is normal

K1_nx911 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_21 # !X1_request_48 & !K1_NOT_climits_a_21);


--K1_nx912 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx912
--operation mode is normal

K1_nx912 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_8 # !X1_request_48 & K1_adc_last_1_8);


--K1_nx913 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx913
--operation mode is normal

K1_nx913 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_8 # !X1_request_48 & K1_adc_last_5_8);


--K1_nx914 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx914
--operation mode is normal

K1_nx914 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_20 # !X1_request_48 & !K1_NOT_climits_a_20);


--K1_nx915 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx915
--operation mode is normal

K1_nx915 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_7 # !X1_request_48 & K1_adc_last_1_7);


--K1_nx916 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx916
--operation mode is normal

K1_nx916 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_7 # !X1_request_48 & K1_adc_last_5_7);


--K1_nx917 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx917
--operation mode is normal

K1_nx917 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_19 # !X1_request_48 & !K1_NOT_climits_a_19);


--K1_nx918 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx918
--operation mode is normal

K1_nx918 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_6 # !X1_request_48 & K1_adc_last_1_6);


--K1_nx919 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx919
--operation mode is normal

K1_nx919 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_6 # !X1_request_48 & K1_adc_last_5_6);


--K1_nx920 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx920
--operation mode is normal

K1_nx920 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_18 # !X1_request_48 & !K1_NOT_climits_a_18);


--K1_nx921 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx921
--operation mode is normal

K1_nx921 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_5 # !X1_request_48 & K1_adc_last_1_5);


--K1_nx922 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx922
--operation mode is normal

K1_nx922 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_5 # !X1_request_48 & K1_adc_last_5_5);


--K1_nx923 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx923
--operation mode is normal

K1_nx923 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_17 # !X1_request_48 & !K1_NOT_climits_a_17);


--K1_nx924 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx924
--operation mode is normal

K1_nx924 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_4 # !X1_request_48 & K1_adc_last_1_4);


--K1_nx925 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx925
--operation mode is normal

K1_nx925 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_4 # !X1_request_48 & K1_adc_last_5_4);


--K1_nx926 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx926
--operation mode is normal

K1_nx926 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_16 # !X1_request_48 & !K1_NOT_climits_a_16);


--K1_nx927 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx927
--operation mode is normal

K1_nx927 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_3 # !X1_request_48 & K1_adc_last_1_3);


--K1_nx928 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx928
--operation mode is normal

K1_nx928 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_3 # !X1_request_48 & K1_adc_last_5_3);


--K1_nx929 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx929
--operation mode is normal

K1_nx929 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_15 # !X1_request_48 & !K1_NOT_climits_a_15);


--K1_nx930 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx930
--operation mode is normal

K1_nx930 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_2 # !X1_request_48 & K1_adc_last_1_2);


--K1_nx931 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx931
--operation mode is normal

K1_nx931 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_2 # !X1_request_48 & K1_adc_last_5_2);


--K1_nx932 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx932
--operation mode is normal

K1_nx932 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_14 # !X1_request_48 & !K1_NOT_climits_a_14);


--K1_nx933 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx933
--operation mode is normal

K1_nx933 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_1 # !X1_request_48 & K1_adc_last_1_1);


--K1_nx934 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx934
--operation mode is normal

K1_nx934 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_1 # !X1_request_48 & K1_adc_last_5_1);


--K1_nx935 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx935
--operation mode is normal

K1_nx935 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_13 # !X1_request_48 & !K1_NOT_climits_a_13);


--K1_nx936 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx936
--operation mode is normal

K1_nx936 = !K1_nx991 & (X1_request_48 & K1_adc_last_3_0 # !X1_request_48 & K1_adc_last_1_0);


--K1_nx937 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx937
--operation mode is normal

K1_nx937 = !K1_nx990 & (X1_request_48 & K1_adc_last_7_0 # !X1_request_48 & K1_adc_last_5_0);


--K1_nx938 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx938
--operation mode is normal

K1_nx938 = X1_request_46 & !X1_request_47 & K1_cfr_12;


--K1_nx939 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx939
--operation mode is normal

K1_nx939 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_12 # !X1_request_48 & !K1_NOT_climits_a_12);


--K1_nx940 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx940
--operation mode is normal

K1_nx940 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_11 # !X1_request_48 & K1_adc_last_0_11);


--K1_nx941 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx941
--operation mode is normal

K1_nx941 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_11 # !X1_request_48 & K1_adc_last_4_11);


--K1_nx942 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx942
--operation mode is normal

K1_nx942 = X1_request_46 & !X1_request_47 & K1_cfr_11;


--K1_nx943 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx943
--operation mode is normal

K1_nx943 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_11 # !X1_request_48 & !K1_NOT_climits_a_11);


--K1_nx944 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx944
--operation mode is normal

K1_nx944 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_10 # !X1_request_48 & K1_adc_last_0_10);


--K1_nx945 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx945
--operation mode is normal

K1_nx945 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_10 # !X1_request_48 & K1_adc_last_4_10);


--K1_nx946 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx946
--operation mode is normal

K1_nx946 = X1_request_46 & !X1_request_47 & K1_cfr_10;


--K1_nx947 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx947
--operation mode is normal

K1_nx947 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_10 # !X1_request_48 & !K1_NOT_climits_a_10);


--K1_nx948 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx948
--operation mode is normal

K1_nx948 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_9 # !X1_request_48 & K1_adc_last_0_9);


--K1_nx949 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx949
--operation mode is normal

K1_nx949 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_9 # !X1_request_48 & K1_adc_last_4_9);


--K1_nx950 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx950
--operation mode is normal

K1_nx950 = X1_request_46 & !X1_request_47 & K1_cfr_9;


--K1_nx951 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx951
--operation mode is normal

K1_nx951 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_9 # !X1_request_48 & !K1_NOT_climits_a_9);


--K1_nx952 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx952
--operation mode is normal

K1_nx952 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_8 # !X1_request_48 & K1_adc_last_0_8);


--K1_nx953 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx953
--operation mode is normal

K1_nx953 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_8 # !X1_request_48 & K1_adc_last_4_8);


--K1_nx954 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx954
--operation mode is normal

K1_nx954 = X1_request_46 & !X1_request_47 & K1_cfr_8;


--K1_nx955 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx955
--operation mode is normal

K1_nx955 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_8 # !X1_request_48 & !K1_NOT_climits_a_8);


--K1_nx956 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx956
--operation mode is normal

K1_nx956 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_7 # !X1_request_48 & K1_adc_last_0_7);


--K1_nx957 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx957
--operation mode is normal

K1_nx957 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_7 # !X1_request_48 & K1_adc_last_4_7);


--K1_nx958 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx958
--operation mode is normal

K1_nx958 = X1_request_46 & !X1_request_47 & K1_cfr_7;


--K1_nx959 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx959
--operation mode is normal

K1_nx959 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_7 # !X1_request_48 & !K1_NOT_climits_a_7);


--K1_nx960 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx960
--operation mode is normal

K1_nx960 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_6 # !X1_request_48 & K1_adc_last_0_6);


--K1_nx961 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx961
--operation mode is normal

K1_nx961 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_6 # !X1_request_48 & K1_adc_last_4_6);


--K1_nx962 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx962
--operation mode is normal

K1_nx962 = X1_request_46 & !X1_request_47 & K1_cfr_6;


--K1_nx963 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx963
--operation mode is normal

K1_nx963 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_6 # !X1_request_48 & !K1_NOT_climits_a_6);


--K1_nx964 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx964
--operation mode is normal

K1_nx964 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_5 # !X1_request_48 & K1_adc_last_0_5);


--K1_nx965 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx965
--operation mode is normal

K1_nx965 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_5 # !X1_request_48 & K1_adc_last_4_5);


--K1_nx966 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx966
--operation mode is normal

K1_nx966 = X1_request_46 & !X1_request_47 & K1_cfr_5;


--K1_nx967 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx967
--operation mode is normal

K1_nx967 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_5 # !X1_request_48 & !K1_NOT_climits_a_5);


--K1_nx968 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx968
--operation mode is normal

K1_nx968 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_4 # !X1_request_48 & K1_adc_last_0_4);


--K1_nx969 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx969
--operation mode is normal

K1_nx969 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_4 # !X1_request_48 & K1_adc_last_4_4);


--K1_nx970 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx970
--operation mode is normal

K1_nx970 = X1_request_46 & !X1_request_47 & K1_cfr_4;


--K1_nx971 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx971
--operation mode is normal

K1_nx971 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_4 # !X1_request_48 & !K1_NOT_climits_a_4);


--K1_nx972 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx972
--operation mode is normal

K1_nx972 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_3 # !X1_request_48 & K1_adc_last_0_3);


--K1_nx973 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx973
--operation mode is normal

K1_nx973 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_3 # !X1_request_48 & K1_adc_last_4_3);


--K1_nx974 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx974
--operation mode is normal

K1_nx974 = X1_request_46 & !X1_request_47 & K1_cfr_3;


--K1_nx975 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx975
--operation mode is normal

K1_nx975 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_3 # !X1_request_48 & !K1_NOT_climits_a_3);


--K1_nx976 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx976
--operation mode is normal

K1_nx976 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_2 # !X1_request_48 & K1_adc_last_0_2);


--K1_nx977 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx977
--operation mode is normal

K1_nx977 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_2 # !X1_request_48 & K1_adc_last_4_2);


--K1_nx978 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx978
--operation mode is normal

K1_nx978 = X1_request_46 & !X1_request_47 & K1_cfr_2;


--K1_nx979 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx979
--operation mode is normal

K1_nx979 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_2 # !X1_request_48 & !K1_NOT_climits_a_2);


--K1_nx980 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx980
--operation mode is normal

K1_nx980 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_1 # !X1_request_48 & K1_adc_last_0_1);


--K1_nx981 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx981
--operation mode is normal

K1_nx981 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_1 # !X1_request_48 & K1_adc_last_4_1);


--K1_nx982 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx982
--operation mode is normal

K1_nx982 = X1_request_46 & !X1_request_47 & K1_cfr_1;


--K1_nx983 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx983
--operation mode is normal

K1_nx983 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_1 # !X1_request_48 & !K1_NOT_climits_a_1);


--K1_nx984 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx984
--operation mode is normal

K1_nx984 = !K1_nx991 & (X1_request_48 & K1_adc_last_2_0 # !X1_request_48 & K1_adc_last_0_0);


--K1_nx985 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx985
--operation mode is normal

K1_nx985 = !K1_nx990 & (X1_request_48 & K1_adc_last_6_0 # !X1_request_48 & K1_adc_last_4_0);


--K1_nx986 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx986
--operation mode is normal

K1_nx986 = X1_request_46 & !X1_request_47 & K1_cfr_0;


--K1_nx987 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx987
--operation mode is normal

K1_nx987 = !K1_nx993 & (X1_request_48 & !K1_NOT_climits_d_0 # !X1_request_48 & !K1_NOT_climits_a_0);


--K1_nx988 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx988
--operation mode is normal

K1_nx988 = K1_b_3 & K1_sm_5 & K1_ix38_ix21_nx8 # !K1_b_3 & K1_sm_2;


--K1_nx989 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx989
--operation mode is normal

K1_nx989 = !K1_send_cfr & K1_start_cyc & !K1_nx692;


--K1_nx990 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx990
--operation mode is normal

K1_nx990 = X1_request_46 # !X1_request_47;


--K1_nx991 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx991
--operation mode is normal

K1_nx991 = X1_request_46 # X1_request_47;


--K1_nx992 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx992
--operation mode is normal

K1_nx992 = K1_nx902 & (K1_nx692 # !K1_send_cfr & K1_start_cyc);


--K1_nx993 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx993
--operation mode is normal

K1_nx993 = !X1_request_47 # !X1_request_46;


--K1_RDATA_23 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_23
--operation mode is normal

K1_RDATA_23 = K1_nx903 # K1_nx904 # K1_nx905;


--K1_RDATA_22 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_22
--operation mode is normal

K1_RDATA_22 = K1_nx906 # K1_nx907 # K1_nx908;


--K1_RDATA_21 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_21
--operation mode is normal

K1_RDATA_21 = K1_nx909 # K1_nx910 # K1_nx911;


--K1_RDATA_20 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_20
--operation mode is normal

K1_RDATA_20 = K1_nx912 # K1_nx913 # K1_nx914;


--K1_RDATA_19 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_19
--operation mode is normal

K1_RDATA_19 = K1_nx915 # K1_nx916 # K1_nx917;


--K1_RDATA_18 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_18
--operation mode is normal

K1_RDATA_18 = K1_nx918 # K1_nx919 # K1_nx920;


--K1_RDATA_17 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_17
--operation mode is normal

K1_RDATA_17 = K1_nx921 # K1_nx922 # K1_nx923;


--K1_RDATA_16 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_16
--operation mode is normal

K1_RDATA_16 = K1_nx924 # K1_nx925 # K1_nx926;


--K1_RDATA_15 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_15
--operation mode is normal

K1_RDATA_15 = K1_nx927 # K1_nx928 # K1_nx929;


--K1_RDATA_14 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_14
--operation mode is normal

K1_RDATA_14 = K1_nx930 # K1_nx931 # K1_nx932;


--K1_RDATA_13 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_13
--operation mode is normal

K1_RDATA_13 = K1_nx933 # K1_nx934 # K1_nx935;


--K1_RDATA_12 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_12
--operation mode is normal

K1_RDATA_12 = K1_nx936 # K1_nx937 # K1_nx938 # K1_nx939;


--K1_RDATA_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_11
--operation mode is normal

K1_RDATA_11 = K1_nx940 # K1_nx941 # K1_nx942 # K1_nx943;


--K1_RDATA_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_10
--operation mode is normal

K1_RDATA_10 = K1_nx944 # K1_nx945 # K1_nx946 # K1_nx947;


--K1_RDATA_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_9
--operation mode is normal

K1_RDATA_9 = K1_nx948 # K1_nx949 # K1_nx950 # K1_nx951;


--K1_RDATA_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_8
--operation mode is normal

K1_RDATA_8 = K1_nx952 # K1_nx953 # K1_nx954 # K1_nx955;


--K1_RDATA_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_7
--operation mode is normal

K1_RDATA_7 = K1_nx956 # K1_nx957 # K1_nx958 # K1_nx959;


--K1_RDATA_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_6
--operation mode is normal

K1_RDATA_6 = K1_nx960 # K1_nx961 # K1_nx962 # K1_nx963;


--K1_RDATA_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_5
--operation mode is normal

K1_RDATA_5 = K1_nx964 # K1_nx965 # K1_nx966 # K1_nx967;


--K1_RDATA_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_4
--operation mode is normal

K1_RDATA_4 = K1_nx968 # K1_nx969 # K1_nx970 # K1_nx971;


--K1_RDATA_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_3
--operation mode is normal

K1_RDATA_3 = K1_nx972 # K1_nx973 # K1_nx974 # K1_nx975;


--K1_RDATA_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_2
--operation mode is normal

K1_RDATA_2 = K1_nx976 # K1_nx977 # K1_nx978 # K1_nx979;


--K1_RDATA_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_1
--operation mode is normal

K1_RDATA_1 = K1_nx980 # K1_nx981 # K1_nx982 # K1_nx983;


--K1_RDATA_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|RDATA_0
--operation mode is normal

K1_RDATA_0 = K1_nx984 # K1_nx985 # K1_nx986 # K1_nx987;


--K1_modgen_gt_181_nx30 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx30
--operation mode is arithmetic

K1_modgen_gt_181_nx30 = CARRY(K1_adc_last_4_0 & K1_NOT_climits_a_0);


--K1_modgen_gt_181_nx32 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx32
--operation mode is arithmetic

K1_modgen_gt_181_nx32 = CARRY(K1_NOT_climits_a_1 & !K1_adc_last_4_1 & !K1_modgen_gt_181_nx30 # !K1_NOT_climits_a_1 & (!K1_modgen_gt_181_nx30 # !K1_adc_last_4_1));


--K1_modgen_gt_181_nx34 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx34
--operation mode is arithmetic

K1_modgen_gt_181_nx34 = CARRY(K1_NOT_climits_a_2 & (K1_adc_last_4_2 # !K1_modgen_gt_181_nx32) # !K1_NOT_climits_a_2 & K1_adc_last_4_2 & !K1_modgen_gt_181_nx32);


--K1_modgen_gt_181_nx36 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx36
--operation mode is arithmetic

K1_modgen_gt_181_nx36 = CARRY(K1_NOT_climits_a_3 & !K1_adc_last_4_3 & !K1_modgen_gt_181_nx34 # !K1_NOT_climits_a_3 & (!K1_modgen_gt_181_nx34 # !K1_adc_last_4_3));


--K1_modgen_gt_181_nx38 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx38
--operation mode is arithmetic

K1_modgen_gt_181_nx38 = CARRY(K1_NOT_climits_a_4 & (K1_adc_last_4_4 # !K1_modgen_gt_181_nx36) # !K1_NOT_climits_a_4 & K1_adc_last_4_4 & !K1_modgen_gt_181_nx36);


--K1_modgen_gt_181_nx40 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx40
--operation mode is arithmetic

K1_modgen_gt_181_nx40 = CARRY(K1_NOT_climits_a_5 & !K1_adc_last_4_5 & !K1_modgen_gt_181_nx38 # !K1_NOT_climits_a_5 & (!K1_modgen_gt_181_nx38 # !K1_adc_last_4_5));


--K1_modgen_gt_181_nx42 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx42
--operation mode is arithmetic

K1_modgen_gt_181_nx42 = CARRY(K1_NOT_climits_a_6 & (K1_adc_last_4_6 # !K1_modgen_gt_181_nx40) # !K1_NOT_climits_a_6 & K1_adc_last_4_6 & !K1_modgen_gt_181_nx40);


--K1_modgen_gt_181_nx44 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx44
--operation mode is arithmetic

K1_modgen_gt_181_nx44 = CARRY(K1_NOT_climits_a_7 & !K1_adc_last_4_7 & !K1_modgen_gt_181_nx42 # !K1_NOT_climits_a_7 & (!K1_modgen_gt_181_nx42 # !K1_adc_last_4_7));


--K1_modgen_gt_181_nx46 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx46
--operation mode is arithmetic

K1_modgen_gt_181_nx46 = CARRY(K1_NOT_climits_a_8 & (K1_adc_last_4_8 # !K1_modgen_gt_181_nx44) # !K1_NOT_climits_a_8 & K1_adc_last_4_8 & !K1_modgen_gt_181_nx44);


--K1_modgen_gt_181_nx48 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx48
--operation mode is arithmetic

K1_modgen_gt_181_nx48 = CARRY(K1_NOT_climits_a_9 & !K1_adc_last_4_9 & !K1_modgen_gt_181_nx46 # !K1_NOT_climits_a_9 & (!K1_modgen_gt_181_nx46 # !K1_adc_last_4_9));


--K1_modgen_gt_181_nx50 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_181_nx50
--operation mode is arithmetic

K1_modgen_gt_181_nx50 = CARRY(K1_NOT_climits_a_10 & (K1_adc_last_4_10 # !K1_modgen_gt_181_nx48) # !K1_NOT_climits_a_10 & K1_adc_last_4_10 & !K1_modgen_gt_181_nx48);


--K1_nx2777 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx2777
--operation mode is normal

K1_nx2777_carry_eqn = K1_modgen_gt_181_nx50;
K1_nx2777 = K1_NOT_climits_a_11 & (K1_adc_last_4_11 # K1_nx2777_carry_eqn) # !K1_NOT_climits_a_11 & K1_adc_last_4_11 & K1_nx2777_carry_eqn;


--K1_modgen_gt_182_nx30 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx30
--operation mode is arithmetic

K1_modgen_gt_182_nx30 = CARRY(K1_adc_last_5_0 & K1_NOT_climits_a_12);


--K1_modgen_gt_182_nx32 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx32
--operation mode is arithmetic

K1_modgen_gt_182_nx32 = CARRY(K1_NOT_climits_a_13 & !K1_adc_last_5_1 & !K1_modgen_gt_182_nx30 # !K1_NOT_climits_a_13 & (!K1_modgen_gt_182_nx30 # !K1_adc_last_5_1));


--K1_modgen_gt_182_nx34 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx34
--operation mode is arithmetic

K1_modgen_gt_182_nx34 = CARRY(K1_NOT_climits_a_14 & (K1_adc_last_5_2 # !K1_modgen_gt_182_nx32) # !K1_NOT_climits_a_14 & K1_adc_last_5_2 & !K1_modgen_gt_182_nx32);


--K1_modgen_gt_182_nx36 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx36
--operation mode is arithmetic

K1_modgen_gt_182_nx36 = CARRY(K1_NOT_climits_a_15 & !K1_adc_last_5_3 & !K1_modgen_gt_182_nx34 # !K1_NOT_climits_a_15 & (!K1_modgen_gt_182_nx34 # !K1_adc_last_5_3));


--K1_modgen_gt_182_nx38 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx38
--operation mode is arithmetic

K1_modgen_gt_182_nx38 = CARRY(K1_NOT_climits_a_16 & (K1_adc_last_5_4 # !K1_modgen_gt_182_nx36) # !K1_NOT_climits_a_16 & K1_adc_last_5_4 & !K1_modgen_gt_182_nx36);


--K1_modgen_gt_182_nx40 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx40
--operation mode is arithmetic

K1_modgen_gt_182_nx40 = CARRY(K1_NOT_climits_a_17 & !K1_adc_last_5_5 & !K1_modgen_gt_182_nx38 # !K1_NOT_climits_a_17 & (!K1_modgen_gt_182_nx38 # !K1_adc_last_5_5));


--K1_modgen_gt_182_nx42 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx42
--operation mode is arithmetic

K1_modgen_gt_182_nx42 = CARRY(K1_NOT_climits_a_18 & (K1_adc_last_5_6 # !K1_modgen_gt_182_nx40) # !K1_NOT_climits_a_18 & K1_adc_last_5_6 & !K1_modgen_gt_182_nx40);


--K1_modgen_gt_182_nx44 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx44
--operation mode is arithmetic

K1_modgen_gt_182_nx44 = CARRY(K1_NOT_climits_a_19 & !K1_adc_last_5_7 & !K1_modgen_gt_182_nx42 # !K1_NOT_climits_a_19 & (!K1_modgen_gt_182_nx42 # !K1_adc_last_5_7));


--K1_modgen_gt_182_nx46 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx46
--operation mode is arithmetic

K1_modgen_gt_182_nx46 = CARRY(K1_NOT_climits_a_20 & (K1_adc_last_5_8 # !K1_modgen_gt_182_nx44) # !K1_NOT_climits_a_20 & K1_adc_last_5_8 & !K1_modgen_gt_182_nx44);


--K1_modgen_gt_182_nx48 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx48
--operation mode is arithmetic

K1_modgen_gt_182_nx48 = CARRY(K1_NOT_climits_a_21 & !K1_adc_last_5_9 & !K1_modgen_gt_182_nx46 # !K1_NOT_climits_a_21 & (!K1_modgen_gt_182_nx46 # !K1_adc_last_5_9));


--K1_modgen_gt_182_nx50 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_182_nx50
--operation mode is arithmetic

K1_modgen_gt_182_nx50 = CARRY(K1_NOT_climits_a_22 & (K1_adc_last_5_10 # !K1_modgen_gt_182_nx48) # !K1_NOT_climits_a_22 & K1_adc_last_5_10 & !K1_modgen_gt_182_nx48);


--K1_nx2780 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx2780
--operation mode is normal

K1_nx2780_carry_eqn = K1_modgen_gt_182_nx50;
K1_nx2780 = K1_NOT_climits_a_23 & (K1_adc_last_5_11 # K1_nx2780_carry_eqn) # !K1_NOT_climits_a_23 & K1_adc_last_5_11 & K1_nx2780_carry_eqn;


--K1_modgen_gt_183_nx30 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx30
--operation mode is arithmetic

K1_modgen_gt_183_nx30 = CARRY(K1_adc_last_6_0 & K1_NOT_climits_d_0);


--K1_modgen_gt_183_nx32 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx32
--operation mode is arithmetic

K1_modgen_gt_183_nx32 = CARRY(K1_NOT_climits_d_1 & !K1_adc_last_6_1 & !K1_modgen_gt_183_nx30 # !K1_NOT_climits_d_1 & (!K1_modgen_gt_183_nx30 # !K1_adc_last_6_1));


--K1_modgen_gt_183_nx34 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx34
--operation mode is arithmetic

K1_modgen_gt_183_nx34 = CARRY(K1_NOT_climits_d_2 & (K1_adc_last_6_2 # !K1_modgen_gt_183_nx32) # !K1_NOT_climits_d_2 & K1_adc_last_6_2 & !K1_modgen_gt_183_nx32);


--K1_modgen_gt_183_nx36 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx36
--operation mode is arithmetic

K1_modgen_gt_183_nx36 = CARRY(K1_NOT_climits_d_3 & !K1_adc_last_6_3 & !K1_modgen_gt_183_nx34 # !K1_NOT_climits_d_3 & (!K1_modgen_gt_183_nx34 # !K1_adc_last_6_3));


--K1_modgen_gt_183_nx38 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx38
--operation mode is arithmetic

K1_modgen_gt_183_nx38 = CARRY(K1_NOT_climits_d_4 & (K1_adc_last_6_4 # !K1_modgen_gt_183_nx36) # !K1_NOT_climits_d_4 & K1_adc_last_6_4 & !K1_modgen_gt_183_nx36);


--K1_modgen_gt_183_nx40 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx40
--operation mode is arithmetic

K1_modgen_gt_183_nx40 = CARRY(K1_NOT_climits_d_5 & !K1_adc_last_6_5 & !K1_modgen_gt_183_nx38 # !K1_NOT_climits_d_5 & (!K1_modgen_gt_183_nx38 # !K1_adc_last_6_5));


--K1_modgen_gt_183_nx42 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx42
--operation mode is arithmetic

K1_modgen_gt_183_nx42 = CARRY(K1_NOT_climits_d_6 & (K1_adc_last_6_6 # !K1_modgen_gt_183_nx40) # !K1_NOT_climits_d_6 & K1_adc_last_6_6 & !K1_modgen_gt_183_nx40);


--K1_modgen_gt_183_nx44 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx44
--operation mode is arithmetic

K1_modgen_gt_183_nx44 = CARRY(K1_NOT_climits_d_7 & !K1_adc_last_6_7 & !K1_modgen_gt_183_nx42 # !K1_NOT_climits_d_7 & (!K1_modgen_gt_183_nx42 # !K1_adc_last_6_7));


--K1_modgen_gt_183_nx46 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx46
--operation mode is arithmetic

K1_modgen_gt_183_nx46 = CARRY(K1_NOT_climits_d_8 & (K1_adc_last_6_8 # !K1_modgen_gt_183_nx44) # !K1_NOT_climits_d_8 & K1_adc_last_6_8 & !K1_modgen_gt_183_nx44);


--K1_modgen_gt_183_nx48 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx48
--operation mode is arithmetic

K1_modgen_gt_183_nx48 = CARRY(K1_NOT_climits_d_9 & !K1_adc_last_6_9 & !K1_modgen_gt_183_nx46 # !K1_NOT_climits_d_9 & (!K1_modgen_gt_183_nx46 # !K1_adc_last_6_9));


--K1_modgen_gt_183_nx50 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_183_nx50
--operation mode is arithmetic

K1_modgen_gt_183_nx50 = CARRY(K1_NOT_climits_d_10 & (K1_adc_last_6_10 # !K1_modgen_gt_183_nx48) # !K1_NOT_climits_d_10 & K1_adc_last_6_10 & !K1_modgen_gt_183_nx48);


--K1_nx2783 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx2783
--operation mode is normal

K1_nx2783_carry_eqn = K1_modgen_gt_183_nx50;
K1_nx2783 = K1_NOT_climits_d_11 & (K1_adc_last_6_11 # K1_nx2783_carry_eqn) # !K1_NOT_climits_d_11 & K1_adc_last_6_11 & K1_nx2783_carry_eqn;


--K1_modgen_gt_184_nx30 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx30
--operation mode is arithmetic

K1_modgen_gt_184_nx30 = CARRY(K1_adc_last_7_0 & K1_NOT_climits_d_12);


--K1_modgen_gt_184_nx32 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx32
--operation mode is arithmetic

K1_modgen_gt_184_nx32 = CARRY(K1_NOT_climits_d_13 & !K1_adc_last_7_1 & !K1_modgen_gt_184_nx30 # !K1_NOT_climits_d_13 & (!K1_modgen_gt_184_nx30 # !K1_adc_last_7_1));


--K1_modgen_gt_184_nx34 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx34
--operation mode is arithmetic

K1_modgen_gt_184_nx34 = CARRY(K1_NOT_climits_d_14 & (K1_adc_last_7_2 # !K1_modgen_gt_184_nx32) # !K1_NOT_climits_d_14 & K1_adc_last_7_2 & !K1_modgen_gt_184_nx32);


--K1_modgen_gt_184_nx36 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx36
--operation mode is arithmetic

K1_modgen_gt_184_nx36 = CARRY(K1_NOT_climits_d_15 & !K1_adc_last_7_3 & !K1_modgen_gt_184_nx34 # !K1_NOT_climits_d_15 & (!K1_modgen_gt_184_nx34 # !K1_adc_last_7_3));


--K1_modgen_gt_184_nx38 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx38
--operation mode is arithmetic

K1_modgen_gt_184_nx38 = CARRY(K1_NOT_climits_d_16 & (K1_adc_last_7_4 # !K1_modgen_gt_184_nx36) # !K1_NOT_climits_d_16 & K1_adc_last_7_4 & !K1_modgen_gt_184_nx36);


--K1_modgen_gt_184_nx40 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx40
--operation mode is arithmetic

K1_modgen_gt_184_nx40 = CARRY(K1_NOT_climits_d_17 & !K1_adc_last_7_5 & !K1_modgen_gt_184_nx38 # !K1_NOT_climits_d_17 & (!K1_modgen_gt_184_nx38 # !K1_adc_last_7_5));


--K1_modgen_gt_184_nx42 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx42
--operation mode is arithmetic

K1_modgen_gt_184_nx42 = CARRY(K1_NOT_climits_d_18 & (K1_adc_last_7_6 # !K1_modgen_gt_184_nx40) # !K1_NOT_climits_d_18 & K1_adc_last_7_6 & !K1_modgen_gt_184_nx40);


--K1_modgen_gt_184_nx44 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx44
--operation mode is arithmetic

K1_modgen_gt_184_nx44 = CARRY(K1_NOT_climits_d_19 & !K1_adc_last_7_7 & !K1_modgen_gt_184_nx42 # !K1_NOT_climits_d_19 & (!K1_modgen_gt_184_nx42 # !K1_adc_last_7_7));


--K1_modgen_gt_184_nx46 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx46
--operation mode is arithmetic

K1_modgen_gt_184_nx46 = CARRY(K1_NOT_climits_d_20 & (K1_adc_last_7_8 # !K1_modgen_gt_184_nx44) # !K1_NOT_climits_d_20 & K1_adc_last_7_8 & !K1_modgen_gt_184_nx44);


--K1_modgen_gt_184_nx48 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx48
--operation mode is arithmetic

K1_modgen_gt_184_nx48 = CARRY(K1_NOT_climits_d_21 & !K1_adc_last_7_9 & !K1_modgen_gt_184_nx46 # !K1_NOT_climits_d_21 & (!K1_modgen_gt_184_nx46 # !K1_adc_last_7_9));


--K1_modgen_gt_184_nx50 is ADC_DAC_0:adcdac|seradc_auto:power_adc|modgen_gt_184_nx50
--operation mode is arithmetic

K1_modgen_gt_184_nx50 = CARRY(K1_NOT_climits_d_22 & (K1_adc_last_7_10 # !K1_modgen_gt_184_nx48) # !K1_NOT_climits_d_22 & K1_adc_last_7_10 & !K1_modgen_gt_184_nx48);


--K1_nx2786 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx2786
--operation mode is normal

K1_nx2786_carry_eqn = K1_modgen_gt_184_nx50;
K1_nx2786 = K1_NOT_climits_d_23 & (K1_adc_last_7_11 # K1_nx2786_carry_eqn) # !K1_NOT_climits_d_23 & K1_adc_last_7_11 & K1_nx2786_carry_eqn;


--K1_adc_last_0_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_0
--operation mode is normal

K1_adc_last_0_0_lut_out = T1_RDATA_0;
K1_adc_last_0_0 = DFFEA(K1_adc_last_0_0_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_1
--operation mode is normal

K1_adc_last_0_1_lut_out = T1_RDATA_1;
K1_adc_last_0_1 = DFFEA(K1_adc_last_0_1_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_10
--operation mode is normal

K1_adc_last_0_10_lut_out = T1_RDATA_10;
K1_adc_last_0_10 = DFFEA(K1_adc_last_0_10_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_11
--operation mode is normal

K1_adc_last_0_11_lut_out = T1_RDATA_11;
K1_adc_last_0_11 = DFFEA(K1_adc_last_0_11_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_2
--operation mode is normal

K1_adc_last_0_2_lut_out = T1_RDATA_2;
K1_adc_last_0_2 = DFFEA(K1_adc_last_0_2_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_3
--operation mode is normal

K1_adc_last_0_3_lut_out = T1_RDATA_3;
K1_adc_last_0_3 = DFFEA(K1_adc_last_0_3_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_4
--operation mode is normal

K1_adc_last_0_4_lut_out = T1_RDATA_4;
K1_adc_last_0_4 = DFFEA(K1_adc_last_0_4_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_5
--operation mode is normal

K1_adc_last_0_5_lut_out = T1_RDATA_5;
K1_adc_last_0_5 = DFFEA(K1_adc_last_0_5_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_6
--operation mode is normal

K1_adc_last_0_6_lut_out = T1_RDATA_6;
K1_adc_last_0_6 = DFFEA(K1_adc_last_0_6_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_7
--operation mode is normal

K1_adc_last_0_7_lut_out = T1_RDATA_7;
K1_adc_last_0_7 = DFFEA(K1_adc_last_0_7_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_8
--operation mode is normal

K1_adc_last_0_8_lut_out = T1_RDATA_8;
K1_adc_last_0_8 = DFFEA(K1_adc_last_0_8_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_0_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_0_9
--operation mode is normal

K1_adc_last_0_9_lut_out = T1_RDATA_9;
K1_adc_last_0_9 = DFFEA(K1_adc_last_0_9_lut_out, U1__clk1, VCC, , K1_NOT_nx2189, , );


--K1_adc_last_1_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_0
--operation mode is normal

K1_adc_last_1_0_lut_out = T1_RDATA_0;
K1_adc_last_1_0 = DFFEA(K1_adc_last_1_0_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_1
--operation mode is normal

K1_adc_last_1_1_lut_out = T1_RDATA_1;
K1_adc_last_1_1 = DFFEA(K1_adc_last_1_1_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_10
--operation mode is normal

K1_adc_last_1_10_lut_out = T1_RDATA_10;
K1_adc_last_1_10 = DFFEA(K1_adc_last_1_10_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_11
--operation mode is normal

K1_adc_last_1_11_lut_out = T1_RDATA_11;
K1_adc_last_1_11 = DFFEA(K1_adc_last_1_11_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_2
--operation mode is normal

K1_adc_last_1_2_lut_out = T1_RDATA_2;
K1_adc_last_1_2 = DFFEA(K1_adc_last_1_2_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_3
--operation mode is normal

K1_adc_last_1_3_lut_out = T1_RDATA_3;
K1_adc_last_1_3 = DFFEA(K1_adc_last_1_3_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_4
--operation mode is normal

K1_adc_last_1_4_lut_out = T1_RDATA_4;
K1_adc_last_1_4 = DFFEA(K1_adc_last_1_4_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_5
--operation mode is normal

K1_adc_last_1_5_lut_out = T1_RDATA_5;
K1_adc_last_1_5 = DFFEA(K1_adc_last_1_5_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_6
--operation mode is normal

K1_adc_last_1_6_lut_out = T1_RDATA_6;
K1_adc_last_1_6 = DFFEA(K1_adc_last_1_6_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_7
--operation mode is normal

K1_adc_last_1_7_lut_out = T1_RDATA_7;
K1_adc_last_1_7 = DFFEA(K1_adc_last_1_7_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_8
--operation mode is normal

K1_adc_last_1_8_lut_out = T1_RDATA_8;
K1_adc_last_1_8 = DFFEA(K1_adc_last_1_8_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_1_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_1_9
--operation mode is normal

K1_adc_last_1_9_lut_out = T1_RDATA_9;
K1_adc_last_1_9 = DFFEA(K1_adc_last_1_9_lut_out, U1__clk1, VCC, , K1_NOT_nx2213, , );


--K1_adc_last_2_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_0
--operation mode is normal

K1_adc_last_2_0_lut_out = T1_RDATA_0;
K1_adc_last_2_0 = DFFEA(K1_adc_last_2_0_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_1
--operation mode is normal

K1_adc_last_2_1_lut_out = T1_RDATA_1;
K1_adc_last_2_1 = DFFEA(K1_adc_last_2_1_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_10
--operation mode is normal

K1_adc_last_2_10_lut_out = T1_RDATA_10;
K1_adc_last_2_10 = DFFEA(K1_adc_last_2_10_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_11
--operation mode is normal

K1_adc_last_2_11_lut_out = T1_RDATA_11;
K1_adc_last_2_11 = DFFEA(K1_adc_last_2_11_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_2
--operation mode is normal

K1_adc_last_2_2_lut_out = T1_RDATA_2;
K1_adc_last_2_2 = DFFEA(K1_adc_last_2_2_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_3
--operation mode is normal

K1_adc_last_2_3_lut_out = T1_RDATA_3;
K1_adc_last_2_3 = DFFEA(K1_adc_last_2_3_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_4
--operation mode is normal

K1_adc_last_2_4_lut_out = T1_RDATA_4;
K1_adc_last_2_4 = DFFEA(K1_adc_last_2_4_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_5
--operation mode is normal

K1_adc_last_2_5_lut_out = T1_RDATA_5;
K1_adc_last_2_5 = DFFEA(K1_adc_last_2_5_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_6
--operation mode is normal

K1_adc_last_2_6_lut_out = T1_RDATA_6;
K1_adc_last_2_6 = DFFEA(K1_adc_last_2_6_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_7
--operation mode is normal

K1_adc_last_2_7_lut_out = T1_RDATA_7;
K1_adc_last_2_7 = DFFEA(K1_adc_last_2_7_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_8
--operation mode is normal

K1_adc_last_2_8_lut_out = T1_RDATA_8;
K1_adc_last_2_8 = DFFEA(K1_adc_last_2_8_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_2_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_2_9
--operation mode is normal

K1_adc_last_2_9_lut_out = T1_RDATA_9;
K1_adc_last_2_9 = DFFEA(K1_adc_last_2_9_lut_out, U1__clk1, VCC, , K1_NOT_nx2237, , );


--K1_adc_last_3_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_0
--operation mode is normal

K1_adc_last_3_0_lut_out = T1_RDATA_0;
K1_adc_last_3_0 = DFFEA(K1_adc_last_3_0_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_1
--operation mode is normal

K1_adc_last_3_1_lut_out = T1_RDATA_1;
K1_adc_last_3_1 = DFFEA(K1_adc_last_3_1_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_10
--operation mode is normal

K1_adc_last_3_10_lut_out = T1_RDATA_10;
K1_adc_last_3_10 = DFFEA(K1_adc_last_3_10_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_11
--operation mode is normal

K1_adc_last_3_11_lut_out = T1_RDATA_11;
K1_adc_last_3_11 = DFFEA(K1_adc_last_3_11_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_2
--operation mode is normal

K1_adc_last_3_2_lut_out = T1_RDATA_2;
K1_adc_last_3_2 = DFFEA(K1_adc_last_3_2_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_3
--operation mode is normal

K1_adc_last_3_3_lut_out = T1_RDATA_3;
K1_adc_last_3_3 = DFFEA(K1_adc_last_3_3_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_4
--operation mode is normal

K1_adc_last_3_4_lut_out = T1_RDATA_4;
K1_adc_last_3_4 = DFFEA(K1_adc_last_3_4_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_5
--operation mode is normal

K1_adc_last_3_5_lut_out = T1_RDATA_5;
K1_adc_last_3_5 = DFFEA(K1_adc_last_3_5_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_6
--operation mode is normal

K1_adc_last_3_6_lut_out = T1_RDATA_6;
K1_adc_last_3_6 = DFFEA(K1_adc_last_3_6_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_7
--operation mode is normal

K1_adc_last_3_7_lut_out = T1_RDATA_7;
K1_adc_last_3_7 = DFFEA(K1_adc_last_3_7_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_8
--operation mode is normal

K1_adc_last_3_8_lut_out = T1_RDATA_8;
K1_adc_last_3_8 = DFFEA(K1_adc_last_3_8_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_3_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_3_9
--operation mode is normal

K1_adc_last_3_9_lut_out = T1_RDATA_9;
K1_adc_last_3_9 = DFFEA(K1_adc_last_3_9_lut_out, U1__clk1, VCC, , K1_NOT_nx2261, , );


--K1_adc_last_4_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_0
--operation mode is normal

K1_adc_last_4_0_lut_out = T1_RDATA_0;
K1_adc_last_4_0 = DFFEA(K1_adc_last_4_0_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_1
--operation mode is normal

K1_adc_last_4_1_lut_out = T1_RDATA_1;
K1_adc_last_4_1 = DFFEA(K1_adc_last_4_1_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_10
--operation mode is normal

K1_adc_last_4_10_lut_out = T1_RDATA_10;
K1_adc_last_4_10 = DFFEA(K1_adc_last_4_10_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_11
--operation mode is normal

K1_adc_last_4_11_lut_out = T1_RDATA_11;
K1_adc_last_4_11 = DFFEA(K1_adc_last_4_11_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_2
--operation mode is normal

K1_adc_last_4_2_lut_out = T1_RDATA_2;
K1_adc_last_4_2 = DFFEA(K1_adc_last_4_2_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_3
--operation mode is normal

K1_adc_last_4_3_lut_out = T1_RDATA_3;
K1_adc_last_4_3 = DFFEA(K1_adc_last_4_3_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_4
--operation mode is normal

K1_adc_last_4_4_lut_out = T1_RDATA_4;
K1_adc_last_4_4 = DFFEA(K1_adc_last_4_4_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_5
--operation mode is normal

K1_adc_last_4_5_lut_out = T1_RDATA_5;
K1_adc_last_4_5 = DFFEA(K1_adc_last_4_5_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_6
--operation mode is normal

K1_adc_last_4_6_lut_out = T1_RDATA_6;
K1_adc_last_4_6 = DFFEA(K1_adc_last_4_6_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_7
--operation mode is normal

K1_adc_last_4_7_lut_out = T1_RDATA_7;
K1_adc_last_4_7 = DFFEA(K1_adc_last_4_7_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_8
--operation mode is normal

K1_adc_last_4_8_lut_out = T1_RDATA_8;
K1_adc_last_4_8 = DFFEA(K1_adc_last_4_8_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_4_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_4_9
--operation mode is normal

K1_adc_last_4_9_lut_out = T1_RDATA_9;
K1_adc_last_4_9 = DFFEA(K1_adc_last_4_9_lut_out, U1__clk1, VCC, , K1_NOT_nx2285, , );


--K1_adc_last_5_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_0
--operation mode is normal

K1_adc_last_5_0_lut_out = T1_RDATA_0;
K1_adc_last_5_0 = DFFEA(K1_adc_last_5_0_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_1
--operation mode is normal

K1_adc_last_5_1_lut_out = T1_RDATA_1;
K1_adc_last_5_1 = DFFEA(K1_adc_last_5_1_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_10
--operation mode is normal

K1_adc_last_5_10_lut_out = T1_RDATA_10;
K1_adc_last_5_10 = DFFEA(K1_adc_last_5_10_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_11
--operation mode is normal

K1_adc_last_5_11_lut_out = T1_RDATA_11;
K1_adc_last_5_11 = DFFEA(K1_adc_last_5_11_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_2
--operation mode is normal

K1_adc_last_5_2_lut_out = T1_RDATA_2;
K1_adc_last_5_2 = DFFEA(K1_adc_last_5_2_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_3
--operation mode is normal

K1_adc_last_5_3_lut_out = T1_RDATA_3;
K1_adc_last_5_3 = DFFEA(K1_adc_last_5_3_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_4
--operation mode is normal

K1_adc_last_5_4_lut_out = T1_RDATA_4;
K1_adc_last_5_4 = DFFEA(K1_adc_last_5_4_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_5
--operation mode is normal

K1_adc_last_5_5_lut_out = T1_RDATA_5;
K1_adc_last_5_5 = DFFEA(K1_adc_last_5_5_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_6
--operation mode is normal

K1_adc_last_5_6_lut_out = T1_RDATA_6;
K1_adc_last_5_6 = DFFEA(K1_adc_last_5_6_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_7
--operation mode is normal

K1_adc_last_5_7_lut_out = T1_RDATA_7;
K1_adc_last_5_7 = DFFEA(K1_adc_last_5_7_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_8
--operation mode is normal

K1_adc_last_5_8_lut_out = T1_RDATA_8;
K1_adc_last_5_8 = DFFEA(K1_adc_last_5_8_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_5_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_5_9
--operation mode is normal

K1_adc_last_5_9_lut_out = T1_RDATA_9;
K1_adc_last_5_9 = DFFEA(K1_adc_last_5_9_lut_out, U1__clk1, VCC, , K1_NOT_nx2309, , );


--K1_adc_last_6_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_0
--operation mode is normal

K1_adc_last_6_0_lut_out = T1_RDATA_0;
K1_adc_last_6_0 = DFFEA(K1_adc_last_6_0_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_1
--operation mode is normal

K1_adc_last_6_1_lut_out = T1_RDATA_1;
K1_adc_last_6_1 = DFFEA(K1_adc_last_6_1_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_10
--operation mode is normal

K1_adc_last_6_10_lut_out = T1_RDATA_10;
K1_adc_last_6_10 = DFFEA(K1_adc_last_6_10_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_11
--operation mode is normal

K1_adc_last_6_11_lut_out = T1_RDATA_11;
K1_adc_last_6_11 = DFFEA(K1_adc_last_6_11_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_2
--operation mode is normal

K1_adc_last_6_2_lut_out = T1_RDATA_2;
K1_adc_last_6_2 = DFFEA(K1_adc_last_6_2_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_3
--operation mode is normal

K1_adc_last_6_3_lut_out = T1_RDATA_3;
K1_adc_last_6_3 = DFFEA(K1_adc_last_6_3_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_4
--operation mode is normal

K1_adc_last_6_4_lut_out = T1_RDATA_4;
K1_adc_last_6_4 = DFFEA(K1_adc_last_6_4_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_5
--operation mode is normal

K1_adc_last_6_5_lut_out = T1_RDATA_5;
K1_adc_last_6_5 = DFFEA(K1_adc_last_6_5_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_6
--operation mode is normal

K1_adc_last_6_6_lut_out = T1_RDATA_6;
K1_adc_last_6_6 = DFFEA(K1_adc_last_6_6_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_7
--operation mode is normal

K1_adc_last_6_7_lut_out = T1_RDATA_7;
K1_adc_last_6_7 = DFFEA(K1_adc_last_6_7_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_8
--operation mode is normal

K1_adc_last_6_8_lut_out = T1_RDATA_8;
K1_adc_last_6_8 = DFFEA(K1_adc_last_6_8_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_6_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_6_9
--operation mode is normal

K1_adc_last_6_9_lut_out = T1_RDATA_9;
K1_adc_last_6_9 = DFFEA(K1_adc_last_6_9_lut_out, U1__clk1, VCC, , K1_NOT_nx2333, , );


--K1_adc_last_7_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_0
--operation mode is normal

K1_adc_last_7_0_lut_out = T1_RDATA_0;
K1_adc_last_7_0 = DFFEA(K1_adc_last_7_0_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_1
--operation mode is normal

K1_adc_last_7_1_lut_out = T1_RDATA_1;
K1_adc_last_7_1 = DFFEA(K1_adc_last_7_1_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_10
--operation mode is normal

K1_adc_last_7_10_lut_out = T1_RDATA_10;
K1_adc_last_7_10 = DFFEA(K1_adc_last_7_10_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_11
--operation mode is normal

K1_adc_last_7_11_lut_out = T1_RDATA_11;
K1_adc_last_7_11 = DFFEA(K1_adc_last_7_11_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_2
--operation mode is normal

K1_adc_last_7_2_lut_out = T1_RDATA_2;
K1_adc_last_7_2 = DFFEA(K1_adc_last_7_2_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_3
--operation mode is normal

K1_adc_last_7_3_lut_out = T1_RDATA_3;
K1_adc_last_7_3 = DFFEA(K1_adc_last_7_3_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_4
--operation mode is normal

K1_adc_last_7_4_lut_out = T1_RDATA_4;
K1_adc_last_7_4 = DFFEA(K1_adc_last_7_4_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_5
--operation mode is normal

K1_adc_last_7_5_lut_out = T1_RDATA_5;
K1_adc_last_7_5 = DFFEA(K1_adc_last_7_5_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_6
--operation mode is normal

K1_adc_last_7_6_lut_out = T1_RDATA_6;
K1_adc_last_7_6 = DFFEA(K1_adc_last_7_6_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_7
--operation mode is normal

K1_adc_last_7_7_lut_out = T1_RDATA_7;
K1_adc_last_7_7 = DFFEA(K1_adc_last_7_7_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_8
--operation mode is normal

K1_adc_last_7_8_lut_out = T1_RDATA_8;
K1_adc_last_7_8 = DFFEA(K1_adc_last_7_8_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_adc_last_7_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|adc_last_7_9
--operation mode is normal

K1_adc_last_7_9_lut_out = T1_RDATA_9;
K1_adc_last_7_9 = DFFEA(K1_adc_last_7_9_lut_out, U1__clk1, VCC, , K1_modgen_select_123_nx2, , );


--K1_NOT_ADC_nCSStrt is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_ADC_nCSStrt
--operation mode is normal

K1_NOT_ADC_nCSStrt_lut_out = K1_sm_2;
K1_NOT_ADC_nCSStrt = DFFEA(K1_NOT_ADC_nCSStrt_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_ce_adc is ADC_DAC_0:adcdac|seradc_auto:power_adc|ce_adc
--operation mode is normal

K1_ce_adc_lut_out = K1_sm_6 # K1_modgen_select_136_nx2 # K1_send_cfr & !K1_nx692;
K1_ce_adc = DFFEA(K1_ce_adc_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_cfr_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_0
--operation mode is normal

K1_cfr_0_lut_out = X1_request_31;
K1_cfr_0 = DFFEA(K1_cfr_0_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_1
--operation mode is normal

K1_cfr_1_lut_out = X1_request_30;
K1_cfr_1 = DFFEA(K1_cfr_1_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_10
--operation mode is normal

K1_cfr_10_lut_out = X1_request_21;
K1_cfr_10 = DFFEA(K1_cfr_10_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_11
--operation mode is normal

K1_cfr_11_lut_out = X1_request_20;
K1_cfr_11 = DFFEA(K1_cfr_11_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_12 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_12
--operation mode is normal

K1_cfr_12_lut_out = X1_request_19;
K1_cfr_12 = DFFEA(K1_cfr_12_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_2
--operation mode is normal

K1_cfr_2_lut_out = X1_request_29;
K1_cfr_2 = DFFEA(K1_cfr_2_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_3
--operation mode is normal

K1_cfr_3_lut_out = X1_request_28;
K1_cfr_3 = DFFEA(K1_cfr_3_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_4
--operation mode is normal

K1_cfr_4_lut_out = X1_request_27;
K1_cfr_4 = DFFEA(K1_cfr_4_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_5
--operation mode is normal

K1_cfr_5_lut_out = X1_request_26;
K1_cfr_5 = DFFEA(K1_cfr_5_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_6
--operation mode is normal

K1_cfr_6_lut_out = X1_request_25;
K1_cfr_6 = DFFEA(K1_cfr_6_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_7
--operation mode is normal

K1_cfr_7_lut_out = X1_request_24;
K1_cfr_7 = DFFEA(K1_cfr_7_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_8
--operation mode is normal

K1_cfr_8_lut_out = X1_request_23;
K1_cfr_8 = DFFEA(K1_cfr_8_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cfr_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cfr_9
--operation mode is normal

K1_cfr_9_lut_out = X1_request_22;
K1_cfr_9 = DFFEA(K1_cfr_9_lut_out, U1__clk1, V1_chipRST_n, , K1_nx538, , );


--K1_cl_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cl_0
--operation mode is normal

K1_cl_0_lut_out = K1_nx2777 # K1_nx2783;
K1_cl_0 = DFFEA(K1_cl_0_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_cl_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cl_1
--operation mode is normal

K1_cl_1_lut_out = K1_nx2780 # K1_nx2786;
K1_cl_1 = DFFEA(K1_cl_1_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_NOT_climits_a_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_0
--operation mode is normal

K1_NOT_climits_a_0_lut_out = !X1_request_31;
K1_NOT_climits_a_0 = DFFEA(K1_NOT_climits_a_0_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_1
--operation mode is normal

K1_NOT_climits_a_1_lut_out = !X1_request_30;
K1_NOT_climits_a_1 = DFFEA(K1_NOT_climits_a_1_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_10
--operation mode is normal

K1_NOT_climits_a_10_lut_out = !X1_request_21;
K1_NOT_climits_a_10 = DFFEA(K1_NOT_climits_a_10_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_11
--operation mode is normal

K1_NOT_climits_a_11_lut_out = !X1_request_20;
K1_NOT_climits_a_11 = DFFEA(K1_NOT_climits_a_11_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_12 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_12
--operation mode is normal

K1_NOT_climits_a_12_lut_out = !X1_request_19;
K1_NOT_climits_a_12 = DFFEA(K1_NOT_climits_a_12_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_13 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_13
--operation mode is normal

K1_NOT_climits_a_13_lut_out = K1_NOT_climits_a_13;
K1_NOT_climits_a_13_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L931) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_13_lut_out);
K1_NOT_climits_a_13 = DFFEA(K1_NOT_climits_a_13_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_14 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_14
--operation mode is normal

K1_NOT_climits_a_14_lut_out = K1_NOT_climits_a_14;
K1_NOT_climits_a_14_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L731) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_14_lut_out);
K1_NOT_climits_a_14 = DFFEA(K1_NOT_climits_a_14_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_15 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_15
--operation mode is normal

K1_NOT_climits_a_15_lut_out = K1_NOT_climits_a_15;
K1_NOT_climits_a_15_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L531) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_15_lut_out);
K1_NOT_climits_a_15 = DFFEA(K1_NOT_climits_a_15_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_16 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_16
--operation mode is normal

K1_NOT_climits_a_16_lut_out = K1_NOT_climits_a_16;
K1_NOT_climits_a_16_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L331) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_16_lut_out);
K1_NOT_climits_a_16 = DFFEA(K1_NOT_climits_a_16_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_17 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_17
--operation mode is normal

K1_NOT_climits_a_17_lut_out = K1_NOT_climits_a_17;
K1_NOT_climits_a_17_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L131) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_17_lut_out);
K1_NOT_climits_a_17 = DFFEA(K1_NOT_climits_a_17_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_18 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_18
--operation mode is normal

K1_NOT_climits_a_18_lut_out = K1_NOT_climits_a_18;
K1_NOT_climits_a_18_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L921) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_18_lut_out);
K1_NOT_climits_a_18 = DFFEA(K1_NOT_climits_a_18_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_19 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_19
--operation mode is normal

K1_NOT_climits_a_19_lut_out = K1_NOT_climits_a_19;
K1_NOT_climits_a_19_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L721) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_19_lut_out);
K1_NOT_climits_a_19 = DFFEA(K1_NOT_climits_a_19_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_2
--operation mode is normal

K1_NOT_climits_a_2_lut_out = !X1_request_29;
K1_NOT_climits_a_2 = DFFEA(K1_NOT_climits_a_2_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_20 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_20
--operation mode is normal

K1_NOT_climits_a_20_lut_out = K1_NOT_climits_a_20;
K1_NOT_climits_a_20_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L521) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_20_lut_out);
K1_NOT_climits_a_20 = DFFEA(K1_NOT_climits_a_20_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_21 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_21
--operation mode is normal

K1_NOT_climits_a_21_lut_out = K1_NOT_climits_a_21;
K1_NOT_climits_a_21_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L321) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_21_lut_out);
K1_NOT_climits_a_21 = DFFEA(K1_NOT_climits_a_21_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_22 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_22
--operation mode is normal

K1_NOT_climits_a_22_lut_out = K1_NOT_climits_a_22;
K1_NOT_climits_a_22_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L121) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_22_lut_out);
K1_NOT_climits_a_22 = DFFEA(K1_NOT_climits_a_22_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_23 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_23
--operation mode is normal

K1_NOT_climits_a_23_lut_out = K1_NOT_climits_a_23;
K1_NOT_climits_a_23_sload_eqn = (K1_NOT_ix37_ix9_nx8 & X1L911) # (!K1_NOT_ix37_ix9_nx8 & K1_NOT_climits_a_23_lut_out);
K1_NOT_climits_a_23 = DFFEA(K1_NOT_climits_a_23_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_a_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_3
--operation mode is normal

K1_NOT_climits_a_3_lut_out = !X1_request_28;
K1_NOT_climits_a_3 = DFFEA(K1_NOT_climits_a_3_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_4
--operation mode is normal

K1_NOT_climits_a_4_lut_out = !X1_request_27;
K1_NOT_climits_a_4 = DFFEA(K1_NOT_climits_a_4_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_5
--operation mode is normal

K1_NOT_climits_a_5_lut_out = !X1_request_26;
K1_NOT_climits_a_5 = DFFEA(K1_NOT_climits_a_5_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_6
--operation mode is normal

K1_NOT_climits_a_6_lut_out = !X1_request_25;
K1_NOT_climits_a_6 = DFFEA(K1_NOT_climits_a_6_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_7
--operation mode is normal

K1_NOT_climits_a_7_lut_out = !X1_request_24;
K1_NOT_climits_a_7 = DFFEA(K1_NOT_climits_a_7_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_8
--operation mode is normal

K1_NOT_climits_a_8_lut_out = !X1_request_23;
K1_NOT_climits_a_8 = DFFEA(K1_NOT_climits_a_8_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_a_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_a_9
--operation mode is normal

K1_NOT_climits_a_9_lut_out = !X1_request_22;
K1_NOT_climits_a_9 = DFFEA(K1_NOT_climits_a_9_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx510, , );


--K1_NOT_climits_d_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_0
--operation mode is normal

K1_NOT_climits_d_0_lut_out = !X1_request_31;
K1_NOT_climits_d_0 = DFFEA(K1_NOT_climits_d_0_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_1
--operation mode is normal

K1_NOT_climits_d_1_lut_out = !X1_request_30;
K1_NOT_climits_d_1 = DFFEA(K1_NOT_climits_d_1_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_10
--operation mode is normal

K1_NOT_climits_d_10_lut_out = !X1_request_21;
K1_NOT_climits_d_10 = DFFEA(K1_NOT_climits_d_10_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_11
--operation mode is normal

K1_NOT_climits_d_11_lut_out = !X1_request_20;
K1_NOT_climits_d_11 = DFFEA(K1_NOT_climits_d_11_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_12 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_12
--operation mode is normal

K1_NOT_climits_d_12_lut_out = !X1_request_19;
K1_NOT_climits_d_12 = DFFEA(K1_NOT_climits_d_12_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_13 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_13
--operation mode is normal

K1_NOT_climits_d_13_lut_out = K1_NOT_climits_d_13;
K1_NOT_climits_d_13_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L931) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_13_lut_out);
K1_NOT_climits_d_13 = DFFEA(K1_NOT_climits_d_13_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_14 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_14
--operation mode is normal

K1_NOT_climits_d_14_lut_out = K1_NOT_climits_d_14;
K1_NOT_climits_d_14_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L731) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_14_lut_out);
K1_NOT_climits_d_14 = DFFEA(K1_NOT_climits_d_14_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_15 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_15
--operation mode is normal

K1_NOT_climits_d_15_lut_out = K1_NOT_climits_d_15;
K1_NOT_climits_d_15_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L531) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_15_lut_out);
K1_NOT_climits_d_15 = DFFEA(K1_NOT_climits_d_15_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_16 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_16
--operation mode is normal

K1_NOT_climits_d_16_lut_out = K1_NOT_climits_d_16;
K1_NOT_climits_d_16_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L331) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_16_lut_out);
K1_NOT_climits_d_16 = DFFEA(K1_NOT_climits_d_16_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_17 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_17
--operation mode is normal

K1_NOT_climits_d_17_lut_out = K1_NOT_climits_d_17;
K1_NOT_climits_d_17_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L131) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_17_lut_out);
K1_NOT_climits_d_17 = DFFEA(K1_NOT_climits_d_17_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_18 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_18
--operation mode is normal

K1_NOT_climits_d_18_lut_out = K1_NOT_climits_d_18;
K1_NOT_climits_d_18_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L921) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_18_lut_out);
K1_NOT_climits_d_18 = DFFEA(K1_NOT_climits_d_18_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_19 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_19
--operation mode is normal

K1_NOT_climits_d_19_lut_out = K1_NOT_climits_d_19;
K1_NOT_climits_d_19_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L721) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_19_lut_out);
K1_NOT_climits_d_19 = DFFEA(K1_NOT_climits_d_19_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_2
--operation mode is normal

K1_NOT_climits_d_2_lut_out = !X1_request_29;
K1_NOT_climits_d_2 = DFFEA(K1_NOT_climits_d_2_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_20 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_20
--operation mode is normal

K1_NOT_climits_d_20_lut_out = K1_NOT_climits_d_20;
K1_NOT_climits_d_20_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L521) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_20_lut_out);
K1_NOT_climits_d_20 = DFFEA(K1_NOT_climits_d_20_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_21 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_21
--operation mode is normal

K1_NOT_climits_d_21_lut_out = K1_NOT_climits_d_21;
K1_NOT_climits_d_21_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L321) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_21_lut_out);
K1_NOT_climits_d_21 = DFFEA(K1_NOT_climits_d_21_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_22 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_22
--operation mode is normal

K1_NOT_climits_d_22_lut_out = K1_NOT_climits_d_22;
K1_NOT_climits_d_22_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L121) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_22_lut_out);
K1_NOT_climits_d_22 = DFFEA(K1_NOT_climits_d_22_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_23 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_23
--operation mode is normal

K1_NOT_climits_d_23_lut_out = K1_NOT_climits_d_23;
K1_NOT_climits_d_23_sload_eqn = (K1_NOT_ix37_ix7_nx8 & X1L911) # (!K1_NOT_ix37_ix7_nx8 & K1_NOT_climits_d_23_lut_out);
K1_NOT_climits_d_23 = DFFEA(K1_NOT_climits_d_23_sload_eqn, U1__clk1, V1_chipRST_n, , K1_nx10, , );


--K1_NOT_climits_d_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_3
--operation mode is normal

K1_NOT_climits_d_3_lut_out = !X1_request_28;
K1_NOT_climits_d_3 = DFFEA(K1_NOT_climits_d_3_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_4
--operation mode is normal

K1_NOT_climits_d_4_lut_out = !X1_request_27;
K1_NOT_climits_d_4 = DFFEA(K1_NOT_climits_d_4_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_5
--operation mode is normal

K1_NOT_climits_d_5_lut_out = !X1_request_26;
K1_NOT_climits_d_5 = DFFEA(K1_NOT_climits_d_5_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_6
--operation mode is normal

K1_NOT_climits_d_6_lut_out = !X1_request_25;
K1_NOT_climits_d_6 = DFFEA(K1_NOT_climits_d_6_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_7
--operation mode is normal

K1_NOT_climits_d_7_lut_out = !X1_request_24;
K1_NOT_climits_d_7 = DFFEA(K1_NOT_climits_d_7_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_8
--operation mode is normal

K1_NOT_climits_d_8_lut_out = !X1_request_23;
K1_NOT_climits_d_8 = DFFEA(K1_NOT_climits_d_8_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_NOT_climits_d_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|NOT_climits_d_9
--operation mode is normal

K1_NOT_climits_d_9_lut_out = !X1_request_22;
K1_NOT_climits_d_9 = DFFEA(K1_NOT_climits_d_9_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx462, , );


--K1_cmd_adc_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cmd_adc_1
--operation mode is normal

K1_cmd_adc_1_lut_out = VCC;
K1_cmd_adc_1 = DFFEA(K1_cmd_adc_1_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_cmd_adc_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|cmd_adc_2
--operation mode is normal

K1_cmd_adc_2_lut_out = K1_nx692;
K1_cmd_adc_2 = DFFEA(K1_cmd_adc_2_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_nx538 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx538
--operation mode is normal

K1_nx538 = G1_ce_psply_adc & !V1_rd_wr_oase & X1_request_46 & !X1_request_47;

--K1_send_cfr is ADC_DAC_0:adcdac|seradc_auto:power_adc|send_cfr
--operation mode is normal

K1_send_cfr = DFFEA(K1_nx538, U1__clk1, V1_chipRST_n, , , , );


--K1_nx692 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx692
--operation mode is normal

K1_nx692_lut_out = K1_sm_7 & !T1_RDY & (K1_start_cyc # K1_nx899) # !K1_sm_7 & (K1_start_cyc # K1_nx899);
K1_nx692 = DFFEA(K1_nx692_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_sm_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|sm_1
--operation mode is normal

K1_sm_1_lut_out = K1_send_cfr & !K1_nx692;
K1_sm_1 = DFFEA(K1_sm_1_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_sm_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|sm_2
--operation mode is normal

K1_sm_2_lut_out = K1_nx988 # !K1_send_cfr & K1_start_cyc & !K1_nx692;
K1_sm_2 = DFFEA(K1_sm_2_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_sm_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|sm_3
--operation mode is normal

K1_sm_3_lut_out = K1_sm_6 # K1_modgen_select_136_nx2 # K1_sm_3 & K1_nx900;
K1_sm_3 = DFFEA(K1_sm_3_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_sm_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|sm_4
--operation mode is normal

K1_sm_4_lut_out = K1_sm_3 & !K1_ce_adc & T1_RDY;
K1_sm_4 = DFFEA(K1_sm_4_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_sm_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|sm_5
--operation mode is normal

K1_sm_5_lut_out = K1_sm_2;
K1_sm_5 = DFFEA(K1_sm_5_lut_out, U1__clk1, V1_chipRST_n, , K1_b_3, , );


--K1_sm_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|sm_6
--operation mode is normal

K1_sm_6_lut_out = K1_sm_5 & K1_b_3 & !K1_ix38_ix21_nx8;
K1_sm_6 = DFFEA(K1_sm_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_sm_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|sm_7
--operation mode is normal

K1_sm_7_lut_out = K1_sm_1 # K1_modgen_select_123_nx2 # K1_sm_7 & !T1_RDY;
K1_sm_7 = DFFEA(K1_sm_7_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_start_cyc is ADC_DAC_0:adcdac|seradc_auto:power_adc|start_cyc
--operation mode is normal

K1_start_cyc_lut_out = K1_cfr_12 # G1_ce_psply_adc & !V1_rd_wr_oase & !X1_request_46;
K1_start_cyc = DFFEA(K1_start_cyc_lut_out, U1__clk1, V1_chipRST_n, , , , );


--K1_timer_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_0
--operation mode is normal

K1_timer_0_lut_out = K1_nx898 # K1_nx1229 & K1_nx897 # !K1_nx692;
K1_timer_0 = DFFEA(K1_timer_0_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx1369, , );


--K1_timer_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_1
--operation mode is normal

K1_timer_1_lut_out = K1_nx898 # K1_nx1228 & K1_nx897 # !K1_nx692;
K1_timer_1 = DFFEA(K1_timer_1_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx1369, , );


--K1_timer_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_2
--operation mode is normal

K1_timer_2_lut_out = K1_nx898 # K1_nx1227 & K1_nx897 # !K1_nx692;
K1_timer_2 = DFFEA(K1_timer_2_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx1369, , );


--K1_timer_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_3
--operation mode is normal

K1_timer_3_lut_out = K1_nx898 # K1_nx1226 & K1_nx897 # !K1_nx692;
K1_timer_3 = DFFEA(K1_timer_3_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx1369, , );


--K1_timer_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_4
--operation mode is normal

K1_timer_4_lut_out = K1_nx898 # K1_nx1225 & K1_nx897 # !K1_nx692;
K1_timer_4 = DFFEA(K1_timer_4_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx1369, , );


--K1_timer_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_5
--operation mode is normal

K1_timer_5_lut_out = K1_nx898 # K1_nx1224 & K1_nx897 # !K1_nx692;
K1_timer_5 = DFFEA(K1_timer_5_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx1369, , );


--K1_timer_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_6
--operation mode is normal

K1_timer_6_lut_out = K1_nx898 # K1_nx1223 & K1_nx897 # !K1_nx692;
K1_timer_6 = DFFEA(K1_timer_6_lut_out, U1__clk1, V1_chipRST_n, , K1_NOT_nx1369, , );


--K1_nx1229 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx1229
--operation mode is normal

K1_nx1229 = !K1_timer_0;


--K1_timer_dec_115_nx22 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_dec_115_nx22
--operation mode is arithmetic

K1_timer_dec_115_nx22 = CARRY(K1_timer_0);


--K1_nx1228 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx1228
--operation mode is arithmetic

K1_nx1228_carry_eqn = K1_timer_dec_115_nx22;
K1_nx1228 = K1_timer_1 $ !K1_nx1228_carry_eqn;

--K1_timer_dec_115_nx26 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_dec_115_nx26
--operation mode is arithmetic

K1_timer_dec_115_nx26 = CARRY(!K1_timer_1 & !K1_timer_dec_115_nx22);


--K1_nx1227 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx1227
--operation mode is arithmetic

K1_nx1227_carry_eqn = K1_timer_dec_115_nx26;
K1_nx1227 = K1_timer_2 $ K1_nx1227_carry_eqn;

--K1_timer_dec_115_nx30 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_dec_115_nx30
--operation mode is arithmetic

K1_timer_dec_115_nx30 = CARRY(K1_timer_2 # !K1_timer_dec_115_nx26);


--K1_nx1226 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx1226
--operation mode is arithmetic

K1_nx1226_carry_eqn = K1_timer_dec_115_nx30;
K1_nx1226 = K1_timer_3 $ !K1_nx1226_carry_eqn;

--K1_timer_dec_115_nx34 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_dec_115_nx34
--operation mode is arithmetic

K1_timer_dec_115_nx34 = CARRY(!K1_timer_3 & !K1_timer_dec_115_nx30);


--K1_nx1225 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx1225
--operation mode is arithmetic

K1_nx1225_carry_eqn = K1_timer_dec_115_nx34;
K1_nx1225 = K1_timer_4 $ K1_nx1225_carry_eqn;

--K1_timer_dec_115_nx38 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_dec_115_nx38
--operation mode is arithmetic

K1_timer_dec_115_nx38 = CARRY(K1_timer_4 # !K1_timer_dec_115_nx34);


--K1_nx1224 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx1224
--operation mode is arithmetic

K1_nx1224_carry_eqn = K1_timer_dec_115_nx38;
K1_nx1224 = K1_timer_5 $ !K1_nx1224_carry_eqn;

--K1_timer_dec_115_nx42 is ADC_DAC_0:adcdac|seradc_auto:power_adc|timer_dec_115_nx42
--operation mode is arithmetic

K1_timer_dec_115_nx42 = CARRY(!K1_timer_5 & !K1_timer_dec_115_nx38);


--K1_nx1223 is ADC_DAC_0:adcdac|seradc_auto:power_adc|nx1223
--operation mode is normal

K1_nx1223_carry_eqn = K1_timer_dec_115_nx42;
K1_nx1223 = K1_timer_6 $ K1_nx1223_carry_eqn;


--T1_counter_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|counter_2
--operation mode is arithmetic

T1_counter_2_carry_eqn = T1_counter_nx16;
T1_counter_2_lut_out = T1_counter_2 $ T1_counter_2_carry_eqn;
T1_counter_2_reg_input = T1_sm_2 & T1_counter_2_lut_out;
T1_counter_2 = DFFEA(T1_counter_2_reg_input, U1__clk1, V1_chipRST_n, , T1_NOT_nx499, , );

--T1_counter_nx21 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|counter_nx21
--operation mode is arithmetic

T1_counter_nx21 = CARRY(T1_counter_2 # !T1_counter_nx16);


--T1_counter_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|counter_1
--operation mode is arithmetic

T1_counter_1_carry_eqn = T1_counter_nx10;
T1_counter_1_lut_out = T1_counter_1 $ !T1_counter_1_carry_eqn;
T1_counter_1_reg_input = T1_sm_2 & T1_counter_1_lut_out;
T1_counter_1 = DFFEA(T1_counter_1_reg_input, U1__clk1, V1_chipRST_n, , T1_NOT_nx499, , );

--T1_counter_nx16 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|counter_nx16
--operation mode is arithmetic

T1_counter_nx16 = CARRY(!T1_counter_1 & !T1_counter_nx10);


--T1_counter_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|counter_0
--operation mode is arithmetic

T1_counter_0_lut_out = !T1_counter_0;
T1_counter_0_reg_input = T1_sm_2 & T1_counter_0_lut_out;
T1_counter_0 = DFFEA(T1_counter_0_reg_input, U1__clk1, V1_chipRST_n, , T1_NOT_nx499, , );

--T1_counter_nx10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|counter_nx10
--operation mode is arithmetic

T1_counter_nx10 = CARRY(T1_counter_0);


--T1_counter_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|counter_3
--operation mode is normal

T1_counter_3_carry_eqn = T1_counter_nx21;
T1_counter_3_lut_out = T1_counter_3 $ !T1_counter_3_carry_eqn;
T1_counter_3_reg_input = T1_sm_2 & T1_counter_3_lut_out;
T1_counter_3 = DFFEA(T1_counter_3_reg_input, U1__clk1, V1_chipRST_n, , T1_NOT_nx499, , );


--T1_NOT_nx295 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|NOT_nx295
--operation mode is normal

T1_NOT_nx295 = T1_ADC_SCLK & (T1_counter_3 # T1_counter_2 # !T1_fifo_rd);


--T1_NOT_nx214 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|NOT_nx214
--operation mode is normal

T1_NOT_nx214 = K1_ce_adc & (T1_ADC_SCLK # !T1_nx60) # !K1_ce_adc & T1_nx60 & T1_ADC_SCLK;


--T1_NOT_nx499 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|NOT_nx499
--operation mode is normal

T1_NOT_nx499 = !T1_sm_4 & !T1_ADC_SCLK;


--T1_nx94 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|nx94
--operation mode is normal

T1_nx94 = K1_cmd_adc_1 & !K1_cmd_adc_2 & !T1_nx60;


--T1_nx95 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|nx95
--operation mode is normal

T1_nx95 = T1_counter_3 # T1_counter_2;


--T1_nx96 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|nx96
--operation mode is normal

T1_nx96 = T1_counter_1 # T1_counter_0;


--T1_RDATA_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_0
--operation mode is normal

T1_RDATA_0_lut_out = MSply_ADC_SDO;
T1_RDATA_0 = DFFEA(T1_RDATA_0_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_1
--operation mode is normal

T1_RDATA_1_lut_out = T1_RDATA_0;
T1_RDATA_1 = DFFEA(T1_RDATA_1_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_10
--operation mode is normal

T1_RDATA_10_lut_out = T1_RDATA_9;
T1_RDATA_10 = DFFEA(T1_RDATA_10_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_11
--operation mode is normal

T1_RDATA_11_lut_out = T1_RDATA_10;
T1_RDATA_11 = DFFEA(T1_RDATA_11_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_2
--operation mode is normal

T1_RDATA_2_lut_out = T1_RDATA_1;
T1_RDATA_2 = DFFEA(T1_RDATA_2_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_3
--operation mode is normal

T1_RDATA_3_lut_out = T1_RDATA_2;
T1_RDATA_3 = DFFEA(T1_RDATA_3_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_4
--operation mode is normal

T1_RDATA_4_lut_out = T1_RDATA_3;
T1_RDATA_4 = DFFEA(T1_RDATA_4_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_5
--operation mode is normal

T1_RDATA_5_lut_out = T1_RDATA_4;
T1_RDATA_5 = DFFEA(T1_RDATA_5_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_6
--operation mode is normal

T1_RDATA_6_lut_out = T1_RDATA_5;
T1_RDATA_6 = DFFEA(T1_RDATA_6_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_7
--operation mode is normal

T1_RDATA_7_lut_out = T1_RDATA_6;
T1_RDATA_7 = DFFEA(T1_RDATA_7_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_8
--operation mode is normal

T1_RDATA_8_lut_out = T1_RDATA_7;
T1_RDATA_8 = DFFEA(T1_RDATA_8_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_RDATA_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDATA_9
--operation mode is normal

T1_RDATA_9_lut_out = T1_RDATA_8;
T1_RDATA_9 = DFFEA(T1_RDATA_9_lut_out, U1__clk1, VCC, , T1_NOT_nx295, , );


--T1_datasr_0 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_0
--operation mode is normal

T1_datasr_0_lut_out = K1_cfr_0 & T1_nx94;
T1_datasr_0 = DFFEA(T1_datasr_0_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_1
--operation mode is normal

T1_datasr_1_lut_out = K1_cfr_1 & (T1_nx94 # T1_datasr_0 & T1_ADC_SCLK) # !K1_cfr_1 & T1_datasr_0 & T1_ADC_SCLK;
T1_datasr_1 = DFFEA(T1_datasr_1_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_10 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_10
--operation mode is normal

T1_datasr_10_lut_out = K1_cfr_10 & (T1_nx94 # T1_datasr_9 & T1_ADC_SCLK) # !K1_cfr_10 & T1_datasr_9 & T1_ADC_SCLK;
T1_datasr_10 = DFFEA(T1_datasr_10_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_11 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_11
--operation mode is normal

T1_datasr_11_lut_out = K1_cfr_11 & (T1_nx94 # T1_datasr_10 & T1_ADC_SCLK) # !K1_cfr_11 & T1_datasr_10 & T1_ADC_SCLK;
T1_datasr_11 = DFFEA(T1_datasr_11_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_12 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_12
--operation mode is normal

T1_datasr_12_lut_out = T1_datasr_11 & T1_ADC_SCLK;
T1_datasr_12 = DFFEA(T1_datasr_12_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_13 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_13
--operation mode is normal

T1_datasr_13_lut_out = K1_cmd_adc_1 & (T1_datasr_12 & T1_ADC_SCLK # !T1_nx60) # !K1_cmd_adc_1 & T1_datasr_12 & T1_ADC_SCLK;
T1_datasr_13 = DFFEA(T1_datasr_13_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_14 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_14
--operation mode is normal

T1_datasr_14_lut_out = K1_cmd_adc_2 & (T1_datasr_13 & T1_ADC_SCLK # !T1_nx60) # !K1_cmd_adc_2 & T1_datasr_13 & T1_ADC_SCLK;
T1_datasr_14 = DFFEA(T1_datasr_14_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_ADC_SDI is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|ADC_SDI
--operation mode is normal

T1_ADC_SDI_lut_out = K1_cmd_adc_1 & (T1_datasr_14 & T1_ADC_SCLK # !T1_nx60) # !K1_cmd_adc_1 & T1_datasr_14 & T1_ADC_SCLK;
T1_ADC_SDI = DFFEA(T1_ADC_SDI_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_2
--operation mode is normal

T1_datasr_2_lut_out = K1_cfr_2 & (T1_nx94 # T1_datasr_1 & T1_ADC_SCLK) # !K1_cfr_2 & T1_datasr_1 & T1_ADC_SCLK;
T1_datasr_2 = DFFEA(T1_datasr_2_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_3 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_3
--operation mode is normal

T1_datasr_3_lut_out = K1_cfr_3 & (T1_nx94 # T1_datasr_2 & T1_ADC_SCLK) # !K1_cfr_3 & T1_datasr_2 & T1_ADC_SCLK;
T1_datasr_3 = DFFEA(T1_datasr_3_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_4
--operation mode is normal

T1_datasr_4_lut_out = K1_cfr_4 & (T1_nx94 # T1_datasr_3 & T1_ADC_SCLK) # !K1_cfr_4 & T1_datasr_3 & T1_ADC_SCLK;
T1_datasr_4 = DFFEA(T1_datasr_4_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_5 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_5
--operation mode is normal

T1_datasr_5_lut_out = K1_cfr_5 & (T1_nx94 # T1_datasr_4 & T1_ADC_SCLK) # !K1_cfr_5 & T1_datasr_4 & T1_ADC_SCLK;
T1_datasr_5 = DFFEA(T1_datasr_5_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_6 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_6
--operation mode is normal

T1_datasr_6_lut_out = K1_cfr_6 & (T1_nx94 # T1_datasr_5 & T1_ADC_SCLK) # !K1_cfr_6 & T1_datasr_5 & T1_ADC_SCLK;
T1_datasr_6 = DFFEA(T1_datasr_6_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_7 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_7
--operation mode is normal

T1_datasr_7_lut_out = K1_cfr_7 & (T1_nx94 # T1_datasr_6 & T1_ADC_SCLK) # !K1_cfr_7 & T1_datasr_6 & T1_ADC_SCLK;
T1_datasr_7 = DFFEA(T1_datasr_7_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_8 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_8
--operation mode is normal

T1_datasr_8_lut_out = K1_cfr_8 & (T1_nx94 # T1_datasr_7 & T1_ADC_SCLK) # !K1_cfr_8 & T1_datasr_7 & T1_ADC_SCLK;
T1_datasr_8 = DFFEA(T1_datasr_8_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_datasr_9 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|datasr_9
--operation mode is normal

T1_datasr_9_lut_out = K1_cfr_9 & (T1_nx94 # T1_datasr_8 & T1_ADC_SCLK) # !K1_cfr_9 & T1_datasr_8 & T1_ADC_SCLK;
T1_datasr_9 = DFFEA(T1_datasr_9_lut_out, U1__clk1, VCC, , T1_NOT_nx214, , );


--T1_fifo_rd is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|fifo_rd
--operation mode is normal

T1_fifo_rd_lut_out = K1_cmd_adc_1 & K1_cmd_adc_2;
T1_fifo_rd = DFFEA(T1_fifo_rd_lut_out, U1__clk1, VCC, , T1_modgen_select_108_nx4, , );


--T1_RDY is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|RDY
--operation mode is normal

T1_RDY_lut_out = !K1_ce_adc & !T1_nx60;
T1_RDY = DFFEA(T1_RDY_lut_out, U1__clk1, V1_chipRST_n, , , , );


--T1_nx60 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|nx60
--operation mode is normal

T1_nx60_lut_out = !T1_sm_4 & (K1_ce_adc # T1_nx60);
T1_nx60 = DFFEA(T1_nx60_lut_out, U1__clk1, V1_chipRST_n, , , , );


--T1_modgen_select_108_nx4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|modgen_select_108_nx4
--operation mode is normal

T1_modgen_select_108_nx4 = K1_ce_adc & !T1_nx60;

--T1_sm_1 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|sm_1
--operation mode is normal

T1_sm_1 = DFFEA(T1_modgen_select_108_nx4, U1__clk1, V1_chipRST_n, , , , );


--T1_sm_2 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|sm_2
--operation mode is normal

T1_sm_2_lut_out = T1_sm_1 # T1_ADC_SCLK & (T1_nx95 # T1_nx96);
T1_sm_2 = DFFEA(T1_sm_2_lut_out, U1__clk1, V1_chipRST_n, , , , );


--T1_ADC_SCLK is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|ADC_SCLK
--operation mode is normal

T1_ADC_SCLK_lut_out = T1_sm_2;
T1_ADC_SCLK = DFFEA(T1_ADC_SCLK_lut_out, U1__clk1, V1_chipRST_n, , , , );


--T1_sm_4 is ADC_DAC_0:adcdac|seradc_auto:power_adc|TLV2548:adc|sm_4
--operation mode is normal

T1_sm_4_lut_out = !T1_counter_1 & !T1_counter_0 & T1_ADC_SCLK & !T1_nx95;
T1_sm_4 = DFFEA(T1_sm_4_lut_out, U1__clk1, V1_chipRST_n, , , , );


--J1_addr_sm_3 is ADC_DAC_0:adcdac|pasadac:pdac|addr_sm_3
--operation mode is arithmetic

J1_addr_sm_3_carry_eqn = J1_addr_sm_nx21;
J1_addr_sm_3_lut_out = J1_addr_sm_3 $ J1_addr_sm_3_carry_eqn;
J1_addr_sm_3_reg_input = !J1_nx309 & J1_addr_sm_3_lut_out;
J1_addr_sm_3 = DFFEA(J1_addr_sm_3_reg_input, U1__clk0, VCC, , , , );

--J1_addr_sm_nx26 is ADC_DAC_0:adcdac|pasadac:pdac|addr_sm_nx26
--operation mode is arithmetic

J1_addr_sm_nx26 = CARRY(!J1_addr_sm_nx21 # !J1_addr_sm_3);


--J1_addr_sm_2 is ADC_DAC_0:adcdac|pasadac:pdac|addr_sm_2
--operation mode is arithmetic

J1_addr_sm_2_carry_eqn = J1_addr_sm_nx15;
J1_addr_sm_2_lut_out = J1_addr_sm_2 $ !J1_addr_sm_2_carry_eqn;
J1_addr_sm_2_reg_input = !J1_nx309 & J1_addr_sm_2_lut_out;
J1_addr_sm_2 = DFFEA(J1_addr_sm_2_reg_input, U1__clk0, VCC, , , , );

--J1_addr_sm_nx21 is ADC_DAC_0:adcdac|pasadac:pdac|addr_sm_nx21
--operation mode is arithmetic

J1_addr_sm_nx21 = CARRY(J1_addr_sm_2 & !J1_addr_sm_nx15);


--J1_addr_sm_1 is ADC_DAC_0:adcdac|pasadac:pdac|addr_sm_1
--operation mode is arithmetic

J1_addr_sm_1_carry_eqn = J1_addr_sm_nx9;
J1_addr_sm_1_lut_out = J1_addr_sm_1 $ J1_addr_sm_1_carry_eqn;
J1_addr_sm_1_reg_input = !J1_nx309 & J1_addr_sm_1_lut_out;
J1_addr_sm_1 = DFFEA(J1_addr_sm_1_reg_input, U1__clk0, VCC, , , , );

--J1_addr_sm_nx15 is ADC_DAC_0:adcdac|pasadac:pdac|addr_sm_nx15
--operation mode is arithmetic

J1_addr_sm_nx15 = CARRY(!J1_addr_sm_nx9 # !J1_addr_sm_1);


--J1_addr_sm_0 is ADC_DAC_0:adcdac|pasadac:pdac|addr_sm_0
--operation mode is arithmetic

J1_addr_sm_0_lut_out = J1_addr_sm_0 $ J1_nx315;
J1_addr_sm_0_reg_input = !J1_nx309 & J1_addr_sm_0_lut_out;
J1_addr_sm_0 = DFFEA(J1_addr_sm_0_reg_input, U1__clk0, VCC, , , , );

--J1_addr_sm_nx9 is ADC_DAC_0:adcdac|pasadac:pdac|addr_sm_nx9
--operation mode is arithmetic

J1_addr_sm_nx9 = CARRY(J1_addr_sm_0 & J1_nx315);


--J1_addr_sm_4 is ADC_DAC_0:adcdac|pasadac:pdac|addr_sm_4
--operation mode is normal

J1_addr_sm_4_carry_eqn = J1_addr_sm_nx26;
J1_addr_sm_4_lut_out = J1_addr_sm_4 $ !J1_addr_sm_4_carry_eqn;
J1_addr_sm_4_reg_input = !J1_nx309 & J1_addr_sm_4_lut_out;
J1_addr_sm_4 = DFFEA(J1_addr_sm_4_reg_input, U1__clk0, VCC, , , , );


--J1_wdata_cor_13 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_13
--operation mode is normal

J1_wdata_cor_13 = X1_request_15 & !X1_request_18 # !X1_request_15 & !X1_request_31;


--J1_wdata_cor_12 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_12
--operation mode is normal

J1_wdata_cor_12 = X1_request_15 & !X1_request_19 # !X1_request_15 & !X1_request_30;


--J1_wdata_cor_11 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_11
--operation mode is normal

J1_wdata_cor_11 = X1_request_15 & !X1_request_20 # !X1_request_15 & !X1_request_29;


--J1_wdata_cor_10 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_10
--operation mode is normal

J1_wdata_cor_10 = X1_request_15 & !X1_request_21 # !X1_request_15 & !X1_request_28;


--J1_wdata_cor_9 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_9
--operation mode is normal

J1_wdata_cor_9 = X1_request_15 & !X1_request_22 # !X1_request_15 & !X1_request_27;


--J1_wdata_cor_8 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_8
--operation mode is normal

J1_wdata_cor_8 = X1_request_15 & !X1_request_23 # !X1_request_15 & !X1_request_26;


--J1_wdata_cor_7 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_7
--operation mode is normal

J1_wdata_cor_7 = X1_request_15 & !X1_request_24 # !X1_request_15 & !X1_request_25;


--J1_wdata_cor_6 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_6
--operation mode is normal

J1_wdata_cor_6 = X1_request_15 & !X1_request_25 # !X1_request_15 & !X1_request_24;


--J1_wdata_cor_5 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_5
--operation mode is normal

J1_wdata_cor_5 = X1_request_15 & !X1_request_26 # !X1_request_15 & !X1_request_23;


--J1_wdata_cor_4 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_4
--operation mode is normal

J1_wdata_cor_4 = X1_request_15 & !X1_request_27 # !X1_request_15 & !X1_request_22;


--J1_wdata_cor_3 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_3
--operation mode is normal

J1_wdata_cor_3 = X1_request_15 & !X1_request_28 # !X1_request_15 & !X1_request_21;


--J1_wdata_cor_2 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_2
--operation mode is normal

J1_wdata_cor_2 = X1_request_15 & !X1_request_29 # !X1_request_15 & !X1_request_20;


--J1_wdata_cor_1 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_1
--operation mode is normal

J1_wdata_cor_1 = X1_request_15 & !X1_request_30 # !X1_request_15 & !X1_request_19;


--J1_wdata_cor_0 is ADC_DAC_0:adcdac|pasadac:pdac|wdata_cor_0
--operation mode is normal

J1_wdata_cor_0 = X1_request_15 & !X1_request_31 # !X1_request_15 & !X1_request_18;


--J1_wren_io is ADC_DAC_0:adcdac|pasadac:pdac|wren_io
--operation mode is normal

J1_wren_io = G1_ce_pasa_dac & !V1_rd_wr_oase & X1_request_43;


--J1_wren_cfr is ADC_DAC_0:adcdac|pasadac:pdac|wren_cfr
--operation mode is normal

J1_wren_cfr = G1_ce_pasa_dac & !V1_rd_wr_oase & !X1_request_43;


--J1_nx309 is ADC_DAC_0:adcdac|pasadac:pdac|nx309
--operation mode is normal

J1_nx309 = J1_sm_1 $ !J1_sm_0;


--J1_nx315 is ADC_DAC_0:adcdac|pasadac:pdac|nx315
--operation mode is normal

J1_nx315 = !J1_nx123 & !J1_nx130 & J1_nx139 & J1_nx140;


--J1_nx122 is ADC_DAC_0:adcdac|pasadac:pdac|nx122
--operation mode is normal

J1_nx122 = J1_timer_1 & (J1_timer_0 $ S1_q_b[15] # !S1_q_b[16]) # !J1_timer_1 & (S1_q_b[16] # J1_timer_0 $ S1_q_b[15]);


--J1_nx123 is ADC_DAC_0:adcdac|pasadac:pdac|nx123
--operation mode is normal

J1_nx123 = J1_timer_7 & (J1_timer_6 $ S1_q_b[21] # !S1_q_b[22]) # !J1_timer_7 & (S1_q_b[22] # J1_timer_6 $ S1_q_b[21]);


--J1_nx124 is ADC_DAC_0:adcdac|pasadac:pdac|nx124
--operation mode is normal

J1_nx124 = !S1_q_b[15] & J1_nx126 & J1_nx128 & J1_nx134;


--J1_nx125 is ADC_DAC_0:adcdac|pasadac:pdac|nx125
--operation mode is normal

J1_nx125 = J1_addr_sm_4 # J1_addr_sm_1 # J1_addr_sm_0 # J1_nx138;


--J1_nx126 is ADC_DAC_0:adcdac|pasadac:pdac|nx126
--operation mode is normal

J1_nx126 = !S1_q_b[19] & !S1_q_b[18] & !S1_q_b[17] & !S1_q_b[16];


--J1_nx127 is ADC_DAC_0:adcdac|pasadac:pdac|nx127
--operation mode is normal

J1_nx127 = !J1_sm_1 & (J1_sm_0 & J1_nx123 # !J1_sm_0 & J1_start_s);


--J1_nx128 is ADC_DAC_0:adcdac|pasadac:pdac|nx128
--operation mode is normal

J1_nx128 = !J1_sm_1 & J1_sm_0;


--J1_nx129 is ADC_DAC_0:adcdac|pasadac:pdac|nx129
--operation mode is normal

J1_nx129 = J1_timer_8 $ !S1_q_b[23];


--J1_nx130 is ADC_DAC_0:adcdac|pasadac:pdac|nx130
--operation mode is normal

J1_nx130 = J1_nx122 # J1_nx141 # J1_timer_3 $ S1_q_b[18];


--J1_nx238 is ADC_DAC_0:adcdac|pasadac:pdac|nx238
--operation mode is normal

J1_nx238 = !J1_sm_1 & !J1_sm_0;


--J1_nx131 is ADC_DAC_0:adcdac|pasadac:pdac|nx131
--operation mode is normal

J1_nx131 = X1_request_43 & (S1_q_a[14] & !S1_q_a[2] # !S1_q_a[14] & !S1_q_a[11]);


--J1_nx132 is ADC_DAC_0:adcdac|pasadac:pdac|nx132
--operation mode is normal

J1_nx132 = X1_request_43 & (S1_q_a[14] & !S1_q_a[1] # !S1_q_a[14] & !S1_q_a[12]);


--J1_nx133 is ADC_DAC_0:adcdac|pasadac:pdac|nx133
--operation mode is normal

J1_nx133 = X1_request_43 & (S1_q_a[14] & !S1_q_a[0] # !S1_q_a[14] & !S1_q_a[13]);


--J1_nx134 is ADC_DAC_0:adcdac|pasadac:pdac|nx134
--operation mode is normal

J1_nx134 = !S1_q_b[23] & !S1_q_b[22] & !S1_q_b[21] & !S1_q_b[20];


--J1_nx135 is ADC_DAC_0:adcdac|pasadac:pdac|nx135
--operation mode is normal

J1_nx135 = J1_addr_sm_3 # J1_addr_sm_2 # J1_addr_sm_1 # J1_addr_sm_0;


--J1_nx136 is ADC_DAC_0:adcdac|pasadac:pdac|nx136
--operation mode is normal

J1_nx136 = J1_sm_1 & (J1_addr_sm_4 # J1_nx135);


--J1_nx137 is ADC_DAC_0:adcdac|pasadac:pdac|nx137
--operation mode is normal

J1_nx137 = J1_nx128 & (J1_nx130 # !J1_nx139 # !J1_nx129);


--J1_nx138 is ADC_DAC_0:adcdac|pasadac:pdac|nx138
--operation mode is normal

J1_nx138 = J1_addr_sm_3 # J1_addr_sm_2;


--J1_nx139 is ADC_DAC_0:adcdac|pasadac:pdac|nx139
--operation mode is normal

J1_nx139 = J1_timer_5 & S1_q_b[20] & (J1_timer_4 $ !S1_q_b[19]) # !J1_timer_5 & !S1_q_b[20] & (J1_timer_4 $ !S1_q_b[19]);


--J1_nx140 is ADC_DAC_0:adcdac|pasadac:pdac|nx140
--operation mode is normal

J1_nx140 = !J1_sm_1 & J1_sm_0 & (J1_timer_8 $ !S1_q_b[23]);


--J1_nx141 is ADC_DAC_0:adcdac|pasadac:pdac|nx141
--operation mode is normal

J1_nx141 = J1_timer_2 $ S1_q_b[17];


--J1_nx142 is ADC_DAC_0:adcdac|pasadac:pdac|nx142
--operation mode is normal

J1_nx142 = J1_sm_1 & J1_sm_0;


--J1_RDATA_28 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_28
--operation mode is normal

J1_RDATA_28 = X1_request_43 & S1_q_a[23];


--J1_RDATA_27 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_27
--operation mode is normal

J1_RDATA_27 = X1_request_43 & S1_q_a[22];


--J1_RDATA_26 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_26
--operation mode is normal

J1_RDATA_26 = X1_request_43 & S1_q_a[21];


--J1_RDATA_25 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_25
--operation mode is normal

J1_RDATA_25 = X1_request_43 & S1_q_a[20];


--J1_RDATA_24 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_24
--operation mode is normal

J1_RDATA_24 = X1_request_43 & S1_q_a[19];


--J1_RDATA_23 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_23
--operation mode is normal

J1_RDATA_23 = X1_request_43 & S1_q_a[18];


--J1_RDATA_22 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_22
--operation mode is normal

J1_RDATA_22 = X1_request_43 & S1_q_a[17];


--J1_RDATA_21 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_21
--operation mode is normal

J1_RDATA_21 = X1_request_43 & S1_q_a[16];


--J1_RDATA_20 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_20
--operation mode is normal

J1_RDATA_20 = X1_request_43 & S1_q_a[15];


--J1_RDATA_16 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_16
--operation mode is normal

J1_RDATA_16 = X1_request_43 & S1_q_a[14];


--J1_RDATA_13 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_13
--operation mode is normal

J1_RDATA_13 = X1_request_43 & (S1_q_a[14] & !S1_q_a[13] # !S1_q_a[14] & !S1_q_a[0]);


--J1_RDATA_12 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_12
--operation mode is normal

J1_RDATA_12 = X1_request_43 & (S1_q_a[14] & !S1_q_a[12] # !S1_q_a[14] & !S1_q_a[1]);


--J1_RDATA_11 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_11
--operation mode is normal

J1_RDATA_11 = X1_request_43 & (S1_q_a[14] & !S1_q_a[11] # !S1_q_a[14] & !S1_q_a[2]);


--J1_RDATA_10 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_10
--operation mode is normal

J1_RDATA_10 = X1_request_43 & (S1_q_a[14] & !S1_q_a[10] # !S1_q_a[14] & !S1_q_a[3]);


--J1_RDATA_9 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_9
--operation mode is normal

J1_RDATA_9 = X1_request_43 & (S1_q_a[14] & !S1_q_a[9] # !S1_q_a[14] & !S1_q_a[4]);


--J1_RDATA_8 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_8
--operation mode is normal

J1_RDATA_8 = X1_request_43 & (S1_q_a[14] & !S1_q_a[8] # !S1_q_a[14] & !S1_q_a[5]);


--J1_RDATA_7 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_7
--operation mode is normal

J1_RDATA_7 = X1_request_43 & (S1_q_a[14] & !S1_q_a[7] # !S1_q_a[14] & !S1_q_a[6]);


--J1_RDATA_6 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_6
--operation mode is normal

J1_RDATA_6 = X1_request_43 & (S1_q_a[14] & !S1_q_a[6] # !S1_q_a[14] & !S1_q_a[7]);


--J1_RDATA_5 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_5
--operation mode is normal

J1_RDATA_5 = X1_request_43 & (S1_q_a[14] & !S1_q_a[5] # !S1_q_a[14] & !S1_q_a[8]);


--J1_RDATA_4 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_4
--operation mode is normal

J1_RDATA_4 = X1_request_43 & (S1_q_a[14] & !S1_q_a[4] # !S1_q_a[14] & !S1_q_a[9]);


--J1_RDATA_3 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_3
--operation mode is normal

J1_RDATA_3 = X1_request_43 & (S1_q_a[14] & !S1_q_a[3] # !S1_q_a[14] & !S1_q_a[10]);


--J1_RDATA_2 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_2
--operation mode is normal

J1_RDATA_2 = J1_nx131 # !X1_request_43 & !J1_NOT_cfr_2;


--J1_RDATA_1 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_1
--operation mode is normal

J1_RDATA_1 = J1_nx132 # !X1_request_43 & J1_cfr_1;


--J1_RDATA_0 is ADC_DAC_0:adcdac|pasadac:pdac|RDATA_0
--operation mode is normal

J1_RDATA_0 = J1_nx133 # !X1_request_43 & J1_cfr_0;


--J1_cfr_0 is ADC_DAC_0:adcdac|pasadac:pdac|cfr_0
--operation mode is normal

J1_cfr_0_lut_out = X1_request_31;
J1_cfr_0 = DFFEA(J1_cfr_0_lut_out, U1__clk1, V1_chipRST_n, , J1_wren_cfr, , );


--J1_cfr_1 is ADC_DAC_0:adcdac|pasadac:pdac|cfr_1
--operation mode is normal

J1_cfr_1_lut_out = X1_request_30;
J1_cfr_1 = DFFEA(J1_cfr_1_lut_out, U1__clk1, V1_chipRST_n, , J1_wren_cfr, , );


--J1_NOT_cfr_2 is ADC_DAC_0:adcdac|pasadac:pdac|NOT_cfr_2
--operation mode is normal

J1_NOT_cfr_2_lut_out = !X1_request_29;
J1_NOT_cfr_2 = DFFEA(J1_NOT_cfr_2_lut_out, U1__clk1, V1_chipRST_n, , J1_wren_cfr, , );


--J1_io_start is ADC_DAC_0:adcdac|pasadac:pdac|io_start
--operation mode is normal

J1_io_start_lut_out = G1_ce_pasa_dac & !V1_rd_wr_oase & !X1_request_43 & X1_request_28;
J1_io_start = DFFEA(J1_io_start_lut_out, U1__clk1, V1_chipRST_n, , , , );


--J1_PasaDAC1_CLK is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC1_CLK
--operation mode is normal

J1_PasaDAC1_CLK_lut_out = J1_sm_1 & !J1_sm_0 & !S1_q_b[14];
J1_PasaDAC1_CLK = DFFEA(J1_PasaDAC1_CLK_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC2_CLK is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC2_CLK
--operation mode is normal

J1_PasaDAC2_CLK_lut_out = J1_sm_1 & !J1_sm_0 & S1_q_b[14];
J1_PasaDAC2_CLK = DFFEA(J1_PasaDAC2_CLK_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_0 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_0
--operation mode is normal

J1_PasaDAC_D_0_lut_out = S1_q_b[0];
J1_PasaDAC_D_0 = DFFEA(J1_PasaDAC_D_0_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_1 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_1
--operation mode is normal

J1_PasaDAC_D_1_lut_out = S1_q_b[1];
J1_PasaDAC_D_1 = DFFEA(J1_PasaDAC_D_1_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_10 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_10
--operation mode is normal

J1_PasaDAC_D_10_lut_out = S1_q_b[10];
J1_PasaDAC_D_10 = DFFEA(J1_PasaDAC_D_10_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_11 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_11
--operation mode is normal

J1_PasaDAC_D_11_lut_out = S1_q_b[11];
J1_PasaDAC_D_11 = DFFEA(J1_PasaDAC_D_11_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_12 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_12
--operation mode is normal

J1_PasaDAC_D_12_lut_out = S1_q_b[12];
J1_PasaDAC_D_12 = DFFEA(J1_PasaDAC_D_12_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_13 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_13
--operation mode is normal

J1_PasaDAC_D_13_lut_out = S1_q_b[13];
J1_PasaDAC_D_13 = DFFEA(J1_PasaDAC_D_13_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_2 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_2
--operation mode is normal

J1_PasaDAC_D_2_lut_out = S1_q_b[2];
J1_PasaDAC_D_2 = DFFEA(J1_PasaDAC_D_2_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_3 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_3
--operation mode is normal

J1_PasaDAC_D_3_lut_out = S1_q_b[3];
J1_PasaDAC_D_3 = DFFEA(J1_PasaDAC_D_3_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_4 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_4
--operation mode is normal

J1_PasaDAC_D_4_lut_out = S1_q_b[4];
J1_PasaDAC_D_4 = DFFEA(J1_PasaDAC_D_4_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_5 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_5
--operation mode is normal

J1_PasaDAC_D_5_lut_out = S1_q_b[5];
J1_PasaDAC_D_5 = DFFEA(J1_PasaDAC_D_5_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_6 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_6
--operation mode is normal

J1_PasaDAC_D_6_lut_out = S1_q_b[6];
J1_PasaDAC_D_6 = DFFEA(J1_PasaDAC_D_6_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_7 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_7
--operation mode is normal

J1_PasaDAC_D_7_lut_out = S1_q_b[7];
J1_PasaDAC_D_7 = DFFEA(J1_PasaDAC_D_7_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_8 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_8
--operation mode is normal

J1_PasaDAC_D_8_lut_out = S1_q_b[8];
J1_PasaDAC_D_8 = DFFEA(J1_PasaDAC_D_8_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_D_9 is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_D_9
--operation mode is normal

J1_PasaDAC_D_9_lut_out = S1_q_b[9];
J1_PasaDAC_D_9 = DFFEA(J1_PasaDAC_D_9_lut_out, U1__clk0, VCC, , , , );


--J1_PasaDAC_Sleep is ADC_DAC_0:adcdac|pasadac:pdac|PasaDAC_Sleep
--operation mode is normal

J1_PasaDAC_Sleep_lut_out = !J1_sm_1 & !J1_sm_0 & J1_cfr_1;
J1_PasaDAC_Sleep = DFFEA(J1_PasaDAC_Sleep_lut_out, U1__clk0, VCC, , , , );


--J1_sm_0 is ADC_DAC_0:adcdac|pasadac:pdac|sm_0
--operation mode is normal

J1_sm_0_lut_out = J1_nx124 # J1_nx127 # J1_nx136 # J1_nx137;
J1_sm_0 = DFFEA(J1_sm_0_lut_out, U1__clk0, V1_chipRST_n, , , , );


--J1_sm_1 is ADC_DAC_0:adcdac|pasadac:pdac|sm_1
--operation mode is normal

J1_sm_1_lut_out = J1_nx315 # J1_nx124 # J1_nx125 & J1_nx142;
J1_sm_1 = DFFEA(J1_sm_1_lut_out, U1__clk0, V1_chipRST_n, , , , );


--J1_start_s is ADC_DAC_0:adcdac|pasadac:pdac|start_s
--operation mode is normal

J1_start_s_lut_out = J1_cfr_0 # J1_io_start # AD_SYNC_IN[1] & !J1_NOT_cfr_2;
J1_start_s = DFFEA(J1_start_s_lut_out, U1__clk0, VCC, , , , );


--J1_timer_en is ADC_DAC_0:adcdac|pasadac:pdac|timer_en
--operation mode is normal

J1_timer_en_lut_out = !J1_timer_en & (J1_sm_1 # J1_sm_0);
J1_timer_en = DFFEA(J1_timer_en_lut_out, U1__clk0, VCC, , , , );


--J1_timer_7 is ADC_DAC_0:adcdac|pasadac:pdac|timer_7
--operation mode is arithmetic

J1_timer_7_carry_eqn = J1_timer_nx45;
J1_timer_7_lut_out = J1_timer_7 $ J1_timer_7_carry_eqn;
J1_timer_7_reg_input = !J1_nx238 & J1_timer_7_lut_out;
J1_timer_7 = DFFEA(J1_timer_7_reg_input, U1__clk0, VCC, , , , );

--J1_timer_nx49 is ADC_DAC_0:adcdac|pasadac:pdac|timer_nx49
--operation mode is arithmetic

J1_timer_nx49 = CARRY(!J1_timer_nx45 # !J1_timer_7);


--J1_timer_6 is ADC_DAC_0:adcdac|pasadac:pdac|timer_6
--operation mode is arithmetic

J1_timer_6_carry_eqn = J1_timer_nx40;
J1_timer_6_lut_out = J1_timer_6 $ !J1_timer_6_carry_eqn;
J1_timer_6_reg_input = !J1_nx238 & J1_timer_6_lut_out;
J1_timer_6 = DFFEA(J1_timer_6_reg_input, U1__clk0, VCC, , , , );

--J1_timer_nx45 is ADC_DAC_0:adcdac|pasadac:pdac|timer_nx45
--operation mode is arithmetic

J1_timer_nx45 = CARRY(J1_timer_6 & !J1_timer_nx40);


--J1_timer_5 is ADC_DAC_0:adcdac|pasadac:pdac|timer_5
--operation mode is arithmetic

J1_timer_5_carry_eqn = J1_timer_nx33;
J1_timer_5_lut_out = J1_timer_5 $ J1_timer_5_carry_eqn;
J1_timer_5_reg_input = !J1_nx238 & J1_timer_5_lut_out;
J1_timer_5 = DFFEA(J1_timer_5_reg_input, U1__clk0, VCC, , , , );

--J1_timer_nx40 is ADC_DAC_0:adcdac|pasadac:pdac|timer_nx40
--operation mode is arithmetic

J1_timer_nx40 = CARRY(!J1_timer_nx33 # !J1_timer_5);


--J1_timer_4 is ADC_DAC_0:adcdac|pasadac:pdac|timer_4
--operation mode is arithmetic

J1_timer_4_carry_eqn = J1_timer_nx27;
J1_timer_4_lut_out = J1_timer_4 $ !J1_timer_4_carry_eqn;
J1_timer_4_reg_input = !J1_nx238 & J1_timer_4_lut_out;
J1_timer_4 = DFFEA(J1_timer_4_reg_input, U1__clk0, VCC, , , , );

--J1_timer_nx33 is ADC_DAC_0:adcdac|pasadac:pdac|timer_nx33
--operation mode is arithmetic

J1_timer_nx33 = CARRY(J1_timer_4 & !J1_timer_nx27);


--J1_timer_3 is ADC_DAC_0:adcdac|pasadac:pdac|timer_3
--operation mode is arithmetic

J1_timer_3_carry_eqn = J1_timer_nx21;
J1_timer_3_lut_out = J1_timer_3 $ J1_timer_3_carry_eqn;
J1_timer_3_reg_input = !J1_nx238 & J1_timer_3_lut_out;
J1_timer_3 = DFFEA(J1_timer_3_reg_input, U1__clk0, VCC, , , , );

--J1_timer_nx27 is ADC_DAC_0:adcdac|pasadac:pdac|timer_nx27
--operation mode is arithmetic

J1_timer_nx27 = CARRY(!J1_timer_nx21 # !J1_timer_3);


--J1_timer_2 is ADC_DAC_0:adcdac|pasadac:pdac|timer_2
--operation mode is arithmetic

J1_timer_2_carry_eqn = J1_timer_nx15;
J1_timer_2_lut_out = J1_timer_2 $ !J1_timer_2_carry_eqn;
J1_timer_2_reg_input = !J1_nx238 & J1_timer_2_lut_out;
J1_timer_2 = DFFEA(J1_timer_2_reg_input, U1__clk0, VCC, , , , );

--J1_timer_nx21 is ADC_DAC_0:adcdac|pasadac:pdac|timer_nx21
--operation mode is arithmetic

J1_timer_nx21 = CARRY(J1_timer_2 & !J1_timer_nx15);


--J1_timer_1 is ADC_DAC_0:adcdac|pasadac:pdac|timer_1
--operation mode is arithmetic

J1_timer_1_carry_eqn = J1_timer_nx9;
J1_timer_1_lut_out = J1_timer_1 $ J1_timer_1_carry_eqn;
J1_timer_1_reg_input = !J1_nx238 & J1_timer_1_lut_out;
J1_timer_1 = DFFEA(J1_timer_1_reg_input, U1__clk0, VCC, , , , );

--J1_timer_nx15 is ADC_DAC_0:adcdac|pasadac:pdac|timer_nx15
--operation mode is arithmetic

J1_timer_nx15 = CARRY(!J1_timer_nx9 # !J1_timer_1);


--J1_timer_0 is ADC_DAC_0:adcdac|pasadac:pdac|timer_0
--operation mode is arithmetic

J1_timer_0_lut_out = J1_timer_0 $ J1_timer_en;
J1_timer_0_reg_input = !J1_nx238 & J1_timer_0_lut_out;
J1_timer_0 = DFFEA(J1_timer_0_reg_input, U1__clk0, VCC, , , , );

--J1_timer_nx9 is ADC_DAC_0:adcdac|pasadac:pdac|timer_nx9
--operation mode is arithmetic

J1_timer_nx9 = CARRY(J1_timer_0 & J1_timer_en);


--J1_timer_8 is ADC_DAC_0:adcdac|pasadac:pdac|timer_8
--operation mode is normal

J1_timer_8_carry_eqn = J1_timer_nx49;
J1_timer_8_lut_out = J1_timer_8 $ !J1_timer_8_carry_eqn;
J1_timer_8_reg_input = !J1_nx238 & J1_timer_8_lut_out;
J1_timer_8 = DFFEA(J1_timer_8_reg_input, U1__clk0, VCC, , , , );


--H1_wren_cfr is ADC_DAC_0:adcdac|pasaadc:padc|wren_cfr
--operation mode is normal

H1_wren_cfr = G1_ce_pasa_adc & !V1_rd_wr_oase & X1_request_38;


--H1_nx78 is ADC_DAC_0:adcdac|pasaadc:padc|nx78
--operation mode is normal

H1_nx78 = H1_nx79 # H1_nx80 # !H1_samples_0 # !H1_samples_1;


--H1_nx79 is ADC_DAC_0:adcdac|pasaadc:padc|nx79
--operation mode is normal

H1_nx79 = !H1_samples_6 # !H1_samples_7 # !H1_samples_8 # !H1_samples_9;


--H1_nx80 is ADC_DAC_0:adcdac|pasaadc:padc|nx80
--operation mode is normal

H1_nx80 = !H1_samples_2 # !H1_samples_3 # !H1_samples_4 # !H1_samples_5;


--H1_RDATA_31 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_31
--operation mode is normal

H1_RDATA_31 = !X1_request_38 & Q1_q_b[31];


--H1_RDATA_30 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_30
--operation mode is normal

H1_RDATA_30 = !X1_request_38 & Q1_q_b[30];


--H1_RDATA_29 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_29
--operation mode is normal

H1_RDATA_29 = !X1_request_38 & Q1_q_b[29];


--H1_RDATA_28 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_28
--operation mode is normal

H1_RDATA_28 = !X1_request_38 & Q1_q_b[28];


--H1_RDATA_27 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_27
--operation mode is normal

H1_RDATA_27 = !X1_request_38 & Q1_q_b[27];


--H1_RDATA_26 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_26
--operation mode is normal

H1_RDATA_26 = !X1_request_38 & Q1_q_b[26];


--H1_RDATA_25 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_25
--operation mode is normal

H1_RDATA_25 = !X1_request_38 & Q1_q_b[25];


--H1_RDATA_24 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_24
--operation mode is normal

H1_RDATA_24 = !X1_request_38 & Q1_q_b[24];


--H1_RDATA_23 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_23
--operation mode is normal

H1_RDATA_23 = !X1_request_38 & Q1_q_b[23];


--H1_RDATA_22 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_22
--operation mode is normal

H1_RDATA_22 = !X1_request_38 & Q1_q_b[22];


--H1_RDATA_21 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_21
--operation mode is normal

H1_RDATA_21 = !X1_request_38 & Q1_q_b[21];


--H1_RDATA_20 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_20
--operation mode is normal

H1_RDATA_20 = !X1_request_38 & Q1_q_b[20];


--H1_RDATA_19 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_19
--operation mode is normal

H1_RDATA_19 = !X1_request_38 & Q1_q_b[19];


--H1_RDATA_18 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_18
--operation mode is normal

H1_RDATA_18 = !X1_request_38 & Q1_q_b[18];


--H1_RDATA_17 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_17
--operation mode is normal

H1_RDATA_17 = !X1_request_38 & Q1_q_b[17];


--H1_RDATA_16 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_16
--operation mode is normal

H1_RDATA_16 = !X1_request_38 & Q1_q_b[16];


--H1_RDATA_15 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_15
--operation mode is normal

H1_RDATA_15 = !X1_request_38 & Q1_q_b[15];


--H1_RDATA_14 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_14
--operation mode is normal

H1_RDATA_14 = !X1_request_38 & Q1_q_b[14];


--H1_RDATA_13 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_13
--operation mode is normal

H1_RDATA_13 = !X1_request_38 & Q1_q_b[13];


--H1_RDATA_12 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_12
--operation mode is normal

H1_RDATA_12 = !X1_request_38 & Q1_q_b[12];


--H1_RDATA_11 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_11
--operation mode is normal

H1_RDATA_11 = !X1_request_38 & Q1_q_b[11];


--H1_RDATA_10 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_10
--operation mode is normal

H1_RDATA_10 = !X1_request_38 & Q1_q_b[10];


--H1_RDATA_9 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_9
--operation mode is normal

H1_RDATA_9 = !X1_request_38 & Q1_q_b[9];


--H1_RDATA_8 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_8
--operation mode is normal

H1_RDATA_8 = !X1_request_38 & Q1_q_b[8];


--H1_RDATA_7 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_7
--operation mode is normal

H1_RDATA_7 = !X1_request_38 & Q1_q_b[7];


--H1_RDATA_6 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_6
--operation mode is normal

H1_RDATA_6 = X1_request_38 & !H1_NOT_cfr_6 # !X1_request_38 & Q1_q_b[6];


--H1_RDATA_5 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_5
--operation mode is normal

H1_RDATA_5 = X1_request_38 & H1_cfr_5 # !X1_request_38 & Q1_q_b[5];


--H1_RDATA_4 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_4
--operation mode is normal

H1_RDATA_4 = X1_request_38 & H1_PAADC_MuxnRS # !X1_request_38 & Q1_q_b[4];


--H1_RDATA_3 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_3
--operation mode is normal

H1_RDATA_3 = X1_request_38 & H1_cfr_3 # !X1_request_38 & Q1_q_b[3];


--H1_RDATA_2 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_2
--operation mode is normal

H1_RDATA_2 = X1_request_38 & H1_PAADC_Msel # !X1_request_38 & Q1_q_b[2];


--H1_RDATA_1 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_1
--operation mode is normal

H1_RDATA_1 = X1_request_38 & H1_PAADC_MuxA_1 # !X1_request_38 & Q1_q_b[1];


--H1_RDATA_0 is ADC_DAC_0:adcdac|pasaadc:padc|RDATA_0
--operation mode is normal

H1_RDATA_0 = X1_request_38 & H1_PAADC_MuxA_0 # !X1_request_38 & Q1_q_b[0];


--H1_PAADC_CLK is ADC_DAC_0:adcdac|pasaadc:padc|PAADC_CLK
--operation mode is normal

H1_PAADC_CLK = U1__clk1 $ H1_cfr_5;


--H1_PAADC_STDP is ADC_DAC_0:adcdac|pasaadc:padc|PAADC_STDP
--operation mode is normal

H1_PAADC_STDP = !H1_sm & H1_cfr_3;


--H1_wdata_ram_0 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_0
--operation mode is normal

H1_wdata_ram_0_lut_out = PAADC_D[0];
H1_wdata_ram_0 = DFFEA(H1_wdata_ram_0_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_1 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_1
--operation mode is normal

H1_wdata_ram_1_lut_out = PAADC_D[1];
H1_wdata_ram_1 = DFFEA(H1_wdata_ram_1_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_10 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_10
--operation mode is normal

H1_wdata_ram_10_lut_out = PAADC_D[10];
H1_wdata_ram_10 = DFFEA(H1_wdata_ram_10_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_11 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_11
--operation mode is normal

H1_wdata_ram_11_lut_out = PAADC_D[11];
H1_wdata_ram_11 = DFFEA(H1_wdata_ram_11_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_12 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_12
--operation mode is normal

H1_wdata_ram_12_lut_out = PAADC_OVR;
H1_wdata_ram_12 = DFFEA(H1_wdata_ram_12_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_2 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_2
--operation mode is normal

H1_wdata_ram_2_lut_out = PAADC_D[2];
H1_wdata_ram_2 = DFFEA(H1_wdata_ram_2_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_3 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_3
--operation mode is normal

H1_wdata_ram_3_lut_out = PAADC_D[3];
H1_wdata_ram_3 = DFFEA(H1_wdata_ram_3_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_4 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_4
--operation mode is normal

H1_wdata_ram_4_lut_out = PAADC_D[4];
H1_wdata_ram_4 = DFFEA(H1_wdata_ram_4_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_5 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_5
--operation mode is normal

H1_wdata_ram_5_lut_out = PAADC_D[5];
H1_wdata_ram_5 = DFFEA(H1_wdata_ram_5_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_6 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_6
--operation mode is normal

H1_wdata_ram_6_lut_out = PAADC_D[6];
H1_wdata_ram_6 = DFFEA(H1_wdata_ram_6_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_7 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_7
--operation mode is normal

H1_wdata_ram_7_lut_out = PAADC_D[7];
H1_wdata_ram_7 = DFFEA(H1_wdata_ram_7_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_8 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_8
--operation mode is normal

H1_wdata_ram_8_lut_out = PAADC_D[8];
H1_wdata_ram_8 = DFFEA(H1_wdata_ram_8_lut_out, U1__clk1, VCC, , , , );


--H1_wdata_ram_9 is ADC_DAC_0:adcdac|pasaadc:padc|wdata_ram_9
--operation mode is normal

H1_wdata_ram_9_lut_out = PAADC_D[9];
H1_wdata_ram_9 = DFFEA(H1_wdata_ram_9_lut_out, U1__clk1, VCC, , , , );


--H1_PAADC_MuxA_0 is ADC_DAC_0:adcdac|pasaadc:padc|PAADC_MuxA_0
--operation mode is normal

H1_PAADC_MuxA_0_lut_out = X1_request_31;
H1_PAADC_MuxA_0 = DFFEA(H1_PAADC_MuxA_0_lut_out, U1__clk1, V1_chipRST_n, , H1_wren_cfr, , );


--H1_PAADC_MuxA_1 is ADC_DAC_0:adcdac|pasaadc:padc|PAADC_MuxA_1
--operation mode is normal

H1_PAADC_MuxA_1_lut_out = X1_request_30;
H1_PAADC_MuxA_1 = DFFEA(H1_PAADC_MuxA_1_lut_out, U1__clk1, V1_chipRST_n, , H1_wren_cfr, , );


--H1_PAADC_Msel is ADC_DAC_0:adcdac|pasaadc:padc|PAADC_Msel
--operation mode is normal

H1_PAADC_Msel_lut_out = X1_request_29;
H1_PAADC_Msel = DFFEA(H1_PAADC_Msel_lut_out, U1__clk1, V1_chipRST_n, , H1_wren_cfr, , );


--H1_cfr_3 is ADC_DAC_0:adcdac|pasaadc:padc|cfr_3
--operation mode is normal

H1_cfr_3_lut_out = X1_request_28;
H1_cfr_3 = DFFEA(H1_cfr_3_lut_out, U1__clk1, V1_chipRST_n, , H1_wren_cfr, , );


--H1_PAADC_MuxnRS is ADC_DAC_0:adcdac|pasaadc:padc|PAADC_MuxnRS
--operation mode is normal

H1_PAADC_MuxnRS_lut_out = X1_request_27;
H1_PAADC_MuxnRS = DFFEA(H1_PAADC_MuxnRS_lut_out, U1__clk1, V1_chipRST_n, , H1_wren_cfr, , );


--H1_cfr_5 is ADC_DAC_0:adcdac|pasaadc:padc|cfr_5
--operation mode is normal

H1_cfr_5_lut_out = X1_request_26;
H1_cfr_5 = DFFEA(H1_cfr_5_lut_out, U1__clk1, V1_chipRST_n, , H1_wren_cfr, , );


--H1_NOT_cfr_6 is ADC_DAC_0:adcdac|pasaadc:padc|NOT_cfr_6
--operation mode is normal

H1_NOT_cfr_6_lut_out = !X1_request_25;
H1_NOT_cfr_6 = DFFEA(H1_NOT_cfr_6_lut_out, U1__clk1, V1_chipRST_n, , H1_wren_cfr, , );


--H1_io_start is ADC_DAC_0:adcdac|pasaadc:padc|io_start
--operation mode is normal

H1_io_start_lut_out = G1_ce_pasa_adc & !V1_rd_wr_oase & X1_request_38 & X1_request_24;
H1_io_start = DFFEA(H1_io_start_lut_out, U1__clk1, V1_chipRST_n, , , , );


--H1_sm is ADC_DAC_0:adcdac|pasaadc:padc|sm
--operation mode is normal

H1_sm_lut_out = H1_sm & H1_nx78 # !H1_sm & H1_start_s;
H1_sm = DFFEA(H1_sm_lut_out, U1__clk1, V1_chipRST_n, , , , );


--H1_start_s is ADC_DAC_0:adcdac|pasaadc:padc|start_s
--operation mode is normal

H1_start_s_lut_out = H1_io_start # AD_SYNC_IN[1] & !H1_NOT_cfr_6;
H1_start_s = DFFEA(H1_start_s_lut_out, U1__clk1, VCC, , , , );


--H1_samples_7 is ADC_DAC_0:adcdac|pasaadc:padc|samples_7
--operation mode is arithmetic

H1_samples_7_carry_eqn = H1_samples_nx41;
H1_samples_7_lut_out = H1_samples_7 $ H1_samples_7_carry_eqn;
H1_samples_7_reg_input = H1_sm & H1_samples_7_lut_out;
H1_samples_7 = DFFEA(H1_samples_7_reg_input, U1__clk1, VCC, , , , );

--H1_samples_nx45 is ADC_DAC_0:adcdac|pasaadc:padc|samples_nx45
--operation mode is arithmetic

H1_samples_nx45 = CARRY(!H1_samples_nx41 # !H1_samples_7);


--H1_samples_6 is ADC_DAC_0:adcdac|pasaadc:padc|samples_6
--operation mode is arithmetic

H1_samples_6_carry_eqn = H1_samples_nx37;
H1_samples_6_lut_out = H1_samples_6 $ !H1_samples_6_carry_eqn;
H1_samples_6_reg_input = H1_sm & H1_samples_6_lut_out;
H1_samples_6 = DFFEA(H1_samples_6_reg_input, U1__clk1, VCC, , , , );

--H1_samples_nx41 is ADC_DAC_0:adcdac|pasaadc:padc|samples_nx41
--operation mode is arithmetic

H1_samples_nx41 = CARRY(H1_samples_6 & !H1_samples_nx37);


--H1_samples_5 is ADC_DAC_0:adcdac|pasaadc:padc|samples_5
--operation mode is arithmetic

H1_samples_5_carry_eqn = H1_samples_nx29;
H1_samples_5_lut_out = H1_samples_5 $ H1_samples_5_carry_eqn;
H1_samples_5_reg_input = H1_sm & H1_samples_5_lut_out;
H1_samples_5 = DFFEA(H1_samples_5_reg_input, U1__clk1, VCC, , , , );

--H1_samples_nx37 is ADC_DAC_0:adcdac|pasaadc:padc|samples_nx37
--operation mode is arithmetic

H1_samples_nx37 = CARRY(!H1_samples_nx29 # !H1_samples_5);


--H1_samples_4 is ADC_DAC_0:adcdac|pasaadc:padc|samples_4
--operation mode is arithmetic

H1_samples_4_carry_eqn = H1_samples_nx23;
H1_samples_4_lut_out = H1_samples_4 $ !H1_samples_4_carry_eqn;
H1_samples_4_reg_input = H1_sm & H1_samples_4_lut_out;
H1_samples_4 = DFFEA(H1_samples_4_reg_input, U1__clk1, VCC, , , , );

--H1_samples_nx29 is ADC_DAC_0:adcdac|pasaadc:padc|samples_nx29
--operation mode is arithmetic

H1_samples_nx29 = CARRY(H1_samples_4 & !H1_samples_nx23);


--H1_samples_3 is ADC_DAC_0:adcdac|pasaadc:padc|samples_3
--operation mode is arithmetic

H1_samples_3_carry_eqn = H1_samples_nx17;
H1_samples_3_lut_out = H1_samples_3 $ H1_samples_3_carry_eqn;
H1_samples_3_reg_input = H1_sm & H1_samples_3_lut_out;
H1_samples_3 = DFFEA(H1_samples_3_reg_input, U1__clk1, VCC, , , , );

--H1_samples_nx23 is ADC_DAC_0:adcdac|pasaadc:padc|samples_nx23
--operation mode is arithmetic

H1_samples_nx23 = CARRY(!H1_samples_nx17 # !H1_samples_3);


--H1_samples_2 is ADC_DAC_0:adcdac|pasaadc:padc|samples_2
--operation mode is arithmetic

H1_samples_2_carry_eqn = H1_samples_nx11;
H1_samples_2_lut_out = H1_samples_2 $ !H1_samples_2_carry_eqn;
H1_samples_2_reg_input = H1_sm & H1_samples_2_lut_out;
H1_samples_2 = DFFEA(H1_samples_2_reg_input, U1__clk1, VCC, , , , );

--H1_samples_nx17 is ADC_DAC_0:adcdac|pasaadc:padc|samples_nx17
--operation mode is arithmetic

H1_samples_nx17 = CARRY(H1_samples_2 & !H1_samples_nx11);


--H1_samples_1 is ADC_DAC_0:adcdac|pasaadc:padc|samples_1
--operation mode is arithmetic

H1_samples_1_carry_eqn = H1_samples_nx5;
H1_samples_1_lut_out = H1_samples_1 $ H1_samples_1_carry_eqn;
H1_samples_1_reg_input = H1_sm & H1_samples_1_lut_out;
H1_samples_1 = DFFEA(H1_samples_1_reg_input, U1__clk1, VCC, , , , );

--H1_samples_nx11 is ADC_DAC_0:adcdac|pasaadc:padc|samples_nx11
--operation mode is arithmetic

H1_samples_nx11 = CARRY(!H1_samples_nx5 # !H1_samples_1);


--H1_samples_0 is ADC_DAC_0:adcdac|pasaadc:padc|samples_0
--operation mode is arithmetic

H1_samples_0_lut_out = !H1_samples_0;
H1_samples_0_reg_input = H1_sm & H1_samples_0_lut_out;
H1_samples_0 = DFFEA(H1_samples_0_reg_input, U1__clk1, VCC, , , , );

--H1_samples_nx5 is ADC_DAC_0:adcdac|pasaadc:padc|samples_nx5
--operation mode is arithmetic

H1_samples_nx5 = CARRY(H1_samples_0);


--H1_samples_9 is ADC_DAC_0:adcdac|pasaadc:padc|samples_9
--operation mode is normal

H1_samples_9_carry_eqn = H1_samples_nx49;
H1_samples_9_lut_out = H1_samples_9 $ H1_samples_9_carry_eqn;
H1_samples_9_reg_input = H1_sm & H1_samples_9_lut_out;
H1_samples_9 = DFFEA(H1_samples_9_reg_input, U1__clk1, VCC, , , , );


--H1_samples_8 is ADC_DAC_0:adcdac|pasaadc:padc|samples_8
--operation mode is arithmetic

H1_samples_8_carry_eqn = H1_samples_nx45;
H1_samples_8_lut_out = H1_samples_8 $ !H1_samples_8_carry_eqn;
H1_samples_8_reg_input = H1_sm & H1_samples_8_lut_out;
H1_samples_8 = DFFEA(H1_samples_8_reg_input, U1__clk1, VCC, , , , );

--H1_samples_nx49 is ADC_DAC_0:adcdac|pasaadc:padc|samples_nx49
--operation mode is arithmetic

H1_samples_nx49 = CARRY(H1_samples_8 & !H1_samples_nx45);


--Q1_q_b[0] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[0]
Q1_q_b[0]_PORT_A_data_in = H1_wdata_ram_0;
Q1_q_b[0]_PORT_A_data_in_reg = DFFE(Q1_q_b[0]_PORT_A_data_in, Q1_q_b[0]_clock_0, , , );
Q1_q_b[0]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[0]_PORT_A_address_reg = DFFE(Q1_q_b[0]_PORT_A_address, Q1_q_b[0]_clock_0, , , );
Q1_q_b[0]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[0]_PORT_B_address_reg = DFFE(Q1_q_b[0]_PORT_B_address, Q1_q_b[0]_clock_1, , , );
Q1_q_b[0]_PORT_A_write_enable = H1_sm;
Q1_q_b[0]_PORT_A_write_enable_reg = DFFE(Q1_q_b[0]_PORT_A_write_enable, Q1_q_b[0]_clock_0, , , );
Q1_q_b[0]_PORT_B_read_enable = VCC;
Q1_q_b[0]_PORT_B_read_enable_reg = DFFE(Q1_q_b[0]_PORT_B_read_enable, Q1_q_b[0]_clock_1, , , );
Q1_q_b[0]_clock_0 = U1__clk1;
Q1_q_b[0]_clock_1 = U1__clk1;
Q1_q_b[0]_PORT_B_data_out = MEMORY(Q1_q_b[0]_PORT_A_data_in_reg, , Q1_q_b[0]_PORT_A_address_reg, Q1_q_b[0]_PORT_B_address_reg, Q1_q_b[0]_PORT_A_write_enable_reg, Q1_q_b[0]_PORT_B_read_enable_reg, , , Q1_q_b[0]_clock_0, Q1_q_b[0]_clock_1, , , , );
Q1_q_b[0]_PORT_B_data_out_reg = DFFE(Q1_q_b[0]_PORT_B_data_out, Q1_q_b[0]_clock_1, , , );
Q1_q_b[0] = Q1_q_b[0]_PORT_B_data_out_reg[0];

--Q1_q_b[16] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[16]
Q1_q_b[0]_PORT_A_data_in = H1_wdata_ram_0;
Q1_q_b[0]_PORT_A_data_in_reg = DFFE(Q1_q_b[0]_PORT_A_data_in, Q1_q_b[0]_clock_0, , , );
Q1_q_b[0]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[0]_PORT_A_address_reg = DFFE(Q1_q_b[0]_PORT_A_address, Q1_q_b[0]_clock_0, , , );
Q1_q_b[0]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[0]_PORT_B_address_reg = DFFE(Q1_q_b[0]_PORT_B_address, Q1_q_b[0]_clock_1, , , );
Q1_q_b[0]_PORT_A_write_enable = H1_sm;
Q1_q_b[0]_PORT_A_write_enable_reg = DFFE(Q1_q_b[0]_PORT_A_write_enable, Q1_q_b[0]_clock_0, , , );
Q1_q_b[0]_PORT_B_read_enable = VCC;
Q1_q_b[0]_PORT_B_read_enable_reg = DFFE(Q1_q_b[0]_PORT_B_read_enable, Q1_q_b[0]_clock_1, , , );
Q1_q_b[0]_clock_0 = U1__clk1;
Q1_q_b[0]_clock_1 = U1__clk1;
Q1_q_b[0]_PORT_B_data_out = MEMORY(Q1_q_b[0]_PORT_A_data_in_reg, , Q1_q_b[0]_PORT_A_address_reg, Q1_q_b[0]_PORT_B_address_reg, Q1_q_b[0]_PORT_A_write_enable_reg, Q1_q_b[0]_PORT_B_read_enable_reg, , , Q1_q_b[0]_clock_0, Q1_q_b[0]_clock_1, , , , );
Q1_q_b[0]_PORT_B_data_out_reg = DFFE(Q1_q_b[0]_PORT_B_data_out, Q1_q_b[0]_clock_1, , , );
Q1_q_b[16] = Q1_q_b[0]_PORT_B_data_out_reg[1];


--Q1_q_b[1] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[1]
Q1_q_b[1]_PORT_A_data_in = H1_wdata_ram_1;
Q1_q_b[1]_PORT_A_data_in_reg = DFFE(Q1_q_b[1]_PORT_A_data_in, Q1_q_b[1]_clock_0, , , );
Q1_q_b[1]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[1]_PORT_A_address_reg = DFFE(Q1_q_b[1]_PORT_A_address, Q1_q_b[1]_clock_0, , , );
Q1_q_b[1]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[1]_PORT_B_address_reg = DFFE(Q1_q_b[1]_PORT_B_address, Q1_q_b[1]_clock_1, , , );
Q1_q_b[1]_PORT_A_write_enable = H1_sm;
Q1_q_b[1]_PORT_A_write_enable_reg = DFFE(Q1_q_b[1]_PORT_A_write_enable, Q1_q_b[1]_clock_0, , , );
Q1_q_b[1]_PORT_B_read_enable = VCC;
Q1_q_b[1]_PORT_B_read_enable_reg = DFFE(Q1_q_b[1]_PORT_B_read_enable, Q1_q_b[1]_clock_1, , , );
Q1_q_b[1]_clock_0 = U1__clk1;
Q1_q_b[1]_clock_1 = U1__clk1;
Q1_q_b[1]_PORT_B_data_out = MEMORY(Q1_q_b[1]_PORT_A_data_in_reg, , Q1_q_b[1]_PORT_A_address_reg, Q1_q_b[1]_PORT_B_address_reg, Q1_q_b[1]_PORT_A_write_enable_reg, Q1_q_b[1]_PORT_B_read_enable_reg, , , Q1_q_b[1]_clock_0, Q1_q_b[1]_clock_1, , , , );
Q1_q_b[1]_PORT_B_data_out_reg = DFFE(Q1_q_b[1]_PORT_B_data_out, Q1_q_b[1]_clock_1, , , );
Q1_q_b[1] = Q1_q_b[1]_PORT_B_data_out_reg[0];

--Q1_q_b[17] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[17]
Q1_q_b[1]_PORT_A_data_in = H1_wdata_ram_1;
Q1_q_b[1]_PORT_A_data_in_reg = DFFE(Q1_q_b[1]_PORT_A_data_in, Q1_q_b[1]_clock_0, , , );
Q1_q_b[1]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[1]_PORT_A_address_reg = DFFE(Q1_q_b[1]_PORT_A_address, Q1_q_b[1]_clock_0, , , );
Q1_q_b[1]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[1]_PORT_B_address_reg = DFFE(Q1_q_b[1]_PORT_B_address, Q1_q_b[1]_clock_1, , , );
Q1_q_b[1]_PORT_A_write_enable = H1_sm;
Q1_q_b[1]_PORT_A_write_enable_reg = DFFE(Q1_q_b[1]_PORT_A_write_enable, Q1_q_b[1]_clock_0, , , );
Q1_q_b[1]_PORT_B_read_enable = VCC;
Q1_q_b[1]_PORT_B_read_enable_reg = DFFE(Q1_q_b[1]_PORT_B_read_enable, Q1_q_b[1]_clock_1, , , );
Q1_q_b[1]_clock_0 = U1__clk1;
Q1_q_b[1]_clock_1 = U1__clk1;
Q1_q_b[1]_PORT_B_data_out = MEMORY(Q1_q_b[1]_PORT_A_data_in_reg, , Q1_q_b[1]_PORT_A_address_reg, Q1_q_b[1]_PORT_B_address_reg, Q1_q_b[1]_PORT_A_write_enable_reg, Q1_q_b[1]_PORT_B_read_enable_reg, , , Q1_q_b[1]_clock_0, Q1_q_b[1]_clock_1, , , , );
Q1_q_b[1]_PORT_B_data_out_reg = DFFE(Q1_q_b[1]_PORT_B_data_out, Q1_q_b[1]_clock_1, , , );
Q1_q_b[17] = Q1_q_b[1]_PORT_B_data_out_reg[1];


--Q1_q_b[2] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[2]
Q1_q_b[2]_PORT_A_data_in = H1_wdata_ram_2;
Q1_q_b[2]_PORT_A_data_in_reg = DFFE(Q1_q_b[2]_PORT_A_data_in, Q1_q_b[2]_clock_0, , , );
Q1_q_b[2]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[2]_PORT_A_address_reg = DFFE(Q1_q_b[2]_PORT_A_address, Q1_q_b[2]_clock_0, , , );
Q1_q_b[2]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[2]_PORT_B_address_reg = DFFE(Q1_q_b[2]_PORT_B_address, Q1_q_b[2]_clock_1, , , );
Q1_q_b[2]_PORT_A_write_enable = H1_sm;
Q1_q_b[2]_PORT_A_write_enable_reg = DFFE(Q1_q_b[2]_PORT_A_write_enable, Q1_q_b[2]_clock_0, , , );
Q1_q_b[2]_PORT_B_read_enable = VCC;
Q1_q_b[2]_PORT_B_read_enable_reg = DFFE(Q1_q_b[2]_PORT_B_read_enable, Q1_q_b[2]_clock_1, , , );
Q1_q_b[2]_clock_0 = U1__clk1;
Q1_q_b[2]_clock_1 = U1__clk1;
Q1_q_b[2]_PORT_B_data_out = MEMORY(Q1_q_b[2]_PORT_A_data_in_reg, , Q1_q_b[2]_PORT_A_address_reg, Q1_q_b[2]_PORT_B_address_reg, Q1_q_b[2]_PORT_A_write_enable_reg, Q1_q_b[2]_PORT_B_read_enable_reg, , , Q1_q_b[2]_clock_0, Q1_q_b[2]_clock_1, , , , );
Q1_q_b[2]_PORT_B_data_out_reg = DFFE(Q1_q_b[2]_PORT_B_data_out, Q1_q_b[2]_clock_1, , , );
Q1_q_b[2] = Q1_q_b[2]_PORT_B_data_out_reg[0];

--Q1_q_b[18] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[18]
Q1_q_b[2]_PORT_A_data_in = H1_wdata_ram_2;
Q1_q_b[2]_PORT_A_data_in_reg = DFFE(Q1_q_b[2]_PORT_A_data_in, Q1_q_b[2]_clock_0, , , );
Q1_q_b[2]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[2]_PORT_A_address_reg = DFFE(Q1_q_b[2]_PORT_A_address, Q1_q_b[2]_clock_0, , , );
Q1_q_b[2]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[2]_PORT_B_address_reg = DFFE(Q1_q_b[2]_PORT_B_address, Q1_q_b[2]_clock_1, , , );
Q1_q_b[2]_PORT_A_write_enable = H1_sm;
Q1_q_b[2]_PORT_A_write_enable_reg = DFFE(Q1_q_b[2]_PORT_A_write_enable, Q1_q_b[2]_clock_0, , , );
Q1_q_b[2]_PORT_B_read_enable = VCC;
Q1_q_b[2]_PORT_B_read_enable_reg = DFFE(Q1_q_b[2]_PORT_B_read_enable, Q1_q_b[2]_clock_1, , , );
Q1_q_b[2]_clock_0 = U1__clk1;
Q1_q_b[2]_clock_1 = U1__clk1;
Q1_q_b[2]_PORT_B_data_out = MEMORY(Q1_q_b[2]_PORT_A_data_in_reg, , Q1_q_b[2]_PORT_A_address_reg, Q1_q_b[2]_PORT_B_address_reg, Q1_q_b[2]_PORT_A_write_enable_reg, Q1_q_b[2]_PORT_B_read_enable_reg, , , Q1_q_b[2]_clock_0, Q1_q_b[2]_clock_1, , , , );
Q1_q_b[2]_PORT_B_data_out_reg = DFFE(Q1_q_b[2]_PORT_B_data_out, Q1_q_b[2]_clock_1, , , );
Q1_q_b[18] = Q1_q_b[2]_PORT_B_data_out_reg[1];


--Q1_q_b[3] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[3]
Q1_q_b[3]_PORT_A_data_in = H1_wdata_ram_3;
Q1_q_b[3]_PORT_A_data_in_reg = DFFE(Q1_q_b[3]_PORT_A_data_in, Q1_q_b[3]_clock_0, , , );
Q1_q_b[3]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[3]_PORT_A_address_reg = DFFE(Q1_q_b[3]_PORT_A_address, Q1_q_b[3]_clock_0, , , );
Q1_q_b[3]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[3]_PORT_B_address_reg = DFFE(Q1_q_b[3]_PORT_B_address, Q1_q_b[3]_clock_1, , , );
Q1_q_b[3]_PORT_A_write_enable = H1_sm;
Q1_q_b[3]_PORT_A_write_enable_reg = DFFE(Q1_q_b[3]_PORT_A_write_enable, Q1_q_b[3]_clock_0, , , );
Q1_q_b[3]_PORT_B_read_enable = VCC;
Q1_q_b[3]_PORT_B_read_enable_reg = DFFE(Q1_q_b[3]_PORT_B_read_enable, Q1_q_b[3]_clock_1, , , );
Q1_q_b[3]_clock_0 = U1__clk1;
Q1_q_b[3]_clock_1 = U1__clk1;
Q1_q_b[3]_PORT_B_data_out = MEMORY(Q1_q_b[3]_PORT_A_data_in_reg, , Q1_q_b[3]_PORT_A_address_reg, Q1_q_b[3]_PORT_B_address_reg, Q1_q_b[3]_PORT_A_write_enable_reg, Q1_q_b[3]_PORT_B_read_enable_reg, , , Q1_q_b[3]_clock_0, Q1_q_b[3]_clock_1, , , , );
Q1_q_b[3]_PORT_B_data_out_reg = DFFE(Q1_q_b[3]_PORT_B_data_out, Q1_q_b[3]_clock_1, , , );
Q1_q_b[3] = Q1_q_b[3]_PORT_B_data_out_reg[0];

--Q1_q_b[19] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[19]
Q1_q_b[3]_PORT_A_data_in = H1_wdata_ram_3;
Q1_q_b[3]_PORT_A_data_in_reg = DFFE(Q1_q_b[3]_PORT_A_data_in, Q1_q_b[3]_clock_0, , , );
Q1_q_b[3]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[3]_PORT_A_address_reg = DFFE(Q1_q_b[3]_PORT_A_address, Q1_q_b[3]_clock_0, , , );
Q1_q_b[3]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[3]_PORT_B_address_reg = DFFE(Q1_q_b[3]_PORT_B_address, Q1_q_b[3]_clock_1, , , );
Q1_q_b[3]_PORT_A_write_enable = H1_sm;
Q1_q_b[3]_PORT_A_write_enable_reg = DFFE(Q1_q_b[3]_PORT_A_write_enable, Q1_q_b[3]_clock_0, , , );
Q1_q_b[3]_PORT_B_read_enable = VCC;
Q1_q_b[3]_PORT_B_read_enable_reg = DFFE(Q1_q_b[3]_PORT_B_read_enable, Q1_q_b[3]_clock_1, , , );
Q1_q_b[3]_clock_0 = U1__clk1;
Q1_q_b[3]_clock_1 = U1__clk1;
Q1_q_b[3]_PORT_B_data_out = MEMORY(Q1_q_b[3]_PORT_A_data_in_reg, , Q1_q_b[3]_PORT_A_address_reg, Q1_q_b[3]_PORT_B_address_reg, Q1_q_b[3]_PORT_A_write_enable_reg, Q1_q_b[3]_PORT_B_read_enable_reg, , , Q1_q_b[3]_clock_0, Q1_q_b[3]_clock_1, , , , );
Q1_q_b[3]_PORT_B_data_out_reg = DFFE(Q1_q_b[3]_PORT_B_data_out, Q1_q_b[3]_clock_1, , , );
Q1_q_b[19] = Q1_q_b[3]_PORT_B_data_out_reg[1];


--Q1_q_b[4] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[4]
Q1_q_b[4]_PORT_A_data_in = H1_wdata_ram_4;
Q1_q_b[4]_PORT_A_data_in_reg = DFFE(Q1_q_b[4]_PORT_A_data_in, Q1_q_b[4]_clock_0, , , );
Q1_q_b[4]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[4]_PORT_A_address_reg = DFFE(Q1_q_b[4]_PORT_A_address, Q1_q_b[4]_clock_0, , , );
Q1_q_b[4]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[4]_PORT_B_address_reg = DFFE(Q1_q_b[4]_PORT_B_address, Q1_q_b[4]_clock_1, , , );
Q1_q_b[4]_PORT_A_write_enable = H1_sm;
Q1_q_b[4]_PORT_A_write_enable_reg = DFFE(Q1_q_b[4]_PORT_A_write_enable, Q1_q_b[4]_clock_0, , , );
Q1_q_b[4]_PORT_B_read_enable = VCC;
Q1_q_b[4]_PORT_B_read_enable_reg = DFFE(Q1_q_b[4]_PORT_B_read_enable, Q1_q_b[4]_clock_1, , , );
Q1_q_b[4]_clock_0 = U1__clk1;
Q1_q_b[4]_clock_1 = U1__clk1;
Q1_q_b[4]_PORT_B_data_out = MEMORY(Q1_q_b[4]_PORT_A_data_in_reg, , Q1_q_b[4]_PORT_A_address_reg, Q1_q_b[4]_PORT_B_address_reg, Q1_q_b[4]_PORT_A_write_enable_reg, Q1_q_b[4]_PORT_B_read_enable_reg, , , Q1_q_b[4]_clock_0, Q1_q_b[4]_clock_1, , , , );
Q1_q_b[4]_PORT_B_data_out_reg = DFFE(Q1_q_b[4]_PORT_B_data_out, Q1_q_b[4]_clock_1, , , );
Q1_q_b[4] = Q1_q_b[4]_PORT_B_data_out_reg[0];

--Q1_q_b[20] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[20]
Q1_q_b[4]_PORT_A_data_in = H1_wdata_ram_4;
Q1_q_b[4]_PORT_A_data_in_reg = DFFE(Q1_q_b[4]_PORT_A_data_in, Q1_q_b[4]_clock_0, , , );
Q1_q_b[4]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[4]_PORT_A_address_reg = DFFE(Q1_q_b[4]_PORT_A_address, Q1_q_b[4]_clock_0, , , );
Q1_q_b[4]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[4]_PORT_B_address_reg = DFFE(Q1_q_b[4]_PORT_B_address, Q1_q_b[4]_clock_1, , , );
Q1_q_b[4]_PORT_A_write_enable = H1_sm;
Q1_q_b[4]_PORT_A_write_enable_reg = DFFE(Q1_q_b[4]_PORT_A_write_enable, Q1_q_b[4]_clock_0, , , );
Q1_q_b[4]_PORT_B_read_enable = VCC;
Q1_q_b[4]_PORT_B_read_enable_reg = DFFE(Q1_q_b[4]_PORT_B_read_enable, Q1_q_b[4]_clock_1, , , );
Q1_q_b[4]_clock_0 = U1__clk1;
Q1_q_b[4]_clock_1 = U1__clk1;
Q1_q_b[4]_PORT_B_data_out = MEMORY(Q1_q_b[4]_PORT_A_data_in_reg, , Q1_q_b[4]_PORT_A_address_reg, Q1_q_b[4]_PORT_B_address_reg, Q1_q_b[4]_PORT_A_write_enable_reg, Q1_q_b[4]_PORT_B_read_enable_reg, , , Q1_q_b[4]_clock_0, Q1_q_b[4]_clock_1, , , , );
Q1_q_b[4]_PORT_B_data_out_reg = DFFE(Q1_q_b[4]_PORT_B_data_out, Q1_q_b[4]_clock_1, , , );
Q1_q_b[20] = Q1_q_b[4]_PORT_B_data_out_reg[1];


--Q1_q_b[5] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[5]
Q1_q_b[5]_PORT_A_data_in = H1_wdata_ram_5;
Q1_q_b[5]_PORT_A_data_in_reg = DFFE(Q1_q_b[5]_PORT_A_data_in, Q1_q_b[5]_clock_0, , , );
Q1_q_b[5]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[5]_PORT_A_address_reg = DFFE(Q1_q_b[5]_PORT_A_address, Q1_q_b[5]_clock_0, , , );
Q1_q_b[5]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[5]_PORT_B_address_reg = DFFE(Q1_q_b[5]_PORT_B_address, Q1_q_b[5]_clock_1, , , );
Q1_q_b[5]_PORT_A_write_enable = H1_sm;
Q1_q_b[5]_PORT_A_write_enable_reg = DFFE(Q1_q_b[5]_PORT_A_write_enable, Q1_q_b[5]_clock_0, , , );
Q1_q_b[5]_PORT_B_read_enable = VCC;
Q1_q_b[5]_PORT_B_read_enable_reg = DFFE(Q1_q_b[5]_PORT_B_read_enable, Q1_q_b[5]_clock_1, , , );
Q1_q_b[5]_clock_0 = U1__clk1;
Q1_q_b[5]_clock_1 = U1__clk1;
Q1_q_b[5]_PORT_B_data_out = MEMORY(Q1_q_b[5]_PORT_A_data_in_reg, , Q1_q_b[5]_PORT_A_address_reg, Q1_q_b[5]_PORT_B_address_reg, Q1_q_b[5]_PORT_A_write_enable_reg, Q1_q_b[5]_PORT_B_read_enable_reg, , , Q1_q_b[5]_clock_0, Q1_q_b[5]_clock_1, , , , );
Q1_q_b[5]_PORT_B_data_out_reg = DFFE(Q1_q_b[5]_PORT_B_data_out, Q1_q_b[5]_clock_1, , , );
Q1_q_b[5] = Q1_q_b[5]_PORT_B_data_out_reg[0];

--Q1_q_b[21] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[21]
Q1_q_b[5]_PORT_A_data_in = H1_wdata_ram_5;
Q1_q_b[5]_PORT_A_data_in_reg = DFFE(Q1_q_b[5]_PORT_A_data_in, Q1_q_b[5]_clock_0, , , );
Q1_q_b[5]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[5]_PORT_A_address_reg = DFFE(Q1_q_b[5]_PORT_A_address, Q1_q_b[5]_clock_0, , , );
Q1_q_b[5]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[5]_PORT_B_address_reg = DFFE(Q1_q_b[5]_PORT_B_address, Q1_q_b[5]_clock_1, , , );
Q1_q_b[5]_PORT_A_write_enable = H1_sm;
Q1_q_b[5]_PORT_A_write_enable_reg = DFFE(Q1_q_b[5]_PORT_A_write_enable, Q1_q_b[5]_clock_0, , , );
Q1_q_b[5]_PORT_B_read_enable = VCC;
Q1_q_b[5]_PORT_B_read_enable_reg = DFFE(Q1_q_b[5]_PORT_B_read_enable, Q1_q_b[5]_clock_1, , , );
Q1_q_b[5]_clock_0 = U1__clk1;
Q1_q_b[5]_clock_1 = U1__clk1;
Q1_q_b[5]_PORT_B_data_out = MEMORY(Q1_q_b[5]_PORT_A_data_in_reg, , Q1_q_b[5]_PORT_A_address_reg, Q1_q_b[5]_PORT_B_address_reg, Q1_q_b[5]_PORT_A_write_enable_reg, Q1_q_b[5]_PORT_B_read_enable_reg, , , Q1_q_b[5]_clock_0, Q1_q_b[5]_clock_1, , , , );
Q1_q_b[5]_PORT_B_data_out_reg = DFFE(Q1_q_b[5]_PORT_B_data_out, Q1_q_b[5]_clock_1, , , );
Q1_q_b[21] = Q1_q_b[5]_PORT_B_data_out_reg[1];


--Q1_q_b[6] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[6]
Q1_q_b[6]_PORT_A_data_in = H1_wdata_ram_6;
Q1_q_b[6]_PORT_A_data_in_reg = DFFE(Q1_q_b[6]_PORT_A_data_in, Q1_q_b[6]_clock_0, , , );
Q1_q_b[6]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[6]_PORT_A_address_reg = DFFE(Q1_q_b[6]_PORT_A_address, Q1_q_b[6]_clock_0, , , );
Q1_q_b[6]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[6]_PORT_B_address_reg = DFFE(Q1_q_b[6]_PORT_B_address, Q1_q_b[6]_clock_1, , , );
Q1_q_b[6]_PORT_A_write_enable = H1_sm;
Q1_q_b[6]_PORT_A_write_enable_reg = DFFE(Q1_q_b[6]_PORT_A_write_enable, Q1_q_b[6]_clock_0, , , );
Q1_q_b[6]_PORT_B_read_enable = VCC;
Q1_q_b[6]_PORT_B_read_enable_reg = DFFE(Q1_q_b[6]_PORT_B_read_enable, Q1_q_b[6]_clock_1, , , );
Q1_q_b[6]_clock_0 = U1__clk1;
Q1_q_b[6]_clock_1 = U1__clk1;
Q1_q_b[6]_PORT_B_data_out = MEMORY(Q1_q_b[6]_PORT_A_data_in_reg, , Q1_q_b[6]_PORT_A_address_reg, Q1_q_b[6]_PORT_B_address_reg, Q1_q_b[6]_PORT_A_write_enable_reg, Q1_q_b[6]_PORT_B_read_enable_reg, , , Q1_q_b[6]_clock_0, Q1_q_b[6]_clock_1, , , , );
Q1_q_b[6]_PORT_B_data_out_reg = DFFE(Q1_q_b[6]_PORT_B_data_out, Q1_q_b[6]_clock_1, , , );
Q1_q_b[6] = Q1_q_b[6]_PORT_B_data_out_reg[0];

--Q1_q_b[22] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[22]
Q1_q_b[6]_PORT_A_data_in = H1_wdata_ram_6;
Q1_q_b[6]_PORT_A_data_in_reg = DFFE(Q1_q_b[6]_PORT_A_data_in, Q1_q_b[6]_clock_0, , , );
Q1_q_b[6]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[6]_PORT_A_address_reg = DFFE(Q1_q_b[6]_PORT_A_address, Q1_q_b[6]_clock_0, , , );
Q1_q_b[6]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[6]_PORT_B_address_reg = DFFE(Q1_q_b[6]_PORT_B_address, Q1_q_b[6]_clock_1, , , );
Q1_q_b[6]_PORT_A_write_enable = H1_sm;
Q1_q_b[6]_PORT_A_write_enable_reg = DFFE(Q1_q_b[6]_PORT_A_write_enable, Q1_q_b[6]_clock_0, , , );
Q1_q_b[6]_PORT_B_read_enable = VCC;
Q1_q_b[6]_PORT_B_read_enable_reg = DFFE(Q1_q_b[6]_PORT_B_read_enable, Q1_q_b[6]_clock_1, , , );
Q1_q_b[6]_clock_0 = U1__clk1;
Q1_q_b[6]_clock_1 = U1__clk1;
Q1_q_b[6]_PORT_B_data_out = MEMORY(Q1_q_b[6]_PORT_A_data_in_reg, , Q1_q_b[6]_PORT_A_address_reg, Q1_q_b[6]_PORT_B_address_reg, Q1_q_b[6]_PORT_A_write_enable_reg, Q1_q_b[6]_PORT_B_read_enable_reg, , , Q1_q_b[6]_clock_0, Q1_q_b[6]_clock_1, , , , );
Q1_q_b[6]_PORT_B_data_out_reg = DFFE(Q1_q_b[6]_PORT_B_data_out, Q1_q_b[6]_clock_1, , , );
Q1_q_b[22] = Q1_q_b[6]_PORT_B_data_out_reg[1];


--Q1_q_b[7] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[7]
Q1_q_b[7]_PORT_A_data_in = H1_wdata_ram_7;
Q1_q_b[7]_PORT_A_data_in_reg = DFFE(Q1_q_b[7]_PORT_A_data_in, Q1_q_b[7]_clock_0, , , );
Q1_q_b[7]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[7]_PORT_A_address_reg = DFFE(Q1_q_b[7]_PORT_A_address, Q1_q_b[7]_clock_0, , , );
Q1_q_b[7]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[7]_PORT_B_address_reg = DFFE(Q1_q_b[7]_PORT_B_address, Q1_q_b[7]_clock_1, , , );
Q1_q_b[7]_PORT_A_write_enable = H1_sm;
Q1_q_b[7]_PORT_A_write_enable_reg = DFFE(Q1_q_b[7]_PORT_A_write_enable, Q1_q_b[7]_clock_0, , , );
Q1_q_b[7]_PORT_B_read_enable = VCC;
Q1_q_b[7]_PORT_B_read_enable_reg = DFFE(Q1_q_b[7]_PORT_B_read_enable, Q1_q_b[7]_clock_1, , , );
Q1_q_b[7]_clock_0 = U1__clk1;
Q1_q_b[7]_clock_1 = U1__clk1;
Q1_q_b[7]_PORT_B_data_out = MEMORY(Q1_q_b[7]_PORT_A_data_in_reg, , Q1_q_b[7]_PORT_A_address_reg, Q1_q_b[7]_PORT_B_address_reg, Q1_q_b[7]_PORT_A_write_enable_reg, Q1_q_b[7]_PORT_B_read_enable_reg, , , Q1_q_b[7]_clock_0, Q1_q_b[7]_clock_1, , , , );
Q1_q_b[7]_PORT_B_data_out_reg = DFFE(Q1_q_b[7]_PORT_B_data_out, Q1_q_b[7]_clock_1, , , );
Q1_q_b[7] = Q1_q_b[7]_PORT_B_data_out_reg[0];

--Q1_q_b[23] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[23]
Q1_q_b[7]_PORT_A_data_in = H1_wdata_ram_7;
Q1_q_b[7]_PORT_A_data_in_reg = DFFE(Q1_q_b[7]_PORT_A_data_in, Q1_q_b[7]_clock_0, , , );
Q1_q_b[7]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[7]_PORT_A_address_reg = DFFE(Q1_q_b[7]_PORT_A_address, Q1_q_b[7]_clock_0, , , );
Q1_q_b[7]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[7]_PORT_B_address_reg = DFFE(Q1_q_b[7]_PORT_B_address, Q1_q_b[7]_clock_1, , , );
Q1_q_b[7]_PORT_A_write_enable = H1_sm;
Q1_q_b[7]_PORT_A_write_enable_reg = DFFE(Q1_q_b[7]_PORT_A_write_enable, Q1_q_b[7]_clock_0, , , );
Q1_q_b[7]_PORT_B_read_enable = VCC;
Q1_q_b[7]_PORT_B_read_enable_reg = DFFE(Q1_q_b[7]_PORT_B_read_enable, Q1_q_b[7]_clock_1, , , );
Q1_q_b[7]_clock_0 = U1__clk1;
Q1_q_b[7]_clock_1 = U1__clk1;
Q1_q_b[7]_PORT_B_data_out = MEMORY(Q1_q_b[7]_PORT_A_data_in_reg, , Q1_q_b[7]_PORT_A_address_reg, Q1_q_b[7]_PORT_B_address_reg, Q1_q_b[7]_PORT_A_write_enable_reg, Q1_q_b[7]_PORT_B_read_enable_reg, , , Q1_q_b[7]_clock_0, Q1_q_b[7]_clock_1, , , , );
Q1_q_b[7]_PORT_B_data_out_reg = DFFE(Q1_q_b[7]_PORT_B_data_out, Q1_q_b[7]_clock_1, , , );
Q1_q_b[23] = Q1_q_b[7]_PORT_B_data_out_reg[1];


--Q1_q_b[8] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[8]
Q1_q_b[8]_PORT_A_data_in = H1_wdata_ram_8;
Q1_q_b[8]_PORT_A_data_in_reg = DFFE(Q1_q_b[8]_PORT_A_data_in, Q1_q_b[8]_clock_0, , , );
Q1_q_b[8]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[8]_PORT_A_address_reg = DFFE(Q1_q_b[8]_PORT_A_address, Q1_q_b[8]_clock_0, , , );
Q1_q_b[8]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[8]_PORT_B_address_reg = DFFE(Q1_q_b[8]_PORT_B_address, Q1_q_b[8]_clock_1, , , );
Q1_q_b[8]_PORT_A_write_enable = H1_sm;
Q1_q_b[8]_PORT_A_write_enable_reg = DFFE(Q1_q_b[8]_PORT_A_write_enable, Q1_q_b[8]_clock_0, , , );
Q1_q_b[8]_PORT_B_read_enable = VCC;
Q1_q_b[8]_PORT_B_read_enable_reg = DFFE(Q1_q_b[8]_PORT_B_read_enable, Q1_q_b[8]_clock_1, , , );
Q1_q_b[8]_clock_0 = U1__clk1;
Q1_q_b[8]_clock_1 = U1__clk1;
Q1_q_b[8]_PORT_B_data_out = MEMORY(Q1_q_b[8]_PORT_A_data_in_reg, , Q1_q_b[8]_PORT_A_address_reg, Q1_q_b[8]_PORT_B_address_reg, Q1_q_b[8]_PORT_A_write_enable_reg, Q1_q_b[8]_PORT_B_read_enable_reg, , , Q1_q_b[8]_clock_0, Q1_q_b[8]_clock_1, , , , );
Q1_q_b[8]_PORT_B_data_out_reg = DFFE(Q1_q_b[8]_PORT_B_data_out, Q1_q_b[8]_clock_1, , , );
Q1_q_b[8] = Q1_q_b[8]_PORT_B_data_out_reg[0];

--Q1_q_b[24] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[24]
Q1_q_b[8]_PORT_A_data_in = H1_wdata_ram_8;
Q1_q_b[8]_PORT_A_data_in_reg = DFFE(Q1_q_b[8]_PORT_A_data_in, Q1_q_b[8]_clock_0, , , );
Q1_q_b[8]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[8]_PORT_A_address_reg = DFFE(Q1_q_b[8]_PORT_A_address, Q1_q_b[8]_clock_0, , , );
Q1_q_b[8]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[8]_PORT_B_address_reg = DFFE(Q1_q_b[8]_PORT_B_address, Q1_q_b[8]_clock_1, , , );
Q1_q_b[8]_PORT_A_write_enable = H1_sm;
Q1_q_b[8]_PORT_A_write_enable_reg = DFFE(Q1_q_b[8]_PORT_A_write_enable, Q1_q_b[8]_clock_0, , , );
Q1_q_b[8]_PORT_B_read_enable = VCC;
Q1_q_b[8]_PORT_B_read_enable_reg = DFFE(Q1_q_b[8]_PORT_B_read_enable, Q1_q_b[8]_clock_1, , , );
Q1_q_b[8]_clock_0 = U1__clk1;
Q1_q_b[8]_clock_1 = U1__clk1;
Q1_q_b[8]_PORT_B_data_out = MEMORY(Q1_q_b[8]_PORT_A_data_in_reg, , Q1_q_b[8]_PORT_A_address_reg, Q1_q_b[8]_PORT_B_address_reg, Q1_q_b[8]_PORT_A_write_enable_reg, Q1_q_b[8]_PORT_B_read_enable_reg, , , Q1_q_b[8]_clock_0, Q1_q_b[8]_clock_1, , , , );
Q1_q_b[8]_PORT_B_data_out_reg = DFFE(Q1_q_b[8]_PORT_B_data_out, Q1_q_b[8]_clock_1, , , );
Q1_q_b[24] = Q1_q_b[8]_PORT_B_data_out_reg[1];


--Q1_q_b[9] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[9]
Q1_q_b[9]_PORT_A_data_in = H1_wdata_ram_9;
Q1_q_b[9]_PORT_A_data_in_reg = DFFE(Q1_q_b[9]_PORT_A_data_in, Q1_q_b[9]_clock_0, , , );
Q1_q_b[9]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[9]_PORT_A_address_reg = DFFE(Q1_q_b[9]_PORT_A_address, Q1_q_b[9]_clock_0, , , );
Q1_q_b[9]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[9]_PORT_B_address_reg = DFFE(Q1_q_b[9]_PORT_B_address, Q1_q_b[9]_clock_1, , , );
Q1_q_b[9]_PORT_A_write_enable = H1_sm;
Q1_q_b[9]_PORT_A_write_enable_reg = DFFE(Q1_q_b[9]_PORT_A_write_enable, Q1_q_b[9]_clock_0, , , );
Q1_q_b[9]_PORT_B_read_enable = VCC;
Q1_q_b[9]_PORT_B_read_enable_reg = DFFE(Q1_q_b[9]_PORT_B_read_enable, Q1_q_b[9]_clock_1, , , );
Q1_q_b[9]_clock_0 = U1__clk1;
Q1_q_b[9]_clock_1 = U1__clk1;
Q1_q_b[9]_PORT_B_data_out = MEMORY(Q1_q_b[9]_PORT_A_data_in_reg, , Q1_q_b[9]_PORT_A_address_reg, Q1_q_b[9]_PORT_B_address_reg, Q1_q_b[9]_PORT_A_write_enable_reg, Q1_q_b[9]_PORT_B_read_enable_reg, , , Q1_q_b[9]_clock_0, Q1_q_b[9]_clock_1, , , , );
Q1_q_b[9]_PORT_B_data_out_reg = DFFE(Q1_q_b[9]_PORT_B_data_out, Q1_q_b[9]_clock_1, , , );
Q1_q_b[9] = Q1_q_b[9]_PORT_B_data_out_reg[0];

--Q1_q_b[25] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[25]
Q1_q_b[9]_PORT_A_data_in = H1_wdata_ram_9;
Q1_q_b[9]_PORT_A_data_in_reg = DFFE(Q1_q_b[9]_PORT_A_data_in, Q1_q_b[9]_clock_0, , , );
Q1_q_b[9]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[9]_PORT_A_address_reg = DFFE(Q1_q_b[9]_PORT_A_address, Q1_q_b[9]_clock_0, , , );
Q1_q_b[9]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[9]_PORT_B_address_reg = DFFE(Q1_q_b[9]_PORT_B_address, Q1_q_b[9]_clock_1, , , );
Q1_q_b[9]_PORT_A_write_enable = H1_sm;
Q1_q_b[9]_PORT_A_write_enable_reg = DFFE(Q1_q_b[9]_PORT_A_write_enable, Q1_q_b[9]_clock_0, , , );
Q1_q_b[9]_PORT_B_read_enable = VCC;
Q1_q_b[9]_PORT_B_read_enable_reg = DFFE(Q1_q_b[9]_PORT_B_read_enable, Q1_q_b[9]_clock_1, , , );
Q1_q_b[9]_clock_0 = U1__clk1;
Q1_q_b[9]_clock_1 = U1__clk1;
Q1_q_b[9]_PORT_B_data_out = MEMORY(Q1_q_b[9]_PORT_A_data_in_reg, , Q1_q_b[9]_PORT_A_address_reg, Q1_q_b[9]_PORT_B_address_reg, Q1_q_b[9]_PORT_A_write_enable_reg, Q1_q_b[9]_PORT_B_read_enable_reg, , , Q1_q_b[9]_clock_0, Q1_q_b[9]_clock_1, , , , );
Q1_q_b[9]_PORT_B_data_out_reg = DFFE(Q1_q_b[9]_PORT_B_data_out, Q1_q_b[9]_clock_1, , , );
Q1_q_b[25] = Q1_q_b[9]_PORT_B_data_out_reg[1];


--Q1_q_b[10] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[10]
Q1_q_b[10]_PORT_A_data_in = H1_wdata_ram_10;
Q1_q_b[10]_PORT_A_data_in_reg = DFFE(Q1_q_b[10]_PORT_A_data_in, Q1_q_b[10]_clock_0, , , );
Q1_q_b[10]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[10]_PORT_A_address_reg = DFFE(Q1_q_b[10]_PORT_A_address, Q1_q_b[10]_clock_0, , , );
Q1_q_b[10]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[10]_PORT_B_address_reg = DFFE(Q1_q_b[10]_PORT_B_address, Q1_q_b[10]_clock_1, , , );
Q1_q_b[10]_PORT_A_write_enable = H1_sm;
Q1_q_b[10]_PORT_A_write_enable_reg = DFFE(Q1_q_b[10]_PORT_A_write_enable, Q1_q_b[10]_clock_0, , , );
Q1_q_b[10]_PORT_B_read_enable = VCC;
Q1_q_b[10]_PORT_B_read_enable_reg = DFFE(Q1_q_b[10]_PORT_B_read_enable, Q1_q_b[10]_clock_1, , , );
Q1_q_b[10]_clock_0 = U1__clk1;
Q1_q_b[10]_clock_1 = U1__clk1;
Q1_q_b[10]_PORT_B_data_out = MEMORY(Q1_q_b[10]_PORT_A_data_in_reg, , Q1_q_b[10]_PORT_A_address_reg, Q1_q_b[10]_PORT_B_address_reg, Q1_q_b[10]_PORT_A_write_enable_reg, Q1_q_b[10]_PORT_B_read_enable_reg, , , Q1_q_b[10]_clock_0, Q1_q_b[10]_clock_1, , , , );
Q1_q_b[10]_PORT_B_data_out_reg = DFFE(Q1_q_b[10]_PORT_B_data_out, Q1_q_b[10]_clock_1, , , );
Q1_q_b[10] = Q1_q_b[10]_PORT_B_data_out_reg[0];

--Q1_q_b[26] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[26]
Q1_q_b[10]_PORT_A_data_in = H1_wdata_ram_10;
Q1_q_b[10]_PORT_A_data_in_reg = DFFE(Q1_q_b[10]_PORT_A_data_in, Q1_q_b[10]_clock_0, , , );
Q1_q_b[10]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[10]_PORT_A_address_reg = DFFE(Q1_q_b[10]_PORT_A_address, Q1_q_b[10]_clock_0, , , );
Q1_q_b[10]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[10]_PORT_B_address_reg = DFFE(Q1_q_b[10]_PORT_B_address, Q1_q_b[10]_clock_1, , , );
Q1_q_b[10]_PORT_A_write_enable = H1_sm;
Q1_q_b[10]_PORT_A_write_enable_reg = DFFE(Q1_q_b[10]_PORT_A_write_enable, Q1_q_b[10]_clock_0, , , );
Q1_q_b[10]_PORT_B_read_enable = VCC;
Q1_q_b[10]_PORT_B_read_enable_reg = DFFE(Q1_q_b[10]_PORT_B_read_enable, Q1_q_b[10]_clock_1, , , );
Q1_q_b[10]_clock_0 = U1__clk1;
Q1_q_b[10]_clock_1 = U1__clk1;
Q1_q_b[10]_PORT_B_data_out = MEMORY(Q1_q_b[10]_PORT_A_data_in_reg, , Q1_q_b[10]_PORT_A_address_reg, Q1_q_b[10]_PORT_B_address_reg, Q1_q_b[10]_PORT_A_write_enable_reg, Q1_q_b[10]_PORT_B_read_enable_reg, , , Q1_q_b[10]_clock_0, Q1_q_b[10]_clock_1, , , , );
Q1_q_b[10]_PORT_B_data_out_reg = DFFE(Q1_q_b[10]_PORT_B_data_out, Q1_q_b[10]_clock_1, , , );
Q1_q_b[26] = Q1_q_b[10]_PORT_B_data_out_reg[1];


--Q1_q_b[11] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[11]
Q1_q_b[11]_PORT_A_data_in = H1_wdata_ram_11;
Q1_q_b[11]_PORT_A_data_in_reg = DFFE(Q1_q_b[11]_PORT_A_data_in, Q1_q_b[11]_clock_0, , , );
Q1_q_b[11]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[11]_PORT_A_address_reg = DFFE(Q1_q_b[11]_PORT_A_address, Q1_q_b[11]_clock_0, , , );
Q1_q_b[11]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[11]_PORT_B_address_reg = DFFE(Q1_q_b[11]_PORT_B_address, Q1_q_b[11]_clock_1, , , );
Q1_q_b[11]_PORT_A_write_enable = H1_sm;
Q1_q_b[11]_PORT_A_write_enable_reg = DFFE(Q1_q_b[11]_PORT_A_write_enable, Q1_q_b[11]_clock_0, , , );
Q1_q_b[11]_PORT_B_read_enable = VCC;
Q1_q_b[11]_PORT_B_read_enable_reg = DFFE(Q1_q_b[11]_PORT_B_read_enable, Q1_q_b[11]_clock_1, , , );
Q1_q_b[11]_clock_0 = U1__clk1;
Q1_q_b[11]_clock_1 = U1__clk1;
Q1_q_b[11]_PORT_B_data_out = MEMORY(Q1_q_b[11]_PORT_A_data_in_reg, , Q1_q_b[11]_PORT_A_address_reg, Q1_q_b[11]_PORT_B_address_reg, Q1_q_b[11]_PORT_A_write_enable_reg, Q1_q_b[11]_PORT_B_read_enable_reg, , , Q1_q_b[11]_clock_0, Q1_q_b[11]_clock_1, , , , );
Q1_q_b[11]_PORT_B_data_out_reg = DFFE(Q1_q_b[11]_PORT_B_data_out, Q1_q_b[11]_clock_1, , , );
Q1_q_b[11] = Q1_q_b[11]_PORT_B_data_out_reg[0];

--Q1_q_b[27] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[27]
Q1_q_b[11]_PORT_A_data_in = H1_wdata_ram_11;
Q1_q_b[11]_PORT_A_data_in_reg = DFFE(Q1_q_b[11]_PORT_A_data_in, Q1_q_b[11]_clock_0, , , );
Q1_q_b[11]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[11]_PORT_A_address_reg = DFFE(Q1_q_b[11]_PORT_A_address, Q1_q_b[11]_clock_0, , , );
Q1_q_b[11]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[11]_PORT_B_address_reg = DFFE(Q1_q_b[11]_PORT_B_address, Q1_q_b[11]_clock_1, , , );
Q1_q_b[11]_PORT_A_write_enable = H1_sm;
Q1_q_b[11]_PORT_A_write_enable_reg = DFFE(Q1_q_b[11]_PORT_A_write_enable, Q1_q_b[11]_clock_0, , , );
Q1_q_b[11]_PORT_B_read_enable = VCC;
Q1_q_b[11]_PORT_B_read_enable_reg = DFFE(Q1_q_b[11]_PORT_B_read_enable, Q1_q_b[11]_clock_1, , , );
Q1_q_b[11]_clock_0 = U1__clk1;
Q1_q_b[11]_clock_1 = U1__clk1;
Q1_q_b[11]_PORT_B_data_out = MEMORY(Q1_q_b[11]_PORT_A_data_in_reg, , Q1_q_b[11]_PORT_A_address_reg, Q1_q_b[11]_PORT_B_address_reg, Q1_q_b[11]_PORT_A_write_enable_reg, Q1_q_b[11]_PORT_B_read_enable_reg, , , Q1_q_b[11]_clock_0, Q1_q_b[11]_clock_1, , , , );
Q1_q_b[11]_PORT_B_data_out_reg = DFFE(Q1_q_b[11]_PORT_B_data_out, Q1_q_b[11]_clock_1, , , );
Q1_q_b[27] = Q1_q_b[11]_PORT_B_data_out_reg[1];


--Q1_q_b[12] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[12]
Q1_q_b[12]_PORT_A_data_in = H1_wdata_ram_12;
Q1_q_b[12]_PORT_A_data_in_reg = DFFE(Q1_q_b[12]_PORT_A_data_in, Q1_q_b[12]_clock_0, , , );
Q1_q_b[12]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[12]_PORT_A_address_reg = DFFE(Q1_q_b[12]_PORT_A_address, Q1_q_b[12]_clock_0, , , );
Q1_q_b[12]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[12]_PORT_B_address_reg = DFFE(Q1_q_b[12]_PORT_B_address, Q1_q_b[12]_clock_1, , , );
Q1_q_b[12]_PORT_A_write_enable = H1_sm;
Q1_q_b[12]_PORT_A_write_enable_reg = DFFE(Q1_q_b[12]_PORT_A_write_enable, Q1_q_b[12]_clock_0, , , );
Q1_q_b[12]_PORT_B_read_enable = VCC;
Q1_q_b[12]_PORT_B_read_enable_reg = DFFE(Q1_q_b[12]_PORT_B_read_enable, Q1_q_b[12]_clock_1, , , );
Q1_q_b[12]_clock_0 = U1__clk1;
Q1_q_b[12]_clock_1 = U1__clk1;
Q1_q_b[12]_PORT_B_data_out = MEMORY(Q1_q_b[12]_PORT_A_data_in_reg, , Q1_q_b[12]_PORT_A_address_reg, Q1_q_b[12]_PORT_B_address_reg, Q1_q_b[12]_PORT_A_write_enable_reg, Q1_q_b[12]_PORT_B_read_enable_reg, , , Q1_q_b[12]_clock_0, Q1_q_b[12]_clock_1, , , , );
Q1_q_b[12]_PORT_B_data_out_reg = DFFE(Q1_q_b[12]_PORT_B_data_out, Q1_q_b[12]_clock_1, , , );
Q1_q_b[12] = Q1_q_b[12]_PORT_B_data_out_reg[0];

--Q1_q_b[28] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[28]
Q1_q_b[12]_PORT_A_data_in = H1_wdata_ram_12;
Q1_q_b[12]_PORT_A_data_in_reg = DFFE(Q1_q_b[12]_PORT_A_data_in, Q1_q_b[12]_clock_0, , , );
Q1_q_b[12]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[12]_PORT_A_address_reg = DFFE(Q1_q_b[12]_PORT_A_address, Q1_q_b[12]_clock_0, , , );
Q1_q_b[12]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[12]_PORT_B_address_reg = DFFE(Q1_q_b[12]_PORT_B_address, Q1_q_b[12]_clock_1, , , );
Q1_q_b[12]_PORT_A_write_enable = H1_sm;
Q1_q_b[12]_PORT_A_write_enable_reg = DFFE(Q1_q_b[12]_PORT_A_write_enable, Q1_q_b[12]_clock_0, , , );
Q1_q_b[12]_PORT_B_read_enable = VCC;
Q1_q_b[12]_PORT_B_read_enable_reg = DFFE(Q1_q_b[12]_PORT_B_read_enable, Q1_q_b[12]_clock_1, , , );
Q1_q_b[12]_clock_0 = U1__clk1;
Q1_q_b[12]_clock_1 = U1__clk1;
Q1_q_b[12]_PORT_B_data_out = MEMORY(Q1_q_b[12]_PORT_A_data_in_reg, , Q1_q_b[12]_PORT_A_address_reg, Q1_q_b[12]_PORT_B_address_reg, Q1_q_b[12]_PORT_A_write_enable_reg, Q1_q_b[12]_PORT_B_read_enable_reg, , , Q1_q_b[12]_clock_0, Q1_q_b[12]_clock_1, , , , );
Q1_q_b[12]_PORT_B_data_out_reg = DFFE(Q1_q_b[12]_PORT_B_data_out, Q1_q_b[12]_clock_1, , , );
Q1_q_b[28] = Q1_q_b[12]_PORT_B_data_out_reg[1];


--Q1_q_b[13] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[13]
Q1_q_b[13]_PORT_A_data_in = H1_PAADC_MuxA_0;
Q1_q_b[13]_PORT_A_data_in_reg = DFFE(Q1_q_b[13]_PORT_A_data_in, Q1_q_b[13]_clock_0, , , );
Q1_q_b[13]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[13]_PORT_A_address_reg = DFFE(Q1_q_b[13]_PORT_A_address, Q1_q_b[13]_clock_0, , , );
Q1_q_b[13]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[13]_PORT_B_address_reg = DFFE(Q1_q_b[13]_PORT_B_address, Q1_q_b[13]_clock_1, , , );
Q1_q_b[13]_PORT_A_write_enable = H1_sm;
Q1_q_b[13]_PORT_A_write_enable_reg = DFFE(Q1_q_b[13]_PORT_A_write_enable, Q1_q_b[13]_clock_0, , , );
Q1_q_b[13]_PORT_B_read_enable = VCC;
Q1_q_b[13]_PORT_B_read_enable_reg = DFFE(Q1_q_b[13]_PORT_B_read_enable, Q1_q_b[13]_clock_1, , , );
Q1_q_b[13]_clock_0 = U1__clk1;
Q1_q_b[13]_clock_1 = U1__clk1;
Q1_q_b[13]_PORT_B_data_out = MEMORY(Q1_q_b[13]_PORT_A_data_in_reg, , Q1_q_b[13]_PORT_A_address_reg, Q1_q_b[13]_PORT_B_address_reg, Q1_q_b[13]_PORT_A_write_enable_reg, Q1_q_b[13]_PORT_B_read_enable_reg, , , Q1_q_b[13]_clock_0, Q1_q_b[13]_clock_1, , , , );
Q1_q_b[13]_PORT_B_data_out_reg = DFFE(Q1_q_b[13]_PORT_B_data_out, Q1_q_b[13]_clock_1, , , );
Q1_q_b[13] = Q1_q_b[13]_PORT_B_data_out_reg[0];

--Q1_q_b[29] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[29]
Q1_q_b[13]_PORT_A_data_in = H1_PAADC_MuxA_0;
Q1_q_b[13]_PORT_A_data_in_reg = DFFE(Q1_q_b[13]_PORT_A_data_in, Q1_q_b[13]_clock_0, , , );
Q1_q_b[13]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[13]_PORT_A_address_reg = DFFE(Q1_q_b[13]_PORT_A_address, Q1_q_b[13]_clock_0, , , );
Q1_q_b[13]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[13]_PORT_B_address_reg = DFFE(Q1_q_b[13]_PORT_B_address, Q1_q_b[13]_clock_1, , , );
Q1_q_b[13]_PORT_A_write_enable = H1_sm;
Q1_q_b[13]_PORT_A_write_enable_reg = DFFE(Q1_q_b[13]_PORT_A_write_enable, Q1_q_b[13]_clock_0, , , );
Q1_q_b[13]_PORT_B_read_enable = VCC;
Q1_q_b[13]_PORT_B_read_enable_reg = DFFE(Q1_q_b[13]_PORT_B_read_enable, Q1_q_b[13]_clock_1, , , );
Q1_q_b[13]_clock_0 = U1__clk1;
Q1_q_b[13]_clock_1 = U1__clk1;
Q1_q_b[13]_PORT_B_data_out = MEMORY(Q1_q_b[13]_PORT_A_data_in_reg, , Q1_q_b[13]_PORT_A_address_reg, Q1_q_b[13]_PORT_B_address_reg, Q1_q_b[13]_PORT_A_write_enable_reg, Q1_q_b[13]_PORT_B_read_enable_reg, , , Q1_q_b[13]_clock_0, Q1_q_b[13]_clock_1, , , , );
Q1_q_b[13]_PORT_B_data_out_reg = DFFE(Q1_q_b[13]_PORT_B_data_out, Q1_q_b[13]_clock_1, , , );
Q1_q_b[29] = Q1_q_b[13]_PORT_B_data_out_reg[1];


--Q1_q_b[14] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[14]
Q1_q_b[14]_PORT_A_data_in = H1_PAADC_MuxA_1;
Q1_q_b[14]_PORT_A_data_in_reg = DFFE(Q1_q_b[14]_PORT_A_data_in, Q1_q_b[14]_clock_0, , , );
Q1_q_b[14]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[14]_PORT_A_address_reg = DFFE(Q1_q_b[14]_PORT_A_address, Q1_q_b[14]_clock_0, , , );
Q1_q_b[14]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[14]_PORT_B_address_reg = DFFE(Q1_q_b[14]_PORT_B_address, Q1_q_b[14]_clock_1, , , );
Q1_q_b[14]_PORT_A_write_enable = H1_sm;
Q1_q_b[14]_PORT_A_write_enable_reg = DFFE(Q1_q_b[14]_PORT_A_write_enable, Q1_q_b[14]_clock_0, , , );
Q1_q_b[14]_PORT_B_read_enable = VCC;
Q1_q_b[14]_PORT_B_read_enable_reg = DFFE(Q1_q_b[14]_PORT_B_read_enable, Q1_q_b[14]_clock_1, , , );
Q1_q_b[14]_clock_0 = U1__clk1;
Q1_q_b[14]_clock_1 = U1__clk1;
Q1_q_b[14]_PORT_B_data_out = MEMORY(Q1_q_b[14]_PORT_A_data_in_reg, , Q1_q_b[14]_PORT_A_address_reg, Q1_q_b[14]_PORT_B_address_reg, Q1_q_b[14]_PORT_A_write_enable_reg, Q1_q_b[14]_PORT_B_read_enable_reg, , , Q1_q_b[14]_clock_0, Q1_q_b[14]_clock_1, , , , );
Q1_q_b[14]_PORT_B_data_out_reg = DFFE(Q1_q_b[14]_PORT_B_data_out, Q1_q_b[14]_clock_1, , , );
Q1_q_b[14] = Q1_q_b[14]_PORT_B_data_out_reg[0];

--Q1_q_b[30] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[30]
Q1_q_b[14]_PORT_A_data_in = H1_PAADC_MuxA_1;
Q1_q_b[14]_PORT_A_data_in_reg = DFFE(Q1_q_b[14]_PORT_A_data_in, Q1_q_b[14]_clock_0, , , );
Q1_q_b[14]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[14]_PORT_A_address_reg = DFFE(Q1_q_b[14]_PORT_A_address, Q1_q_b[14]_clock_0, , , );
Q1_q_b[14]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[14]_PORT_B_address_reg = DFFE(Q1_q_b[14]_PORT_B_address, Q1_q_b[14]_clock_1, , , );
Q1_q_b[14]_PORT_A_write_enable = H1_sm;
Q1_q_b[14]_PORT_A_write_enable_reg = DFFE(Q1_q_b[14]_PORT_A_write_enable, Q1_q_b[14]_clock_0, , , );
Q1_q_b[14]_PORT_B_read_enable = VCC;
Q1_q_b[14]_PORT_B_read_enable_reg = DFFE(Q1_q_b[14]_PORT_B_read_enable, Q1_q_b[14]_clock_1, , , );
Q1_q_b[14]_clock_0 = U1__clk1;
Q1_q_b[14]_clock_1 = U1__clk1;
Q1_q_b[14]_PORT_B_data_out = MEMORY(Q1_q_b[14]_PORT_A_data_in_reg, , Q1_q_b[14]_PORT_A_address_reg, Q1_q_b[14]_PORT_B_address_reg, Q1_q_b[14]_PORT_A_write_enable_reg, Q1_q_b[14]_PORT_B_read_enable_reg, , , Q1_q_b[14]_clock_0, Q1_q_b[14]_clock_1, , , , );
Q1_q_b[14]_PORT_B_data_out_reg = DFFE(Q1_q_b[14]_PORT_B_data_out, Q1_q_b[14]_clock_1, , , );
Q1_q_b[30] = Q1_q_b[14]_PORT_B_data_out_reg[1];


--Q1_q_b[15] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[15]
Q1_q_b[15]_PORT_A_data_in = ~GND;
Q1_q_b[15]_PORT_A_data_in_reg = DFFE(Q1_q_b[15]_PORT_A_data_in, Q1_q_b[15]_clock_0, , , );
Q1_q_b[15]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[15]_PORT_A_address_reg = DFFE(Q1_q_b[15]_PORT_A_address, Q1_q_b[15]_clock_0, , , );
Q1_q_b[15]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[15]_PORT_B_address_reg = DFFE(Q1_q_b[15]_PORT_B_address, Q1_q_b[15]_clock_1, , , );
Q1_q_b[15]_PORT_A_write_enable = H1_sm;
Q1_q_b[15]_PORT_A_write_enable_reg = DFFE(Q1_q_b[15]_PORT_A_write_enable, Q1_q_b[15]_clock_0, , , );
Q1_q_b[15]_PORT_B_read_enable = VCC;
Q1_q_b[15]_PORT_B_read_enable_reg = DFFE(Q1_q_b[15]_PORT_B_read_enable, Q1_q_b[15]_clock_1, , , );
Q1_q_b[15]_clock_0 = U1__clk1;
Q1_q_b[15]_clock_1 = U1__clk1;
Q1_q_b[15]_PORT_B_data_out = MEMORY(Q1_q_b[15]_PORT_A_data_in_reg, , Q1_q_b[15]_PORT_A_address_reg, Q1_q_b[15]_PORT_B_address_reg, Q1_q_b[15]_PORT_A_write_enable_reg, Q1_q_b[15]_PORT_B_read_enable_reg, , , Q1_q_b[15]_clock_0, Q1_q_b[15]_clock_1, , , , );
Q1_q_b[15]_PORT_B_data_out_reg = DFFE(Q1_q_b[15]_PORT_B_data_out, Q1_q_b[15]_clock_1, , , );
Q1_q_b[15] = Q1_q_b[15]_PORT_B_data_out_reg[0];

--Q1_q_b[31] is ADC_DAC_0:adcdac|pasaadc:padc|pasaadc_ram:adcram|altsyncram:altsyncram_component|altsyncram_0c21:auto_generated|q_b[31]
Q1_q_b[15]_PORT_A_data_in = ~GND;
Q1_q_b[15]_PORT_A_data_in_reg = DFFE(Q1_q_b[15]_PORT_A_data_in, Q1_q_b[15]_clock_0, , , );
Q1_q_b[15]_PORT_A_address = BUS(H1_samples_0, H1_samples_1, H1_samples_2, H1_samples_3, H1_samples_4, H1_samples_5, H1_samples_6, H1_samples_7, H1_samples_8, H1_samples_9);
Q1_q_b[15]_PORT_A_address_reg = DFFE(Q1_q_b[15]_PORT_A_address, Q1_q_b[15]_clock_0, , , );
Q1_q_b[15]_PORT_B_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44, X1_request_43, X1_request_42, X1_request_41, X1_request_40);
Q1_q_b[15]_PORT_B_address_reg = DFFE(Q1_q_b[15]_PORT_B_address, Q1_q_b[15]_clock_1, , , );
Q1_q_b[15]_PORT_A_write_enable = H1_sm;
Q1_q_b[15]_PORT_A_write_enable_reg = DFFE(Q1_q_b[15]_PORT_A_write_enable, Q1_q_b[15]_clock_0, , , );
Q1_q_b[15]_PORT_B_read_enable = VCC;
Q1_q_b[15]_PORT_B_read_enable_reg = DFFE(Q1_q_b[15]_PORT_B_read_enable, Q1_q_b[15]_clock_1, , , );
Q1_q_b[15]_clock_0 = U1__clk1;
Q1_q_b[15]_clock_1 = U1__clk1;
Q1_q_b[15]_PORT_B_data_out = MEMORY(Q1_q_b[15]_PORT_A_data_in_reg, , Q1_q_b[15]_PORT_A_address_reg, Q1_q_b[15]_PORT_B_address_reg, Q1_q_b[15]_PORT_A_write_enable_reg, Q1_q_b[15]_PORT_B_read_enable_reg, , , Q1_q_b[15]_clock_0, Q1_q_b[15]_clock_1, , , , );
Q1_q_b[15]_PORT_B_data_out_reg = DFFE(Q1_q_b[15]_PORT_B_data_out, Q1_q_b[15]_clock_1, , , );
Q1_q_b[31] = Q1_q_b[15]_PORT_B_data_out_reg[1];


--G1_ix0_nx20 is ADC_DAC_0:adcdac|gio_devices_adc:gio|ix0_nx20
--operation mode is normal

G1_ix0_nx20_lut_out = V1_bus_req;
G1_ix0_nx20 = DFFEA(G1_ix0_nx20_lut_out, U1__clk1, VCC, , , , );


--G1_ix0_nx22 is ADC_DAC_0:adcdac|gio_devices_adc:gio|ix0_nx22
--operation mode is normal

G1_ix0_nx22_regcasc_in = G1_ix0_nx20;
G1_ix0_nx22 = DFFEA(G1_ix0_nx22_regcasc_in, U1__clk1, VCC, , , , );


--G1_ix0_nx24 is ADC_DAC_0:adcdac|gio_devices_adc:gio|ix0_nx24
--operation mode is normal

G1_ix0_nx24_regcasc_in = G1_ix0_nx22;
G1_ix0_nx24 = DFFEA(G1_ix0_nx24_regcasc_in, U1__clk1, VCC, , , , );


--G1_bus_ack is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_ack
--operation mode is normal

G1_bus_ack_regcasc_in = G1_ix0_nx24;
G1_bus_ack = DFFEA(G1_bus_ack_regcasc_in, U1__clk1, VCC, , , , );


--G1_modgen_eq_3_nx22 is ADC_DAC_0:adcdac|gio_devices_adc:gio|modgen_eq_3_nx22
--operation mode is normal

G1_modgen_eq_3_nx22 = X1_request_39 # X1_request_40;


--G1_modgen_eq_3_nx30 is ADC_DAC_0:adcdac|gio_devices_adc:gio|modgen_eq_3_nx30
--operation mode is normal

G1_modgen_eq_3_nx30 = X1_request_35 # X1_request_37 # X1_request_38 # !X1_request_36;


--G1_nx151 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx151
--operation mode is normal

G1_nx151 = !X1_request_33 & X1_request_34 & !X1_request_35 & X1_request_36;


--G1_nx152 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx152
--operation mode is normal

G1_nx152 = B1_VMCM_Shdwn_d & (G1_ce_psply_adc # H1_RDATA_31 & G1_ce_pasa_adc) # !B1_VMCM_Shdwn_d & H1_RDATA_31 & G1_ce_pasa_adc;


--G1_nx153 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx153
--operation mode is normal

G1_nx153 = B1_VMCM_Shdwn_a & (G1_ce_psply_adc # H1_RDATA_30 & G1_ce_pasa_adc) # !B1_VMCM_Shdwn_a & H1_RDATA_30 & G1_ce_pasa_adc;


--G1_nx154 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx154
--operation mode is normal

G1_nx154 = H1_RDATA_28 & (G1_ce_pasa_adc # J1_RDATA_28 & G1_ce_pasa_dac) # !H1_RDATA_28 & J1_RDATA_28 & G1_ce_pasa_dac;


--G1_nx155 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx155
--operation mode is normal

G1_nx155 = H1_RDATA_27 & (G1_ce_pasa_adc # J1_RDATA_27 & G1_ce_pasa_dac) # !H1_RDATA_27 & J1_RDATA_27 & G1_ce_pasa_dac;


--G1_nx156 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx156
--operation mode is normal

G1_nx156 = H1_RDATA_26 & (G1_ce_pasa_adc # J1_RDATA_26 & G1_ce_pasa_dac) # !H1_RDATA_26 & J1_RDATA_26 & G1_ce_pasa_dac;


--G1_nx157 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx157
--operation mode is normal

G1_nx157 = H1_RDATA_25 & (G1_ce_pasa_adc # J1_RDATA_25 & G1_ce_pasa_dac) # !H1_RDATA_25 & J1_RDATA_25 & G1_ce_pasa_dac;


--G1_nx158 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx158
--operation mode is normal

G1_nx158 = H1_RDATA_24 & (G1_ce_pasa_adc # J1_RDATA_24 & G1_ce_pasa_dac) # !H1_RDATA_24 & J1_RDATA_24 & G1_ce_pasa_dac;


--G1_nx159 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx159
--operation mode is normal

G1_nx159 = L1_RDATA_23 & (G1_ce_sc_adc # K1_RDATA_23 & G1_ce_psply_adc) # !L1_RDATA_23 & K1_RDATA_23 & G1_ce_psply_adc;


--G1_nx160 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx160
--operation mode is normal

G1_nx160 = H1_RDATA_23 & (G1_ce_pasa_adc # J1_RDATA_23 & G1_ce_pasa_dac) # !H1_RDATA_23 & J1_RDATA_23 & G1_ce_pasa_dac;


--G1_nx161 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx161
--operation mode is normal

G1_nx161 = L1_RDATA_22 & (G1_ce_sc_adc # K1_RDATA_22 & G1_ce_psply_adc) # !L1_RDATA_22 & K1_RDATA_22 & G1_ce_psply_adc;


--G1_nx162 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx162
--operation mode is normal

G1_nx162 = H1_RDATA_22 & (G1_ce_pasa_adc # J1_RDATA_22 & G1_ce_pasa_dac) # !H1_RDATA_22 & J1_RDATA_22 & G1_ce_pasa_dac;


--G1_nx163 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx163
--operation mode is normal

G1_nx163 = L1_RDATA_21 & (G1_ce_sc_adc # K1_RDATA_21 & G1_ce_psply_adc) # !L1_RDATA_21 & K1_RDATA_21 & G1_ce_psply_adc;


--G1_nx164 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx164
--operation mode is normal

G1_nx164 = H1_RDATA_21 & (G1_ce_pasa_adc # J1_RDATA_21 & G1_ce_pasa_dac) # !H1_RDATA_21 & J1_RDATA_21 & G1_ce_pasa_dac;


--G1_nx165 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx165
--operation mode is normal

G1_nx165 = L1_RDATA_20 & (G1_ce_sc_adc # K1_RDATA_20 & G1_ce_psply_adc) # !L1_RDATA_20 & K1_RDATA_20 & G1_ce_psply_adc;


--G1_nx166 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx166
--operation mode is normal

G1_nx166 = H1_RDATA_20 & (G1_ce_pasa_adc # J1_RDATA_20 & G1_ce_pasa_dac) # !H1_RDATA_20 & J1_RDATA_20 & G1_ce_pasa_dac;


--G1_nx167 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx167
--operation mode is normal

G1_nx167 = K1_RDATA_19 & (G1_ce_psply_adc # H1_RDATA_19 & G1_ce_pasa_adc) # !K1_RDATA_19 & H1_RDATA_19 & G1_ce_pasa_adc;


--G1_nx168 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx168
--operation mode is normal

G1_nx168 = K1_RDATA_18 & (G1_ce_psply_adc # H1_RDATA_18 & G1_ce_pasa_adc) # !K1_RDATA_18 & H1_RDATA_18 & G1_ce_pasa_adc;


--G1_nx169 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx169
--operation mode is normal

G1_nx169 = K1_RDATA_17 & (G1_ce_psply_adc # H1_RDATA_17 & G1_ce_pasa_adc) # !K1_RDATA_17 & H1_RDATA_17 & G1_ce_pasa_adc;


--G1_nx170 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx170
--operation mode is normal

G1_nx170 = L1_RDATA_16 & (G1_ce_sc_adc # K1_RDATA_16 & G1_ce_psply_adc) # !L1_RDATA_16 & K1_RDATA_16 & G1_ce_psply_adc;


--G1_nx171 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx171
--operation mode is normal

G1_nx171 = H1_RDATA_16 & (G1_ce_pasa_adc # J1_RDATA_16 & G1_ce_pasa_dac) # !H1_RDATA_16 & J1_RDATA_16 & G1_ce_pasa_dac;


--G1_nx172 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx172
--operation mode is normal

G1_nx172 = K1_RDATA_15 & (G1_ce_psply_adc # H1_RDATA_15 & G1_ce_pasa_adc) # !K1_RDATA_15 & H1_RDATA_15 & G1_ce_pasa_adc;


--G1_nx173 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx173
--operation mode is normal

G1_nx173 = K1_RDATA_14 & (G1_ce_psply_adc # H1_RDATA_14 & G1_ce_pasa_adc) # !K1_RDATA_14 & H1_RDATA_14 & G1_ce_pasa_adc;


--G1_nx174 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx174
--operation mode is normal

G1_nx174 = L1_RDATA_13 & (G1_ce_sc_adc # K1_RDATA_13 & G1_ce_psply_adc) # !L1_RDATA_13 & K1_RDATA_13 & G1_ce_psply_adc;


--G1_nx175 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx175
--operation mode is normal

G1_nx175 = H1_RDATA_13 & (G1_ce_pasa_adc # J1_RDATA_13 & G1_ce_pasa_dac) # !H1_RDATA_13 & J1_RDATA_13 & G1_ce_pasa_dac;


--G1_nx176 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx176
--operation mode is normal

G1_nx176 = L1_RDATA_12 & (G1_ce_sc_adc # K1_RDATA_12 & G1_ce_psply_adc) # !L1_RDATA_12 & K1_RDATA_12 & G1_ce_psply_adc;


--G1_nx177 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx177
--operation mode is normal

G1_nx177 = H1_RDATA_12 & (G1_ce_pasa_adc # J1_RDATA_12 & G1_ce_pasa_dac) # !H1_RDATA_12 & J1_RDATA_12 & G1_ce_pasa_dac;


--G1_nx178 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx178
--operation mode is normal

G1_nx178 = L1_RDATA_11 & (G1_ce_sc_adc # K1_RDATA_11 & G1_ce_psply_adc) # !L1_RDATA_11 & K1_RDATA_11 & G1_ce_psply_adc;


--G1_nx179 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx179
--operation mode is normal

G1_nx179 = H1_RDATA_11 & (G1_ce_pasa_adc # J1_RDATA_11 & G1_ce_pasa_dac) # !H1_RDATA_11 & J1_RDATA_11 & G1_ce_pasa_dac;


--G1_nx180 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx180
--operation mode is normal

G1_nx180 = L1_RDATA_10 & (G1_ce_sc_adc # K1_RDATA_10 & G1_ce_psply_adc) # !L1_RDATA_10 & K1_RDATA_10 & G1_ce_psply_adc;


--G1_nx181 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx181
--operation mode is normal

G1_nx181 = H1_RDATA_10 & (G1_ce_pasa_adc # J1_RDATA_10 & G1_ce_pasa_dac) # !H1_RDATA_10 & J1_RDATA_10 & G1_ce_pasa_dac;


--G1_nx182 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx182
--operation mode is normal

G1_nx182 = L1_RDATA_9 & (G1_ce_sc_adc # K1_RDATA_9 & G1_ce_psply_adc) # !L1_RDATA_9 & K1_RDATA_9 & G1_ce_psply_adc;


--G1_nx183 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx183
--operation mode is normal

G1_nx183 = H1_RDATA_9 & (G1_ce_pasa_adc # J1_RDATA_9 & G1_ce_pasa_dac) # !H1_RDATA_9 & J1_RDATA_9 & G1_ce_pasa_dac;


--G1_nx184 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx184
--operation mode is normal

G1_nx184 = L1_RDATA_8 & (G1_ce_sc_adc # K1_RDATA_8 & G1_ce_psply_adc) # !L1_RDATA_8 & K1_RDATA_8 & G1_ce_psply_adc;


--G1_nx185 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx185
--operation mode is normal

G1_nx185 = H1_RDATA_8 & (G1_ce_pasa_adc # J1_RDATA_8 & G1_ce_pasa_dac) # !H1_RDATA_8 & J1_RDATA_8 & G1_ce_pasa_dac;


--G1_nx186 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx186
--operation mode is normal

G1_nx186 = L1_RDATA_7 & (G1_ce_sc_adc # K1_RDATA_7 & G1_ce_psply_adc) # !L1_RDATA_7 & K1_RDATA_7 & G1_ce_psply_adc;


--G1_nx187 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx187
--operation mode is normal

G1_nx187 = H1_RDATA_7 & (G1_ce_pasa_adc # J1_RDATA_7 & G1_ce_pasa_dac) # !H1_RDATA_7 & J1_RDATA_7 & G1_ce_pasa_dac;


--G1_nx188 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx188
--operation mode is normal

G1_nx188 = L1_RDATA_6 & (G1_ce_sc_adc # K1_RDATA_6 & G1_ce_psply_adc) # !L1_RDATA_6 & K1_RDATA_6 & G1_ce_psply_adc;


--G1_nx189 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx189
--operation mode is normal

G1_nx189 = H1_RDATA_6 & (G1_ce_pasa_adc # J1_RDATA_6 & G1_ce_pasa_dac) # !H1_RDATA_6 & J1_RDATA_6 & G1_ce_pasa_dac;


--G1_nx190 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx190
--operation mode is normal

G1_nx190 = L1_RDATA_5 & (G1_ce_sc_adc # K1_RDATA_5 & G1_ce_psply_adc) # !L1_RDATA_5 & K1_RDATA_5 & G1_ce_psply_adc;


--G1_nx191 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx191
--operation mode is normal

G1_nx191 = H1_RDATA_5 & (G1_ce_pasa_adc # J1_RDATA_5 & G1_ce_pasa_dac) # !H1_RDATA_5 & J1_RDATA_5 & G1_ce_pasa_dac;


--G1_nx192 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx192
--operation mode is normal

G1_nx192 = L1_RDATA_4 & (G1_ce_sc_adc # K1_RDATA_4 & G1_ce_psply_adc) # !L1_RDATA_4 & K1_RDATA_4 & G1_ce_psply_adc;


--G1_nx193 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx193
--operation mode is normal

G1_nx193 = H1_RDATA_4 & (G1_ce_pasa_adc # J1_RDATA_4 & G1_ce_pasa_dac) # !H1_RDATA_4 & J1_RDATA_4 & G1_ce_pasa_dac;


--G1_nx194 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx194
--operation mode is normal

G1_nx194 = L1_RDATA_3 & (G1_ce_sc_adc # K1_RDATA_3 & G1_ce_psply_adc) # !L1_RDATA_3 & K1_RDATA_3 & G1_ce_psply_adc;


--G1_nx195 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx195
--operation mode is normal

G1_nx195 = H1_RDATA_3 & (G1_ce_pasa_adc # J1_RDATA_3 & G1_ce_pasa_dac) # !H1_RDATA_3 & J1_RDATA_3 & G1_ce_pasa_dac;


--G1_nx196 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx196
--operation mode is normal

G1_nx196 = L1_RDATA_2 & (G1_ce_sc_adc # K1_RDATA_2 & G1_ce_psply_adc) # !L1_RDATA_2 & K1_RDATA_2 & G1_ce_psply_adc;


--G1_nx197 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx197
--operation mode is normal

G1_nx197 = H1_RDATA_2 & (G1_ce_pasa_adc # J1_RDATA_2 & G1_ce_pasa_dac) # !H1_RDATA_2 & J1_RDATA_2 & G1_ce_pasa_dac;


--G1_nx198 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx198
--operation mode is normal

G1_nx198 = L1_RDATA_1 & (G1_ce_sc_adc # K1_RDATA_1 & G1_ce_psply_adc) # !L1_RDATA_1 & K1_RDATA_1 & G1_ce_psply_adc;


--G1_nx199 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx199
--operation mode is normal

G1_nx199 = H1_RDATA_1 & (G1_ce_pasa_adc # J1_RDATA_1 & G1_ce_pasa_dac) # !H1_RDATA_1 & J1_RDATA_1 & G1_ce_pasa_dac;


--G1_nx200 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx200
--operation mode is normal

G1_nx200 = L1_RDATA_0 & (G1_ce_sc_adc # K1_RDATA_0 & G1_ce_psply_adc) # !L1_RDATA_0 & K1_RDATA_0 & G1_ce_psply_adc;


--G1_nx201 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx201
--operation mode is normal

G1_nx201 = H1_RDATA_0 & (G1_ce_pasa_adc # J1_RDATA_0 & G1_ce_pasa_dac) # !H1_RDATA_0 & J1_RDATA_0 & G1_ce_pasa_dac;


--G1_nx202 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx202
--operation mode is normal

G1_nx202 = L1_RDATA_14 & G1_ce_sc_adc;


--G1_nx203 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx203
--operation mode is normal

G1_nx203 = L1_RDATA_15 & G1_ce_sc_adc;


--G1_nx204 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx204
--operation mode is normal

G1_nx204 = L1_RDATA_17 & G1_ce_sc_adc;


--G1_nx205 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx205
--operation mode is normal

G1_nx205 = L1_RDATA_18 & G1_ce_sc_adc;


--G1_nx206 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx206
--operation mode is normal

G1_nx206 = L1_RDATA_19 & G1_ce_sc_adc;


--G1_nx207 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx207
--operation mode is normal

G1_nx207 = !X1_request_39 & X1_request_40;


--G1_nx208 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx208
--operation mode is normal

G1_nx208 = !X1_request_33 & X1_request_34 & !G1_modgen_eq_3_nx22 & !G1_modgen_eq_3_nx30;


--G1_nx209 is ADC_DAC_0:adcdac|gio_devices_adc:gio|nx209
--operation mode is normal

G1_nx209 = !X1_request_33 & X1_request_34;


--G1_bus_dout_31 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_31
--operation mode is normal

G1_bus_dout_31 = G1_nx152 # E1_RDATA_31 & G1_ce_dds;


--G1_bus_dout_30 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_30
--operation mode is normal

G1_bus_dout_30 = G1_nx153 # E1_RDATA_30 & G1_ce_dds;


--G1_bus_dout_29 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_29
--operation mode is normal

G1_bus_dout_29 = E1_RDATA_29 & (G1_ce_dds # H1_RDATA_29 & G1_ce_pasa_adc) # !E1_RDATA_29 & H1_RDATA_29 & G1_ce_pasa_adc;


--G1_bus_dout_28 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_28
--operation mode is normal

G1_bus_dout_28 = G1_nx154 # E1_RDATA_28 & G1_ce_dds;


--G1_bus_dout_27 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_27
--operation mode is normal

G1_bus_dout_27 = G1_nx155 # E1_RDATA_27 & G1_ce_dds;


--G1_bus_dout_26 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_26
--operation mode is normal

G1_bus_dout_26 = G1_nx156 # E1_RDATA_26 & G1_ce_dds;


--G1_bus_dout_25 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_25
--operation mode is normal

G1_bus_dout_25 = G1_nx157 # E1_RDATA_25 & G1_ce_dds;


--G1_bus_dout_24 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_24
--operation mode is normal

G1_bus_dout_24 = G1_nx158 # E1_RDATA_24 & G1_ce_dds;


--G1_bus_dout_23 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_23
--operation mode is normal

G1_bus_dout_23 = G1_nx159 # G1_nx160 # E1_RDATA_23 & G1_ce_dds;


--G1_bus_dout_22 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_22
--operation mode is normal

G1_bus_dout_22 = G1_nx161 # G1_nx162 # E1_RDATA_22 & G1_ce_dds;


--G1_bus_dout_21 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_21
--operation mode is normal

G1_bus_dout_21 = G1_nx163 # G1_nx164 # E1_RDATA_21 & G1_ce_dds;


--G1_bus_dout_20 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_20
--operation mode is normal

G1_bus_dout_20 = G1_nx165 # G1_nx166 # E1_RDATA_20 & G1_ce_dds;


--G1_bus_dout_19 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_19
--operation mode is normal

G1_bus_dout_19 = G1_nx167 # G1_nx206 # E1_RDATA_19 & G1_ce_dds;


--G1_bus_dout_18 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_18
--operation mode is normal

G1_bus_dout_18 = G1_nx168 # G1_nx205 # E1_RDATA_18 & G1_ce_dds;


--G1_bus_dout_17 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_17
--operation mode is normal

G1_bus_dout_17 = G1_nx169 # G1_nx204 # E1_RDATA_17 & G1_ce_dds;


--G1_bus_dout_16 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_16
--operation mode is normal

G1_bus_dout_16 = G1_nx170 # G1_nx171 # E1_RDATA_16 & G1_ce_dds;


--G1_bus_dout_15 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_15
--operation mode is normal

G1_bus_dout_15 = G1_nx172 # G1_nx203 # E1_RDATA_15 & G1_ce_dds;


--G1_bus_dout_14 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_14
--operation mode is normal

G1_bus_dout_14 = G1_nx173 # G1_nx202 # E1_RDATA_14 & G1_ce_dds;


--G1_bus_dout_13 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_13
--operation mode is normal

G1_bus_dout_13 = G1_nx174 # G1_nx175 # E1_RDATA_13 & G1_ce_dds;


--G1_bus_dout_12 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_12
--operation mode is normal

G1_bus_dout_12 = G1_nx176 # G1_nx177 # E1_RDATA_12 & G1_ce_dds;


--G1_bus_dout_11 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_11
--operation mode is normal

G1_bus_dout_11 = G1_nx178 # G1_nx179 # E1_RDATA_11 & G1_ce_dds;


--G1_bus_dout_10 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_10
--operation mode is normal

G1_bus_dout_10 = G1_nx180 # G1_nx181 # E1_RDATA_10 & G1_ce_dds;


--G1_bus_dout_9 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_9
--operation mode is normal

G1_bus_dout_9 = G1_nx182 # G1_nx183 # E1_RDATA_9 & G1_ce_dds;


--G1_bus_dout_8 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_8
--operation mode is normal

G1_bus_dout_8 = G1_nx184 # G1_nx185 # E1_RDATA_8 & G1_ce_dds;


--G1_bus_dout_7 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_7
--operation mode is normal

G1_bus_dout_7 = G1_nx186 # G1_nx187 # E1_RDATA_7 & G1_ce_dds;


--G1_bus_dout_6 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_6
--operation mode is normal

G1_bus_dout_6 = G1_nx188 # G1_nx189 # E1_RDATA_6 & G1_ce_dds;


--G1_bus_dout_5 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_5
--operation mode is normal

G1_bus_dout_5 = G1_nx190 # G1_nx191 # E1_RDATA_5 & G1_ce_dds;


--G1_bus_dout_4 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_4
--operation mode is normal

G1_bus_dout_4 = G1_nx192 # G1_nx193 # E1_RDATA_4 & G1_ce_dds;


--G1_bus_dout_3 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_3
--operation mode is normal

G1_bus_dout_3 = G1_nx194 # G1_nx195 # E1_RDATA_3 & G1_ce_dds;


--G1_bus_dout_2 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_2
--operation mode is normal

G1_bus_dout_2 = G1_nx196 # G1_nx197 # E1_RDATA_2 & G1_ce_dds;


--G1_bus_dout_1 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_1
--operation mode is normal

G1_bus_dout_1 = G1_nx198 # G1_nx199 # E1_RDATA_1 & G1_ce_dds;


--G1_bus_dout_0 is ADC_DAC_0:adcdac|gio_devices_adc:gio|bus_dout_0
--operation mode is normal

G1_bus_dout_0 = G1_nx200 # G1_nx201 # E1_RDATA_0 & G1_ce_dds;


--G1_ce_1sdac is ADC_DAC_0:adcdac|gio_devices_adc:gio|ce_1sdac
--operation mode is normal

G1_ce_1sdac_lut_out = !X1_request_41 & !X1_request_42 & G1_nx208;
G1_ce_1sdac_reg_input = V1_bus_req & G1_ce_1sdac_lut_out;
G1_ce_1sdac = DFFEA(G1_ce_1sdac_reg_input, U1__clk1, VCC, , , , );


--G1_ce_2sdac is ADC_DAC_0:adcdac|gio_devices_adc:gio|ce_2sdac
--operation mode is normal

G1_ce_2sdac_lut_out = !X1_request_33 & X1_request_34 & !G1_modgen_eq_3_nx30 & G1_nx207;
G1_ce_2sdac_reg_input = V1_bus_req & G1_ce_2sdac_lut_out;
G1_ce_2sdac = DFFEA(G1_ce_2sdac_reg_input, U1__clk1, VCC, , , , );


--G1_ce_digpot is ADC_DAC_0:adcdac|gio_devices_adc:gio|ce_digpot
--operation mode is normal

G1_ce_digpot_lut_out = X1_request_41 & X1_request_42 & G1_nx208;
G1_ce_digpot_reg_input = V1_bus_req & G1_ce_digpot_lut_out;
G1_ce_digpot = DFFEA(G1_ce_digpot_reg_input, U1__clk1, VCC, , , , );


--G1_ce_shutdn is ADC_DAC_0:adcdac|gio_devices_adc:gio|ce_shutdn
--operation mode is normal

G1_ce_shutdn_lut_out = X1_request_41 & !X1_request_42 & G1_nx208;
G1_ce_shutdn_reg_input = V1_bus_req & G1_ce_shutdn_lut_out;
G1_ce_shutdn = DFFEA(G1_ce_shutdn_reg_input, U1__clk1, VCC, , , , );


--G1_ce_pasa_dac is ADC_DAC_0:adcdac|gio_devices_adc:gio|ce_pasa_dac
--operation mode is normal

G1_ce_pasa_dac_lut_out = !X1_request_37 & X1_request_38 & G1_nx151 & G1_nx207;
G1_ce_pasa_dac_reg_input = V1_bus_req & G1_ce_pasa_dac_lut_out;
G1_ce_pasa_dac = DFFEA(G1_ce_pasa_dac_reg_input, U1__clk1, VCC, , , , );


--G1_ce_psply_adc is ADC_DAC_0:adcdac|gio_devices_adc:gio|ce_psply_adc
--operation mode is normal

G1_ce_psply_adc_lut_out = !X1_request_37 & X1_request_38 & !G1_modgen_eq_3_nx22 & G1_nx151;
G1_ce_psply_adc_reg_input = V1_bus_req & G1_ce_psply_adc_lut_out;
G1_ce_psply_adc = DFFEA(G1_ce_psply_adc_reg_input, U1__clk1, VCC, , , , );


--G1_ce_sc_adc is ADC_DAC_0:adcdac|gio_devices_adc:gio|ce_sc_adc
--operation mode is normal

G1_ce_sc_adc_lut_out = X1_request_39 & X1_request_40 & !G1_modgen_eq_3_nx30 & G1_nx209;
G1_ce_sc_adc_reg_input = V1_bus_req & G1_ce_sc_adc_lut_out;
G1_ce_sc_adc = DFFEA(G1_ce_sc_adc_reg_input, U1__clk1, VCC, , , , );


--G1_ce_dds is ADC_DAC_0:adcdac|gio_devices_adc:gio|ce_dds
--operation mode is normal

G1_ce_dds_lut_out = X1_request_39 & !X1_request_40 & !G1_modgen_eq_3_nx30 & G1_nx209;
G1_ce_dds_reg_input = V1_bus_req & G1_ce_dds_lut_out;
G1_ce_dds = DFFEA(G1_ce_dds_reg_input, U1__clk1, VCC, , , , );


--G1_ce_pasa_adc is ADC_DAC_0:adcdac|gio_devices_adc:gio|ce_pasa_adc
--operation mode is normal

G1_ce_pasa_adc_lut_out = X1_request_37 & G1_nx151;
G1_ce_pasa_adc_reg_input = V1_bus_req & G1_ce_pasa_adc_lut_out;
G1_ce_pasa_adc = DFFEA(G1_ce_pasa_adc_reg_input, U1__clk1, VCC, , , , );


--F4_B_5 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_5
--operation mode is arithmetic

F4_B_5_carry_eqn = F4_B_nx35;
F4_B_5_lut_out = F4_B_5 $ F4_B_5_carry_eqn;
F4_B_5 = DFFEA(F4_B_5_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_B_nx45 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_nx45
--operation mode is arithmetic

F4_B_nx45 = CARRY(F4_B_5 $ !F4_NOT_UDn # !F4_B_nx35);


--F4_B_4 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_4
--operation mode is arithmetic

F4_B_4_carry_eqn = F4_B_nx25;
F4_B_4_lut_out = F4_B_4 $ !F4_B_4_carry_eqn;
F4_B_4 = DFFEA(F4_B_4_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_B_nx35 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_nx35
--operation mode is arithmetic

F4_B_nx35 = CARRY(!F4_B_nx25 & (F4_B_4 $ F4_NOT_UDn));


--F4_B_3 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_3
--operation mode is arithmetic

F4_B_3_carry_eqn = F4_B_nx19;
F4_B_3_lut_out = F4_B_3 $ F4_B_3_carry_eqn;
F4_B_3 = DFFEA(F4_B_3_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_B_nx25 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_nx25
--operation mode is arithmetic

F4_B_nx25 = CARRY(F4_B_3 $ !F4_NOT_UDn # !F4_B_nx19);


--F4_B_2 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_2
--operation mode is arithmetic

F4_B_2_carry_eqn = F4_B_nx13;
F4_B_2_lut_out = F4_B_2 $ !F4_B_2_carry_eqn;
F4_B_2 = DFFEA(F4_B_2_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_B_nx19 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_nx19
--operation mode is arithmetic

F4_B_nx19 = CARRY(!F4_B_nx13 & (F4_B_2 $ F4_NOT_UDn));


--F4_B_1 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_1
--operation mode is arithmetic

F4_B_1_carry_eqn = F4_B_nx7;
F4_B_1_lut_out = F4_B_1 $ F4_B_1_carry_eqn;
F4_B_1 = DFFEA(F4_B_1_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_B_nx13 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_nx13
--operation mode is arithmetic

F4_B_nx13 = CARRY(F4_B_1 $ !F4_NOT_UDn # !F4_B_nx7);


--F4_B_0 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_0
--operation mode is arithmetic

F4_B_0_carry_eqn = F4_B_nx56;
F4_B_0_lut_out = F4_NOT_nx144 $ F4_B_0_carry_eqn;
F4_B_0 = DFFEA(F4_B_0_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_B_nx7 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_nx7
--operation mode is arithmetic

F4_B_nx7 = CARRY(F4_NOT_nx144 & (F4_NOT_UDn $ F4_B_nx56));


--F4_B_nx56 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_nx56
--operation mode is arithmetic

F4_B_nx56 = CARRY(F4_B_0);


--F4_B_6 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|B_6
--operation mode is normal

F4_B_6_carry_eqn = F4_B_nx45;
F4_B_6_lut_out = F4_B_6 $ !F4_B_6_carry_eqn;
F4_B_6 = DFFEA(F4_B_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--F4_cnt_4 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_4
--operation mode is arithmetic

F4_cnt_4_carry_eqn = F4_cnt_nx24;
F4_cnt_4_lut_out = F4_cnt_4 $ !F4_cnt_4_carry_eqn;
F4_cnt_4 = DFFEA(F4_cnt_4_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_cnt_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_nx28
--operation mode is arithmetic

F4_cnt_nx28 = CARRY(F4_cnt_4 & !F4_cnt_nx24);


--F4_cnt_3 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_3
--operation mode is arithmetic

F4_cnt_3_carry_eqn = F4_cnt_nx18;
F4_cnt_3_lut_out = F4_cnt_3 $ F4_cnt_3_carry_eqn;
F4_cnt_3 = DFFEA(F4_cnt_3_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_cnt_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_nx24
--operation mode is arithmetic

F4_cnt_nx24 = CARRY(!F4_cnt_nx18 # !F4_cnt_3);


--F4_cnt_2 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_2
--operation mode is arithmetic

F4_cnt_2_carry_eqn = F4_cnt_nx12;
F4_cnt_2_lut_out = F4_cnt_2 $ !F4_cnt_2_carry_eqn;
F4_cnt_2 = DFFEA(F4_cnt_2_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_cnt_nx18 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_nx18
--operation mode is arithmetic

F4_cnt_nx18 = CARRY(F4_cnt_2 & !F4_cnt_nx12);


--F4_cnt_1 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_1
--operation mode is arithmetic

F4_cnt_1_carry_eqn = F4_cnt_nx6;
F4_cnt_1_lut_out = F4_cnt_1 $ F4_cnt_1_carry_eqn;
F4_cnt_1 = DFFEA(F4_cnt_1_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_cnt_nx12 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_nx12
--operation mode is arithmetic

F4_cnt_nx12 = CARRY(!F4_cnt_nx6 # !F4_cnt_1);


--F4_cnt_0 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_0
--operation mode is arithmetic

F4_cnt_0_lut_out = !F4_cnt_0;
F4_cnt_0 = DFFEA(F4_cnt_0_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_cnt_nx6 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_nx6
--operation mode is arithmetic

F4_cnt_nx6 = CARRY(F4_cnt_0);


--F4_cnt_6 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_6
--operation mode is normal

F4_cnt_6_carry_eqn = F4_cnt_nx32;
F4_cnt_6_lut_out = F4_cnt_6 $ !F4_cnt_6_carry_eqn;
F4_cnt_6 = DFFEA(F4_cnt_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--F4_cnt_5 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_5
--operation mode is arithmetic

F4_cnt_5_carry_eqn = F4_cnt_nx28;
F4_cnt_5_lut_out = F4_cnt_5 $ F4_cnt_5_carry_eqn;
F4_cnt_5 = DFFEA(F4_cnt_5_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F4_cnt_nx32 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|cnt_nx32
--operation mode is arithmetic

F4_cnt_nx32 = CARRY(!F4_cnt_nx28 # !F4_cnt_5);


--F4_nx12 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx12
--operation mode is normal

F4_nx12 = !V1_rd_wr_oase & G1_ce_digpot & !X1_request_0;


--F4_nx65 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx65
--operation mode is normal

F4_nx65 = F4_cnt_6 & !F4_cnt_5 & !F4_cnt_0 & F4_nx572;


--F4_NOT_nx79 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|NOT_nx79
--operation mode is normal

F4_NOT_nx79 = F4_nx65 & (F4_nx66 # F4_nx68);


--F4_NOT_nx149 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|NOT_nx149
--operation mode is normal

F4_NOT_nx149 = !F4_nx571 & F4_nx572 & (F4_nx544 # !F4_cnt_6);


--F4_NOT_nx144 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|NOT_nx144
--operation mode is normal

F4_NOT_nx144 = F4_cnt_6 & F4_nx544 & !F4_nx571 & F4_nx572;


--F4_nx337 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx337
--operation mode is normal

F4_nx337 = F4_nx544 # !V1_rd_wr_oase & G1_ce_digpot & X1_request_0;


--F4_NOT_nx14 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|NOT_nx14
--operation mode is normal

F4_NOT_nx14 = X1_request_2 & X1_request_1 & F4_nx573;


--F4_nx571 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx571
--operation mode is normal

F4_nx571 = F4_cnt_0 # !F4_cnt_5;


--F4_nx572 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx572
--operation mode is normal

F4_nx572 = !F4_cnt_4 & !F4_cnt_3 & !F4_cnt_2 & !F4_cnt_1;


--F4_nx573 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx573
--operation mode is normal

F4_nx573 = X1_request_3 # X1_request_4 # X1_request_5;


--F4_modgen_gt_387_nx20 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_387_nx20
--operation mode is arithmetic

F4_modgen_gt_387_nx20 = CARRY(!F4_nx589 & !F4_B_0);


--F4_modgen_gt_387_nx22 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_387_nx22
--operation mode is arithmetic

F4_modgen_gt_387_nx22 = CARRY(F4_B_1 & (F4_nx584 # !F4_modgen_gt_387_nx20) # !F4_B_1 & F4_nx584 & !F4_modgen_gt_387_nx20);


--F4_modgen_gt_387_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_387_nx24
--operation mode is arithmetic

F4_modgen_gt_387_nx24 = CARRY(F4_B_2 & F4_a_2 & !F4_modgen_gt_387_nx22 # !F4_B_2 & (F4_a_2 # !F4_modgen_gt_387_nx22));


--F4_modgen_gt_387_nx26 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_387_nx26
--operation mode is arithmetic

F4_modgen_gt_387_nx26 = CARRY(F4_B_3 & (!F4_modgen_gt_387_nx24 # !F4_a_3) # !F4_B_3 & !F4_a_3 & !F4_modgen_gt_387_nx24);


--F4_modgen_gt_387_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_387_nx28
--operation mode is arithmetic

F4_modgen_gt_387_nx28 = CARRY(F4_B_4 & F4_a_4 & !F4_modgen_gt_387_nx26 # !F4_B_4 & (F4_a_4 # !F4_modgen_gt_387_nx26));


--F4_modgen_gt_387_nx30 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_387_nx30
--operation mode is arithmetic

F4_modgen_gt_387_nx30 = CARRY(F4_B_5 & (F4_nx579 # !F4_modgen_gt_387_nx28) # !F4_B_5 & F4_nx579 & !F4_modgen_gt_387_nx28);


--F4_nx66 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx66
--operation mode is normal

F4_nx66_carry_eqn = F4_modgen_gt_387_nx30;
F4_nx66 = F4_B_6 & !F4_nx574 & !F4_nx66_carry_eqn # !F4_B_6 & (!F4_nx66_carry_eqn # !F4_nx574);


--F4_modgen_gt_389_nx20 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_389_nx20
--operation mode is arithmetic

F4_modgen_gt_389_nx20 = CARRY(F4_B_0 & F4_nx589);


--F4_modgen_gt_389_nx22 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_389_nx22
--operation mode is arithmetic

F4_modgen_gt_389_nx22 = CARRY(F4_nx584 & !F4_B_1 & !F4_modgen_gt_389_nx20 # !F4_nx584 & (!F4_modgen_gt_389_nx20 # !F4_B_1));


--F4_modgen_gt_389_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_389_nx24
--operation mode is arithmetic

F4_modgen_gt_389_nx24 = CARRY(F4_a_2 & F4_B_2 & !F4_modgen_gt_389_nx22 # !F4_a_2 & (F4_B_2 # !F4_modgen_gt_389_nx22));


--F4_modgen_gt_389_nx26 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_389_nx26
--operation mode is arithmetic

F4_modgen_gt_389_nx26 = CARRY(F4_a_3 & (!F4_modgen_gt_389_nx24 # !F4_B_3) # !F4_a_3 & !F4_B_3 & !F4_modgen_gt_389_nx24);


--F4_modgen_gt_389_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_389_nx28
--operation mode is arithmetic

F4_modgen_gt_389_nx28 = CARRY(F4_a_4 & F4_B_4 & !F4_modgen_gt_389_nx26 # !F4_a_4 & (F4_B_4 # !F4_modgen_gt_389_nx26));


--F4_modgen_gt_389_nx30 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|modgen_gt_389_nx30
--operation mode is arithmetic

F4_modgen_gt_389_nx30 = CARRY(F4_nx579 & !F4_B_5 & !F4_modgen_gt_389_nx28 # !F4_nx579 & (!F4_modgen_gt_389_nx28 # !F4_B_5));


--F4_nx68 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx68
--operation mode is normal

F4_nx68_carry_eqn = F4_modgen_gt_389_nx30;
F4_nx68 = F4_nx574 & (F4_B_6 # !F4_nx68_carry_eqn) # !F4_nx574 & F4_B_6 & !F4_nx68_carry_eqn;


--F4_nx589 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx589
--operation mode is normal

F4_nx589_lut_out = !X1_request_7;
F4_nx589_reg_input = !F4_NOT_nx14 & F4_nx589_lut_out;
F4_nx589 = DFFEA(F4_nx589_reg_input, U1__clk1, V1_chipRST_n, , F4_nx12, , );


--F4_nx584 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx584
--operation mode is normal

F4_nx584_lut_out = !X1_request_6;
F4_nx584_reg_input = !F4_NOT_nx14 & F4_nx584_lut_out;
F4_nx584 = DFFEA(F4_nx584_reg_input, U1__clk1, V1_chipRST_n, , F4_nx12, , );


--F4_a_2 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|a_2
--operation mode is normal

F4_a_2_lut_out = X1_request_5;
F4_a_2_reg_input = !F4_NOT_nx14 & F4_a_2_lut_out;
F4_a_2 = DFFEA(F4_a_2_reg_input, U1__clk1, V1_chipRST_n, , F4_nx12, , );


--F4_a_3 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|a_3
--operation mode is normal

F4_a_3_lut_out = X1_request_4;
F4_a_3_reg_input = !F4_NOT_nx14 & F4_a_3_lut_out;
F4_a_3 = DFFEA(F4_a_3_reg_input, U1__clk1, V1_chipRST_n, , F4_nx12, , );


--F4_a_4 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|a_4
--operation mode is normal

F4_a_4_lut_out = X1_request_3;
F4_a_4_reg_input = !F4_NOT_nx14 & F4_a_4_lut_out;
F4_a_4 = DFFEA(F4_a_4_reg_input, U1__clk1, V1_chipRST_n, , F4_nx12, , );


--F4_nx579 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx579
--operation mode is normal

F4_nx579_lut_out = !X1_request_2;
F4_nx579_reg_input = !F4_NOT_nx14 & F4_nx579_lut_out;
F4_nx579 = DFFEA(F4_nx579_reg_input, U1__clk1, V1_chipRST_n, , F4_nx12, , );


--F4_nx574 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx574
--operation mode is normal

F4_nx574_lut_out = !X1_request_1;
F4_nx574_reg_input = !F4_NOT_nx14 & F4_nx574_lut_out;
F4_nx574 = DFFEA(F4_nx574_reg_input, U1__clk1, V1_chipRST_n, , F4_nx12, , );


--F4_nx544 is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|nx544
--operation mode is normal

F4_nx544_lut_out = F4_nx66 # F4_nx68;
F4_nx544 = DFFEA(F4_nx544_lut_out, U1__clk1, V1_chipRST_n, , F4_nx65, , );


--F4_NOT_CSn is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|NOT_CSn
--operation mode is normal

F4_NOT_CSn_lut_out = V1_rd_wr_oase # F4_nx544 # !X1_request_0 # !G1_ce_digpot;
F4_NOT_CSn = DFFEA(F4_NOT_CSn_lut_out, U1__clk1, V1_chipRST_n, , F4_nx337, , );


--F4_NOT_INCn is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|NOT_INCn
--operation mode is normal

F4_NOT_INCn_lut_out = F4_cnt_6 # F4_cnt_0 # !F4_nx572 # !F4_cnt_5;
F4_NOT_INCn = DFFEA(F4_NOT_INCn_lut_out, U1__clk1, V1_chipRST_n, , F4_NOT_nx149, , );


--F4_NOT_UDn is ADC_DAC_0:adcdac|digpot4:dgi_3_dgpot|NOT_UDn
--operation mode is normal

F4_NOT_UDn_lut_out = !F4_nx66;
F4_NOT_UDn = DFFEA(F4_NOT_UDn_lut_out, U1__clk1, V1_chipRST_n, , F4_NOT_nx79, , );


--F3_B_5 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_5
--operation mode is arithmetic

F3_B_5_carry_eqn = F3_B_nx35;
F3_B_5_lut_out = F3_B_5 $ F3_B_5_carry_eqn;
F3_B_5 = DFFEA(F3_B_5_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_B_nx45 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_nx45
--operation mode is arithmetic

F3_B_nx45 = CARRY(F3_B_5 $ !F3_NOT_UDn # !F3_B_nx35);


--F3_B_4 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_4
--operation mode is arithmetic

F3_B_4_carry_eqn = F3_B_nx25;
F3_B_4_lut_out = F3_B_4 $ !F3_B_4_carry_eqn;
F3_B_4 = DFFEA(F3_B_4_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_B_nx35 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_nx35
--operation mode is arithmetic

F3_B_nx35 = CARRY(!F3_B_nx25 & (F3_B_4 $ F3_NOT_UDn));


--F3_B_3 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_3
--operation mode is arithmetic

F3_B_3_carry_eqn = F3_B_nx19;
F3_B_3_lut_out = F3_B_3 $ F3_B_3_carry_eqn;
F3_B_3 = DFFEA(F3_B_3_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_B_nx25 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_nx25
--operation mode is arithmetic

F3_B_nx25 = CARRY(F3_B_3 $ !F3_NOT_UDn # !F3_B_nx19);


--F3_B_2 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_2
--operation mode is arithmetic

F3_B_2_carry_eqn = F3_B_nx13;
F3_B_2_lut_out = F3_B_2 $ !F3_B_2_carry_eqn;
F3_B_2 = DFFEA(F3_B_2_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_B_nx19 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_nx19
--operation mode is arithmetic

F3_B_nx19 = CARRY(!F3_B_nx13 & (F3_B_2 $ F3_NOT_UDn));


--F3_B_1 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_1
--operation mode is arithmetic

F3_B_1_carry_eqn = F3_B_nx7;
F3_B_1_lut_out = F3_B_1 $ F3_B_1_carry_eqn;
F3_B_1 = DFFEA(F3_B_1_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_B_nx13 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_nx13
--operation mode is arithmetic

F3_B_nx13 = CARRY(F3_B_1 $ !F3_NOT_UDn # !F3_B_nx7);


--F3_B_0 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_0
--operation mode is arithmetic

F3_B_0_carry_eqn = F3_B_nx56;
F3_B_0_lut_out = F3_NOT_nx144 $ F3_B_0_carry_eqn;
F3_B_0 = DFFEA(F3_B_0_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_B_nx7 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_nx7
--operation mode is arithmetic

F3_B_nx7 = CARRY(F3_NOT_nx144 & (F3_NOT_UDn $ F3_B_nx56));


--F3_B_nx56 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_nx56
--operation mode is arithmetic

F3_B_nx56 = CARRY(F3_B_0);


--F3_B_6 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|B_6
--operation mode is normal

F3_B_6_carry_eqn = F3_B_nx45;
F3_B_6_lut_out = F3_B_6 $ !F3_B_6_carry_eqn;
F3_B_6 = DFFEA(F3_B_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--F3_cnt_4 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_4
--operation mode is arithmetic

F3_cnt_4_carry_eqn = F3_cnt_nx24;
F3_cnt_4_lut_out = F3_cnt_4 $ !F3_cnt_4_carry_eqn;
F3_cnt_4 = DFFEA(F3_cnt_4_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_cnt_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_nx28
--operation mode is arithmetic

F3_cnt_nx28 = CARRY(F3_cnt_4 & !F3_cnt_nx24);


--F3_cnt_3 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_3
--operation mode is arithmetic

F3_cnt_3_carry_eqn = F3_cnt_nx18;
F3_cnt_3_lut_out = F3_cnt_3 $ F3_cnt_3_carry_eqn;
F3_cnt_3 = DFFEA(F3_cnt_3_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_cnt_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_nx24
--operation mode is arithmetic

F3_cnt_nx24 = CARRY(!F3_cnt_nx18 # !F3_cnt_3);


--F3_cnt_2 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_2
--operation mode is arithmetic

F3_cnt_2_carry_eqn = F3_cnt_nx12;
F3_cnt_2_lut_out = F3_cnt_2 $ !F3_cnt_2_carry_eqn;
F3_cnt_2 = DFFEA(F3_cnt_2_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_cnt_nx18 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_nx18
--operation mode is arithmetic

F3_cnt_nx18 = CARRY(F3_cnt_2 & !F3_cnt_nx12);


--F3_cnt_1 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_1
--operation mode is arithmetic

F3_cnt_1_carry_eqn = F3_cnt_nx6;
F3_cnt_1_lut_out = F3_cnt_1 $ F3_cnt_1_carry_eqn;
F3_cnt_1 = DFFEA(F3_cnt_1_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_cnt_nx12 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_nx12
--operation mode is arithmetic

F3_cnt_nx12 = CARRY(!F3_cnt_nx6 # !F3_cnt_1);


--F3_cnt_0 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_0
--operation mode is arithmetic

F3_cnt_0_lut_out = !F3_cnt_0;
F3_cnt_0 = DFFEA(F3_cnt_0_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_cnt_nx6 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_nx6
--operation mode is arithmetic

F3_cnt_nx6 = CARRY(F3_cnt_0);


--F3_cnt_6 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_6
--operation mode is normal

F3_cnt_6_carry_eqn = F3_cnt_nx32;
F3_cnt_6_lut_out = F3_cnt_6 $ !F3_cnt_6_carry_eqn;
F3_cnt_6 = DFFEA(F3_cnt_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--F3_cnt_5 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_5
--operation mode is arithmetic

F3_cnt_5_carry_eqn = F3_cnt_nx28;
F3_cnt_5_lut_out = F3_cnt_5 $ F3_cnt_5_carry_eqn;
F3_cnt_5 = DFFEA(F3_cnt_5_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F3_cnt_nx32 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|cnt_nx32
--operation mode is arithmetic

F3_cnt_nx32 = CARRY(!F3_cnt_nx28 # !F3_cnt_5);


--F3_nx12 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx12
--operation mode is normal

F3_nx12 = !V1_rd_wr_oase & G1_ce_digpot & !X1_request_8;


--F3_nx65 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx65
--operation mode is normal

F3_nx65 = F3_cnt_6 & !F3_cnt_5 & !F3_cnt_0 & F3_nx572;


--F3_NOT_nx79 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|NOT_nx79
--operation mode is normal

F3_NOT_nx79 = F3_nx65 & (F3_nx66 # F3_nx68);


--F3_NOT_nx149 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|NOT_nx149
--operation mode is normal

F3_NOT_nx149 = !F3_nx571 & F3_nx572 & (F3_nx544 # !F3_cnt_6);


--F3_NOT_nx144 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|NOT_nx144
--operation mode is normal

F3_NOT_nx144 = F3_cnt_6 & F3_nx544 & !F3_nx571 & F3_nx572;


--F3_nx337 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx337
--operation mode is normal

F3_nx337 = F3_nx544 # !V1_rd_wr_oase & G1_ce_digpot & X1_request_8;


--F3_NOT_nx14 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|NOT_nx14
--operation mode is normal

F3_NOT_nx14 = X1_request_10 & X1_request_9 & F3_nx573;


--F3_nx571 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx571
--operation mode is normal

F3_nx571 = F3_cnt_0 # !F3_cnt_5;


--F3_nx572 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx572
--operation mode is normal

F3_nx572 = !F3_cnt_4 & !F3_cnt_3 & !F3_cnt_2 & !F3_cnt_1;


--F3_nx573 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx573
--operation mode is normal

F3_nx573 = X1_request_11 # X1_request_12 # X1_request_13;


--F3_modgen_gt_387_nx20 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_387_nx20
--operation mode is arithmetic

F3_modgen_gt_387_nx20 = CARRY(!F3_nx589 & !F3_B_0);


--F3_modgen_gt_387_nx22 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_387_nx22
--operation mode is arithmetic

F3_modgen_gt_387_nx22 = CARRY(F3_B_1 & (F3_nx584 # !F3_modgen_gt_387_nx20) # !F3_B_1 & F3_nx584 & !F3_modgen_gt_387_nx20);


--F3_modgen_gt_387_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_387_nx24
--operation mode is arithmetic

F3_modgen_gt_387_nx24 = CARRY(F3_B_2 & F3_a_2 & !F3_modgen_gt_387_nx22 # !F3_B_2 & (F3_a_2 # !F3_modgen_gt_387_nx22));


--F3_modgen_gt_387_nx26 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_387_nx26
--operation mode is arithmetic

F3_modgen_gt_387_nx26 = CARRY(F3_B_3 & (!F3_modgen_gt_387_nx24 # !F3_a_3) # !F3_B_3 & !F3_a_3 & !F3_modgen_gt_387_nx24);


--F3_modgen_gt_387_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_387_nx28
--operation mode is arithmetic

F3_modgen_gt_387_nx28 = CARRY(F3_B_4 & F3_a_4 & !F3_modgen_gt_387_nx26 # !F3_B_4 & (F3_a_4 # !F3_modgen_gt_387_nx26));


--F3_modgen_gt_387_nx30 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_387_nx30
--operation mode is arithmetic

F3_modgen_gt_387_nx30 = CARRY(F3_B_5 & (F3_nx579 # !F3_modgen_gt_387_nx28) # !F3_B_5 & F3_nx579 & !F3_modgen_gt_387_nx28);


--F3_nx66 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx66
--operation mode is normal

F3_nx66_carry_eqn = F3_modgen_gt_387_nx30;
F3_nx66 = F3_B_6 & !F3_nx574 & !F3_nx66_carry_eqn # !F3_B_6 & (!F3_nx66_carry_eqn # !F3_nx574);


--F3_modgen_gt_389_nx20 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_389_nx20
--operation mode is arithmetic

F3_modgen_gt_389_nx20 = CARRY(F3_B_0 & F3_nx589);


--F3_modgen_gt_389_nx22 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_389_nx22
--operation mode is arithmetic

F3_modgen_gt_389_nx22 = CARRY(F3_nx584 & !F3_B_1 & !F3_modgen_gt_389_nx20 # !F3_nx584 & (!F3_modgen_gt_389_nx20 # !F3_B_1));


--F3_modgen_gt_389_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_389_nx24
--operation mode is arithmetic

F3_modgen_gt_389_nx24 = CARRY(F3_a_2 & F3_B_2 & !F3_modgen_gt_389_nx22 # !F3_a_2 & (F3_B_2 # !F3_modgen_gt_389_nx22));


--F3_modgen_gt_389_nx26 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_389_nx26
--operation mode is arithmetic

F3_modgen_gt_389_nx26 = CARRY(F3_a_3 & (!F3_modgen_gt_389_nx24 # !F3_B_3) # !F3_a_3 & !F3_B_3 & !F3_modgen_gt_389_nx24);


--F3_modgen_gt_389_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_389_nx28
--operation mode is arithmetic

F3_modgen_gt_389_nx28 = CARRY(F3_a_4 & F3_B_4 & !F3_modgen_gt_389_nx26 # !F3_a_4 & (F3_B_4 # !F3_modgen_gt_389_nx26));


--F3_modgen_gt_389_nx30 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|modgen_gt_389_nx30
--operation mode is arithmetic

F3_modgen_gt_389_nx30 = CARRY(F3_nx579 & !F3_B_5 & !F3_modgen_gt_389_nx28 # !F3_nx579 & (!F3_modgen_gt_389_nx28 # !F3_B_5));


--F3_nx68 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx68
--operation mode is normal

F3_nx68_carry_eqn = F3_modgen_gt_389_nx30;
F3_nx68 = F3_nx574 & (F3_B_6 # !F3_nx68_carry_eqn) # !F3_nx574 & F3_B_6 & !F3_nx68_carry_eqn;


--F3_nx589 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx589
--operation mode is normal

F3_nx589_lut_out = !X1_request_15;
F3_nx589_reg_input = !F3_NOT_nx14 & F3_nx589_lut_out;
F3_nx589 = DFFEA(F3_nx589_reg_input, U1__clk1, V1_chipRST_n, , F3_nx12, , );


--F3_nx584 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx584
--operation mode is normal

F3_nx584_lut_out = !X1_request_14;
F3_nx584_reg_input = !F3_NOT_nx14 & F3_nx584_lut_out;
F3_nx584 = DFFEA(F3_nx584_reg_input, U1__clk1, V1_chipRST_n, , F3_nx12, , );


--F3_a_2 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|a_2
--operation mode is normal

F3_a_2_lut_out = X1_request_13;
F3_a_2_reg_input = !F3_NOT_nx14 & F3_a_2_lut_out;
F3_a_2 = DFFEA(F3_a_2_reg_input, U1__clk1, V1_chipRST_n, , F3_nx12, , );


--F3_a_3 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|a_3
--operation mode is normal

F3_a_3_lut_out = X1_request_12;
F3_a_3_reg_input = !F3_NOT_nx14 & F3_a_3_lut_out;
F3_a_3 = DFFEA(F3_a_3_reg_input, U1__clk1, V1_chipRST_n, , F3_nx12, , );


--F3_a_4 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|a_4
--operation mode is normal

F3_a_4_lut_out = X1_request_11;
F3_a_4_reg_input = !F3_NOT_nx14 & F3_a_4_lut_out;
F3_a_4 = DFFEA(F3_a_4_reg_input, U1__clk1, V1_chipRST_n, , F3_nx12, , );


--F3_nx579 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx579
--operation mode is normal

F3_nx579_lut_out = !X1_request_10;
F3_nx579_reg_input = !F3_NOT_nx14 & F3_nx579_lut_out;
F3_nx579 = DFFEA(F3_nx579_reg_input, U1__clk1, V1_chipRST_n, , F3_nx12, , );


--F3_nx574 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx574
--operation mode is normal

F3_nx574_lut_out = !X1_request_9;
F3_nx574_reg_input = !F3_NOT_nx14 & F3_nx574_lut_out;
F3_nx574 = DFFEA(F3_nx574_reg_input, U1__clk1, V1_chipRST_n, , F3_nx12, , );


--F3_nx544 is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|nx544
--operation mode is normal

F3_nx544_lut_out = F3_nx66 # F3_nx68;
F3_nx544 = DFFEA(F3_nx544_lut_out, U1__clk1, V1_chipRST_n, , F3_nx65, , );


--F3_NOT_CSn is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|NOT_CSn
--operation mode is normal

F3_NOT_CSn_lut_out = V1_rd_wr_oase # F3_nx544 # !X1_request_8 # !G1_ce_digpot;
F3_NOT_CSn = DFFEA(F3_NOT_CSn_lut_out, U1__clk1, V1_chipRST_n, , F3_nx337, , );


--F3_NOT_INCn is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|NOT_INCn
--operation mode is normal

F3_NOT_INCn_lut_out = F3_cnt_6 # F3_cnt_0 # !F3_nx572 # !F3_cnt_5;
F3_NOT_INCn = DFFEA(F3_NOT_INCn_lut_out, U1__clk1, V1_chipRST_n, , F3_NOT_nx149, , );


--F3_NOT_UDn is ADC_DAC_0:adcdac|digpot4:dgi_2_dgpot|NOT_UDn
--operation mode is normal

F3_NOT_UDn_lut_out = !F3_nx66;
F3_NOT_UDn = DFFEA(F3_NOT_UDn_lut_out, U1__clk1, V1_chipRST_n, , F3_NOT_nx79, , );


--F2_B_5 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_5
--operation mode is arithmetic

F2_B_5_carry_eqn = F2_B_nx35;
F2_B_5_lut_out = F2_B_5 $ F2_B_5_carry_eqn;
F2_B_5 = DFFEA(F2_B_5_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_B_nx45 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_nx45
--operation mode is arithmetic

F2_B_nx45 = CARRY(F2_B_5 $ !F2_NOT_UDn # !F2_B_nx35);


--F2_B_4 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_4
--operation mode is arithmetic

F2_B_4_carry_eqn = F2_B_nx25;
F2_B_4_lut_out = F2_B_4 $ !F2_B_4_carry_eqn;
F2_B_4 = DFFEA(F2_B_4_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_B_nx35 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_nx35
--operation mode is arithmetic

F2_B_nx35 = CARRY(!F2_B_nx25 & (F2_B_4 $ F2_NOT_UDn));


--F2_B_3 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_3
--operation mode is arithmetic

F2_B_3_carry_eqn = F2_B_nx19;
F2_B_3_lut_out = F2_B_3 $ F2_B_3_carry_eqn;
F2_B_3 = DFFEA(F2_B_3_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_B_nx25 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_nx25
--operation mode is arithmetic

F2_B_nx25 = CARRY(F2_B_3 $ !F2_NOT_UDn # !F2_B_nx19);


--F2_B_2 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_2
--operation mode is arithmetic

F2_B_2_carry_eqn = F2_B_nx13;
F2_B_2_lut_out = F2_B_2 $ !F2_B_2_carry_eqn;
F2_B_2 = DFFEA(F2_B_2_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_B_nx19 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_nx19
--operation mode is arithmetic

F2_B_nx19 = CARRY(!F2_B_nx13 & (F2_B_2 $ F2_NOT_UDn));


--F2_B_1 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_1
--operation mode is arithmetic

F2_B_1_carry_eqn = F2_B_nx7;
F2_B_1_lut_out = F2_B_1 $ F2_B_1_carry_eqn;
F2_B_1 = DFFEA(F2_B_1_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_B_nx13 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_nx13
--operation mode is arithmetic

F2_B_nx13 = CARRY(F2_B_1 $ !F2_NOT_UDn # !F2_B_nx7);


--F2_B_0 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_0
--operation mode is arithmetic

F2_B_0_carry_eqn = F2_B_nx56;
F2_B_0_lut_out = F2_NOT_nx144 $ F2_B_0_carry_eqn;
F2_B_0 = DFFEA(F2_B_0_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_B_nx7 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_nx7
--operation mode is arithmetic

F2_B_nx7 = CARRY(F2_NOT_nx144 & (F2_NOT_UDn $ F2_B_nx56));


--F2_B_nx56 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_nx56
--operation mode is arithmetic

F2_B_nx56 = CARRY(F2_B_0);


--F2_B_6 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|B_6
--operation mode is normal

F2_B_6_carry_eqn = F2_B_nx45;
F2_B_6_lut_out = F2_B_6 $ !F2_B_6_carry_eqn;
F2_B_6 = DFFEA(F2_B_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--F2_cnt_4 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_4
--operation mode is arithmetic

F2_cnt_4_carry_eqn = F2_cnt_nx24;
F2_cnt_4_lut_out = F2_cnt_4 $ !F2_cnt_4_carry_eqn;
F2_cnt_4 = DFFEA(F2_cnt_4_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_cnt_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_nx28
--operation mode is arithmetic

F2_cnt_nx28 = CARRY(F2_cnt_4 & !F2_cnt_nx24);


--F2_cnt_3 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_3
--operation mode is arithmetic

F2_cnt_3_carry_eqn = F2_cnt_nx18;
F2_cnt_3_lut_out = F2_cnt_3 $ F2_cnt_3_carry_eqn;
F2_cnt_3 = DFFEA(F2_cnt_3_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_cnt_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_nx24
--operation mode is arithmetic

F2_cnt_nx24 = CARRY(!F2_cnt_nx18 # !F2_cnt_3);


--F2_cnt_2 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_2
--operation mode is arithmetic

F2_cnt_2_carry_eqn = F2_cnt_nx12;
F2_cnt_2_lut_out = F2_cnt_2 $ !F2_cnt_2_carry_eqn;
F2_cnt_2 = DFFEA(F2_cnt_2_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_cnt_nx18 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_nx18
--operation mode is arithmetic

F2_cnt_nx18 = CARRY(F2_cnt_2 & !F2_cnt_nx12);


--F2_cnt_1 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_1
--operation mode is arithmetic

F2_cnt_1_carry_eqn = F2_cnt_nx6;
F2_cnt_1_lut_out = F2_cnt_1 $ F2_cnt_1_carry_eqn;
F2_cnt_1 = DFFEA(F2_cnt_1_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_cnt_nx12 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_nx12
--operation mode is arithmetic

F2_cnt_nx12 = CARRY(!F2_cnt_nx6 # !F2_cnt_1);


--F2_cnt_0 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_0
--operation mode is arithmetic

F2_cnt_0_lut_out = !F2_cnt_0;
F2_cnt_0 = DFFEA(F2_cnt_0_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_cnt_nx6 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_nx6
--operation mode is arithmetic

F2_cnt_nx6 = CARRY(F2_cnt_0);


--F2_cnt_6 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_6
--operation mode is normal

F2_cnt_6_carry_eqn = F2_cnt_nx32;
F2_cnt_6_lut_out = F2_cnt_6 $ !F2_cnt_6_carry_eqn;
F2_cnt_6 = DFFEA(F2_cnt_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--F2_cnt_5 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_5
--operation mode is arithmetic

F2_cnt_5_carry_eqn = F2_cnt_nx28;
F2_cnt_5_lut_out = F2_cnt_5 $ F2_cnt_5_carry_eqn;
F2_cnt_5 = DFFEA(F2_cnt_5_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F2_cnt_nx32 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|cnt_nx32
--operation mode is arithmetic

F2_cnt_nx32 = CARRY(!F2_cnt_nx28 # !F2_cnt_5);


--F2_nx12 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx12
--operation mode is normal

F2_nx12 = !V1_rd_wr_oase & G1_ce_digpot & !X1_request_16;


--F2_nx65 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx65
--operation mode is normal

F2_nx65 = F2_cnt_6 & !F2_cnt_5 & !F2_cnt_0 & F2_nx572;


--F2_NOT_nx79 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|NOT_nx79
--operation mode is normal

F2_NOT_nx79 = F2_nx65 & (F2_nx66 # F2_nx68);


--F2_NOT_nx149 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|NOT_nx149
--operation mode is normal

F2_NOT_nx149 = !F2_nx571 & F2_nx572 & (F2_nx544 # !F2_cnt_6);


--F2_NOT_nx144 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|NOT_nx144
--operation mode is normal

F2_NOT_nx144 = F2_cnt_6 & F2_nx544 & !F2_nx571 & F2_nx572;


--F2_nx337 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx337
--operation mode is normal

F2_nx337 = F2_nx544 # !V1_rd_wr_oase & G1_ce_digpot & X1_request_16;


--F2_NOT_nx14 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|NOT_nx14
--operation mode is normal

F2_NOT_nx14 = X1_request_18 & X1_request_17 & F2_nx573;


--F2_nx571 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx571
--operation mode is normal

F2_nx571 = F2_cnt_0 # !F2_cnt_5;


--F2_nx572 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx572
--operation mode is normal

F2_nx572 = !F2_cnt_4 & !F2_cnt_3 & !F2_cnt_2 & !F2_cnt_1;


--F2_nx573 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx573
--operation mode is normal

F2_nx573 = X1_request_19 # X1_request_20 # X1_request_21;


--F2_modgen_gt_387_nx20 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_387_nx20
--operation mode is arithmetic

F2_modgen_gt_387_nx20 = CARRY(!F2_nx589 & !F2_B_0);


--F2_modgen_gt_387_nx22 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_387_nx22
--operation mode is arithmetic

F2_modgen_gt_387_nx22 = CARRY(F2_B_1 & (F2_nx584 # !F2_modgen_gt_387_nx20) # !F2_B_1 & F2_nx584 & !F2_modgen_gt_387_nx20);


--F2_modgen_gt_387_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_387_nx24
--operation mode is arithmetic

F2_modgen_gt_387_nx24 = CARRY(F2_B_2 & F2_a_2 & !F2_modgen_gt_387_nx22 # !F2_B_2 & (F2_a_2 # !F2_modgen_gt_387_nx22));


--F2_modgen_gt_387_nx26 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_387_nx26
--operation mode is arithmetic

F2_modgen_gt_387_nx26 = CARRY(F2_B_3 & (!F2_modgen_gt_387_nx24 # !F2_a_3) # !F2_B_3 & !F2_a_3 & !F2_modgen_gt_387_nx24);


--F2_modgen_gt_387_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_387_nx28
--operation mode is arithmetic

F2_modgen_gt_387_nx28 = CARRY(F2_B_4 & F2_a_4 & !F2_modgen_gt_387_nx26 # !F2_B_4 & (F2_a_4 # !F2_modgen_gt_387_nx26));


--F2_modgen_gt_387_nx30 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_387_nx30
--operation mode is arithmetic

F2_modgen_gt_387_nx30 = CARRY(F2_B_5 & (F2_nx579 # !F2_modgen_gt_387_nx28) # !F2_B_5 & F2_nx579 & !F2_modgen_gt_387_nx28);


--F2_nx66 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx66
--operation mode is normal

F2_nx66_carry_eqn = F2_modgen_gt_387_nx30;
F2_nx66 = F2_B_6 & !F2_nx574 & !F2_nx66_carry_eqn # !F2_B_6 & (!F2_nx66_carry_eqn # !F2_nx574);


--F2_modgen_gt_389_nx20 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_389_nx20
--operation mode is arithmetic

F2_modgen_gt_389_nx20 = CARRY(F2_B_0 & F2_nx589);


--F2_modgen_gt_389_nx22 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_389_nx22
--operation mode is arithmetic

F2_modgen_gt_389_nx22 = CARRY(F2_nx584 & !F2_B_1 & !F2_modgen_gt_389_nx20 # !F2_nx584 & (!F2_modgen_gt_389_nx20 # !F2_B_1));


--F2_modgen_gt_389_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_389_nx24
--operation mode is arithmetic

F2_modgen_gt_389_nx24 = CARRY(F2_a_2 & F2_B_2 & !F2_modgen_gt_389_nx22 # !F2_a_2 & (F2_B_2 # !F2_modgen_gt_389_nx22));


--F2_modgen_gt_389_nx26 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_389_nx26
--operation mode is arithmetic

F2_modgen_gt_389_nx26 = CARRY(F2_a_3 & (!F2_modgen_gt_389_nx24 # !F2_B_3) # !F2_a_3 & !F2_B_3 & !F2_modgen_gt_389_nx24);


--F2_modgen_gt_389_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_389_nx28
--operation mode is arithmetic

F2_modgen_gt_389_nx28 = CARRY(F2_a_4 & F2_B_4 & !F2_modgen_gt_389_nx26 # !F2_a_4 & (F2_B_4 # !F2_modgen_gt_389_nx26));


--F2_modgen_gt_389_nx30 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|modgen_gt_389_nx30
--operation mode is arithmetic

F2_modgen_gt_389_nx30 = CARRY(F2_nx579 & !F2_B_5 & !F2_modgen_gt_389_nx28 # !F2_nx579 & (!F2_modgen_gt_389_nx28 # !F2_B_5));


--F2_nx68 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx68
--operation mode is normal

F2_nx68_carry_eqn = F2_modgen_gt_389_nx30;
F2_nx68 = F2_nx574 & (F2_B_6 # !F2_nx68_carry_eqn) # !F2_nx574 & F2_B_6 & !F2_nx68_carry_eqn;


--F2_nx589 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx589
--operation mode is normal

F2_nx589_lut_out = !X1_request_23;
F2_nx589_reg_input = !F2_NOT_nx14 & F2_nx589_lut_out;
F2_nx589 = DFFEA(F2_nx589_reg_input, U1__clk1, V1_chipRST_n, , F2_nx12, , );


--F2_nx584 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx584
--operation mode is normal

F2_nx584_lut_out = !X1_request_22;
F2_nx584_reg_input = !F2_NOT_nx14 & F2_nx584_lut_out;
F2_nx584 = DFFEA(F2_nx584_reg_input, U1__clk1, V1_chipRST_n, , F2_nx12, , );


--F2_a_2 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|a_2
--operation mode is normal

F2_a_2_lut_out = X1_request_21;
F2_a_2_reg_input = !F2_NOT_nx14 & F2_a_2_lut_out;
F2_a_2 = DFFEA(F2_a_2_reg_input, U1__clk1, V1_chipRST_n, , F2_nx12, , );


--F2_a_3 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|a_3
--operation mode is normal

F2_a_3_lut_out = X1_request_20;
F2_a_3_reg_input = !F2_NOT_nx14 & F2_a_3_lut_out;
F2_a_3 = DFFEA(F2_a_3_reg_input, U1__clk1, V1_chipRST_n, , F2_nx12, , );


--F2_a_4 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|a_4
--operation mode is normal

F2_a_4_lut_out = X1_request_19;
F2_a_4_reg_input = !F2_NOT_nx14 & F2_a_4_lut_out;
F2_a_4 = DFFEA(F2_a_4_reg_input, U1__clk1, V1_chipRST_n, , F2_nx12, , );


--F2_nx579 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx579
--operation mode is normal

F2_nx579_lut_out = !X1_request_18;
F2_nx579_reg_input = !F2_NOT_nx14 & F2_nx579_lut_out;
F2_nx579 = DFFEA(F2_nx579_reg_input, U1__clk1, V1_chipRST_n, , F2_nx12, , );


--F2_nx574 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx574
--operation mode is normal

F2_nx574_lut_out = !X1_request_17;
F2_nx574_reg_input = !F2_NOT_nx14 & F2_nx574_lut_out;
F2_nx574 = DFFEA(F2_nx574_reg_input, U1__clk1, V1_chipRST_n, , F2_nx12, , );


--F2_nx544 is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|nx544
--operation mode is normal

F2_nx544_lut_out = F2_nx66 # F2_nx68;
F2_nx544 = DFFEA(F2_nx544_lut_out, U1__clk1, V1_chipRST_n, , F2_nx65, , );


--F2_NOT_CSn is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|NOT_CSn
--operation mode is normal

F2_NOT_CSn_lut_out = V1_rd_wr_oase # F2_nx544 # !X1_request_16 # !G1_ce_digpot;
F2_NOT_CSn = DFFEA(F2_NOT_CSn_lut_out, U1__clk1, V1_chipRST_n, , F2_nx337, , );


--F2_NOT_INCn is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|NOT_INCn
--operation mode is normal

F2_NOT_INCn_lut_out = F2_cnt_6 # F2_cnt_0 # !F2_nx572 # !F2_cnt_5;
F2_NOT_INCn = DFFEA(F2_NOT_INCn_lut_out, U1__clk1, V1_chipRST_n, , F2_NOT_nx149, , );


--F2_NOT_UDn is ADC_DAC_0:adcdac|digpot4:dgi_1_dgpot|NOT_UDn
--operation mode is normal

F2_NOT_UDn_lut_out = !F2_nx66;
F2_NOT_UDn = DFFEA(F2_NOT_UDn_lut_out, U1__clk1, V1_chipRST_n, , F2_NOT_nx79, , );


--F1_B_5 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_5
--operation mode is arithmetic

F1_B_5_carry_eqn = F1_B_nx35;
F1_B_5_lut_out = F1_B_5 $ F1_B_5_carry_eqn;
F1_B_5 = DFFEA(F1_B_5_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_B_nx45 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_nx45
--operation mode is arithmetic

F1_B_nx45 = CARRY(F1_B_5 $ !F1_NOT_UDn # !F1_B_nx35);


--F1_B_4 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_4
--operation mode is arithmetic

F1_B_4_carry_eqn = F1_B_nx25;
F1_B_4_lut_out = F1_B_4 $ !F1_B_4_carry_eqn;
F1_B_4 = DFFEA(F1_B_4_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_B_nx35 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_nx35
--operation mode is arithmetic

F1_B_nx35 = CARRY(!F1_B_nx25 & (F1_B_4 $ F1_NOT_UDn));


--F1_B_3 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_3
--operation mode is arithmetic

F1_B_3_carry_eqn = F1_B_nx19;
F1_B_3_lut_out = F1_B_3 $ F1_B_3_carry_eqn;
F1_B_3 = DFFEA(F1_B_3_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_B_nx25 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_nx25
--operation mode is arithmetic

F1_B_nx25 = CARRY(F1_B_3 $ !F1_NOT_UDn # !F1_B_nx19);


--F1_B_2 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_2
--operation mode is arithmetic

F1_B_2_carry_eqn = F1_B_nx13;
F1_B_2_lut_out = F1_B_2 $ !F1_B_2_carry_eqn;
F1_B_2 = DFFEA(F1_B_2_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_B_nx19 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_nx19
--operation mode is arithmetic

F1_B_nx19 = CARRY(!F1_B_nx13 & (F1_B_2 $ F1_NOT_UDn));


--F1_B_1 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_1
--operation mode is arithmetic

F1_B_1_carry_eqn = F1_B_nx7;
F1_B_1_lut_out = F1_B_1 $ F1_B_1_carry_eqn;
F1_B_1 = DFFEA(F1_B_1_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_B_nx13 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_nx13
--operation mode is arithmetic

F1_B_nx13 = CARRY(F1_B_1 $ !F1_NOT_UDn # !F1_B_nx7);


--F1_B_0 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_0
--operation mode is arithmetic

F1_B_0_carry_eqn = F1_B_nx56;
F1_B_0_lut_out = F1_NOT_nx144 $ F1_B_0_carry_eqn;
F1_B_0 = DFFEA(F1_B_0_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_B_nx7 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_nx7
--operation mode is arithmetic

F1_B_nx7 = CARRY(F1_NOT_nx144 & (F1_NOT_UDn $ F1_B_nx56));


--F1_B_nx56 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_nx56
--operation mode is arithmetic

F1_B_nx56 = CARRY(F1_B_0);


--F1_B_6 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|B_6
--operation mode is normal

F1_B_6_carry_eqn = F1_B_nx45;
F1_B_6_lut_out = F1_B_6 $ !F1_B_6_carry_eqn;
F1_B_6 = DFFEA(F1_B_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--F1_cnt_4 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_4
--operation mode is arithmetic

F1_cnt_4_carry_eqn = F1_cnt_nx24;
F1_cnt_4_lut_out = F1_cnt_4 $ !F1_cnt_4_carry_eqn;
F1_cnt_4 = DFFEA(F1_cnt_4_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_cnt_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_nx28
--operation mode is arithmetic

F1_cnt_nx28 = CARRY(F1_cnt_4 & !F1_cnt_nx24);


--F1_cnt_3 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_3
--operation mode is arithmetic

F1_cnt_3_carry_eqn = F1_cnt_nx18;
F1_cnt_3_lut_out = F1_cnt_3 $ F1_cnt_3_carry_eqn;
F1_cnt_3 = DFFEA(F1_cnt_3_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_cnt_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_nx24
--operation mode is arithmetic

F1_cnt_nx24 = CARRY(!F1_cnt_nx18 # !F1_cnt_3);


--F1_cnt_2 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_2
--operation mode is arithmetic

F1_cnt_2_carry_eqn = F1_cnt_nx12;
F1_cnt_2_lut_out = F1_cnt_2 $ !F1_cnt_2_carry_eqn;
F1_cnt_2 = DFFEA(F1_cnt_2_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_cnt_nx18 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_nx18
--operation mode is arithmetic

F1_cnt_nx18 = CARRY(F1_cnt_2 & !F1_cnt_nx12);


--F1_cnt_1 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_1
--operation mode is arithmetic

F1_cnt_1_carry_eqn = F1_cnt_nx6;
F1_cnt_1_lut_out = F1_cnt_1 $ F1_cnt_1_carry_eqn;
F1_cnt_1 = DFFEA(F1_cnt_1_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_cnt_nx12 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_nx12
--operation mode is arithmetic

F1_cnt_nx12 = CARRY(!F1_cnt_nx6 # !F1_cnt_1);


--F1_cnt_0 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_0
--operation mode is arithmetic

F1_cnt_0_lut_out = !F1_cnt_0;
F1_cnt_0 = DFFEA(F1_cnt_0_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_cnt_nx6 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_nx6
--operation mode is arithmetic

F1_cnt_nx6 = CARRY(F1_cnt_0);


--F1_cnt_6 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_6
--operation mode is normal

F1_cnt_6_carry_eqn = F1_cnt_nx32;
F1_cnt_6_lut_out = F1_cnt_6 $ !F1_cnt_6_carry_eqn;
F1_cnt_6 = DFFEA(F1_cnt_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--F1_cnt_5 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_5
--operation mode is arithmetic

F1_cnt_5_carry_eqn = F1_cnt_nx28;
F1_cnt_5_lut_out = F1_cnt_5 $ F1_cnt_5_carry_eqn;
F1_cnt_5 = DFFEA(F1_cnt_5_lut_out, U1__clk1, V1_chipRST_n, , , , );

--F1_cnt_nx32 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|cnt_nx32
--operation mode is arithmetic

F1_cnt_nx32 = CARRY(!F1_cnt_nx28 # !F1_cnt_5);


--F1_nx12 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx12
--operation mode is normal

F1_nx12 = !V1_rd_wr_oase & G1_ce_digpot & !X1_request_24;


--F1_nx65 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx65
--operation mode is normal

F1_nx65 = F1_cnt_6 & !F1_cnt_5 & !F1_cnt_0 & F1_nx572;


--F1_NOT_nx79 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|NOT_nx79
--operation mode is normal

F1_NOT_nx79 = F1_nx65 & (F1_nx66 # F1_nx68);


--F1_NOT_nx149 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|NOT_nx149
--operation mode is normal

F1_NOT_nx149 = !F1_nx571 & F1_nx572 & (F1_nx544 # !F1_cnt_6);


--F1_NOT_nx144 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|NOT_nx144
--operation mode is normal

F1_NOT_nx144 = F1_cnt_6 & F1_nx544 & !F1_nx571 & F1_nx572;


--F1_nx337 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx337
--operation mode is normal

F1_nx337 = F1_nx544 # !V1_rd_wr_oase & G1_ce_digpot & X1_request_24;


--F1_NOT_nx14 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|NOT_nx14
--operation mode is normal

F1_NOT_nx14 = X1_request_26 & X1_request_25 & F1_nx573;


--F1_nx571 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx571
--operation mode is normal

F1_nx571 = F1_cnt_0 # !F1_cnt_5;


--F1_nx572 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx572
--operation mode is normal

F1_nx572 = !F1_cnt_4 & !F1_cnt_3 & !F1_cnt_2 & !F1_cnt_1;


--F1_nx573 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx573
--operation mode is normal

F1_nx573 = X1_request_27 # X1_request_28 # X1_request_29;


--F1_modgen_gt_387_nx20 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_387_nx20
--operation mode is arithmetic

F1_modgen_gt_387_nx20 = CARRY(!F1_nx589 & !F1_B_0);


--F1_modgen_gt_387_nx22 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_387_nx22
--operation mode is arithmetic

F1_modgen_gt_387_nx22 = CARRY(F1_B_1 & (F1_nx584 # !F1_modgen_gt_387_nx20) # !F1_B_1 & F1_nx584 & !F1_modgen_gt_387_nx20);


--F1_modgen_gt_387_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_387_nx24
--operation mode is arithmetic

F1_modgen_gt_387_nx24 = CARRY(F1_B_2 & F1_a_2 & !F1_modgen_gt_387_nx22 # !F1_B_2 & (F1_a_2 # !F1_modgen_gt_387_nx22));


--F1_modgen_gt_387_nx26 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_387_nx26
--operation mode is arithmetic

F1_modgen_gt_387_nx26 = CARRY(F1_B_3 & (!F1_modgen_gt_387_nx24 # !F1_a_3) # !F1_B_3 & !F1_a_3 & !F1_modgen_gt_387_nx24);


--F1_modgen_gt_387_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_387_nx28
--operation mode is arithmetic

F1_modgen_gt_387_nx28 = CARRY(F1_B_4 & F1_a_4 & !F1_modgen_gt_387_nx26 # !F1_B_4 & (F1_a_4 # !F1_modgen_gt_387_nx26));


--F1_modgen_gt_387_nx30 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_387_nx30
--operation mode is arithmetic

F1_modgen_gt_387_nx30 = CARRY(F1_B_5 & (F1_nx579 # !F1_modgen_gt_387_nx28) # !F1_B_5 & F1_nx579 & !F1_modgen_gt_387_nx28);


--F1_nx66 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx66
--operation mode is normal

F1_nx66_carry_eqn = F1_modgen_gt_387_nx30;
F1_nx66 = F1_B_6 & !F1_nx574 & !F1_nx66_carry_eqn # !F1_B_6 & (!F1_nx66_carry_eqn # !F1_nx574);


--F1_modgen_gt_389_nx20 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_389_nx20
--operation mode is arithmetic

F1_modgen_gt_389_nx20 = CARRY(F1_B_0 & F1_nx589);


--F1_modgen_gt_389_nx22 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_389_nx22
--operation mode is arithmetic

F1_modgen_gt_389_nx22 = CARRY(F1_nx584 & !F1_B_1 & !F1_modgen_gt_389_nx20 # !F1_nx584 & (!F1_modgen_gt_389_nx20 # !F1_B_1));


--F1_modgen_gt_389_nx24 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_389_nx24
--operation mode is arithmetic

F1_modgen_gt_389_nx24 = CARRY(F1_a_2 & F1_B_2 & !F1_modgen_gt_389_nx22 # !F1_a_2 & (F1_B_2 # !F1_modgen_gt_389_nx22));


--F1_modgen_gt_389_nx26 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_389_nx26
--operation mode is arithmetic

F1_modgen_gt_389_nx26 = CARRY(F1_a_3 & (!F1_modgen_gt_389_nx24 # !F1_B_3) # !F1_a_3 & !F1_B_3 & !F1_modgen_gt_389_nx24);


--F1_modgen_gt_389_nx28 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_389_nx28
--operation mode is arithmetic

F1_modgen_gt_389_nx28 = CARRY(F1_a_4 & F1_B_4 & !F1_modgen_gt_389_nx26 # !F1_a_4 & (F1_B_4 # !F1_modgen_gt_389_nx26));


--F1_modgen_gt_389_nx30 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|modgen_gt_389_nx30
--operation mode is arithmetic

F1_modgen_gt_389_nx30 = CARRY(F1_nx579 & !F1_B_5 & !F1_modgen_gt_389_nx28 # !F1_nx579 & (!F1_modgen_gt_389_nx28 # !F1_B_5));


--F1_nx68 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx68
--operation mode is normal

F1_nx68_carry_eqn = F1_modgen_gt_389_nx30;
F1_nx68 = F1_nx574 & (F1_B_6 # !F1_nx68_carry_eqn) # !F1_nx574 & F1_B_6 & !F1_nx68_carry_eqn;


--F1_nx589 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx589
--operation mode is normal

F1_nx589_lut_out = !X1_request_31;
F1_nx589_reg_input = !F1_NOT_nx14 & F1_nx589_lut_out;
F1_nx589 = DFFEA(F1_nx589_reg_input, U1__clk1, V1_chipRST_n, , F1_nx12, , );


--F1_nx584 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx584
--operation mode is normal

F1_nx584_lut_out = !X1_request_30;
F1_nx584_reg_input = !F1_NOT_nx14 & F1_nx584_lut_out;
F1_nx584 = DFFEA(F1_nx584_reg_input, U1__clk1, V1_chipRST_n, , F1_nx12, , );


--F1_a_2 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|a_2
--operation mode is normal

F1_a_2_lut_out = X1_request_29;
F1_a_2_reg_input = !F1_NOT_nx14 & F1_a_2_lut_out;
F1_a_2 = DFFEA(F1_a_2_reg_input, U1__clk1, V1_chipRST_n, , F1_nx12, , );


--F1_a_3 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|a_3
--operation mode is normal

F1_a_3_lut_out = X1_request_28;
F1_a_3_reg_input = !F1_NOT_nx14 & F1_a_3_lut_out;
F1_a_3 = DFFEA(F1_a_3_reg_input, U1__clk1, V1_chipRST_n, , F1_nx12, , );


--F1_a_4 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|a_4
--operation mode is normal

F1_a_4_lut_out = X1_request_27;
F1_a_4_reg_input = !F1_NOT_nx14 & F1_a_4_lut_out;
F1_a_4 = DFFEA(F1_a_4_reg_input, U1__clk1, V1_chipRST_n, , F1_nx12, , );


--F1_nx579 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx579
--operation mode is normal

F1_nx579_lut_out = !X1_request_26;
F1_nx579_reg_input = !F1_NOT_nx14 & F1_nx579_lut_out;
F1_nx579 = DFFEA(F1_nx579_reg_input, U1__clk1, V1_chipRST_n, , F1_nx12, , );


--F1_nx574 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx574
--operation mode is normal

F1_nx574_lut_out = !X1_request_25;
F1_nx574_reg_input = !F1_NOT_nx14 & F1_nx574_lut_out;
F1_nx574 = DFFEA(F1_nx574_reg_input, U1__clk1, V1_chipRST_n, , F1_nx12, , );


--F1_nx544 is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|nx544
--operation mode is normal

F1_nx544_lut_out = F1_nx66 # F1_nx68;
F1_nx544 = DFFEA(F1_nx544_lut_out, U1__clk1, V1_chipRST_n, , F1_nx65, , );


--F1_NOT_CSn is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|NOT_CSn
--operation mode is normal

F1_NOT_CSn_lut_out = V1_rd_wr_oase # F1_nx544 # !X1_request_24 # !G1_ce_digpot;
F1_NOT_CSn = DFFEA(F1_NOT_CSn_lut_out, U1__clk1, V1_chipRST_n, , F1_nx337, , );


--F1_NOT_INCn is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|NOT_INCn
--operation mode is normal

F1_NOT_INCn_lut_out = F1_cnt_6 # F1_cnt_0 # !F1_nx572 # !F1_cnt_5;
F1_NOT_INCn = DFFEA(F1_NOT_INCn_lut_out, U1__clk1, V1_chipRST_n, , F1_NOT_nx149, , );


--F1_NOT_UDn is ADC_DAC_0:adcdac|digpot4:dgi_0_dgpot|NOT_UDn
--operation mode is normal

F1_NOT_UDn_lut_out = !F1_nx66;
F1_NOT_UDn = DFFEA(F1_NOT_UDn_lut_out, U1__clk1, V1_chipRST_n, , F1_NOT_nx79, , );


--E1_nx8 is ADC_DAC_0:adcdac|DDS:ddsi|nx8
--operation mode is normal

E1_nx8 = G1_ce_dds & !V1_rd_wr_oase;


--E1_NOT_nx429 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx429
--operation mode is normal

E1_NOT_nx429 = X1_request_46 & !X1_request_47 & !X1_request_48 & E1_nx8;


--E1_NOT_nx543 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx543
--operation mode is normal

E1_NOT_nx543 = G1_ce_dds & !V1_rd_wr_oase & !X1_request_48 & E1_nx859;


--E1_NOT_nx1490 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx1490
--operation mode is normal

E1_NOT_nx1490 = E1_NOT_sm_top_0 & (E1_sm_top_6 # E1_sm_top_1) # !E1_NOT_sm_top_0 & !E1_flag2send;


--E1_NOT_nx1526 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx1526
--operation mode is normal

E1_NOT_nx1526 = E1_NOT_sm_top_0 & (E1_sm_top_4 # E1_sm_top_2) # !E1_NOT_sm_top_0 & E1_flag2send;


--E1_NOT_nx1511 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx1511
--operation mode is normal

E1_NOT_nx1511 = E1_nx792 # E1_NOT_sm_top_0 & E1_nx791 # !E1_NOT_sm_top_0 & E1_flag2send;


--E1_NOT_nx1467 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx1467
--operation mode is normal

E1_NOT_nx1467 = !E1_nx791 & E1_nx839 & (E1_nx850 # !E1_nx790);


--E1_NOT_nx2089 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx2089
--operation mode is normal

E1_NOT_nx2089 = E1_nx801 # E1_byte_counter_2 & E1_byte_counter_1 & E1_nx802;


--E1_NOT_nx2121 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx2121
--operation mode is normal

E1_NOT_nx2121 = E1_nx801 # E1_byte_counter_2 & !E1_byte_counter_1 & E1_nx804;


--E1_NOT_nx2153 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx2153
--operation mode is normal

E1_NOT_nx2153 = E1_nx801 # E1_byte_counter_2 & !E1_byte_counter_1 & E1_nx802;


--E1_NOT_nx2185 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx2185
--operation mode is normal

E1_NOT_nx2185 = E1_nx801 # !E1_byte_counter_2 & E1_byte_counter_1 & E1_nx804;


--E1_NOT_nx2217 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx2217
--operation mode is normal

E1_NOT_nx2217 = E1_nx801 # !E1_byte_counter_2 & E1_byte_counter_1 & E1_nx802;


--E1_NOT_nx2249 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx2249
--operation mode is normal

E1_NOT_nx2249 = E1_nx801 # !E1_byte_counter_2 & !E1_byte_counter_1 & E1_nx804;


--E1_nx2672 is ADC_DAC_0:adcdac|DDS:ddsi|nx2672
--operation mode is normal

E1_nx2672 = E1_b_1_dup_404 & (E1_sm_sr_3 # E1_sm_sr_1) # !E1_nx538;


--E1_nx2685 is ADC_DAC_0:adcdac|DDS:ddsi|nx2685
--operation mode is normal

E1_nx2685 = E1_b_1_dup_411 & (E1_sm_sr_3 # E1_sm_sr_1) # !E1_nx538;


--E1_nx2698 is ADC_DAC_0:adcdac|DDS:ddsi|nx2698
--operation mode is normal

E1_nx2698 = E1_b_1_dup_418 & (E1_sm_sr_3 # E1_sm_sr_1) # !E1_nx538;


--E1_nx2701 is ADC_DAC_0:adcdac|DDS:ddsi|nx2701
--operation mode is normal

E1_nx2701 = E1_sm_sr_3 # E1_sm_sr_1 # !E1_nx538;


--E1_NOT_nx2793 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx2793
--operation mode is normal

E1_NOT_nx2793 = E1_sm_sr_1 & E1_clkdivs;


--E1_NOT_nx2817 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx2817
--operation mode is normal

E1_NOT_nx2817 = E1_clkdivs & (E1_nx538 & E1_sm_sr_4 # !E1_nx538 & E1_nx845);


--E1_nx749 is ADC_DAC_0:adcdac|DDS:ddsi|nx749
--operation mode is normal

E1_nx749 = E1_byte_counter_0 & !E1_nx784 & (E1_sm_top_5 # E1_sm_top_3);


--E1_nx750 is ADC_DAC_0:adcdac|DDS:ddsi|nx750
--operation mode is normal

E1_nx750 = E1_iword2send_0 & E1_b_0_dup_234 & E1_nx788 # !E1_iword2send_0 & (E1_nx803 # E1_b_0_dup_234 & E1_nx788);


--E1_nx751 is ADC_DAC_0:adcdac|DDS:ddsi|nx751
--operation mode is normal

E1_nx751 = E1_sm_top_4 & (E1_nx800 # E1_sm_sr_5 & !E1_nx786) # !E1_sm_top_4 & E1_sm_sr_5 & !E1_nx786;


--E1_nx752 is ADC_DAC_0:adcdac|DDS:ddsi|nx752
--operation mode is normal

E1_nx752 = E1_sm_top_3 & !E1_nx790 & (E1_nx784 # !E1_byte_counter_0);


--E1_nx753 is ADC_DAC_0:adcdac|DDS:ddsi|nx753
--operation mode is normal

E1_nx753 = E1_sm_sr_4 & (E1_byte_send_6 # E1_bytes2send_31 & E1_nx798) # !E1_sm_sr_4 & E1_bytes2send_31 & E1_nx798;


--E1_nx754 is ADC_DAC_0:adcdac|DDS:ddsi|nx754
--operation mode is normal

E1_nx754 = E1_bytes2send_47 & (E1_nx794 # E1_bytes2send_23 & E1_nx799) # !E1_bytes2send_47 & E1_bytes2send_23 & E1_nx799;


--E1_nx755 is ADC_DAC_0:adcdac|DDS:ddsi|nx755
--operation mode is normal

E1_nx755 = E1_bytes2send_39 & (E1_nx796 # E1_iword2send_7 & E1_nx793) # !E1_bytes2send_39 & E1_iword2send_7 & E1_nx793;


--E1_nx756 is ADC_DAC_0:adcdac|DDS:ddsi|nx756
--operation mode is normal

E1_nx756 = E1_bytes2send_15 & (E1_nx795 # E1_bytes2send_7 & E1_nx797) # !E1_bytes2send_15 & E1_bytes2send_7 & E1_nx797;


--E1_nx757 is ADC_DAC_0:adcdac|DDS:ddsi|nx757
--operation mode is normal

E1_nx757 = E1_sm_sr_4 & (E1_byte_send_5 # E1_bytes2send_30 & E1_nx798) # !E1_sm_sr_4 & E1_bytes2send_30 & E1_nx798;


--E1_nx758 is ADC_DAC_0:adcdac|DDS:ddsi|nx758
--operation mode is normal

E1_nx758 = E1_bytes2send_46 & (E1_nx794 # E1_bytes2send_22 & E1_nx799) # !E1_bytes2send_46 & E1_bytes2send_22 & E1_nx799;


--E1_nx759 is ADC_DAC_0:adcdac|DDS:ddsi|nx759
--operation mode is normal

E1_nx759 = E1_bytes2send_38 & (E1_nx796 # E1_iword2send_6 & E1_nx793) # !E1_bytes2send_38 & E1_iword2send_6 & E1_nx793;


--E1_nx760 is ADC_DAC_0:adcdac|DDS:ddsi|nx760
--operation mode is normal

E1_nx760 = E1_bytes2send_14 & (E1_nx795 # E1_bytes2send_6 & E1_nx797) # !E1_bytes2send_14 & E1_bytes2send_6 & E1_nx797;


--E1_nx761 is ADC_DAC_0:adcdac|DDS:ddsi|nx761
--operation mode is normal

E1_nx761 = E1_sm_sr_4 & (E1_byte_send_4 # E1_bytes2send_29 & E1_nx798) # !E1_sm_sr_4 & E1_bytes2send_29 & E1_nx798;


--E1_nx762 is ADC_DAC_0:adcdac|DDS:ddsi|nx762
--operation mode is normal

E1_nx762 = E1_bytes2send_45 & (E1_nx794 # E1_bytes2send_21 & E1_nx799) # !E1_bytes2send_45 & E1_bytes2send_21 & E1_nx799;


--E1_nx763 is ADC_DAC_0:adcdac|DDS:ddsi|nx763
--operation mode is normal

E1_nx763 = E1_bytes2send_37 & (E1_nx796 # E1_iword2send_5 & E1_nx793) # !E1_bytes2send_37 & E1_iword2send_5 & E1_nx793;


--E1_nx764 is ADC_DAC_0:adcdac|DDS:ddsi|nx764
--operation mode is normal

E1_nx764 = E1_bytes2send_13 & (E1_nx795 # E1_bytes2send_5 & E1_nx797) # !E1_bytes2send_13 & E1_bytes2send_5 & E1_nx797;


--E1_nx765 is ADC_DAC_0:adcdac|DDS:ddsi|nx765
--operation mode is normal

E1_nx765 = E1_sm_sr_4 & (E1_byte_send_3 # E1_bytes2send_28 & E1_nx798) # !E1_sm_sr_4 & E1_bytes2send_28 & E1_nx798;


--E1_nx766 is ADC_DAC_0:adcdac|DDS:ddsi|nx766
--operation mode is normal

E1_nx766 = E1_bytes2send_44 & (E1_nx794 # E1_bytes2send_20 & E1_nx799) # !E1_bytes2send_44 & E1_bytes2send_20 & E1_nx799;


--E1_nx767 is ADC_DAC_0:adcdac|DDS:ddsi|nx767
--operation mode is normal

E1_nx767 = E1_bytes2send_36 & (E1_nx796 # E1_iword2send_4 & E1_nx793) # !E1_bytes2send_36 & E1_iword2send_4 & E1_nx793;


--E1_nx768 is ADC_DAC_0:adcdac|DDS:ddsi|nx768
--operation mode is normal

E1_nx768 = E1_bytes2send_12 & (E1_nx795 # E1_bytes2send_4 & E1_nx797) # !E1_bytes2send_12 & E1_bytes2send_4 & E1_nx797;


--E1_nx769 is ADC_DAC_0:adcdac|DDS:ddsi|nx769
--operation mode is normal

E1_nx769 = E1_sm_sr_4 & (E1_byte_send_2 # E1_bytes2send_27 & E1_nx798) # !E1_sm_sr_4 & E1_bytes2send_27 & E1_nx798;


--E1_nx770 is ADC_DAC_0:adcdac|DDS:ddsi|nx770
--operation mode is normal

E1_nx770 = E1_bytes2send_43 & (E1_nx794 # E1_bytes2send_19 & E1_nx799) # !E1_bytes2send_43 & E1_bytes2send_19 & E1_nx799;


--E1_nx771 is ADC_DAC_0:adcdac|DDS:ddsi|nx771
--operation mode is normal

E1_nx771 = E1_bytes2send_35 & (E1_nx796 # E1_iword2send_3 & E1_nx793) # !E1_bytes2send_35 & E1_iword2send_3 & E1_nx793;


--E1_nx772 is ADC_DAC_0:adcdac|DDS:ddsi|nx772
--operation mode is normal

E1_nx772 = E1_bytes2send_11 & (E1_nx795 # E1_bytes2send_3 & E1_nx797) # !E1_bytes2send_11 & E1_bytes2send_3 & E1_nx797;


--E1_nx773 is ADC_DAC_0:adcdac|DDS:ddsi|nx773
--operation mode is normal

E1_nx773 = E1_sm_sr_4 & (E1_byte_send_1 # E1_bytes2send_26 & E1_nx798) # !E1_sm_sr_4 & E1_bytes2send_26 & E1_nx798;


--E1_nx774 is ADC_DAC_0:adcdac|DDS:ddsi|nx774
--operation mode is normal

E1_nx774 = E1_bytes2send_42 & (E1_nx794 # E1_bytes2send_18 & E1_nx799) # !E1_bytes2send_42 & E1_bytes2send_18 & E1_nx799;


--E1_nx775 is ADC_DAC_0:adcdac|DDS:ddsi|nx775
--operation mode is normal

E1_nx775 = E1_bytes2send_34 & (E1_nx796 # E1_iword2send_2 & E1_nx793) # !E1_bytes2send_34 & E1_iword2send_2 & E1_nx793;


--E1_nx776 is ADC_DAC_0:adcdac|DDS:ddsi|nx776
--operation mode is normal

E1_nx776 = E1_bytes2send_10 & (E1_nx795 # E1_bytes2send_2 & E1_nx797) # !E1_bytes2send_10 & E1_bytes2send_2 & E1_nx797;


--E1_nx777 is ADC_DAC_0:adcdac|DDS:ddsi|nx777
--operation mode is normal

E1_nx777 = E1_sm_sr_4 & (E1_byte_send_0 # E1_bytes2send_25 & E1_nx798) # !E1_sm_sr_4 & E1_bytes2send_25 & E1_nx798;


--E1_nx778 is ADC_DAC_0:adcdac|DDS:ddsi|nx778
--operation mode is normal

E1_nx778 = E1_bytes2send_41 & (E1_nx794 # E1_bytes2send_17 & E1_nx799) # !E1_bytes2send_41 & E1_bytes2send_17 & E1_nx799;


--E1_nx779 is ADC_DAC_0:adcdac|DDS:ddsi|nx779
--operation mode is normal

E1_nx779 = E1_bytes2send_33 & (E1_nx796 # E1_iword2send_1 & E1_nx793) # !E1_bytes2send_33 & E1_iword2send_1 & E1_nx793;


--E1_nx780 is ADC_DAC_0:adcdac|DDS:ddsi|nx780
--operation mode is normal

E1_nx780 = E1_bytes2send_9 & (E1_nx795 # E1_bytes2send_1 & E1_nx797) # !E1_bytes2send_9 & E1_bytes2send_1 & E1_nx797;


--E1_nx781 is ADC_DAC_0:adcdac|DDS:ddsi|nx781
--operation mode is normal

E1_nx781 = E1_bytes2send_40 & (E1_nx794 # E1_bytes2send_16 & E1_nx799) # !E1_bytes2send_40 & E1_bytes2send_16 & E1_nx799;


--E1_nx782 is ADC_DAC_0:adcdac|DDS:ddsi|nx782
--operation mode is normal

E1_nx782 = E1_bytes2send_32 & (E1_nx796 # E1_iword2send_0 & E1_nx793) # !E1_bytes2send_32 & E1_iword2send_0 & E1_nx793;


--E1_nx783 is ADC_DAC_0:adcdac|DDS:ddsi|nx783
--operation mode is normal

E1_nx783 = E1_bytes2send_8 & (E1_nx795 # E1_bytes2send_0 & E1_nx797) # !E1_bytes2send_8 & E1_bytes2send_0 & E1_nx797;


--E1_nx784 is ADC_DAC_0:adcdac|DDS:ddsi|nx784
--operation mode is normal

E1_nx784 = E1_byte_counter_2 # E1_byte_counter_1;


--E1_a_1 is ADC_DAC_0:adcdac|DDS:ddsi|a_1
--operation mode is normal

E1_a_1 = !X1_request_46 & !X1_request_47 & !X1_request_48;


--E1_nx785 is ADC_DAC_0:adcdac|DDS:ddsi|nx785
--operation mode is normal

E1_nx785 = !X1_request_46 & X1_request_47 & !X1_request_48;


--E1_nx786 is ADC_DAC_0:adcdac|DDS:ddsi|nx786
--operation mode is normal

E1_nx786 = !E1_iword2send_7 # !E1_sm_top_1;


--E1_a_3 is ADC_DAC_0:adcdac|DDS:ddsi|a_3
--operation mode is normal

E1_a_3 = !X1_request_46 & !X1_request_47 & X1_request_48;


--E1_nx787 is ADC_DAC_0:adcdac|DDS:ddsi|nx787
--operation mode is normal

E1_nx787 = !X1_request_46 & X1_request_47 & X1_request_48;


--E1_nx788 is ADC_DAC_0:adcdac|DDS:ddsi|nx788
--operation mode is normal

E1_nx788 = E1_sm_top_5 # E1_sm_top_3;


--E1_nx789 is ADC_DAC_0:adcdac|DDS:ddsi|nx789
--operation mode is normal

E1_nx789 = E1_iword2send_0 # !E1_iword2send_1;


--E1_nx790 is ADC_DAC_0:adcdac|DDS:ddsi|nx790
--operation mode is normal

E1_nx790 = !E1_clkdivs # !E1_sm_sr_5;


--E1_nx791 is ADC_DAC_0:adcdac|DDS:ddsi|nx791
--operation mode is normal

E1_nx791 = E1_sm_top_4 # E1_sm_top_2;


--E1_nx792 is ADC_DAC_0:adcdac|DDS:ddsi|nx792
--operation mode is normal

E1_nx792 = E1_sm_sr_3 # E1_sm_sr_1;


--E1_nx793 is ADC_DAC_0:adcdac|DDS:ddsi|nx793
--operation mode is normal

E1_nx793 = !E1_byte_counter_2 & !E1_byte_counter_1 & !E1_byte_counter_0 & !E1_nx538;


--E1_nx794 is ADC_DAC_0:adcdac|DDS:ddsi|nx794
--operation mode is normal

E1_nx794 = E1_byte_counter_2 & E1_byte_counter_1 & !E1_byte_counter_0 & !E1_nx538;


--E1_nx795 is ADC_DAC_0:adcdac|DDS:ddsi|nx795
--operation mode is normal

E1_nx795 = !E1_byte_counter_2 & E1_byte_counter_1 & !E1_byte_counter_0 & !E1_nx538;


--E1_nx796 is ADC_DAC_0:adcdac|DDS:ddsi|nx796
--operation mode is normal

E1_nx796 = E1_byte_counter_2 & !E1_byte_counter_1 & E1_byte_counter_0 & !E1_nx538;


--E1_nx797 is ADC_DAC_0:adcdac|DDS:ddsi|nx797
--operation mode is normal

E1_nx797 = !E1_byte_counter_2 & !E1_byte_counter_1 & E1_byte_counter_0 & !E1_nx538;


--E1_nx798 is ADC_DAC_0:adcdac|DDS:ddsi|nx798
--operation mode is normal

E1_nx798 = E1_byte_counter_2 & !E1_byte_counter_1 & !E1_byte_counter_0 & !E1_nx538;


--E1_nx799 is ADC_DAC_0:adcdac|DDS:ddsi|nx799
--operation mode is normal

E1_nx799 = E1_byte_counter_1 & E1_byte_counter_0 & !E1_nx538;


--E1_nx800 is ADC_DAC_0:adcdac|DDS:ddsi|nx800
--operation mode is normal

E1_nx800 = E1_nx538 # !E1_clkdivs;


--E1_nx801 is ADC_DAC_0:adcdac|DDS:ddsi|nx801
--operation mode is normal

E1_nx801 = E1_sm_top_1 & E1_iword2send_7 & (!E1_sm_sr_5 # !E1_sm_top_5);


--E1_nx802 is ADC_DAC_0:adcdac|DDS:ddsi|nx802
--operation mode is normal

E1_nx802 = E1_sm_top_5 & E1_sm_sr_5 & !E1_byte_counter_0;


--E1_nx803 is ADC_DAC_0:adcdac|DDS:ddsi|nx803
--operation mode is normal

E1_nx803 = E1_sm_top_1 & !E1_iword2send_3;


--E1_nx804 is ADC_DAC_0:adcdac|DDS:ddsi|nx804
--operation mode is normal

E1_nx804 = E1_sm_top_5 & E1_sm_sr_5 & E1_byte_counter_0;


--E1_nx805 is ADC_DAC_0:adcdac|DDS:ddsi|nx805
--operation mode is normal

E1_nx805 = E1_iword2send_7 & (E1_a_3 # E1_bytes_rcvd_23 & E1_nx785) # !E1_iword2send_7 & E1_bytes_rcvd_23 & E1_nx785;


--E1_nx806 is ADC_DAC_0:adcdac|DDS:ddsi|nx806
--operation mode is normal

E1_nx806 = E1_iword2send_6 & (E1_a_3 # E1_bytes_rcvd_22 & E1_nx785) # !E1_iword2send_6 & E1_bytes_rcvd_22 & E1_nx785;


--E1_nx807 is ADC_DAC_0:adcdac|DDS:ddsi|nx807
--operation mode is normal

E1_nx807 = E1_iword2send_5 & (E1_a_3 # E1_bytes_rcvd_21 & E1_nx785) # !E1_iword2send_5 & E1_bytes_rcvd_21 & E1_nx785;


--E1_nx808 is ADC_DAC_0:adcdac|DDS:ddsi|nx808
--operation mode is normal

E1_nx808 = E1_iword2send_4 & (E1_a_3 # E1_bytes_rcvd_20 & E1_nx785) # !E1_iword2send_4 & E1_bytes_rcvd_20 & E1_nx785;


--E1_nx809 is ADC_DAC_0:adcdac|DDS:ddsi|nx809
--operation mode is normal

E1_nx809 = E1_iword2send_3 & (E1_a_3 # E1_bytes_rcvd_19 & E1_nx785) # !E1_iword2send_3 & E1_bytes_rcvd_19 & E1_nx785;


--E1_nx810 is ADC_DAC_0:adcdac|DDS:ddsi|nx810
--operation mode is normal

E1_nx810 = E1_iword2send_2 & (E1_a_3 # E1_bytes_rcvd_18 & E1_nx785) # !E1_iword2send_2 & E1_bytes_rcvd_18 & E1_nx785;


--E1_nx811 is ADC_DAC_0:adcdac|DDS:ddsi|nx811
--operation mode is normal

E1_nx811 = E1_iword2send_1 & (E1_a_3 # E1_bytes_rcvd_17 & E1_nx785) # !E1_iword2send_1 & E1_bytes_rcvd_17 & E1_nx785;


--E1_nx812 is ADC_DAC_0:adcdac|DDS:ddsi|nx812
--operation mode is normal

E1_nx812 = E1_iword2send_0 & (E1_a_3 # E1_bytes_rcvd_16 & E1_nx785) # !E1_iword2send_0 & E1_bytes_rcvd_16 & E1_nx785;


--E1_nx813 is ADC_DAC_0:adcdac|DDS:ddsi|nx813
--operation mode is normal

E1_nx813 = E1_bytes2send_15 & (E1_a_1 # E1_bytes_rcvd_15 & E1_nx785) # !E1_bytes2send_15 & E1_bytes_rcvd_15 & E1_nx785;


--E1_nx814 is ADC_DAC_0:adcdac|DDS:ddsi|nx814
--operation mode is normal

E1_nx814 = E1_bytes2send_14 & (E1_a_1 # E1_bytes_rcvd_14 & E1_nx785) # !E1_bytes2send_14 & E1_bytes_rcvd_14 & E1_nx785;


--E1_nx815 is ADC_DAC_0:adcdac|DDS:ddsi|nx815
--operation mode is normal

E1_nx815 = E1_bytes2send_13 & (E1_a_1 # E1_bytes_rcvd_13 & E1_nx785) # !E1_bytes2send_13 & E1_bytes_rcvd_13 & E1_nx785;


--E1_nx816 is ADC_DAC_0:adcdac|DDS:ddsi|nx816
--operation mode is normal

E1_nx816 = E1_bytes2send_12 & (E1_a_1 # E1_bytes_rcvd_12 & E1_nx785) # !E1_bytes2send_12 & E1_bytes_rcvd_12 & E1_nx785;


--E1_nx817 is ADC_DAC_0:adcdac|DDS:ddsi|nx817
--operation mode is normal

E1_nx817 = E1_bytes2send_11 & (E1_a_1 # E1_bytes_rcvd_11 & E1_nx785) # !E1_bytes2send_11 & E1_bytes_rcvd_11 & E1_nx785;


--E1_nx818 is ADC_DAC_0:adcdac|DDS:ddsi|nx818
--operation mode is normal

E1_nx818 = E1_bytes2send_10 & (E1_a_1 # E1_bytes_rcvd_10 & E1_nx785) # !E1_bytes2send_10 & E1_bytes_rcvd_10 & E1_nx785;


--E1_nx819 is ADC_DAC_0:adcdac|DDS:ddsi|nx819
--operation mode is normal

E1_nx819 = E1_bytes2send_9 & (E1_a_1 # E1_bytes_rcvd_9 & E1_nx785) # !E1_bytes2send_9 & E1_bytes_rcvd_9 & E1_nx785;


--E1_nx820 is ADC_DAC_0:adcdac|DDS:ddsi|nx820
--operation mode is normal

E1_nx820 = E1_bytes2send_8 & (E1_a_1 # E1_bytes_rcvd_8 & E1_nx785) # !E1_bytes2send_8 & E1_bytes_rcvd_8 & E1_nx785;


--E1_nx821 is ADC_DAC_0:adcdac|DDS:ddsi|nx821
--operation mode is normal

E1_nx821 = E1_bytes2send_39 & (E1_a_3 # E1_bytes_rcvd_39 & E1_nx787) # !E1_bytes2send_39 & E1_bytes_rcvd_39 & E1_nx787;


--E1_nx822 is ADC_DAC_0:adcdac|DDS:ddsi|nx822
--operation mode is normal

E1_nx822 = E1_bytes2send_7 & (E1_a_1 # E1_bytes_rcvd_7 & E1_nx785) # !E1_bytes2send_7 & E1_bytes_rcvd_7 & E1_nx785;


--E1_nx823 is ADC_DAC_0:adcdac|DDS:ddsi|nx823
--operation mode is normal

E1_nx823 = E1_bytes2send_38 & (E1_a_3 # E1_bytes_rcvd_38 & E1_nx787) # !E1_bytes2send_38 & E1_bytes_rcvd_38 & E1_nx787;


--E1_nx824 is ADC_DAC_0:adcdac|DDS:ddsi|nx824
--operation mode is normal

E1_nx824 = E1_bytes2send_6 & (E1_a_1 # E1_bytes_rcvd_6 & E1_nx785) # !E1_bytes2send_6 & E1_bytes_rcvd_6 & E1_nx785;


--E1_nx825 is ADC_DAC_0:adcdac|DDS:ddsi|nx825
--operation mode is normal

E1_nx825 = E1_bytes2send_37 & (E1_a_3 # E1_bytes_rcvd_37 & E1_nx787) # !E1_bytes2send_37 & E1_bytes_rcvd_37 & E1_nx787;


--E1_nx826 is ADC_DAC_0:adcdac|DDS:ddsi|nx826
--operation mode is normal

E1_nx826 = E1_bytes2send_5 & (E1_a_1 # E1_bytes_rcvd_5 & E1_nx785) # !E1_bytes2send_5 & E1_bytes_rcvd_5 & E1_nx785;


--E1_nx827 is ADC_DAC_0:adcdac|DDS:ddsi|nx827
--operation mode is normal

E1_nx827 = E1_bytes2send_36 & (E1_a_3 # E1_bytes_rcvd_36 & E1_nx787) # !E1_bytes2send_36 & E1_bytes_rcvd_36 & E1_nx787;


--E1_nx828 is ADC_DAC_0:adcdac|DDS:ddsi|nx828
--operation mode is normal

E1_nx828 = E1_bytes2send_4 & (E1_a_1 # E1_bytes_rcvd_4 & E1_nx785) # !E1_bytes2send_4 & E1_bytes_rcvd_4 & E1_nx785;


--E1_nx829 is ADC_DAC_0:adcdac|DDS:ddsi|nx829
--operation mode is normal

E1_nx829 = E1_bytes2send_35 & (E1_a_3 # E1_bytes_rcvd_35 & E1_nx787) # !E1_bytes2send_35 & E1_bytes_rcvd_35 & E1_nx787;


--E1_nx830 is ADC_DAC_0:adcdac|DDS:ddsi|nx830
--operation mode is normal

E1_nx830 = E1_bytes2send_3 & (E1_a_1 # E1_bytes_rcvd_3 & E1_nx785) # !E1_bytes2send_3 & E1_bytes_rcvd_3 & E1_nx785;


--E1_nx831 is ADC_DAC_0:adcdac|DDS:ddsi|nx831
--operation mode is normal

E1_nx831 = E1_bytes2send_34 & (E1_a_3 # E1_bytes_rcvd_34 & E1_nx787) # !E1_bytes2send_34 & E1_bytes_rcvd_34 & E1_nx787;


--E1_nx832 is ADC_DAC_0:adcdac|DDS:ddsi|nx832
--operation mode is normal

E1_nx832 = E1_bytes2send_2 & (E1_a_1 # E1_bytes_rcvd_2 & E1_nx785) # !E1_bytes2send_2 & E1_bytes_rcvd_2 & E1_nx785;


--E1_nx833 is ADC_DAC_0:adcdac|DDS:ddsi|nx833
--operation mode is normal

E1_nx833 = E1_bytes2send_33 & (E1_a_3 # E1_bytes_rcvd_33 & E1_nx787) # !E1_bytes2send_33 & E1_bytes_rcvd_33 & E1_nx787;


--E1_nx834 is ADC_DAC_0:adcdac|DDS:ddsi|nx834
--operation mode is normal

E1_nx834 = E1_bytes2send_1 & (E1_a_1 # E1_bytes_rcvd_1 & E1_nx785) # !E1_bytes2send_1 & E1_bytes_rcvd_1 & E1_nx785;


--E1_nx835 is ADC_DAC_0:adcdac|DDS:ddsi|nx835
--operation mode is normal

E1_nx835 = E1_bytes2send_32 & (E1_a_3 # E1_bytes_rcvd_32 & E1_nx787) # !E1_bytes2send_32 & E1_bytes_rcvd_32 & E1_nx787;


--E1_nx836 is ADC_DAC_0:adcdac|DDS:ddsi|nx836
--operation mode is normal

E1_nx836 = E1_bytes2send_0 & (E1_a_1 # E1_bytes_rcvd_0 & E1_nx785) # !E1_bytes2send_0 & E1_bytes_rcvd_0 & E1_nx785;


--E1_nx837 is ADC_DAC_0:adcdac|DDS:ddsi|nx837
--operation mode is normal

E1_nx837 = E1_nx803 & (E1_iword2send_2 & (E1_iword2send_0 # !E1_iword2send_1) # !E1_iword2send_2 & E1_iword2send_1);


--E1_nx838 is ADC_DAC_0:adcdac|DDS:ddsi|nx838
--operation mode is normal

E1_nx838 = E1_sm_top_1 & (E1_iword2send_3 & (E1_iword2send_2 # E1_nx789) # !E1_iword2send_3 & !E1_iword2send_2);


--E1_nx839 is ADC_DAC_0:adcdac|DDS:ddsi|nx839
--operation mode is normal

E1_nx839 = E1_byte_counter_2 # E1_byte_counter_1 # E1_byte_counter_0 # !E1_sm_top_6;


--E1_nx840 is ADC_DAC_0:adcdac|DDS:ddsi|nx840
--operation mode is normal

E1_nx840 = E1_sm_top_6 # E1_sm_top_5 # E1_sm_top_3;


--E1_nx841 is ADC_DAC_0:adcdac|DDS:ddsi|nx841
--operation mode is normal

E1_nx841 = E1_sm_top_5 & E1_sm_sr_5 & (E1_nx784 # !E1_byte_counter_0);


--E1_nx842 is ADC_DAC_0:adcdac|DDS:ddsi|nx842
--operation mode is normal

E1_nx842 = E1_sm_sr_2 & (!E1_bit_counter_0 # !E1_bit_counter_1 # !E1_bit_counter_2);


--E1_nx843 is ADC_DAC_0:adcdac|DDS:ddsi|nx843
--operation mode is normal

E1_nx843 = E1_bit_counter_2 & E1_bit_counter_1 & E1_bit_counter_0;


--E1_nx844 is ADC_DAC_0:adcdac|DDS:ddsi|nx844
--operation mode is normal

E1_nx844 = E1_bytes2send_24 & E1_nx798;


--E1_nx845 is ADC_DAC_0:adcdac|DDS:ddsi|nx845
--operation mode is normal

E1_nx845 = E1_start_sm & !E1_read_flag;


--E1_nx846 is ADC_DAC_0:adcdac|DDS:ddsi|nx846
--operation mode is normal

E1_nx846 = E1_sm_top_1 & E1_sm_sr_5 & !E1_iword2send_7;


--E1_nx847 is ADC_DAC_0:adcdac|DDS:ddsi|nx847
--operation mode is normal

E1_nx847 = E1_byte_counter_0 & !E1_nx784 & E1_nx788 & !E1_nx790;


--E1_nx848 is ADC_DAC_0:adcdac|DDS:ddsi|nx848
--operation mode is normal

E1_nx848 = E1_sm_top_1 & !E1_nx789 & (E1_iword2send_3 $ E1_iword2send_2);


--E1_nx849 is ADC_DAC_0:adcdac|DDS:ddsi|nx849
--operation mode is normal

E1_nx849 = E1_sm_top_6 & E1_b_0_dup_234;


--E1_nx850 is ADC_DAC_0:adcdac|DDS:ddsi|nx850
--operation mode is normal

E1_nx850 = !E1_sm_top_5 & !E1_sm_top_3 & (E1_sm_sr_5 # !E1_sm_top_1);


--E1_nx851 is ADC_DAC_0:adcdac|DDS:ddsi|nx851
--operation mode is normal

E1_nx851 = !X1_request_46 & X1_request_47 & X1_request_48 & E1_bytes_rcvd_40;


--E1_nx852 is ADC_DAC_0:adcdac|DDS:ddsi|nx852
--operation mode is normal

E1_nx852 = !X1_request_46 & X1_request_47 & X1_request_48 & E1_bytes_rcvd_41;


--E1_nx853 is ADC_DAC_0:adcdac|DDS:ddsi|nx853
--operation mode is normal

E1_nx853 = !X1_request_46 & X1_request_47 & X1_request_48 & E1_bytes_rcvd_42;


--E1_nx854 is ADC_DAC_0:adcdac|DDS:ddsi|nx854
--operation mode is normal

E1_nx854 = !X1_request_46 & X1_request_47 & X1_request_48 & E1_bytes_rcvd_43;


--E1_nx855 is ADC_DAC_0:adcdac|DDS:ddsi|nx855
--operation mode is normal

E1_nx855 = !X1_request_46 & X1_request_47 & X1_request_48 & E1_bytes_rcvd_44;


--E1_nx856 is ADC_DAC_0:adcdac|DDS:ddsi|nx856
--operation mode is normal

E1_nx856 = !X1_request_46 & X1_request_47 & X1_request_48 & E1_bytes_rcvd_45;


--E1_nx857 is ADC_DAC_0:adcdac|DDS:ddsi|nx857
--operation mode is normal

E1_nx857 = !X1_request_46 & X1_request_47 & X1_request_48 & E1_bytes_rcvd_46;


--E1_nx858 is ADC_DAC_0:adcdac|DDS:ddsi|nx858
--operation mode is normal

E1_nx858 = !X1_request_46 & X1_request_47 & X1_request_48 & E1_bytes_rcvd_47;


--E1_nx859 is ADC_DAC_0:adcdac|DDS:ddsi|nx859
--operation mode is normal

E1_nx859 = !X1_request_46 & !X1_request_47;


--E1_RDATA_31 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_31
--operation mode is normal

E1_RDATA_31 = E1_bytes2send_31 & (E1_a_1 # E1_bytes_rcvd_31 & E1_nx785) # !E1_bytes2send_31 & E1_bytes_rcvd_31 & E1_nx785;


--E1_RDATA_30 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_30
--operation mode is normal

E1_RDATA_30 = E1_bytes2send_30 & (E1_a_1 # E1_bytes_rcvd_30 & E1_nx785) # !E1_bytes2send_30 & E1_bytes_rcvd_30 & E1_nx785;


--E1_RDATA_29 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_29
--operation mode is normal

E1_RDATA_29 = E1_bytes2send_29 & (E1_a_1 # E1_bytes_rcvd_29 & E1_nx785) # !E1_bytes2send_29 & E1_bytes_rcvd_29 & E1_nx785;


--E1_RDATA_28 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_28
--operation mode is normal

E1_RDATA_28 = E1_bytes2send_28 & (E1_a_1 # E1_bytes_rcvd_28 & E1_nx785) # !E1_bytes2send_28 & E1_bytes_rcvd_28 & E1_nx785;


--E1_RDATA_27 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_27
--operation mode is normal

E1_RDATA_27 = E1_bytes2send_27 & (E1_a_1 # E1_bytes_rcvd_27 & E1_nx785) # !E1_bytes2send_27 & E1_bytes_rcvd_27 & E1_nx785;


--E1_RDATA_26 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_26
--operation mode is normal

E1_RDATA_26 = E1_bytes2send_26 & (E1_a_1 # E1_bytes_rcvd_26 & E1_nx785) # !E1_bytes2send_26 & E1_bytes_rcvd_26 & E1_nx785;


--E1_RDATA_25 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_25
--operation mode is normal

E1_RDATA_25 = E1_bytes2send_25 & (E1_a_1 # E1_bytes_rcvd_25 & E1_nx785) # !E1_bytes2send_25 & E1_bytes_rcvd_25 & E1_nx785;


--E1_RDATA_24 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_24
--operation mode is normal

E1_RDATA_24 = E1_bytes2send_24 & (E1_a_1 # E1_bytes_rcvd_24 & E1_nx785) # !E1_bytes2send_24 & E1_bytes_rcvd_24 & E1_nx785;


--E1_RDATA_23 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_23
--operation mode is normal

E1_RDATA_23 = E1_nx805 # E1_bytes2send_23 & E1_a_1;


--E1_RDATA_22 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_22
--operation mode is normal

E1_RDATA_22 = E1_nx806 # E1_bytes2send_22 & E1_a_1;


--E1_RDATA_21 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_21
--operation mode is normal

E1_RDATA_21 = E1_nx807 # E1_bytes2send_21 & E1_a_1;


--E1_RDATA_20 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_20
--operation mode is normal

E1_RDATA_20 = E1_nx808 # E1_bytes2send_20 & E1_a_1;


--E1_RDATA_19 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_19
--operation mode is normal

E1_RDATA_19 = E1_nx809 # E1_bytes2send_19 & E1_a_1;


--E1_RDATA_18 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_18
--operation mode is normal

E1_RDATA_18 = E1_nx810 # E1_bytes2send_18 & E1_a_1;


--E1_RDATA_17 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_17
--operation mode is normal

E1_RDATA_17 = E1_nx811 # E1_bytes2send_17 & E1_a_1;


--E1_RDATA_16 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_16
--operation mode is normal

E1_RDATA_16 = E1_nx812 # E1_bytes2send_16 & E1_a_1;


--E1_RDATA_15 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_15
--operation mode is normal

E1_RDATA_15 = E1_nx813 # E1_nx858 # E1_bytes2send_47 & E1_a_3;


--E1_RDATA_14 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_14
--operation mode is normal

E1_RDATA_14 = E1_nx814 # E1_nx857 # E1_bytes2send_46 & E1_a_3;


--E1_RDATA_13 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_13
--operation mode is normal

E1_RDATA_13 = E1_nx815 # E1_nx856 # E1_bytes2send_45 & E1_a_3;


--E1_RDATA_12 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_12
--operation mode is normal

E1_RDATA_12 = E1_nx816 # E1_nx855 # E1_bytes2send_44 & E1_a_3;


--E1_RDATA_11 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_11
--operation mode is normal

E1_RDATA_11 = E1_nx817 # E1_nx854 # E1_bytes2send_43 & E1_a_3;


--E1_RDATA_10 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_10
--operation mode is normal

E1_RDATA_10 = E1_nx818 # E1_nx853 # E1_bytes2send_42 & E1_a_3;


--E1_RDATA_9 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_9
--operation mode is normal

E1_RDATA_9 = E1_nx819 # E1_nx852 # E1_bytes2send_41 & E1_a_3;


--E1_RDATA_8 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_8
--operation mode is normal

E1_RDATA_8 = E1_nx820 # E1_nx851 # E1_bytes2send_40 & E1_a_3;


--E1_RDATA_7 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_7
--operation mode is normal

E1_RDATA_7 = E1_nx821 # E1_nx822 # X1_request_46 & E1_config_7;


--E1_RDATA_6 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_6
--operation mode is normal

E1_RDATA_6 = E1_nx823 # E1_nx824 # X1_request_46 & E1_config_6;


--E1_RDATA_5 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_5
--operation mode is normal

E1_RDATA_5 = E1_nx825 # E1_nx826 # X1_request_46 & E1_DDS_FSK;


--E1_RDATA_4 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_4
--operation mode is normal

E1_RDATA_4 = E1_nx827 # E1_nx828 # X1_request_46 & E1_DDS_ShKey;


--E1_RDATA_3 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_3
--operation mode is normal

E1_RDATA_3 = E1_nx829 # E1_nx830 # X1_request_46 & E1_config_3;


--E1_RDATA_2 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_2
--operation mode is normal

E1_RDATA_2 = E1_nx831 # E1_nx832 # X1_request_46 & E1_config_2;


--E1_RDATA_1 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_1
--operation mode is normal

E1_RDATA_1 = E1_nx833 # E1_nx834 # X1_request_46 & E1_config_1;


--E1_RDATA_0 is ADC_DAC_0:adcdac|DDS:ddsi|RDATA_0
--operation mode is normal

E1_RDATA_0 = E1_nx835 # E1_nx836 # X1_request_46 & E1_config_0;


--E1_DDS_UDCLK is ADC_DAC_0:adcdac|DDS:ddsi|DDS_UDCLK
--operation mode is normal

E1_DDS_UDCLK = E1_config_2 # E1_config_3 & !E1_NOT_udclk;


--E1_DDS_MRST is ADC_DAC_0:adcdac|DDS:ddsi|DDS_MRST
--operation mode is normal

E1_DDS_MRST = E1_config_0 # !V1_chipRST_n;


--E1_DDS_MCLK is ADC_DAC_0:adcdac|DDS:ddsi|DDS_MCLK
--operation mode is normal

E1_DDS_MCLK = U1__clk1 & E1_config_1;


--E1_bit_counter_0 is ADC_DAC_0:adcdac|DDS:ddsi|bit_counter_0
--operation mode is normal

E1_bit_counter_0_lut_out = E1_bit_counter_0;
E1_bit_counter_0_sload_eqn = (E1_nx2701 & E1_nx2698) # (!E1_nx2701 & E1_bit_counter_0_lut_out);
E1_bit_counter_0 = DFFEA(E1_bit_counter_0_sload_eqn, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_bit_counter_1 is ADC_DAC_0:adcdac|DDS:ddsi|bit_counter_1
--operation mode is normal

E1_bit_counter_1_lut_out = E1_bit_counter_1;
E1_bit_counter_1_sload_eqn = (E1_nx2701 & E1_nx2685) # (!E1_nx2701 & E1_bit_counter_1_lut_out);
E1_bit_counter_1 = DFFEA(E1_bit_counter_1_sload_eqn, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_bit_counter_2 is ADC_DAC_0:adcdac|DDS:ddsi|bit_counter_2
--operation mode is normal

E1_bit_counter_2_lut_out = E1_bit_counter_2;
E1_bit_counter_2_sload_eqn = (E1_nx2701 & E1_nx2672) # (!E1_nx2701 & E1_bit_counter_2_lut_out);
E1_bit_counter_2 = DFFEA(E1_bit_counter_2_sload_eqn, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_byte_counter_0 is ADC_DAC_0:adcdac|DDS:ddsi|byte_counter_0
--operation mode is normal

E1_byte_counter_0_lut_out = E1_nx749 # E1_nx848 # E1_b_0_dup_240 & E1_nx840;
E1_byte_counter_0 = DFFEA(E1_byte_counter_0_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx1467, , );


--E1_byte_counter_1 is ADC_DAC_0:adcdac|DDS:ddsi|byte_counter_1
--operation mode is normal

E1_byte_counter_1_lut_out = E1_nx749 # E1_nx750 # E1_nx838 # E1_nx849;
E1_byte_counter_1 = DFFEA(E1_byte_counter_1_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx1467, , );


--E1_byte_counter_2 is ADC_DAC_0:adcdac|DDS:ddsi|byte_counter_2
--operation mode is normal

E1_byte_counter_2_lut_out = E1_nx749 # E1_nx837 # E1_b_0 & E1_nx840;
E1_byte_counter_2 = DFFEA(E1_byte_counter_2_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx1467, , );


--E1_byte_recv_0 is ADC_DAC_0:adcdac|DDS:ddsi|byte_recv_0
--operation mode is normal

E1_byte_recv_0_lut_out = DDS_SDO & (E1_sm_sr_1 # E1_byte_recv_0) # !DDS_SDO & !E1_sm_sr_1 & E1_byte_recv_0;
E1_byte_recv_0 = DFFEA(E1_byte_recv_0_lut_out, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_byte_recv_1 is ADC_DAC_0:adcdac|DDS:ddsi|byte_recv_1
--operation mode is normal

E1_byte_recv_1_lut_out = E1_byte_recv_0;
E1_byte_recv_1 = DFFEA(E1_byte_recv_1_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2793, , );


--E1_byte_recv_2 is ADC_DAC_0:adcdac|DDS:ddsi|byte_recv_2
--operation mode is normal

E1_byte_recv_2_lut_out = E1_byte_recv_1;
E1_byte_recv_2 = DFFEA(E1_byte_recv_2_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2793, , );


--E1_byte_recv_3 is ADC_DAC_0:adcdac|DDS:ddsi|byte_recv_3
--operation mode is normal

E1_byte_recv_3_lut_out = E1_byte_recv_2;
E1_byte_recv_3 = DFFEA(E1_byte_recv_3_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2793, , );


--E1_byte_recv_4 is ADC_DAC_0:adcdac|DDS:ddsi|byte_recv_4
--operation mode is normal

E1_byte_recv_4_lut_out = E1_byte_recv_3;
E1_byte_recv_4 = DFFEA(E1_byte_recv_4_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2793, , );


--E1_byte_recv_5 is ADC_DAC_0:adcdac|DDS:ddsi|byte_recv_5
--operation mode is normal

E1_byte_recv_5_lut_out = E1_byte_recv_4;
E1_byte_recv_5 = DFFEA(E1_byte_recv_5_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2793, , );


--E1_byte_recv_6 is ADC_DAC_0:adcdac|DDS:ddsi|byte_recv_6
--operation mode is normal

E1_byte_recv_6_lut_out = E1_byte_recv_5;
E1_byte_recv_6 = DFFEA(E1_byte_recv_6_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2793, , );


--E1_byte_recv_7 is ADC_DAC_0:adcdac|DDS:ddsi|byte_recv_7
--operation mode is normal

E1_byte_recv_7_lut_out = E1_byte_recv_6;
E1_byte_recv_7 = DFFEA(E1_byte_recv_7_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2793, , );


--E1_byte_send_0 is ADC_DAC_0:adcdac|DDS:ddsi|byte_send_0
--operation mode is normal

E1_byte_send_0_lut_out = E1_nx781 # E1_nx782 # E1_nx783 # E1_nx844;
E1_byte_send_0 = DFFEA(E1_byte_send_0_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2817, , );


--E1_byte_send_1 is ADC_DAC_0:adcdac|DDS:ddsi|byte_send_1
--operation mode is normal

E1_byte_send_1_lut_out = E1_nx777 # E1_nx778 # E1_nx779 # E1_nx780;
E1_byte_send_1 = DFFEA(E1_byte_send_1_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2817, , );


--E1_byte_send_2 is ADC_DAC_0:adcdac|DDS:ddsi|byte_send_2
--operation mode is normal

E1_byte_send_2_lut_out = E1_nx773 # E1_nx774 # E1_nx775 # E1_nx776;
E1_byte_send_2 = DFFEA(E1_byte_send_2_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2817, , );


--E1_byte_send_3 is ADC_DAC_0:adcdac|DDS:ddsi|byte_send_3
--operation mode is normal

E1_byte_send_3_lut_out = E1_nx769 # E1_nx770 # E1_nx771 # E1_nx772;
E1_byte_send_3 = DFFEA(E1_byte_send_3_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2817, , );


--E1_byte_send_4 is ADC_DAC_0:adcdac|DDS:ddsi|byte_send_4
--operation mode is normal

E1_byte_send_4_lut_out = E1_nx765 # E1_nx766 # E1_nx767 # E1_nx768;
E1_byte_send_4 = DFFEA(E1_byte_send_4_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2817, , );


--E1_byte_send_5 is ADC_DAC_0:adcdac|DDS:ddsi|byte_send_5
--operation mode is normal

E1_byte_send_5_lut_out = E1_nx761 # E1_nx762 # E1_nx763 # E1_nx764;
E1_byte_send_5 = DFFEA(E1_byte_send_5_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2817, , );


--E1_byte_send_6 is ADC_DAC_0:adcdac|DDS:ddsi|byte_send_6
--operation mode is normal

E1_byte_send_6_lut_out = E1_nx757 # E1_nx758 # E1_nx759 # E1_nx760;
E1_byte_send_6 = DFFEA(E1_byte_send_6_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2817, , );


--E1_byte_send_7 is ADC_DAC_0:adcdac|DDS:ddsi|byte_send_7
--operation mode is normal

E1_byte_send_7_lut_out = E1_nx753 # E1_nx754 # E1_nx755 # E1_nx756;
E1_byte_send_7 = DFFEA(E1_byte_send_7_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx2817, , );


--E1_bytes2send_0 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_0
--operation mode is normal

E1_bytes2send_0_lut_out = X1_request_31;
E1_bytes2send_0 = DFFEA(E1_bytes2send_0_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx543, , );


--E1_bytes2send_1 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_1
--operation mode is normal

E1_bytes2send_1_lut_out = X1_request_30;
E1_bytes2send_1 = DFFEA(E1_bytes2send_1_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx543, , );


--E1_bytes2send_10 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_10
--operation mode is normal

E1_bytes2send_10_lut_out = E1_bytes2send_10;
E1_bytes2send_10_sload_eqn = (E1_a_1 & X1_request_21) # (!E1_a_1 & E1_bytes2send_10_lut_out);
E1_bytes2send_10 = DFFEA(E1_bytes2send_10_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_11 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_11
--operation mode is normal

E1_bytes2send_11_lut_out = E1_bytes2send_11;
E1_bytes2send_11_sload_eqn = (E1_a_1 & X1_request_20) # (!E1_a_1 & E1_bytes2send_11_lut_out);
E1_bytes2send_11 = DFFEA(E1_bytes2send_11_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_12 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_12
--operation mode is normal

E1_bytes2send_12_lut_out = E1_bytes2send_12;
E1_bytes2send_12_sload_eqn = (E1_a_1 & X1_request_19) # (!E1_a_1 & E1_bytes2send_12_lut_out);
E1_bytes2send_12 = DFFEA(E1_bytes2send_12_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_13 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_13
--operation mode is normal

E1_bytes2send_13_lut_out = E1_bytes2send_13;
E1_bytes2send_13_sload_eqn = (E1_a_1 & X1_request_18) # (!E1_a_1 & E1_bytes2send_13_lut_out);
E1_bytes2send_13 = DFFEA(E1_bytes2send_13_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_14 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_14
--operation mode is normal

E1_bytes2send_14_lut_out = E1_bytes2send_14;
E1_bytes2send_14_sload_eqn = (E1_a_1 & X1_request_17) # (!E1_a_1 & E1_bytes2send_14_lut_out);
E1_bytes2send_14 = DFFEA(E1_bytes2send_14_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_15 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_15
--operation mode is normal

E1_bytes2send_15_lut_out = E1_bytes2send_15;
E1_bytes2send_15_sload_eqn = (E1_a_1 & X1_request_16) # (!E1_a_1 & E1_bytes2send_15_lut_out);
E1_bytes2send_15 = DFFEA(E1_bytes2send_15_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_16 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_16
--operation mode is normal

E1_bytes2send_16_lut_out = E1_bytes2send_16;
E1_bytes2send_16_sload_eqn = (E1_a_1 & X1_request_15) # (!E1_a_1 & E1_bytes2send_16_lut_out);
E1_bytes2send_16 = DFFEA(E1_bytes2send_16_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_17 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_17
--operation mode is normal

E1_bytes2send_17_lut_out = E1_bytes2send_17;
E1_bytes2send_17_sload_eqn = (E1_a_1 & X1_request_14) # (!E1_a_1 & E1_bytes2send_17_lut_out);
E1_bytes2send_17 = DFFEA(E1_bytes2send_17_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_18 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_18
--operation mode is normal

E1_bytes2send_18_lut_out = E1_bytes2send_18;
E1_bytes2send_18_sload_eqn = (E1_a_1 & X1_request_13) # (!E1_a_1 & E1_bytes2send_18_lut_out);
E1_bytes2send_18 = DFFEA(E1_bytes2send_18_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_19 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_19
--operation mode is normal

E1_bytes2send_19_lut_out = E1_bytes2send_19;
E1_bytes2send_19_sload_eqn = (E1_a_1 & X1_request_12) # (!E1_a_1 & E1_bytes2send_19_lut_out);
E1_bytes2send_19 = DFFEA(E1_bytes2send_19_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_2 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_2
--operation mode is normal

E1_bytes2send_2_lut_out = X1_request_29;
E1_bytes2send_2 = DFFEA(E1_bytes2send_2_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx543, , );


--E1_bytes2send_20 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_20
--operation mode is normal

E1_bytes2send_20_lut_out = E1_bytes2send_20;
E1_bytes2send_20_sload_eqn = (E1_a_1 & X1_request_11) # (!E1_a_1 & E1_bytes2send_20_lut_out);
E1_bytes2send_20 = DFFEA(E1_bytes2send_20_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_21 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_21
--operation mode is normal

E1_bytes2send_21_lut_out = E1_bytes2send_21;
E1_bytes2send_21_sload_eqn = (E1_a_1 & X1_request_10) # (!E1_a_1 & E1_bytes2send_21_lut_out);
E1_bytes2send_21 = DFFEA(E1_bytes2send_21_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_22 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_22
--operation mode is normal

E1_bytes2send_22_lut_out = E1_bytes2send_22;
E1_bytes2send_22_sload_eqn = (E1_a_1 & X1_request_9) # (!E1_a_1 & E1_bytes2send_22_lut_out);
E1_bytes2send_22 = DFFEA(E1_bytes2send_22_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_23 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_23
--operation mode is normal

E1_bytes2send_23_lut_out = E1_bytes2send_23;
E1_bytes2send_23_sload_eqn = (E1_a_1 & X1_request_8) # (!E1_a_1 & E1_bytes2send_23_lut_out);
E1_bytes2send_23 = DFFEA(E1_bytes2send_23_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_24 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_24
--operation mode is normal

E1_bytes2send_24_lut_out = E1_bytes2send_24;
E1_bytes2send_24_sload_eqn = (E1_a_1 & X1_request_7) # (!E1_a_1 & E1_bytes2send_24_lut_out);
E1_bytes2send_24 = DFFEA(E1_bytes2send_24_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_25 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_25
--operation mode is normal

E1_bytes2send_25_lut_out = E1_bytes2send_25;
E1_bytes2send_25_sload_eqn = (E1_a_1 & X1_request_6) # (!E1_a_1 & E1_bytes2send_25_lut_out);
E1_bytes2send_25 = DFFEA(E1_bytes2send_25_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_26 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_26
--operation mode is normal

E1_bytes2send_26_lut_out = E1_bytes2send_26;
E1_bytes2send_26_sload_eqn = (E1_a_1 & X1_request_5) # (!E1_a_1 & E1_bytes2send_26_lut_out);
E1_bytes2send_26 = DFFEA(E1_bytes2send_26_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_27 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_27
--operation mode is normal

E1_bytes2send_27_lut_out = E1_bytes2send_27;
E1_bytes2send_27_sload_eqn = (E1_a_1 & X1_request_4) # (!E1_a_1 & E1_bytes2send_27_lut_out);
E1_bytes2send_27 = DFFEA(E1_bytes2send_27_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_28 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_28
--operation mode is normal

E1_bytes2send_28_lut_out = E1_bytes2send_28;
E1_bytes2send_28_sload_eqn = (E1_a_1 & X1_request_3) # (!E1_a_1 & E1_bytes2send_28_lut_out);
E1_bytes2send_28 = DFFEA(E1_bytes2send_28_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_29 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_29
--operation mode is normal

E1_bytes2send_29_lut_out = E1_bytes2send_29;
E1_bytes2send_29_sload_eqn = (E1_a_1 & X1_request_2) # (!E1_a_1 & E1_bytes2send_29_lut_out);
E1_bytes2send_29 = DFFEA(E1_bytes2send_29_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_3 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_3
--operation mode is normal

E1_bytes2send_3_lut_out = X1_request_28;
E1_bytes2send_3 = DFFEA(E1_bytes2send_3_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx543, , );


--E1_bytes2send_30 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_30
--operation mode is normal

E1_bytes2send_30_lut_out = E1_bytes2send_30;
E1_bytes2send_30_sload_eqn = (E1_a_1 & X1_request_1) # (!E1_a_1 & E1_bytes2send_30_lut_out);
E1_bytes2send_30 = DFFEA(E1_bytes2send_30_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_31 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_31
--operation mode is normal

E1_bytes2send_31_lut_out = E1_bytes2send_31;
E1_bytes2send_31_sload_eqn = (E1_a_1 & X1_request_0) # (!E1_a_1 & E1_bytes2send_31_lut_out);
E1_bytes2send_31 = DFFEA(E1_bytes2send_31_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_32 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_32
--operation mode is normal

E1_bytes2send_32_lut_out = X1_request_31;
E1_bytes2send_32 = DFFEA(E1_bytes2send_32_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx479, , );


--E1_bytes2send_33 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_33
--operation mode is normal

E1_bytes2send_33_lut_out = X1_request_30;
E1_bytes2send_33 = DFFEA(E1_bytes2send_33_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx479, , );


--E1_bytes2send_34 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_34
--operation mode is normal

E1_bytes2send_34_lut_out = X1_request_29;
E1_bytes2send_34 = DFFEA(E1_bytes2send_34_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx479, , );


--E1_bytes2send_35 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_35
--operation mode is normal

E1_bytes2send_35_lut_out = X1_request_28;
E1_bytes2send_35 = DFFEA(E1_bytes2send_35_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx479, , );


--E1_bytes2send_36 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_36
--operation mode is normal

E1_bytes2send_36_lut_out = X1_request_27;
E1_bytes2send_36 = DFFEA(E1_bytes2send_36_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx479, , );


--E1_bytes2send_37 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_37
--operation mode is normal

E1_bytes2send_37_lut_out = X1_request_26;
E1_bytes2send_37 = DFFEA(E1_bytes2send_37_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx479, , );


--E1_bytes2send_38 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_38
--operation mode is normal

E1_bytes2send_38_lut_out = X1_request_25;
E1_bytes2send_38 = DFFEA(E1_bytes2send_38_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx479, , );


--E1_bytes2send_39 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_39
--operation mode is normal

E1_bytes2send_39_lut_out = X1_request_24;
E1_bytes2send_39 = DFFEA(E1_bytes2send_39_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx479, , );


--E1_bytes2send_4 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_4
--operation mode is normal

E1_bytes2send_4_lut_out = X1_request_27;
E1_bytes2send_4 = DFFEA(E1_bytes2send_4_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx543, , );


--E1_bytes2send_40 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_40
--operation mode is normal

E1_bytes2send_40_lut_out = E1_bytes2send_40;
E1_bytes2send_40_sload_eqn = (E1_a_3 & X1_request_23) # (!E1_a_3 & E1_bytes2send_40_lut_out);
E1_bytes2send_40 = DFFEA(E1_bytes2send_40_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_41 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_41
--operation mode is normal

E1_bytes2send_41_lut_out = E1_bytes2send_41;
E1_bytes2send_41_sload_eqn = (E1_a_3 & X1_request_22) # (!E1_a_3 & E1_bytes2send_41_lut_out);
E1_bytes2send_41 = DFFEA(E1_bytes2send_41_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_42 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_42
--operation mode is normal

E1_bytes2send_42_lut_out = E1_bytes2send_42;
E1_bytes2send_42_sload_eqn = (E1_a_3 & X1_request_21) # (!E1_a_3 & E1_bytes2send_42_lut_out);
E1_bytes2send_42 = DFFEA(E1_bytes2send_42_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_43 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_43
--operation mode is normal

E1_bytes2send_43_lut_out = E1_bytes2send_43;
E1_bytes2send_43_sload_eqn = (E1_a_3 & X1_request_20) # (!E1_a_3 & E1_bytes2send_43_lut_out);
E1_bytes2send_43 = DFFEA(E1_bytes2send_43_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_44 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_44
--operation mode is normal

E1_bytes2send_44_lut_out = E1_bytes2send_44;
E1_bytes2send_44_sload_eqn = (E1_a_3 & X1_request_19) # (!E1_a_3 & E1_bytes2send_44_lut_out);
E1_bytes2send_44 = DFFEA(E1_bytes2send_44_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_45 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_45
--operation mode is normal

E1_bytes2send_45_lut_out = E1_bytes2send_45;
E1_bytes2send_45_sload_eqn = (E1_a_3 & X1_request_18) # (!E1_a_3 & E1_bytes2send_45_lut_out);
E1_bytes2send_45 = DFFEA(E1_bytes2send_45_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_46 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_46
--operation mode is normal

E1_bytes2send_46_lut_out = E1_bytes2send_46;
E1_bytes2send_46_sload_eqn = (E1_a_3 & X1_request_17) # (!E1_a_3 & E1_bytes2send_46_lut_out);
E1_bytes2send_46 = DFFEA(E1_bytes2send_46_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_47 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_47
--operation mode is normal

E1_bytes2send_47_lut_out = E1_bytes2send_47;
E1_bytes2send_47_sload_eqn = (E1_a_3 & X1_request_16) # (!E1_a_3 & E1_bytes2send_47_lut_out);
E1_bytes2send_47 = DFFEA(E1_bytes2send_47_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_5 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_5
--operation mode is normal

E1_bytes2send_5_lut_out = X1_request_26;
E1_bytes2send_5 = DFFEA(E1_bytes2send_5_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx543, , );


--E1_bytes2send_6 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_6
--operation mode is normal

E1_bytes2send_6_lut_out = X1_request_25;
E1_bytes2send_6 = DFFEA(E1_bytes2send_6_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx543, , );


--E1_bytes2send_7 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_7
--operation mode is normal

E1_bytes2send_7_lut_out = X1_request_24;
E1_bytes2send_7 = DFFEA(E1_bytes2send_7_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx543, , );


--E1_bytes2send_8 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_8
--operation mode is normal

E1_bytes2send_8_lut_out = E1_bytes2send_8;
E1_bytes2send_8_sload_eqn = (E1_a_1 & X1_request_23) # (!E1_a_1 & E1_bytes2send_8_lut_out);
E1_bytes2send_8 = DFFEA(E1_bytes2send_8_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes2send_9 is ADC_DAC_0:adcdac|DDS:ddsi|bytes2send_9
--operation mode is normal

E1_bytes2send_9_lut_out = E1_bytes2send_9;
E1_bytes2send_9_sload_eqn = (E1_a_1 & X1_request_22) # (!E1_a_1 & E1_bytes2send_9_lut_out);
E1_bytes2send_9 = DFFEA(E1_bytes2send_9_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_bytes_rcvd_0 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_0
--operation mode is normal

E1_bytes_rcvd_0_lut_out = E1_nx2247;
E1_bytes_rcvd_0 = DFFEA(E1_bytes_rcvd_0_lut_out, U1__clk1, VCC, , E1_NOT_nx2249, , );


--E1_bytes_rcvd_1 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_1
--operation mode is normal

E1_bytes_rcvd_1_lut_out = E1_nx2243;
E1_bytes_rcvd_1 = DFFEA(E1_bytes_rcvd_1_lut_out, U1__clk1, VCC, , E1_NOT_nx2249, , );


--E1_bytes_rcvd_10 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_10
--operation mode is normal

E1_bytes_rcvd_10_lut_out = E1_nx2239;
E1_bytes_rcvd_10 = DFFEA(E1_bytes_rcvd_10_lut_out, U1__clk1, VCC, , E1_NOT_nx2217, , );


--E1_bytes_rcvd_11 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_11
--operation mode is normal

E1_bytes_rcvd_11_lut_out = E1_nx2235;
E1_bytes_rcvd_11 = DFFEA(E1_bytes_rcvd_11_lut_out, U1__clk1, VCC, , E1_NOT_nx2217, , );


--E1_bytes_rcvd_12 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_12
--operation mode is normal

E1_bytes_rcvd_12_lut_out = E1_nx2231;
E1_bytes_rcvd_12 = DFFEA(E1_bytes_rcvd_12_lut_out, U1__clk1, VCC, , E1_NOT_nx2217, , );


--E1_bytes_rcvd_13 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_13
--operation mode is normal

E1_bytes_rcvd_13_lut_out = E1_nx2227;
E1_bytes_rcvd_13 = DFFEA(E1_bytes_rcvd_13_lut_out, U1__clk1, VCC, , E1_NOT_nx2217, , );


--E1_bytes_rcvd_14 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_14
--operation mode is normal

E1_bytes_rcvd_14_lut_out = E1_nx2223;
E1_bytes_rcvd_14 = DFFEA(E1_bytes_rcvd_14_lut_out, U1__clk1, VCC, , E1_NOT_nx2217, , );


--E1_bytes_rcvd_15 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_15
--operation mode is normal

E1_bytes_rcvd_15_lut_out = E1_nx2219;
E1_bytes_rcvd_15 = DFFEA(E1_bytes_rcvd_15_lut_out, U1__clk1, VCC, , E1_NOT_nx2217, , );


--E1_bytes_rcvd_16 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_16
--operation mode is normal

E1_bytes_rcvd_16_lut_out = E1_nx2247;
E1_bytes_rcvd_16 = DFFEA(E1_bytes_rcvd_16_lut_out, U1__clk1, VCC, , E1_NOT_nx2185, , );


--E1_bytes_rcvd_17 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_17
--operation mode is normal

E1_bytes_rcvd_17_lut_out = E1_nx2243;
E1_bytes_rcvd_17 = DFFEA(E1_bytes_rcvd_17_lut_out, U1__clk1, VCC, , E1_NOT_nx2185, , );


--E1_bytes_rcvd_18 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_18
--operation mode is normal

E1_bytes_rcvd_18_lut_out = E1_nx2239;
E1_bytes_rcvd_18 = DFFEA(E1_bytes_rcvd_18_lut_out, U1__clk1, VCC, , E1_NOT_nx2185, , );


--E1_bytes_rcvd_19 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_19
--operation mode is normal

E1_bytes_rcvd_19_lut_out = E1_nx2235;
E1_bytes_rcvd_19 = DFFEA(E1_bytes_rcvd_19_lut_out, U1__clk1, VCC, , E1_NOT_nx2185, , );


--E1_bytes_rcvd_2 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_2
--operation mode is normal

E1_bytes_rcvd_2_lut_out = E1_nx2239;
E1_bytes_rcvd_2 = DFFEA(E1_bytes_rcvd_2_lut_out, U1__clk1, VCC, , E1_NOT_nx2249, , );


--E1_bytes_rcvd_20 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_20
--operation mode is normal

E1_bytes_rcvd_20_lut_out = E1_nx2231;
E1_bytes_rcvd_20 = DFFEA(E1_bytes_rcvd_20_lut_out, U1__clk1, VCC, , E1_NOT_nx2185, , );


--E1_bytes_rcvd_21 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_21
--operation mode is normal

E1_bytes_rcvd_21_lut_out = E1_nx2227;
E1_bytes_rcvd_21 = DFFEA(E1_bytes_rcvd_21_lut_out, U1__clk1, VCC, , E1_NOT_nx2185, , );


--E1_bytes_rcvd_22 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_22
--operation mode is normal

E1_bytes_rcvd_22_lut_out = E1_nx2223;
E1_bytes_rcvd_22 = DFFEA(E1_bytes_rcvd_22_lut_out, U1__clk1, VCC, , E1_NOT_nx2185, , );


--E1_bytes_rcvd_23 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_23
--operation mode is normal

E1_bytes_rcvd_23_lut_out = E1_nx2219;
E1_bytes_rcvd_23 = DFFEA(E1_bytes_rcvd_23_lut_out, U1__clk1, VCC, , E1_NOT_nx2185, , );


--E1_bytes_rcvd_24 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_24
--operation mode is normal

E1_bytes_rcvd_24_lut_out = E1_nx2247;
E1_bytes_rcvd_24 = DFFEA(E1_bytes_rcvd_24_lut_out, U1__clk1, VCC, , E1_NOT_nx2153, , );


--E1_bytes_rcvd_25 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_25
--operation mode is normal

E1_bytes_rcvd_25_lut_out = E1_nx2243;
E1_bytes_rcvd_25 = DFFEA(E1_bytes_rcvd_25_lut_out, U1__clk1, VCC, , E1_NOT_nx2153, , );


--E1_bytes_rcvd_26 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_26
--operation mode is normal

E1_bytes_rcvd_26_lut_out = E1_nx2239;
E1_bytes_rcvd_26 = DFFEA(E1_bytes_rcvd_26_lut_out, U1__clk1, VCC, , E1_NOT_nx2153, , );


--E1_bytes_rcvd_27 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_27
--operation mode is normal

E1_bytes_rcvd_27_lut_out = E1_nx2235;
E1_bytes_rcvd_27 = DFFEA(E1_bytes_rcvd_27_lut_out, U1__clk1, VCC, , E1_NOT_nx2153, , );


--E1_bytes_rcvd_28 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_28
--operation mode is normal

E1_bytes_rcvd_28_lut_out = E1_nx2231;
E1_bytes_rcvd_28 = DFFEA(E1_bytes_rcvd_28_lut_out, U1__clk1, VCC, , E1_NOT_nx2153, , );


--E1_bytes_rcvd_29 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_29
--operation mode is normal

E1_bytes_rcvd_29_lut_out = E1_nx2227;
E1_bytes_rcvd_29 = DFFEA(E1_bytes_rcvd_29_lut_out, U1__clk1, VCC, , E1_NOT_nx2153, , );


--E1_bytes_rcvd_3 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_3
--operation mode is normal

E1_bytes_rcvd_3_lut_out = E1_nx2235;
E1_bytes_rcvd_3 = DFFEA(E1_bytes_rcvd_3_lut_out, U1__clk1, VCC, , E1_NOT_nx2249, , );


--E1_bytes_rcvd_30 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_30
--operation mode is normal

E1_bytes_rcvd_30_lut_out = E1_nx2223;
E1_bytes_rcvd_30 = DFFEA(E1_bytes_rcvd_30_lut_out, U1__clk1, VCC, , E1_NOT_nx2153, , );


--E1_bytes_rcvd_31 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_31
--operation mode is normal

E1_bytes_rcvd_31_lut_out = E1_nx2219;
E1_bytes_rcvd_31 = DFFEA(E1_bytes_rcvd_31_lut_out, U1__clk1, VCC, , E1_NOT_nx2153, , );


--E1_bytes_rcvd_32 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_32
--operation mode is normal

E1_bytes_rcvd_32_lut_out = E1_nx2247;
E1_bytes_rcvd_32 = DFFEA(E1_bytes_rcvd_32_lut_out, U1__clk1, VCC, , E1_NOT_nx2121, , );


--E1_bytes_rcvd_33 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_33
--operation mode is normal

E1_bytes_rcvd_33_lut_out = E1_nx2243;
E1_bytes_rcvd_33 = DFFEA(E1_bytes_rcvd_33_lut_out, U1__clk1, VCC, , E1_NOT_nx2121, , );


--E1_bytes_rcvd_34 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_34
--operation mode is normal

E1_bytes_rcvd_34_lut_out = E1_nx2239;
E1_bytes_rcvd_34 = DFFEA(E1_bytes_rcvd_34_lut_out, U1__clk1, VCC, , E1_NOT_nx2121, , );


--E1_bytes_rcvd_35 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_35
--operation mode is normal

E1_bytes_rcvd_35_lut_out = E1_nx2235;
E1_bytes_rcvd_35 = DFFEA(E1_bytes_rcvd_35_lut_out, U1__clk1, VCC, , E1_NOT_nx2121, , );


--E1_bytes_rcvd_36 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_36
--operation mode is normal

E1_bytes_rcvd_36_lut_out = E1_nx2231;
E1_bytes_rcvd_36 = DFFEA(E1_bytes_rcvd_36_lut_out, U1__clk1, VCC, , E1_NOT_nx2121, , );


--E1_bytes_rcvd_37 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_37
--operation mode is normal

E1_bytes_rcvd_37_lut_out = E1_nx2227;
E1_bytes_rcvd_37 = DFFEA(E1_bytes_rcvd_37_lut_out, U1__clk1, VCC, , E1_NOT_nx2121, , );


--E1_bytes_rcvd_38 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_38
--operation mode is normal

E1_bytes_rcvd_38_lut_out = E1_nx2223;
E1_bytes_rcvd_38 = DFFEA(E1_bytes_rcvd_38_lut_out, U1__clk1, VCC, , E1_NOT_nx2121, , );


--E1_bytes_rcvd_39 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_39
--operation mode is normal

E1_bytes_rcvd_39_lut_out = E1_nx2219;
E1_bytes_rcvd_39 = DFFEA(E1_bytes_rcvd_39_lut_out, U1__clk1, VCC, , E1_NOT_nx2121, , );


--E1_bytes_rcvd_4 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_4
--operation mode is normal

E1_bytes_rcvd_4_lut_out = E1_nx2231;
E1_bytes_rcvd_4 = DFFEA(E1_bytes_rcvd_4_lut_out, U1__clk1, VCC, , E1_NOT_nx2249, , );


--E1_nx2247 is ADC_DAC_0:adcdac|DDS:ddsi|nx2247
--operation mode is normal

E1_nx2247 = E1_byte_recv_0 & (!E1_iword2send_7 # !E1_sm_top_1);

--E1_bytes_rcvd_40 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_40
--operation mode is normal

E1_bytes_rcvd_40 = DFFEA(E1_nx2247, U1__clk1, VCC, , E1_NOT_nx2089, , );


--E1_nx2243 is ADC_DAC_0:adcdac|DDS:ddsi|nx2243
--operation mode is normal

E1_nx2243 = E1_byte_recv_1 & (!E1_iword2send_7 # !E1_sm_top_1);

--E1_bytes_rcvd_41 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_41
--operation mode is normal

E1_bytes_rcvd_41 = DFFEA(E1_nx2243, U1__clk1, VCC, , E1_NOT_nx2089, , );


--E1_nx2239 is ADC_DAC_0:adcdac|DDS:ddsi|nx2239
--operation mode is normal

E1_nx2239 = E1_byte_recv_2 & (!E1_iword2send_7 # !E1_sm_top_1);

--E1_bytes_rcvd_42 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_42
--operation mode is normal

E1_bytes_rcvd_42 = DFFEA(E1_nx2239, U1__clk1, VCC, , E1_NOT_nx2089, , );


--E1_nx2235 is ADC_DAC_0:adcdac|DDS:ddsi|nx2235
--operation mode is normal

E1_nx2235 = E1_byte_recv_3 & (!E1_iword2send_7 # !E1_sm_top_1);

--E1_bytes_rcvd_43 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_43
--operation mode is normal

E1_bytes_rcvd_43 = DFFEA(E1_nx2235, U1__clk1, VCC, , E1_NOT_nx2089, , );


--E1_nx2231 is ADC_DAC_0:adcdac|DDS:ddsi|nx2231
--operation mode is normal

E1_nx2231 = E1_byte_recv_4 & (!E1_iword2send_7 # !E1_sm_top_1);

--E1_bytes_rcvd_44 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_44
--operation mode is normal

E1_bytes_rcvd_44 = DFFEA(E1_nx2231, U1__clk1, VCC, , E1_NOT_nx2089, , );


--E1_nx2227 is ADC_DAC_0:adcdac|DDS:ddsi|nx2227
--operation mode is normal

E1_nx2227 = E1_byte_recv_5 & (!E1_iword2send_7 # !E1_sm_top_1);

--E1_bytes_rcvd_45 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_45
--operation mode is normal

E1_bytes_rcvd_45 = DFFEA(E1_nx2227, U1__clk1, VCC, , E1_NOT_nx2089, , );


--E1_nx2223 is ADC_DAC_0:adcdac|DDS:ddsi|nx2223
--operation mode is normal

E1_nx2223 = E1_byte_recv_6 & (!E1_iword2send_7 # !E1_sm_top_1);

--E1_bytes_rcvd_46 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_46
--operation mode is normal

E1_bytes_rcvd_46 = DFFEA(E1_nx2223, U1__clk1, VCC, , E1_NOT_nx2089, , );


--E1_nx2219 is ADC_DAC_0:adcdac|DDS:ddsi|nx2219
--operation mode is normal

E1_nx2219 = E1_byte_recv_7 & (!E1_iword2send_7 # !E1_sm_top_1);

--E1_bytes_rcvd_47 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_47
--operation mode is normal

E1_bytes_rcvd_47 = DFFEA(E1_nx2219, U1__clk1, VCC, , E1_NOT_nx2089, , );


--E1_bytes_rcvd_5 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_5
--operation mode is normal

E1_bytes_rcvd_5_lut_out = E1_nx2227;
E1_bytes_rcvd_5 = DFFEA(E1_bytes_rcvd_5_lut_out, U1__clk1, VCC, , E1_NOT_nx2249, , );


--E1_bytes_rcvd_6 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_6
--operation mode is normal

E1_bytes_rcvd_6_lut_out = E1_nx2223;
E1_bytes_rcvd_6 = DFFEA(E1_bytes_rcvd_6_lut_out, U1__clk1, VCC, , E1_NOT_nx2249, , );


--E1_bytes_rcvd_7 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_7
--operation mode is normal

E1_bytes_rcvd_7_lut_out = E1_nx2219;
E1_bytes_rcvd_7 = DFFEA(E1_bytes_rcvd_7_lut_out, U1__clk1, VCC, , E1_NOT_nx2249, , );


--E1_bytes_rcvd_8 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_8
--operation mode is normal

E1_bytes_rcvd_8_lut_out = E1_nx2247;
E1_bytes_rcvd_8 = DFFEA(E1_bytes_rcvd_8_lut_out, U1__clk1, VCC, , E1_NOT_nx2217, , );


--E1_bytes_rcvd_9 is ADC_DAC_0:adcdac|DDS:ddsi|bytes_rcvd_9
--operation mode is normal

E1_bytes_rcvd_9_lut_out = E1_nx2243;
E1_bytes_rcvd_9 = DFFEA(E1_bytes_rcvd_9_lut_out, U1__clk1, VCC, , E1_NOT_nx2217, , );


--E1_clkdivs is ADC_DAC_0:adcdac|DDS:ddsi|clkdivs
--operation mode is normal

E1_clkdivs_lut_out = !E1_start_sm & !E1_nx538 # !E1_clkdivs;
E1_clkdivs = DFFEA(E1_clkdivs_lut_out, U1__clk1, V1_chipRST_n, , , , );


--E1_config_0 is ADC_DAC_0:adcdac|DDS:ddsi|config_0
--operation mode is normal

E1_config_0_lut_out = X1_request_31;
E1_config_0 = DFFEA(E1_config_0_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx429, , );


--E1_config_1 is ADC_DAC_0:adcdac|DDS:ddsi|config_1
--operation mode is normal

E1_config_1_lut_out = X1_request_30;
E1_config_1 = DFFEA(E1_config_1_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx429, , );


--E1_config_2 is ADC_DAC_0:adcdac|DDS:ddsi|config_2
--operation mode is normal

E1_config_2_lut_out = X1_request_29;
E1_config_2 = DFFEA(E1_config_2_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx429, , );


--E1_config_3 is ADC_DAC_0:adcdac|DDS:ddsi|config_3
--operation mode is normal

E1_config_3_lut_out = X1_request_28;
E1_config_3 = DFFEA(E1_config_3_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx429, , );


--E1_DDS_ShKey is ADC_DAC_0:adcdac|DDS:ddsi|DDS_ShKey
--operation mode is normal

E1_DDS_ShKey_lut_out = X1_request_27;
E1_DDS_ShKey = DFFEA(E1_DDS_ShKey_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx429, , );


--E1_DDS_FSK is ADC_DAC_0:adcdac|DDS:ddsi|DDS_FSK
--operation mode is normal

E1_DDS_FSK_lut_out = X1_request_26;
E1_DDS_FSK = DFFEA(E1_DDS_FSK_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx429, , );


--E1_config_6 is ADC_DAC_0:adcdac|DDS:ddsi|config_6
--operation mode is normal

E1_config_6_lut_out = X1_request_25;
E1_config_6 = DFFEA(E1_config_6_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx429, , );


--E1_config_7 is ADC_DAC_0:adcdac|DDS:ddsi|config_7
--operation mode is normal

E1_config_7_lut_out = X1_request_24;
E1_config_7 = DFFEA(E1_config_7_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx429, , );


--E1_NOT_DDS_CSn is ADC_DAC_0:adcdac|DDS:ddsi|NOT_DDS_CSn
--operation mode is normal

E1_NOT_DDS_CSn_lut_out = E1_flag2send # E1_NOT_sm_top_0;
E1_NOT_DDS_CSn = DFFEA(E1_NOT_DDS_CSn_lut_out, U1__clk1, V1_chipRST_n, , , , );


--E1_NOT_DDS_IORST is ADC_DAC_0:adcdac|DDS:ddsi|NOT_DDS_IORST
--operation mode is normal

E1_NOT_DDS_IORST_lut_out = E1_flag2send;
E1_NOT_DDS_IORST = DFFEA(E1_NOT_DDS_IORST_lut_out, U1__clk1, V1_chipRST_n, , !E1_NOT_sm_top_0, , );


--E1_DDS_SCLK is ADC_DAC_0:adcdac|DDS:ddsi|DDS_SCLK
--operation mode is normal

E1_DDS_SCLK_lut_out = E1_sm_sr_4 # E1_sm_sr_1;
E1_DDS_SCLK = DFFEA(E1_DDS_SCLK_lut_out, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_DDS_SDI is ADC_DAC_0:adcdac|DDS:ddsi|DDS_SDI
--operation mode is normal

E1_DDS_SDI_lut_out = E1_sm_sr_3 & E1_byte_send_7 # !E1_sm_sr_3 & E1_DDS_SDI;
E1_DDS_SDI = DFFEA(E1_DDS_SDI_lut_out, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_NOT_nx479 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_nx479
--operation mode is normal

E1_NOT_nx479 = G1_ce_dds & !V1_rd_wr_oase & X1_request_48 & E1_nx859;

--E1_flag2send is ADC_DAC_0:adcdac|DDS:ddsi|flag2send
--operation mode is normal

E1_flag2send = DFFEA(E1_NOT_nx479, U1__clk1, V1_chipRST_n, , , , );


--E1_iword2send_0 is ADC_DAC_0:adcdac|DDS:ddsi|iword2send_0
--operation mode is normal

E1_iword2send_0_lut_out = E1_iword2send_0;
E1_iword2send_0_sload_eqn = (E1_a_3 & X1_request_15) # (!E1_a_3 & E1_iword2send_0_lut_out);
E1_iword2send_0 = DFFEA(E1_iword2send_0_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_iword2send_1 is ADC_DAC_0:adcdac|DDS:ddsi|iword2send_1
--operation mode is normal

E1_iword2send_1_lut_out = E1_iword2send_1;
E1_iword2send_1_sload_eqn = (E1_a_3 & X1_request_14) # (!E1_a_3 & E1_iword2send_1_lut_out);
E1_iword2send_1 = DFFEA(E1_iword2send_1_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_iword2send_2 is ADC_DAC_0:adcdac|DDS:ddsi|iword2send_2
--operation mode is normal

E1_iword2send_2_lut_out = E1_iword2send_2;
E1_iword2send_2_sload_eqn = (E1_a_3 & X1_request_13) # (!E1_a_3 & E1_iword2send_2_lut_out);
E1_iword2send_2 = DFFEA(E1_iword2send_2_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_iword2send_3 is ADC_DAC_0:adcdac|DDS:ddsi|iword2send_3
--operation mode is normal

E1_iword2send_3_lut_out = E1_iword2send_3;
E1_iword2send_3_sload_eqn = (E1_a_3 & X1_request_12) # (!E1_a_3 & E1_iword2send_3_lut_out);
E1_iword2send_3 = DFFEA(E1_iword2send_3_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_iword2send_4 is ADC_DAC_0:adcdac|DDS:ddsi|iword2send_4
--operation mode is normal

E1_iword2send_4_lut_out = E1_iword2send_4;
E1_iword2send_4_sload_eqn = (E1_a_3 & X1_request_11) # (!E1_a_3 & E1_iword2send_4_lut_out);
E1_iword2send_4 = DFFEA(E1_iword2send_4_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_iword2send_5 is ADC_DAC_0:adcdac|DDS:ddsi|iword2send_5
--operation mode is normal

E1_iword2send_5_lut_out = E1_iword2send_5;
E1_iword2send_5_sload_eqn = (E1_a_3 & X1_request_10) # (!E1_a_3 & E1_iword2send_5_lut_out);
E1_iword2send_5 = DFFEA(E1_iword2send_5_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_iword2send_6 is ADC_DAC_0:adcdac|DDS:ddsi|iword2send_6
--operation mode is normal

E1_iword2send_6_lut_out = E1_iword2send_6;
E1_iword2send_6_sload_eqn = (E1_a_3 & X1_request_9) # (!E1_a_3 & E1_iword2send_6_lut_out);
E1_iword2send_6 = DFFEA(E1_iword2send_6_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_iword2send_7 is ADC_DAC_0:adcdac|DDS:ddsi|iword2send_7
--operation mode is normal

E1_iword2send_7_lut_out = E1_iword2send_7;
E1_iword2send_7_sload_eqn = (E1_a_3 & X1_request_8) # (!E1_a_3 & E1_iword2send_7_lut_out);
E1_iword2send_7 = DFFEA(E1_iword2send_7_sload_eqn, U1__clk1, V1_chipRST_n, , E1_nx8, , );


--E1_read_flag is ADC_DAC_0:adcdac|DDS:ddsi|read_flag
--operation mode is normal

E1_read_flag_lut_out = E1_sm_top_4;
E1_read_flag = DFFEA(E1_read_flag_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx1526, , );


--E1_nx538 is ADC_DAC_0:adcdac|DDS:ddsi|nx538
--operation mode is normal

E1_nx538_lut_out = !E1_sm_sr_5 & (E1_start_sm # E1_nx538);
E1_nx538 = DFFEA(E1_nx538_lut_out, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_sm_sr_1 is ADC_DAC_0:adcdac|DDS:ddsi|sm_sr_1
--operation mode is normal

E1_sm_sr_1_lut_out = E1_nx842 # E1_start_sm & E1_read_flag & !E1_nx538;
E1_sm_sr_1 = DFFEA(E1_sm_sr_1_lut_out, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_sm_sr_2 is ADC_DAC_0:adcdac|DDS:ddsi|sm_sr_2
--operation mode is normal

E1_sm_sr_2_lut_out = E1_sm_sr_1;
E1_sm_sr_2 = DFFEA(E1_sm_sr_2_lut_out, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_sm_sr_3 is ADC_DAC_0:adcdac|DDS:ddsi|sm_sr_3
--operation mode is normal

E1_sm_sr_3_lut_out = E1_sm_sr_4 & (!E1_nx538 & E1_nx845 # !E1_nx843) # !E1_sm_sr_4 & !E1_nx538 & E1_nx845;
E1_sm_sr_3 = DFFEA(E1_sm_sr_3_lut_out, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_sm_sr_4 is ADC_DAC_0:adcdac|DDS:ddsi|sm_sr_4
--operation mode is normal

E1_sm_sr_4_lut_out = E1_sm_sr_3;
E1_sm_sr_4 = DFFEA(E1_sm_sr_4_lut_out, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_sm_sr_5 is ADC_DAC_0:adcdac|DDS:ddsi|sm_sr_5
--operation mode is normal

E1_sm_sr_5_lut_out = E1_nx843 & (E1_sm_sr_4 # E1_sm_sr_2);
E1_sm_sr_5 = DFFEA(E1_sm_sr_5_lut_out, U1__clk1, V1_chipRST_n, , E1_clkdivs, , );


--E1_NOT_sm_top_0 is ADC_DAC_0:adcdac|DDS:ddsi|NOT_sm_top_0
--operation mode is normal

E1_NOT_sm_top_0_lut_out = E1_nx839 & (E1_flag2send # E1_NOT_sm_top_0);
E1_NOT_sm_top_0 = DFFEA(E1_NOT_sm_top_0_lut_out, U1__clk1, V1_chipRST_n, , , , );


--E1_sm_top_1 is ADC_DAC_0:adcdac|DDS:ddsi|sm_top_1
--operation mode is normal

E1_sm_top_1_lut_out = E1_sm_top_1 & (E1_flag2send & !E1_NOT_sm_top_0 # !E1_sm_sr_5) # !E1_sm_top_1 & E1_flag2send & !E1_NOT_sm_top_0;
E1_sm_top_1 = DFFEA(E1_sm_top_1_lut_out, U1__clk1, V1_chipRST_n, , , , );


--E1_sm_top_2 is ADC_DAC_0:adcdac|DDS:ddsi|sm_top_2
--operation mode is normal

E1_sm_top_2_lut_out = E1_nx752 # E1_nx846 # E1_sm_top_2 & E1_nx800;
E1_sm_top_2 = DFFEA(E1_sm_top_2_lut_out, U1__clk1, V1_chipRST_n, , , , );


--E1_sm_top_3 is ADC_DAC_0:adcdac|DDS:ddsi|sm_top_3
--operation mode is normal

E1_sm_top_3_lut_out = E1_sm_top_3 & (E1_nx790 # E1_sm_top_2 & !E1_nx800) # !E1_sm_top_3 & E1_sm_top_2 & !E1_nx800;
E1_sm_top_3 = DFFEA(E1_sm_top_3_lut_out, U1__clk1, V1_chipRST_n, , , , );


--E1_sm_top_4 is ADC_DAC_0:adcdac|DDS:ddsi|sm_top_4
--operation mode is normal

E1_sm_top_4_lut_out = E1_nx751 # E1_clkdivs & E1_nx841;
E1_sm_top_4 = DFFEA(E1_sm_top_4_lut_out, U1__clk1, V1_chipRST_n, , , , );


--E1_sm_top_5 is ADC_DAC_0:adcdac|DDS:ddsi|sm_top_5
--operation mode is normal

E1_sm_top_5_lut_out = E1_sm_top_5 & (E1_nx790 # E1_sm_top_4 & !E1_nx800) # !E1_sm_top_5 & E1_sm_top_4 & !E1_nx800;
E1_sm_top_5 = DFFEA(E1_sm_top_5_lut_out, U1__clk1, V1_chipRST_n, , , , );


--E1_sm_top_6 is ADC_DAC_0:adcdac|DDS:ddsi|sm_top_6
--operation mode is normal

E1_sm_top_6_lut_out = E1_nx847 # E1_sm_top_6 & (E1_byte_counter_0 # E1_nx784);
E1_sm_top_6 = DFFEA(E1_sm_top_6_lut_out, U1__clk1, V1_chipRST_n, , , , );


--E1_start_sm is ADC_DAC_0:adcdac|DDS:ddsi|start_sm
--operation mode is normal

E1_start_sm_lut_out = E1_sm_top_4 # E1_sm_top_2 # E1_flag2send & !E1_NOT_sm_top_0;
E1_start_sm = DFFEA(E1_start_sm_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx1511, , );


--E1_NOT_udclk is ADC_DAC_0:adcdac|DDS:ddsi|NOT_udclk
--operation mode is normal

E1_NOT_udclk_lut_out = E1_sm_top_1;
E1_NOT_udclk = DFFEA(E1_NOT_udclk_lut_out, U1__clk1, V1_chipRST_n, , E1_NOT_nx1490, , );


--E1_b_0_dup_240 is ADC_DAC_0:adcdac|DDS:ddsi|b_0_dup_240
--operation mode is normal

E1_b_0_dup_240 = !E1_byte_counter_0;


--E1_result_dec_273_nx14 is ADC_DAC_0:adcdac|DDS:ddsi|result_dec_273_nx14
--operation mode is arithmetic

E1_result_dec_273_nx14 = CARRY(E1_byte_counter_0);


--E1_b_0_dup_234 is ADC_DAC_0:adcdac|DDS:ddsi|b_0_dup_234
--operation mode is arithmetic

E1_b_0_dup_234_carry_eqn = E1_result_dec_273_nx14;
E1_b_0_dup_234 = E1_byte_counter_1 $ !E1_b_0_dup_234_carry_eqn;

--E1_result_dec_273_nx18 is ADC_DAC_0:adcdac|DDS:ddsi|result_dec_273_nx18
--operation mode is arithmetic

E1_result_dec_273_nx18 = CARRY(!E1_byte_counter_1 & !E1_result_dec_273_nx14);


--E1_b_0 is ADC_DAC_0:adcdac|DDS:ddsi|b_0
--operation mode is normal

E1_b_0_carry_eqn = E1_result_dec_273_nx18;
E1_b_0 = E1_byte_counter_2 $ E1_b_0_carry_eqn;


--E1_b_1_dup_418 is ADC_DAC_0:adcdac|DDS:ddsi|b_1_dup_418
--operation mode is normal

E1_b_1_dup_418 = !E1_bit_counter_0;


--E1_result_dec_316_nx14 is ADC_DAC_0:adcdac|DDS:ddsi|result_dec_316_nx14
--operation mode is arithmetic

E1_result_dec_316_nx14 = CARRY(E1_bit_counter_0);


--E1_b_1_dup_411 is ADC_DAC_0:adcdac|DDS:ddsi|b_1_dup_411
--operation mode is arithmetic

E1_b_1_dup_411_carry_eqn = E1_result_dec_316_nx14;
E1_b_1_dup_411 = E1_bit_counter_1 $ !E1_b_1_dup_411_carry_eqn;

--E1_result_dec_316_nx18 is ADC_DAC_0:adcdac|DDS:ddsi|result_dec_316_nx18
--operation mode is arithmetic

E1_result_dec_316_nx18 = CARRY(!E1_bit_counter_1 & !E1_result_dec_316_nx14);


--E1_b_1_dup_404 is ADC_DAC_0:adcdac|DDS:ddsi|b_1_dup_404
--operation mode is normal

E1_b_1_dup_404_carry_eqn = E1_result_dec_316_nx18;
E1_b_1_dup_404 = E1_bit_counter_2 $ E1_b_1_dup_404_carry_eqn;


--S1_q_a[14] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[14]
S1_q_a[14]_PORT_A_data_in = X1_request_15;
S1_q_a[14]_PORT_A_data_in_reg = DFFE(S1_q_a[14]_PORT_A_data_in, S1_q_a[14]_clock_0, , , );
S1_q_a[14]_PORT_B_data_in = ~GND;
S1_q_a[14]_PORT_B_data_in_reg = DFFE(S1_q_a[14]_PORT_B_data_in, S1_q_a[14]_clock_1, , , );
S1_q_a[14]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[14]_PORT_A_address_reg = DFFE(S1_q_a[14]_PORT_A_address, S1_q_a[14]_clock_0, , , );
S1_q_a[14]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[14]_PORT_B_address_reg = DFFE(S1_q_a[14]_PORT_B_address, S1_q_a[14]_clock_1, , , );
S1_q_a[14]_PORT_A_write_enable = J1_wren_io;
S1_q_a[14]_PORT_A_write_enable_reg = DFFE(S1_q_a[14]_PORT_A_write_enable, S1_q_a[14]_clock_0, , , );
S1_q_a[14]_PORT_B_write_enable = GND;
S1_q_a[14]_PORT_B_write_enable_reg = DFFE(S1_q_a[14]_PORT_B_write_enable, S1_q_a[14]_clock_1, , , );
S1_q_a[14]_clock_0 = U1__clk1;
S1_q_a[14]_clock_1 = U1__clk0;
S1_q_a[14]_PORT_A_data_out = MEMORY(S1_q_a[14]_PORT_A_data_in_reg, S1_q_a[14]_PORT_B_data_in_reg, S1_q_a[14]_PORT_A_address_reg, S1_q_a[14]_PORT_B_address_reg, S1_q_a[14]_PORT_A_write_enable_reg, S1_q_a[14]_PORT_B_write_enable_reg, , , S1_q_a[14]_clock_0, S1_q_a[14]_clock_1, , , , );
S1_q_a[14]_PORT_A_data_out_reg = DFFE(S1_q_a[14]_PORT_A_data_out, S1_q_a[14]_clock_0, , , );
S1_q_a[14] = S1_q_a[14]_PORT_A_data_out_reg[0];

--S1_q_b[14] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[14]
S1_q_b[14]_PORT_A_data_in = X1_request_15;
S1_q_b[14]_PORT_A_data_in_reg = DFFE(S1_q_b[14]_PORT_A_data_in, S1_q_b[14]_clock_0, , , );
S1_q_b[14]_PORT_B_data_in = ~GND;
S1_q_b[14]_PORT_B_data_in_reg = DFFE(S1_q_b[14]_PORT_B_data_in, S1_q_b[14]_clock_1, , , );
S1_q_b[14]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[14]_PORT_A_address_reg = DFFE(S1_q_b[14]_PORT_A_address, S1_q_b[14]_clock_0, , , );
S1_q_b[14]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[14]_PORT_B_address_reg = DFFE(S1_q_b[14]_PORT_B_address, S1_q_b[14]_clock_1, , , );
S1_q_b[14]_PORT_A_write_enable = J1_wren_io;
S1_q_b[14]_PORT_A_write_enable_reg = DFFE(S1_q_b[14]_PORT_A_write_enable, S1_q_b[14]_clock_0, , , );
S1_q_b[14]_PORT_B_write_enable = GND;
S1_q_b[14]_PORT_B_write_enable_reg = DFFE(S1_q_b[14]_PORT_B_write_enable, S1_q_b[14]_clock_1, , , );
S1_q_b[14]_clock_0 = U1__clk1;
S1_q_b[14]_clock_1 = U1__clk0;
S1_q_b[14]_PORT_B_data_out = MEMORY(S1_q_b[14]_PORT_A_data_in_reg, S1_q_b[14]_PORT_B_data_in_reg, S1_q_b[14]_PORT_A_address_reg, S1_q_b[14]_PORT_B_address_reg, S1_q_b[14]_PORT_A_write_enable_reg, S1_q_b[14]_PORT_B_write_enable_reg, , , S1_q_b[14]_clock_0, S1_q_b[14]_clock_1, , , , );
S1_q_b[14] = S1_q_b[14]_PORT_B_data_out[0];


--S1_q_a[0] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[0]
S1_q_a[0]_PORT_A_data_in = J1_wdata_cor_0;
S1_q_a[0]_PORT_A_data_in_reg = DFFE(S1_q_a[0]_PORT_A_data_in, S1_q_a[0]_clock_0, , , );
S1_q_a[0]_PORT_B_data_in = ~GND;
S1_q_a[0]_PORT_B_data_in_reg = DFFE(S1_q_a[0]_PORT_B_data_in, S1_q_a[0]_clock_1, , , );
S1_q_a[0]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[0]_PORT_A_address_reg = DFFE(S1_q_a[0]_PORT_A_address, S1_q_a[0]_clock_0, , , );
S1_q_a[0]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[0]_PORT_B_address_reg = DFFE(S1_q_a[0]_PORT_B_address, S1_q_a[0]_clock_1, , , );
S1_q_a[0]_PORT_A_write_enable = J1_wren_io;
S1_q_a[0]_PORT_A_write_enable_reg = DFFE(S1_q_a[0]_PORT_A_write_enable, S1_q_a[0]_clock_0, , , );
S1_q_a[0]_PORT_B_write_enable = GND;
S1_q_a[0]_PORT_B_write_enable_reg = DFFE(S1_q_a[0]_PORT_B_write_enable, S1_q_a[0]_clock_1, , , );
S1_q_a[0]_clock_0 = U1__clk1;
S1_q_a[0]_clock_1 = U1__clk0;
S1_q_a[0]_PORT_A_data_out = MEMORY(S1_q_a[0]_PORT_A_data_in_reg, S1_q_a[0]_PORT_B_data_in_reg, S1_q_a[0]_PORT_A_address_reg, S1_q_a[0]_PORT_B_address_reg, S1_q_a[0]_PORT_A_write_enable_reg, S1_q_a[0]_PORT_B_write_enable_reg, , , S1_q_a[0]_clock_0, S1_q_a[0]_clock_1, , , , );
S1_q_a[0]_PORT_A_data_out_reg = DFFE(S1_q_a[0]_PORT_A_data_out, S1_q_a[0]_clock_0, , , );
S1_q_a[0] = S1_q_a[0]_PORT_A_data_out_reg[0];

--S1_q_b[0] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[0]
S1_q_b[0]_PORT_A_data_in = J1_wdata_cor_0;
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_data_in = ~GND;
S1_q_b[0]_PORT_B_data_in_reg = DFFE(S1_q_b[0]_PORT_B_data_in, S1_q_b[0]_clock_1, , , );
S1_q_b[0]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[0]_PORT_B_address_reg = DFFE(S1_q_b[0]_PORT_B_address, S1_q_b[0]_clock_1, , , );
S1_q_b[0]_PORT_A_write_enable = J1_wren_io;
S1_q_b[0]_PORT_A_write_enable_reg = DFFE(S1_q_b[0]_PORT_A_write_enable, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_B_write_enable = GND;
S1_q_b[0]_PORT_B_write_enable_reg = DFFE(S1_q_b[0]_PORT_B_write_enable, S1_q_b[0]_clock_1, , , );
S1_q_b[0]_clock_0 = U1__clk1;
S1_q_b[0]_clock_1 = U1__clk0;
S1_q_b[0]_PORT_B_data_out = MEMORY(S1_q_b[0]_PORT_A_data_in_reg, S1_q_b[0]_PORT_B_data_in_reg, S1_q_b[0]_PORT_A_address_reg, S1_q_b[0]_PORT_B_address_reg, S1_q_b[0]_PORT_A_write_enable_reg, S1_q_b[0]_PORT_B_write_enable_reg, , , S1_q_b[0]_clock_0, S1_q_b[0]_clock_1, , , , );
S1_q_b[0] = S1_q_b[0]_PORT_B_data_out[0];


--S1_q_a[1] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[1]
S1_q_a[1]_PORT_A_data_in = J1_wdata_cor_1;
S1_q_a[1]_PORT_A_data_in_reg = DFFE(S1_q_a[1]_PORT_A_data_in, S1_q_a[1]_clock_0, , , );
S1_q_a[1]_PORT_B_data_in = ~GND;
S1_q_a[1]_PORT_B_data_in_reg = DFFE(S1_q_a[1]_PORT_B_data_in, S1_q_a[1]_clock_1, , , );
S1_q_a[1]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[1]_PORT_A_address_reg = DFFE(S1_q_a[1]_PORT_A_address, S1_q_a[1]_clock_0, , , );
S1_q_a[1]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[1]_PORT_B_address_reg = DFFE(S1_q_a[1]_PORT_B_address, S1_q_a[1]_clock_1, , , );
S1_q_a[1]_PORT_A_write_enable = J1_wren_io;
S1_q_a[1]_PORT_A_write_enable_reg = DFFE(S1_q_a[1]_PORT_A_write_enable, S1_q_a[1]_clock_0, , , );
S1_q_a[1]_PORT_B_write_enable = GND;
S1_q_a[1]_PORT_B_write_enable_reg = DFFE(S1_q_a[1]_PORT_B_write_enable, S1_q_a[1]_clock_1, , , );
S1_q_a[1]_clock_0 = U1__clk1;
S1_q_a[1]_clock_1 = U1__clk0;
S1_q_a[1]_PORT_A_data_out = MEMORY(S1_q_a[1]_PORT_A_data_in_reg, S1_q_a[1]_PORT_B_data_in_reg, S1_q_a[1]_PORT_A_address_reg, S1_q_a[1]_PORT_B_address_reg, S1_q_a[1]_PORT_A_write_enable_reg, S1_q_a[1]_PORT_B_write_enable_reg, , , S1_q_a[1]_clock_0, S1_q_a[1]_clock_1, , , , );
S1_q_a[1]_PORT_A_data_out_reg = DFFE(S1_q_a[1]_PORT_A_data_out, S1_q_a[1]_clock_0, , , );
S1_q_a[1] = S1_q_a[1]_PORT_A_data_out_reg[0];

--S1_q_b[1] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[1]
S1_q_b[1]_PORT_A_data_in = J1_wdata_cor_1;
S1_q_b[1]_PORT_A_data_in_reg = DFFE(S1_q_b[1]_PORT_A_data_in, S1_q_b[1]_clock_0, , , );
S1_q_b[1]_PORT_B_data_in = ~GND;
S1_q_b[1]_PORT_B_data_in_reg = DFFE(S1_q_b[1]_PORT_B_data_in, S1_q_b[1]_clock_1, , , );
S1_q_b[1]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[1]_PORT_A_address_reg = DFFE(S1_q_b[1]_PORT_A_address, S1_q_b[1]_clock_0, , , );
S1_q_b[1]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[1]_PORT_B_address_reg = DFFE(S1_q_b[1]_PORT_B_address, S1_q_b[1]_clock_1, , , );
S1_q_b[1]_PORT_A_write_enable = J1_wren_io;
S1_q_b[1]_PORT_A_write_enable_reg = DFFE(S1_q_b[1]_PORT_A_write_enable, S1_q_b[1]_clock_0, , , );
S1_q_b[1]_PORT_B_write_enable = GND;
S1_q_b[1]_PORT_B_write_enable_reg = DFFE(S1_q_b[1]_PORT_B_write_enable, S1_q_b[1]_clock_1, , , );
S1_q_b[1]_clock_0 = U1__clk1;
S1_q_b[1]_clock_1 = U1__clk0;
S1_q_b[1]_PORT_B_data_out = MEMORY(S1_q_b[1]_PORT_A_data_in_reg, S1_q_b[1]_PORT_B_data_in_reg, S1_q_b[1]_PORT_A_address_reg, S1_q_b[1]_PORT_B_address_reg, S1_q_b[1]_PORT_A_write_enable_reg, S1_q_b[1]_PORT_B_write_enable_reg, , , S1_q_b[1]_clock_0, S1_q_b[1]_clock_1, , , , );
S1_q_b[1] = S1_q_b[1]_PORT_B_data_out[0];


--S1_q_a[2] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[2]
S1_q_a[2]_PORT_A_data_in = J1_wdata_cor_2;
S1_q_a[2]_PORT_A_data_in_reg = DFFE(S1_q_a[2]_PORT_A_data_in, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_data_in = ~GND;
S1_q_a[2]_PORT_B_data_in_reg = DFFE(S1_q_a[2]_PORT_B_data_in, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[2]_PORT_A_address_reg = DFFE(S1_q_a[2]_PORT_A_address, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[2]_PORT_B_address_reg = DFFE(S1_q_a[2]_PORT_B_address, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_PORT_A_write_enable = J1_wren_io;
S1_q_a[2]_PORT_A_write_enable_reg = DFFE(S1_q_a[2]_PORT_A_write_enable, S1_q_a[2]_clock_0, , , );
S1_q_a[2]_PORT_B_write_enable = GND;
S1_q_a[2]_PORT_B_write_enable_reg = DFFE(S1_q_a[2]_PORT_B_write_enable, S1_q_a[2]_clock_1, , , );
S1_q_a[2]_clock_0 = U1__clk1;
S1_q_a[2]_clock_1 = U1__clk0;
S1_q_a[2]_PORT_A_data_out = MEMORY(S1_q_a[2]_PORT_A_data_in_reg, S1_q_a[2]_PORT_B_data_in_reg, S1_q_a[2]_PORT_A_address_reg, S1_q_a[2]_PORT_B_address_reg, S1_q_a[2]_PORT_A_write_enable_reg, S1_q_a[2]_PORT_B_write_enable_reg, , , S1_q_a[2]_clock_0, S1_q_a[2]_clock_1, , , , );
S1_q_a[2]_PORT_A_data_out_reg = DFFE(S1_q_a[2]_PORT_A_data_out, S1_q_a[2]_clock_0, , , );
S1_q_a[2] = S1_q_a[2]_PORT_A_data_out_reg[0];

--S1_q_b[2] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[2]
S1_q_b[2]_PORT_A_data_in = J1_wdata_cor_2;
S1_q_b[2]_PORT_A_data_in_reg = DFFE(S1_q_b[2]_PORT_A_data_in, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_data_in = ~GND;
S1_q_b[2]_PORT_B_data_in_reg = DFFE(S1_q_b[2]_PORT_B_data_in, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[2]_PORT_A_address_reg = DFFE(S1_q_b[2]_PORT_A_address, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[2]_PORT_B_address_reg = DFFE(S1_q_b[2]_PORT_B_address, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_PORT_A_write_enable = J1_wren_io;
S1_q_b[2]_PORT_A_write_enable_reg = DFFE(S1_q_b[2]_PORT_A_write_enable, S1_q_b[2]_clock_0, , , );
S1_q_b[2]_PORT_B_write_enable = GND;
S1_q_b[2]_PORT_B_write_enable_reg = DFFE(S1_q_b[2]_PORT_B_write_enable, S1_q_b[2]_clock_1, , , );
S1_q_b[2]_clock_0 = U1__clk1;
S1_q_b[2]_clock_1 = U1__clk0;
S1_q_b[2]_PORT_B_data_out = MEMORY(S1_q_b[2]_PORT_A_data_in_reg, S1_q_b[2]_PORT_B_data_in_reg, S1_q_b[2]_PORT_A_address_reg, S1_q_b[2]_PORT_B_address_reg, S1_q_b[2]_PORT_A_write_enable_reg, S1_q_b[2]_PORT_B_write_enable_reg, , , S1_q_b[2]_clock_0, S1_q_b[2]_clock_1, , , , );
S1_q_b[2] = S1_q_b[2]_PORT_B_data_out[0];


--S1_q_a[3] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[3]
S1_q_a[3]_PORT_A_data_in = J1_wdata_cor_3;
S1_q_a[3]_PORT_A_data_in_reg = DFFE(S1_q_a[3]_PORT_A_data_in, S1_q_a[3]_clock_0, , , );
S1_q_a[3]_PORT_B_data_in = ~GND;
S1_q_a[3]_PORT_B_data_in_reg = DFFE(S1_q_a[3]_PORT_B_data_in, S1_q_a[3]_clock_1, , , );
S1_q_a[3]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[3]_PORT_A_address_reg = DFFE(S1_q_a[3]_PORT_A_address, S1_q_a[3]_clock_0, , , );
S1_q_a[3]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[3]_PORT_B_address_reg = DFFE(S1_q_a[3]_PORT_B_address, S1_q_a[3]_clock_1, , , );
S1_q_a[3]_PORT_A_write_enable = J1_wren_io;
S1_q_a[3]_PORT_A_write_enable_reg = DFFE(S1_q_a[3]_PORT_A_write_enable, S1_q_a[3]_clock_0, , , );
S1_q_a[3]_PORT_B_write_enable = GND;
S1_q_a[3]_PORT_B_write_enable_reg = DFFE(S1_q_a[3]_PORT_B_write_enable, S1_q_a[3]_clock_1, , , );
S1_q_a[3]_clock_0 = U1__clk1;
S1_q_a[3]_clock_1 = U1__clk0;
S1_q_a[3]_PORT_A_data_out = MEMORY(S1_q_a[3]_PORT_A_data_in_reg, S1_q_a[3]_PORT_B_data_in_reg, S1_q_a[3]_PORT_A_address_reg, S1_q_a[3]_PORT_B_address_reg, S1_q_a[3]_PORT_A_write_enable_reg, S1_q_a[3]_PORT_B_write_enable_reg, , , S1_q_a[3]_clock_0, S1_q_a[3]_clock_1, , , , );
S1_q_a[3]_PORT_A_data_out_reg = DFFE(S1_q_a[3]_PORT_A_data_out, S1_q_a[3]_clock_0, , , );
S1_q_a[3] = S1_q_a[3]_PORT_A_data_out_reg[0];

--S1_q_b[3] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[3]
S1_q_b[3]_PORT_A_data_in = J1_wdata_cor_3;
S1_q_b[3]_PORT_A_data_in_reg = DFFE(S1_q_b[3]_PORT_A_data_in, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_data_in = ~GND;
S1_q_b[3]_PORT_B_data_in_reg = DFFE(S1_q_b[3]_PORT_B_data_in, S1_q_b[3]_clock_1, , , );
S1_q_b[3]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[3]_PORT_A_address_reg = DFFE(S1_q_b[3]_PORT_A_address, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[3]_PORT_B_address_reg = DFFE(S1_q_b[3]_PORT_B_address, S1_q_b[3]_clock_1, , , );
S1_q_b[3]_PORT_A_write_enable = J1_wren_io;
S1_q_b[3]_PORT_A_write_enable_reg = DFFE(S1_q_b[3]_PORT_A_write_enable, S1_q_b[3]_clock_0, , , );
S1_q_b[3]_PORT_B_write_enable = GND;
S1_q_b[3]_PORT_B_write_enable_reg = DFFE(S1_q_b[3]_PORT_B_write_enable, S1_q_b[3]_clock_1, , , );
S1_q_b[3]_clock_0 = U1__clk1;
S1_q_b[3]_clock_1 = U1__clk0;
S1_q_b[3]_PORT_B_data_out = MEMORY(S1_q_b[3]_PORT_A_data_in_reg, S1_q_b[3]_PORT_B_data_in_reg, S1_q_b[3]_PORT_A_address_reg, S1_q_b[3]_PORT_B_address_reg, S1_q_b[3]_PORT_A_write_enable_reg, S1_q_b[3]_PORT_B_write_enable_reg, , , S1_q_b[3]_clock_0, S1_q_b[3]_clock_1, , , , );
S1_q_b[3] = S1_q_b[3]_PORT_B_data_out[0];


--S1_q_a[4] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[4]
S1_q_a[4]_PORT_A_data_in = J1_wdata_cor_4;
S1_q_a[4]_PORT_A_data_in_reg = DFFE(S1_q_a[4]_PORT_A_data_in, S1_q_a[4]_clock_0, , , );
S1_q_a[4]_PORT_B_data_in = ~GND;
S1_q_a[4]_PORT_B_data_in_reg = DFFE(S1_q_a[4]_PORT_B_data_in, S1_q_a[4]_clock_1, , , );
S1_q_a[4]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[4]_PORT_A_address_reg = DFFE(S1_q_a[4]_PORT_A_address, S1_q_a[4]_clock_0, , , );
S1_q_a[4]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[4]_PORT_B_address_reg = DFFE(S1_q_a[4]_PORT_B_address, S1_q_a[4]_clock_1, , , );
S1_q_a[4]_PORT_A_write_enable = J1_wren_io;
S1_q_a[4]_PORT_A_write_enable_reg = DFFE(S1_q_a[4]_PORT_A_write_enable, S1_q_a[4]_clock_0, , , );
S1_q_a[4]_PORT_B_write_enable = GND;
S1_q_a[4]_PORT_B_write_enable_reg = DFFE(S1_q_a[4]_PORT_B_write_enable, S1_q_a[4]_clock_1, , , );
S1_q_a[4]_clock_0 = U1__clk1;
S1_q_a[4]_clock_1 = U1__clk0;
S1_q_a[4]_PORT_A_data_out = MEMORY(S1_q_a[4]_PORT_A_data_in_reg, S1_q_a[4]_PORT_B_data_in_reg, S1_q_a[4]_PORT_A_address_reg, S1_q_a[4]_PORT_B_address_reg, S1_q_a[4]_PORT_A_write_enable_reg, S1_q_a[4]_PORT_B_write_enable_reg, , , S1_q_a[4]_clock_0, S1_q_a[4]_clock_1, , , , );
S1_q_a[4]_PORT_A_data_out_reg = DFFE(S1_q_a[4]_PORT_A_data_out, S1_q_a[4]_clock_0, , , );
S1_q_a[4] = S1_q_a[4]_PORT_A_data_out_reg[0];

--S1_q_b[4] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[4]
S1_q_b[4]_PORT_A_data_in = J1_wdata_cor_4;
S1_q_b[4]_PORT_A_data_in_reg = DFFE(S1_q_b[4]_PORT_A_data_in, S1_q_b[4]_clock_0, , , );
S1_q_b[4]_PORT_B_data_in = ~GND;
S1_q_b[4]_PORT_B_data_in_reg = DFFE(S1_q_b[4]_PORT_B_data_in, S1_q_b[4]_clock_1, , , );
S1_q_b[4]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[4]_PORT_A_address_reg = DFFE(S1_q_b[4]_PORT_A_address, S1_q_b[4]_clock_0, , , );
S1_q_b[4]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[4]_PORT_B_address_reg = DFFE(S1_q_b[4]_PORT_B_address, S1_q_b[4]_clock_1, , , );
S1_q_b[4]_PORT_A_write_enable = J1_wren_io;
S1_q_b[4]_PORT_A_write_enable_reg = DFFE(S1_q_b[4]_PORT_A_write_enable, S1_q_b[4]_clock_0, , , );
S1_q_b[4]_PORT_B_write_enable = GND;
S1_q_b[4]_PORT_B_write_enable_reg = DFFE(S1_q_b[4]_PORT_B_write_enable, S1_q_b[4]_clock_1, , , );
S1_q_b[4]_clock_0 = U1__clk1;
S1_q_b[4]_clock_1 = U1__clk0;
S1_q_b[4]_PORT_B_data_out = MEMORY(S1_q_b[4]_PORT_A_data_in_reg, S1_q_b[4]_PORT_B_data_in_reg, S1_q_b[4]_PORT_A_address_reg, S1_q_b[4]_PORT_B_address_reg, S1_q_b[4]_PORT_A_write_enable_reg, S1_q_b[4]_PORT_B_write_enable_reg, , , S1_q_b[4]_clock_0, S1_q_b[4]_clock_1, , , , );
S1_q_b[4] = S1_q_b[4]_PORT_B_data_out[0];


--S1_q_a[5] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[5]
S1_q_a[5]_PORT_A_data_in = J1_wdata_cor_5;
S1_q_a[5]_PORT_A_data_in_reg = DFFE(S1_q_a[5]_PORT_A_data_in, S1_q_a[5]_clock_0, , , );
S1_q_a[5]_PORT_B_data_in = ~GND;
S1_q_a[5]_PORT_B_data_in_reg = DFFE(S1_q_a[5]_PORT_B_data_in, S1_q_a[5]_clock_1, , , );
S1_q_a[5]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[5]_PORT_A_address_reg = DFFE(S1_q_a[5]_PORT_A_address, S1_q_a[5]_clock_0, , , );
S1_q_a[5]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[5]_PORT_B_address_reg = DFFE(S1_q_a[5]_PORT_B_address, S1_q_a[5]_clock_1, , , );
S1_q_a[5]_PORT_A_write_enable = J1_wren_io;
S1_q_a[5]_PORT_A_write_enable_reg = DFFE(S1_q_a[5]_PORT_A_write_enable, S1_q_a[5]_clock_0, , , );
S1_q_a[5]_PORT_B_write_enable = GND;
S1_q_a[5]_PORT_B_write_enable_reg = DFFE(S1_q_a[5]_PORT_B_write_enable, S1_q_a[5]_clock_1, , , );
S1_q_a[5]_clock_0 = U1__clk1;
S1_q_a[5]_clock_1 = U1__clk0;
S1_q_a[5]_PORT_A_data_out = MEMORY(S1_q_a[5]_PORT_A_data_in_reg, S1_q_a[5]_PORT_B_data_in_reg, S1_q_a[5]_PORT_A_address_reg, S1_q_a[5]_PORT_B_address_reg, S1_q_a[5]_PORT_A_write_enable_reg, S1_q_a[5]_PORT_B_write_enable_reg, , , S1_q_a[5]_clock_0, S1_q_a[5]_clock_1, , , , );
S1_q_a[5]_PORT_A_data_out_reg = DFFE(S1_q_a[5]_PORT_A_data_out, S1_q_a[5]_clock_0, , , );
S1_q_a[5] = S1_q_a[5]_PORT_A_data_out_reg[0];

--S1_q_b[5] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[5]
S1_q_b[5]_PORT_A_data_in = J1_wdata_cor_5;
S1_q_b[5]_PORT_A_data_in_reg = DFFE(S1_q_b[5]_PORT_A_data_in, S1_q_b[5]_clock_0, , , );
S1_q_b[5]_PORT_B_data_in = ~GND;
S1_q_b[5]_PORT_B_data_in_reg = DFFE(S1_q_b[5]_PORT_B_data_in, S1_q_b[5]_clock_1, , , );
S1_q_b[5]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[5]_PORT_A_address_reg = DFFE(S1_q_b[5]_PORT_A_address, S1_q_b[5]_clock_0, , , );
S1_q_b[5]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[5]_PORT_B_address_reg = DFFE(S1_q_b[5]_PORT_B_address, S1_q_b[5]_clock_1, , , );
S1_q_b[5]_PORT_A_write_enable = J1_wren_io;
S1_q_b[5]_PORT_A_write_enable_reg = DFFE(S1_q_b[5]_PORT_A_write_enable, S1_q_b[5]_clock_0, , , );
S1_q_b[5]_PORT_B_write_enable = GND;
S1_q_b[5]_PORT_B_write_enable_reg = DFFE(S1_q_b[5]_PORT_B_write_enable, S1_q_b[5]_clock_1, , , );
S1_q_b[5]_clock_0 = U1__clk1;
S1_q_b[5]_clock_1 = U1__clk0;
S1_q_b[5]_PORT_B_data_out = MEMORY(S1_q_b[5]_PORT_A_data_in_reg, S1_q_b[5]_PORT_B_data_in_reg, S1_q_b[5]_PORT_A_address_reg, S1_q_b[5]_PORT_B_address_reg, S1_q_b[5]_PORT_A_write_enable_reg, S1_q_b[5]_PORT_B_write_enable_reg, , , S1_q_b[5]_clock_0, S1_q_b[5]_clock_1, , , , );
S1_q_b[5] = S1_q_b[5]_PORT_B_data_out[0];


--S1_q_a[6] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[6]
S1_q_a[6]_PORT_A_data_in = J1_wdata_cor_6;
S1_q_a[6]_PORT_A_data_in_reg = DFFE(S1_q_a[6]_PORT_A_data_in, S1_q_a[6]_clock_0, , , );
S1_q_a[6]_PORT_B_data_in = ~GND;
S1_q_a[6]_PORT_B_data_in_reg = DFFE(S1_q_a[6]_PORT_B_data_in, S1_q_a[6]_clock_1, , , );
S1_q_a[6]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[6]_PORT_A_address_reg = DFFE(S1_q_a[6]_PORT_A_address, S1_q_a[6]_clock_0, , , );
S1_q_a[6]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[6]_PORT_B_address_reg = DFFE(S1_q_a[6]_PORT_B_address, S1_q_a[6]_clock_1, , , );
S1_q_a[6]_PORT_A_write_enable = J1_wren_io;
S1_q_a[6]_PORT_A_write_enable_reg = DFFE(S1_q_a[6]_PORT_A_write_enable, S1_q_a[6]_clock_0, , , );
S1_q_a[6]_PORT_B_write_enable = GND;
S1_q_a[6]_PORT_B_write_enable_reg = DFFE(S1_q_a[6]_PORT_B_write_enable, S1_q_a[6]_clock_1, , , );
S1_q_a[6]_clock_0 = U1__clk1;
S1_q_a[6]_clock_1 = U1__clk0;
S1_q_a[6]_PORT_A_data_out = MEMORY(S1_q_a[6]_PORT_A_data_in_reg, S1_q_a[6]_PORT_B_data_in_reg, S1_q_a[6]_PORT_A_address_reg, S1_q_a[6]_PORT_B_address_reg, S1_q_a[6]_PORT_A_write_enable_reg, S1_q_a[6]_PORT_B_write_enable_reg, , , S1_q_a[6]_clock_0, S1_q_a[6]_clock_1, , , , );
S1_q_a[6]_PORT_A_data_out_reg = DFFE(S1_q_a[6]_PORT_A_data_out, S1_q_a[6]_clock_0, , , );
S1_q_a[6] = S1_q_a[6]_PORT_A_data_out_reg[0];

--S1_q_b[6] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[6]
S1_q_b[6]_PORT_A_data_in = J1_wdata_cor_6;
S1_q_b[6]_PORT_A_data_in_reg = DFFE(S1_q_b[6]_PORT_A_data_in, S1_q_b[6]_clock_0, , , );
S1_q_b[6]_PORT_B_data_in = ~GND;
S1_q_b[6]_PORT_B_data_in_reg = DFFE(S1_q_b[6]_PORT_B_data_in, S1_q_b[6]_clock_1, , , );
S1_q_b[6]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[6]_PORT_A_address_reg = DFFE(S1_q_b[6]_PORT_A_address, S1_q_b[6]_clock_0, , , );
S1_q_b[6]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[6]_PORT_B_address_reg = DFFE(S1_q_b[6]_PORT_B_address, S1_q_b[6]_clock_1, , , );
S1_q_b[6]_PORT_A_write_enable = J1_wren_io;
S1_q_b[6]_PORT_A_write_enable_reg = DFFE(S1_q_b[6]_PORT_A_write_enable, S1_q_b[6]_clock_0, , , );
S1_q_b[6]_PORT_B_write_enable = GND;
S1_q_b[6]_PORT_B_write_enable_reg = DFFE(S1_q_b[6]_PORT_B_write_enable, S1_q_b[6]_clock_1, , , );
S1_q_b[6]_clock_0 = U1__clk1;
S1_q_b[6]_clock_1 = U1__clk0;
S1_q_b[6]_PORT_B_data_out = MEMORY(S1_q_b[6]_PORT_A_data_in_reg, S1_q_b[6]_PORT_B_data_in_reg, S1_q_b[6]_PORT_A_address_reg, S1_q_b[6]_PORT_B_address_reg, S1_q_b[6]_PORT_A_write_enable_reg, S1_q_b[6]_PORT_B_write_enable_reg, , , S1_q_b[6]_clock_0, S1_q_b[6]_clock_1, , , , );
S1_q_b[6] = S1_q_b[6]_PORT_B_data_out[0];


--S1_q_a[7] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[7]
S1_q_a[7]_PORT_A_data_in = J1_wdata_cor_7;
S1_q_a[7]_PORT_A_data_in_reg = DFFE(S1_q_a[7]_PORT_A_data_in, S1_q_a[7]_clock_0, , , );
S1_q_a[7]_PORT_B_data_in = ~GND;
S1_q_a[7]_PORT_B_data_in_reg = DFFE(S1_q_a[7]_PORT_B_data_in, S1_q_a[7]_clock_1, , , );
S1_q_a[7]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[7]_PORT_A_address_reg = DFFE(S1_q_a[7]_PORT_A_address, S1_q_a[7]_clock_0, , , );
S1_q_a[7]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[7]_PORT_B_address_reg = DFFE(S1_q_a[7]_PORT_B_address, S1_q_a[7]_clock_1, , , );
S1_q_a[7]_PORT_A_write_enable = J1_wren_io;
S1_q_a[7]_PORT_A_write_enable_reg = DFFE(S1_q_a[7]_PORT_A_write_enable, S1_q_a[7]_clock_0, , , );
S1_q_a[7]_PORT_B_write_enable = GND;
S1_q_a[7]_PORT_B_write_enable_reg = DFFE(S1_q_a[7]_PORT_B_write_enable, S1_q_a[7]_clock_1, , , );
S1_q_a[7]_clock_0 = U1__clk1;
S1_q_a[7]_clock_1 = U1__clk0;
S1_q_a[7]_PORT_A_data_out = MEMORY(S1_q_a[7]_PORT_A_data_in_reg, S1_q_a[7]_PORT_B_data_in_reg, S1_q_a[7]_PORT_A_address_reg, S1_q_a[7]_PORT_B_address_reg, S1_q_a[7]_PORT_A_write_enable_reg, S1_q_a[7]_PORT_B_write_enable_reg, , , S1_q_a[7]_clock_0, S1_q_a[7]_clock_1, , , , );
S1_q_a[7]_PORT_A_data_out_reg = DFFE(S1_q_a[7]_PORT_A_data_out, S1_q_a[7]_clock_0, , , );
S1_q_a[7] = S1_q_a[7]_PORT_A_data_out_reg[0];

--S1_q_b[7] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[7]
S1_q_b[7]_PORT_A_data_in = J1_wdata_cor_7;
S1_q_b[7]_PORT_A_data_in_reg = DFFE(S1_q_b[7]_PORT_A_data_in, S1_q_b[7]_clock_0, , , );
S1_q_b[7]_PORT_B_data_in = ~GND;
S1_q_b[7]_PORT_B_data_in_reg = DFFE(S1_q_b[7]_PORT_B_data_in, S1_q_b[7]_clock_1, , , );
S1_q_b[7]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[7]_PORT_A_address_reg = DFFE(S1_q_b[7]_PORT_A_address, S1_q_b[7]_clock_0, , , );
S1_q_b[7]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[7]_PORT_B_address_reg = DFFE(S1_q_b[7]_PORT_B_address, S1_q_b[7]_clock_1, , , );
S1_q_b[7]_PORT_A_write_enable = J1_wren_io;
S1_q_b[7]_PORT_A_write_enable_reg = DFFE(S1_q_b[7]_PORT_A_write_enable, S1_q_b[7]_clock_0, , , );
S1_q_b[7]_PORT_B_write_enable = GND;
S1_q_b[7]_PORT_B_write_enable_reg = DFFE(S1_q_b[7]_PORT_B_write_enable, S1_q_b[7]_clock_1, , , );
S1_q_b[7]_clock_0 = U1__clk1;
S1_q_b[7]_clock_1 = U1__clk0;
S1_q_b[7]_PORT_B_data_out = MEMORY(S1_q_b[7]_PORT_A_data_in_reg, S1_q_b[7]_PORT_B_data_in_reg, S1_q_b[7]_PORT_A_address_reg, S1_q_b[7]_PORT_B_address_reg, S1_q_b[7]_PORT_A_write_enable_reg, S1_q_b[7]_PORT_B_write_enable_reg, , , S1_q_b[7]_clock_0, S1_q_b[7]_clock_1, , , , );
S1_q_b[7] = S1_q_b[7]_PORT_B_data_out[0];


--S1_q_a[8] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[8]
S1_q_a[8]_PORT_A_data_in = J1_wdata_cor_8;
S1_q_a[8]_PORT_A_data_in_reg = DFFE(S1_q_a[8]_PORT_A_data_in, S1_q_a[8]_clock_0, , , );
S1_q_a[8]_PORT_B_data_in = ~GND;
S1_q_a[8]_PORT_B_data_in_reg = DFFE(S1_q_a[8]_PORT_B_data_in, S1_q_a[8]_clock_1, , , );
S1_q_a[8]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[8]_PORT_A_address_reg = DFFE(S1_q_a[8]_PORT_A_address, S1_q_a[8]_clock_0, , , );
S1_q_a[8]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[8]_PORT_B_address_reg = DFFE(S1_q_a[8]_PORT_B_address, S1_q_a[8]_clock_1, , , );
S1_q_a[8]_PORT_A_write_enable = J1_wren_io;
S1_q_a[8]_PORT_A_write_enable_reg = DFFE(S1_q_a[8]_PORT_A_write_enable, S1_q_a[8]_clock_0, , , );
S1_q_a[8]_PORT_B_write_enable = GND;
S1_q_a[8]_PORT_B_write_enable_reg = DFFE(S1_q_a[8]_PORT_B_write_enable, S1_q_a[8]_clock_1, , , );
S1_q_a[8]_clock_0 = U1__clk1;
S1_q_a[8]_clock_1 = U1__clk0;
S1_q_a[8]_PORT_A_data_out = MEMORY(S1_q_a[8]_PORT_A_data_in_reg, S1_q_a[8]_PORT_B_data_in_reg, S1_q_a[8]_PORT_A_address_reg, S1_q_a[8]_PORT_B_address_reg, S1_q_a[8]_PORT_A_write_enable_reg, S1_q_a[8]_PORT_B_write_enable_reg, , , S1_q_a[8]_clock_0, S1_q_a[8]_clock_1, , , , );
S1_q_a[8]_PORT_A_data_out_reg = DFFE(S1_q_a[8]_PORT_A_data_out, S1_q_a[8]_clock_0, , , );
S1_q_a[8] = S1_q_a[8]_PORT_A_data_out_reg[0];

--S1_q_b[8] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[8]
S1_q_b[8]_PORT_A_data_in = J1_wdata_cor_8;
S1_q_b[8]_PORT_A_data_in_reg = DFFE(S1_q_b[8]_PORT_A_data_in, S1_q_b[8]_clock_0, , , );
S1_q_b[8]_PORT_B_data_in = ~GND;
S1_q_b[8]_PORT_B_data_in_reg = DFFE(S1_q_b[8]_PORT_B_data_in, S1_q_b[8]_clock_1, , , );
S1_q_b[8]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[8]_PORT_A_address_reg = DFFE(S1_q_b[8]_PORT_A_address, S1_q_b[8]_clock_0, , , );
S1_q_b[8]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[8]_PORT_B_address_reg = DFFE(S1_q_b[8]_PORT_B_address, S1_q_b[8]_clock_1, , , );
S1_q_b[8]_PORT_A_write_enable = J1_wren_io;
S1_q_b[8]_PORT_A_write_enable_reg = DFFE(S1_q_b[8]_PORT_A_write_enable, S1_q_b[8]_clock_0, , , );
S1_q_b[8]_PORT_B_write_enable = GND;
S1_q_b[8]_PORT_B_write_enable_reg = DFFE(S1_q_b[8]_PORT_B_write_enable, S1_q_b[8]_clock_1, , , );
S1_q_b[8]_clock_0 = U1__clk1;
S1_q_b[8]_clock_1 = U1__clk0;
S1_q_b[8]_PORT_B_data_out = MEMORY(S1_q_b[8]_PORT_A_data_in_reg, S1_q_b[8]_PORT_B_data_in_reg, S1_q_b[8]_PORT_A_address_reg, S1_q_b[8]_PORT_B_address_reg, S1_q_b[8]_PORT_A_write_enable_reg, S1_q_b[8]_PORT_B_write_enable_reg, , , S1_q_b[8]_clock_0, S1_q_b[8]_clock_1, , , , );
S1_q_b[8] = S1_q_b[8]_PORT_B_data_out[0];


--S1_q_a[9] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[9]
S1_q_a[9]_PORT_A_data_in = J1_wdata_cor_9;
S1_q_a[9]_PORT_A_data_in_reg = DFFE(S1_q_a[9]_PORT_A_data_in, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_data_in = ~GND;
S1_q_a[9]_PORT_B_data_in_reg = DFFE(S1_q_a[9]_PORT_B_data_in, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[9]_PORT_A_address_reg = DFFE(S1_q_a[9]_PORT_A_address, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[9]_PORT_B_address_reg = DFFE(S1_q_a[9]_PORT_B_address, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_PORT_A_write_enable = J1_wren_io;
S1_q_a[9]_PORT_A_write_enable_reg = DFFE(S1_q_a[9]_PORT_A_write_enable, S1_q_a[9]_clock_0, , , );
S1_q_a[9]_PORT_B_write_enable = GND;
S1_q_a[9]_PORT_B_write_enable_reg = DFFE(S1_q_a[9]_PORT_B_write_enable, S1_q_a[9]_clock_1, , , );
S1_q_a[9]_clock_0 = U1__clk1;
S1_q_a[9]_clock_1 = U1__clk0;
S1_q_a[9]_PORT_A_data_out = MEMORY(S1_q_a[9]_PORT_A_data_in_reg, S1_q_a[9]_PORT_B_data_in_reg, S1_q_a[9]_PORT_A_address_reg, S1_q_a[9]_PORT_B_address_reg, S1_q_a[9]_PORT_A_write_enable_reg, S1_q_a[9]_PORT_B_write_enable_reg, , , S1_q_a[9]_clock_0, S1_q_a[9]_clock_1, , , , );
S1_q_a[9]_PORT_A_data_out_reg = DFFE(S1_q_a[9]_PORT_A_data_out, S1_q_a[9]_clock_0, , , );
S1_q_a[9] = S1_q_a[9]_PORT_A_data_out_reg[0];

--S1_q_b[9] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[9]
S1_q_b[9]_PORT_A_data_in = J1_wdata_cor_9;
S1_q_b[9]_PORT_A_data_in_reg = DFFE(S1_q_b[9]_PORT_A_data_in, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_data_in = ~GND;
S1_q_b[9]_PORT_B_data_in_reg = DFFE(S1_q_b[9]_PORT_B_data_in, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[9]_PORT_A_address_reg = DFFE(S1_q_b[9]_PORT_A_address, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[9]_PORT_B_address_reg = DFFE(S1_q_b[9]_PORT_B_address, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_PORT_A_write_enable = J1_wren_io;
S1_q_b[9]_PORT_A_write_enable_reg = DFFE(S1_q_b[9]_PORT_A_write_enable, S1_q_b[9]_clock_0, , , );
S1_q_b[9]_PORT_B_write_enable = GND;
S1_q_b[9]_PORT_B_write_enable_reg = DFFE(S1_q_b[9]_PORT_B_write_enable, S1_q_b[9]_clock_1, , , );
S1_q_b[9]_clock_0 = U1__clk1;
S1_q_b[9]_clock_1 = U1__clk0;
S1_q_b[9]_PORT_B_data_out = MEMORY(S1_q_b[9]_PORT_A_data_in_reg, S1_q_b[9]_PORT_B_data_in_reg, S1_q_b[9]_PORT_A_address_reg, S1_q_b[9]_PORT_B_address_reg, S1_q_b[9]_PORT_A_write_enable_reg, S1_q_b[9]_PORT_B_write_enable_reg, , , S1_q_b[9]_clock_0, S1_q_b[9]_clock_1, , , , );
S1_q_b[9] = S1_q_b[9]_PORT_B_data_out[0];


--S1_q_a[10] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[10]
S1_q_a[10]_PORT_A_data_in = J1_wdata_cor_10;
S1_q_a[10]_PORT_A_data_in_reg = DFFE(S1_q_a[10]_PORT_A_data_in, S1_q_a[10]_clock_0, , , );
S1_q_a[10]_PORT_B_data_in = ~GND;
S1_q_a[10]_PORT_B_data_in_reg = DFFE(S1_q_a[10]_PORT_B_data_in, S1_q_a[10]_clock_1, , , );
S1_q_a[10]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[10]_PORT_A_address_reg = DFFE(S1_q_a[10]_PORT_A_address, S1_q_a[10]_clock_0, , , );
S1_q_a[10]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[10]_PORT_B_address_reg = DFFE(S1_q_a[10]_PORT_B_address, S1_q_a[10]_clock_1, , , );
S1_q_a[10]_PORT_A_write_enable = J1_wren_io;
S1_q_a[10]_PORT_A_write_enable_reg = DFFE(S1_q_a[10]_PORT_A_write_enable, S1_q_a[10]_clock_0, , , );
S1_q_a[10]_PORT_B_write_enable = GND;
S1_q_a[10]_PORT_B_write_enable_reg = DFFE(S1_q_a[10]_PORT_B_write_enable, S1_q_a[10]_clock_1, , , );
S1_q_a[10]_clock_0 = U1__clk1;
S1_q_a[10]_clock_1 = U1__clk0;
S1_q_a[10]_PORT_A_data_out = MEMORY(S1_q_a[10]_PORT_A_data_in_reg, S1_q_a[10]_PORT_B_data_in_reg, S1_q_a[10]_PORT_A_address_reg, S1_q_a[10]_PORT_B_address_reg, S1_q_a[10]_PORT_A_write_enable_reg, S1_q_a[10]_PORT_B_write_enable_reg, , , S1_q_a[10]_clock_0, S1_q_a[10]_clock_1, , , , );
S1_q_a[10]_PORT_A_data_out_reg = DFFE(S1_q_a[10]_PORT_A_data_out, S1_q_a[10]_clock_0, , , );
S1_q_a[10] = S1_q_a[10]_PORT_A_data_out_reg[0];

--S1_q_b[10] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[10]
S1_q_b[10]_PORT_A_data_in = J1_wdata_cor_10;
S1_q_b[10]_PORT_A_data_in_reg = DFFE(S1_q_b[10]_PORT_A_data_in, S1_q_b[10]_clock_0, , , );
S1_q_b[10]_PORT_B_data_in = ~GND;
S1_q_b[10]_PORT_B_data_in_reg = DFFE(S1_q_b[10]_PORT_B_data_in, S1_q_b[10]_clock_1, , , );
S1_q_b[10]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[10]_PORT_A_address_reg = DFFE(S1_q_b[10]_PORT_A_address, S1_q_b[10]_clock_0, , , );
S1_q_b[10]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[10]_PORT_B_address_reg = DFFE(S1_q_b[10]_PORT_B_address, S1_q_b[10]_clock_1, , , );
S1_q_b[10]_PORT_A_write_enable = J1_wren_io;
S1_q_b[10]_PORT_A_write_enable_reg = DFFE(S1_q_b[10]_PORT_A_write_enable, S1_q_b[10]_clock_0, , , );
S1_q_b[10]_PORT_B_write_enable = GND;
S1_q_b[10]_PORT_B_write_enable_reg = DFFE(S1_q_b[10]_PORT_B_write_enable, S1_q_b[10]_clock_1, , , );
S1_q_b[10]_clock_0 = U1__clk1;
S1_q_b[10]_clock_1 = U1__clk0;
S1_q_b[10]_PORT_B_data_out = MEMORY(S1_q_b[10]_PORT_A_data_in_reg, S1_q_b[10]_PORT_B_data_in_reg, S1_q_b[10]_PORT_A_address_reg, S1_q_b[10]_PORT_B_address_reg, S1_q_b[10]_PORT_A_write_enable_reg, S1_q_b[10]_PORT_B_write_enable_reg, , , S1_q_b[10]_clock_0, S1_q_b[10]_clock_1, , , , );
S1_q_b[10] = S1_q_b[10]_PORT_B_data_out[0];


--S1_q_a[11] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[11]
S1_q_a[11]_PORT_A_data_in = J1_wdata_cor_11;
S1_q_a[11]_PORT_A_data_in_reg = DFFE(S1_q_a[11]_PORT_A_data_in, S1_q_a[11]_clock_0, , , );
S1_q_a[11]_PORT_B_data_in = ~GND;
S1_q_a[11]_PORT_B_data_in_reg = DFFE(S1_q_a[11]_PORT_B_data_in, S1_q_a[11]_clock_1, , , );
S1_q_a[11]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[11]_PORT_A_address_reg = DFFE(S1_q_a[11]_PORT_A_address, S1_q_a[11]_clock_0, , , );
S1_q_a[11]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[11]_PORT_B_address_reg = DFFE(S1_q_a[11]_PORT_B_address, S1_q_a[11]_clock_1, , , );
S1_q_a[11]_PORT_A_write_enable = J1_wren_io;
S1_q_a[11]_PORT_A_write_enable_reg = DFFE(S1_q_a[11]_PORT_A_write_enable, S1_q_a[11]_clock_0, , , );
S1_q_a[11]_PORT_B_write_enable = GND;
S1_q_a[11]_PORT_B_write_enable_reg = DFFE(S1_q_a[11]_PORT_B_write_enable, S1_q_a[11]_clock_1, , , );
S1_q_a[11]_clock_0 = U1__clk1;
S1_q_a[11]_clock_1 = U1__clk0;
S1_q_a[11]_PORT_A_data_out = MEMORY(S1_q_a[11]_PORT_A_data_in_reg, S1_q_a[11]_PORT_B_data_in_reg, S1_q_a[11]_PORT_A_address_reg, S1_q_a[11]_PORT_B_address_reg, S1_q_a[11]_PORT_A_write_enable_reg, S1_q_a[11]_PORT_B_write_enable_reg, , , S1_q_a[11]_clock_0, S1_q_a[11]_clock_1, , , , );
S1_q_a[11]_PORT_A_data_out_reg = DFFE(S1_q_a[11]_PORT_A_data_out, S1_q_a[11]_clock_0, , , );
S1_q_a[11] = S1_q_a[11]_PORT_A_data_out_reg[0];

--S1_q_b[11] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[11]
S1_q_b[11]_PORT_A_data_in = J1_wdata_cor_11;
S1_q_b[11]_PORT_A_data_in_reg = DFFE(S1_q_b[11]_PORT_A_data_in, S1_q_b[11]_clock_0, , , );
S1_q_b[11]_PORT_B_data_in = ~GND;
S1_q_b[11]_PORT_B_data_in_reg = DFFE(S1_q_b[11]_PORT_B_data_in, S1_q_b[11]_clock_1, , , );
S1_q_b[11]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[11]_PORT_A_address_reg = DFFE(S1_q_b[11]_PORT_A_address, S1_q_b[11]_clock_0, , , );
S1_q_b[11]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[11]_PORT_B_address_reg = DFFE(S1_q_b[11]_PORT_B_address, S1_q_b[11]_clock_1, , , );
S1_q_b[11]_PORT_A_write_enable = J1_wren_io;
S1_q_b[11]_PORT_A_write_enable_reg = DFFE(S1_q_b[11]_PORT_A_write_enable, S1_q_b[11]_clock_0, , , );
S1_q_b[11]_PORT_B_write_enable = GND;
S1_q_b[11]_PORT_B_write_enable_reg = DFFE(S1_q_b[11]_PORT_B_write_enable, S1_q_b[11]_clock_1, , , );
S1_q_b[11]_clock_0 = U1__clk1;
S1_q_b[11]_clock_1 = U1__clk0;
S1_q_b[11]_PORT_B_data_out = MEMORY(S1_q_b[11]_PORT_A_data_in_reg, S1_q_b[11]_PORT_B_data_in_reg, S1_q_b[11]_PORT_A_address_reg, S1_q_b[11]_PORT_B_address_reg, S1_q_b[11]_PORT_A_write_enable_reg, S1_q_b[11]_PORT_B_write_enable_reg, , , S1_q_b[11]_clock_0, S1_q_b[11]_clock_1, , , , );
S1_q_b[11] = S1_q_b[11]_PORT_B_data_out[0];


--S1_q_a[12] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[12]
S1_q_a[12]_PORT_A_data_in = J1_wdata_cor_12;
S1_q_a[12]_PORT_A_data_in_reg = DFFE(S1_q_a[12]_PORT_A_data_in, S1_q_a[12]_clock_0, , , );
S1_q_a[12]_PORT_B_data_in = ~GND;
S1_q_a[12]_PORT_B_data_in_reg = DFFE(S1_q_a[12]_PORT_B_data_in, S1_q_a[12]_clock_1, , , );
S1_q_a[12]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[12]_PORT_A_address_reg = DFFE(S1_q_a[12]_PORT_A_address, S1_q_a[12]_clock_0, , , );
S1_q_a[12]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[12]_PORT_B_address_reg = DFFE(S1_q_a[12]_PORT_B_address, S1_q_a[12]_clock_1, , , );
S1_q_a[12]_PORT_A_write_enable = J1_wren_io;
S1_q_a[12]_PORT_A_write_enable_reg = DFFE(S1_q_a[12]_PORT_A_write_enable, S1_q_a[12]_clock_0, , , );
S1_q_a[12]_PORT_B_write_enable = GND;
S1_q_a[12]_PORT_B_write_enable_reg = DFFE(S1_q_a[12]_PORT_B_write_enable, S1_q_a[12]_clock_1, , , );
S1_q_a[12]_clock_0 = U1__clk1;
S1_q_a[12]_clock_1 = U1__clk0;
S1_q_a[12]_PORT_A_data_out = MEMORY(S1_q_a[12]_PORT_A_data_in_reg, S1_q_a[12]_PORT_B_data_in_reg, S1_q_a[12]_PORT_A_address_reg, S1_q_a[12]_PORT_B_address_reg, S1_q_a[12]_PORT_A_write_enable_reg, S1_q_a[12]_PORT_B_write_enable_reg, , , S1_q_a[12]_clock_0, S1_q_a[12]_clock_1, , , , );
S1_q_a[12]_PORT_A_data_out_reg = DFFE(S1_q_a[12]_PORT_A_data_out, S1_q_a[12]_clock_0, , , );
S1_q_a[12] = S1_q_a[12]_PORT_A_data_out_reg[0];

--S1_q_b[12] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[12]
S1_q_b[12]_PORT_A_data_in = J1_wdata_cor_12;
S1_q_b[12]_PORT_A_data_in_reg = DFFE(S1_q_b[12]_PORT_A_data_in, S1_q_b[12]_clock_0, , , );
S1_q_b[12]_PORT_B_data_in = ~GND;
S1_q_b[12]_PORT_B_data_in_reg = DFFE(S1_q_b[12]_PORT_B_data_in, S1_q_b[12]_clock_1, , , );
S1_q_b[12]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[12]_PORT_A_address_reg = DFFE(S1_q_b[12]_PORT_A_address, S1_q_b[12]_clock_0, , , );
S1_q_b[12]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[12]_PORT_B_address_reg = DFFE(S1_q_b[12]_PORT_B_address, S1_q_b[12]_clock_1, , , );
S1_q_b[12]_PORT_A_write_enable = J1_wren_io;
S1_q_b[12]_PORT_A_write_enable_reg = DFFE(S1_q_b[12]_PORT_A_write_enable, S1_q_b[12]_clock_0, , , );
S1_q_b[12]_PORT_B_write_enable = GND;
S1_q_b[12]_PORT_B_write_enable_reg = DFFE(S1_q_b[12]_PORT_B_write_enable, S1_q_b[12]_clock_1, , , );
S1_q_b[12]_clock_0 = U1__clk1;
S1_q_b[12]_clock_1 = U1__clk0;
S1_q_b[12]_PORT_B_data_out = MEMORY(S1_q_b[12]_PORT_A_data_in_reg, S1_q_b[12]_PORT_B_data_in_reg, S1_q_b[12]_PORT_A_address_reg, S1_q_b[12]_PORT_B_address_reg, S1_q_b[12]_PORT_A_write_enable_reg, S1_q_b[12]_PORT_B_write_enable_reg, , , S1_q_b[12]_clock_0, S1_q_b[12]_clock_1, , , , );
S1_q_b[12] = S1_q_b[12]_PORT_B_data_out[0];


--S1_q_a[13] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[13]
S1_q_a[13]_PORT_A_data_in = J1_wdata_cor_13;
S1_q_a[13]_PORT_A_data_in_reg = DFFE(S1_q_a[13]_PORT_A_data_in, S1_q_a[13]_clock_0, , , );
S1_q_a[13]_PORT_B_data_in = ~GND;
S1_q_a[13]_PORT_B_data_in_reg = DFFE(S1_q_a[13]_PORT_B_data_in, S1_q_a[13]_clock_1, , , );
S1_q_a[13]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[13]_PORT_A_address_reg = DFFE(S1_q_a[13]_PORT_A_address, S1_q_a[13]_clock_0, , , );
S1_q_a[13]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[13]_PORT_B_address_reg = DFFE(S1_q_a[13]_PORT_B_address, S1_q_a[13]_clock_1, , , );
S1_q_a[13]_PORT_A_write_enable = J1_wren_io;
S1_q_a[13]_PORT_A_write_enable_reg = DFFE(S1_q_a[13]_PORT_A_write_enable, S1_q_a[13]_clock_0, , , );
S1_q_a[13]_PORT_B_write_enable = GND;
S1_q_a[13]_PORT_B_write_enable_reg = DFFE(S1_q_a[13]_PORT_B_write_enable, S1_q_a[13]_clock_1, , , );
S1_q_a[13]_clock_0 = U1__clk1;
S1_q_a[13]_clock_1 = U1__clk0;
S1_q_a[13]_PORT_A_data_out = MEMORY(S1_q_a[13]_PORT_A_data_in_reg, S1_q_a[13]_PORT_B_data_in_reg, S1_q_a[13]_PORT_A_address_reg, S1_q_a[13]_PORT_B_address_reg, S1_q_a[13]_PORT_A_write_enable_reg, S1_q_a[13]_PORT_B_write_enable_reg, , , S1_q_a[13]_clock_0, S1_q_a[13]_clock_1, , , , );
S1_q_a[13]_PORT_A_data_out_reg = DFFE(S1_q_a[13]_PORT_A_data_out, S1_q_a[13]_clock_0, , , );
S1_q_a[13] = S1_q_a[13]_PORT_A_data_out_reg[0];

--S1_q_b[13] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[13]
S1_q_b[13]_PORT_A_data_in = J1_wdata_cor_13;
S1_q_b[13]_PORT_A_data_in_reg = DFFE(S1_q_b[13]_PORT_A_data_in, S1_q_b[13]_clock_0, , , );
S1_q_b[13]_PORT_B_data_in = ~GND;
S1_q_b[13]_PORT_B_data_in_reg = DFFE(S1_q_b[13]_PORT_B_data_in, S1_q_b[13]_clock_1, , , );
S1_q_b[13]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[13]_PORT_A_address_reg = DFFE(S1_q_b[13]_PORT_A_address, S1_q_b[13]_clock_0, , , );
S1_q_b[13]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[13]_PORT_B_address_reg = DFFE(S1_q_b[13]_PORT_B_address, S1_q_b[13]_clock_1, , , );
S1_q_b[13]_PORT_A_write_enable = J1_wren_io;
S1_q_b[13]_PORT_A_write_enable_reg = DFFE(S1_q_b[13]_PORT_A_write_enable, S1_q_b[13]_clock_0, , , );
S1_q_b[13]_PORT_B_write_enable = GND;
S1_q_b[13]_PORT_B_write_enable_reg = DFFE(S1_q_b[13]_PORT_B_write_enable, S1_q_b[13]_clock_1, , , );
S1_q_b[13]_clock_0 = U1__clk1;
S1_q_b[13]_clock_1 = U1__clk0;
S1_q_b[13]_PORT_B_data_out = MEMORY(S1_q_b[13]_PORT_A_data_in_reg, S1_q_b[13]_PORT_B_data_in_reg, S1_q_b[13]_PORT_A_address_reg, S1_q_b[13]_PORT_B_address_reg, S1_q_b[13]_PORT_A_write_enable_reg, S1_q_b[13]_PORT_B_write_enable_reg, , , S1_q_b[13]_clock_0, S1_q_b[13]_clock_1, , , , );
S1_q_b[13] = S1_q_b[13]_PORT_B_data_out[0];


--S1_q_a[15] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[15]
S1_q_a[15]_PORT_A_data_in = X1_request_11;
S1_q_a[15]_PORT_A_data_in_reg = DFFE(S1_q_a[15]_PORT_A_data_in, S1_q_a[15]_clock_0, , , );
S1_q_a[15]_PORT_B_data_in = ~GND;
S1_q_a[15]_PORT_B_data_in_reg = DFFE(S1_q_a[15]_PORT_B_data_in, S1_q_a[15]_clock_1, , , );
S1_q_a[15]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[15]_PORT_A_address_reg = DFFE(S1_q_a[15]_PORT_A_address, S1_q_a[15]_clock_0, , , );
S1_q_a[15]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[15]_PORT_B_address_reg = DFFE(S1_q_a[15]_PORT_B_address, S1_q_a[15]_clock_1, , , );
S1_q_a[15]_PORT_A_write_enable = J1_wren_io;
S1_q_a[15]_PORT_A_write_enable_reg = DFFE(S1_q_a[15]_PORT_A_write_enable, S1_q_a[15]_clock_0, , , );
S1_q_a[15]_PORT_B_write_enable = GND;
S1_q_a[15]_PORT_B_write_enable_reg = DFFE(S1_q_a[15]_PORT_B_write_enable, S1_q_a[15]_clock_1, , , );
S1_q_a[15]_clock_0 = U1__clk1;
S1_q_a[15]_clock_1 = U1__clk0;
S1_q_a[15]_PORT_A_data_out = MEMORY(S1_q_a[15]_PORT_A_data_in_reg, S1_q_a[15]_PORT_B_data_in_reg, S1_q_a[15]_PORT_A_address_reg, S1_q_a[15]_PORT_B_address_reg, S1_q_a[15]_PORT_A_write_enable_reg, S1_q_a[15]_PORT_B_write_enable_reg, , , S1_q_a[15]_clock_0, S1_q_a[15]_clock_1, , , , );
S1_q_a[15]_PORT_A_data_out_reg = DFFE(S1_q_a[15]_PORT_A_data_out, S1_q_a[15]_clock_0, , , );
S1_q_a[15] = S1_q_a[15]_PORT_A_data_out_reg[0];

--S1_q_b[15] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[15]
S1_q_b[15]_PORT_A_data_in = X1_request_11;
S1_q_b[15]_PORT_A_data_in_reg = DFFE(S1_q_b[15]_PORT_A_data_in, S1_q_b[15]_clock_0, , , );
S1_q_b[15]_PORT_B_data_in = ~GND;
S1_q_b[15]_PORT_B_data_in_reg = DFFE(S1_q_b[15]_PORT_B_data_in, S1_q_b[15]_clock_1, , , );
S1_q_b[15]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[15]_PORT_A_address_reg = DFFE(S1_q_b[15]_PORT_A_address, S1_q_b[15]_clock_0, , , );
S1_q_b[15]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[15]_PORT_B_address_reg = DFFE(S1_q_b[15]_PORT_B_address, S1_q_b[15]_clock_1, , , );
S1_q_b[15]_PORT_A_write_enable = J1_wren_io;
S1_q_b[15]_PORT_A_write_enable_reg = DFFE(S1_q_b[15]_PORT_A_write_enable, S1_q_b[15]_clock_0, , , );
S1_q_b[15]_PORT_B_write_enable = GND;
S1_q_b[15]_PORT_B_write_enable_reg = DFFE(S1_q_b[15]_PORT_B_write_enable, S1_q_b[15]_clock_1, , , );
S1_q_b[15]_clock_0 = U1__clk1;
S1_q_b[15]_clock_1 = U1__clk0;
S1_q_b[15]_PORT_B_data_out = MEMORY(S1_q_b[15]_PORT_A_data_in_reg, S1_q_b[15]_PORT_B_data_in_reg, S1_q_b[15]_PORT_A_address_reg, S1_q_b[15]_PORT_B_address_reg, S1_q_b[15]_PORT_A_write_enable_reg, S1_q_b[15]_PORT_B_write_enable_reg, , , S1_q_b[15]_clock_0, S1_q_b[15]_clock_1, , , , );
S1_q_b[15] = S1_q_b[15]_PORT_B_data_out[0];


--S1_q_a[22] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[22]
S1_q_a[22]_PORT_A_data_in = X1_request_4;
S1_q_a[22]_PORT_A_data_in_reg = DFFE(S1_q_a[22]_PORT_A_data_in, S1_q_a[22]_clock_0, , , );
S1_q_a[22]_PORT_B_data_in = ~GND;
S1_q_a[22]_PORT_B_data_in_reg = DFFE(S1_q_a[22]_PORT_B_data_in, S1_q_a[22]_clock_1, , , );
S1_q_a[22]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[22]_PORT_A_address_reg = DFFE(S1_q_a[22]_PORT_A_address, S1_q_a[22]_clock_0, , , );
S1_q_a[22]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[22]_PORT_B_address_reg = DFFE(S1_q_a[22]_PORT_B_address, S1_q_a[22]_clock_1, , , );
S1_q_a[22]_PORT_A_write_enable = J1_wren_io;
S1_q_a[22]_PORT_A_write_enable_reg = DFFE(S1_q_a[22]_PORT_A_write_enable, S1_q_a[22]_clock_0, , , );
S1_q_a[22]_PORT_B_write_enable = GND;
S1_q_a[22]_PORT_B_write_enable_reg = DFFE(S1_q_a[22]_PORT_B_write_enable, S1_q_a[22]_clock_1, , , );
S1_q_a[22]_clock_0 = U1__clk1;
S1_q_a[22]_clock_1 = U1__clk0;
S1_q_a[22]_PORT_A_data_out = MEMORY(S1_q_a[22]_PORT_A_data_in_reg, S1_q_a[22]_PORT_B_data_in_reg, S1_q_a[22]_PORT_A_address_reg, S1_q_a[22]_PORT_B_address_reg, S1_q_a[22]_PORT_A_write_enable_reg, S1_q_a[22]_PORT_B_write_enable_reg, , , S1_q_a[22]_clock_0, S1_q_a[22]_clock_1, , , , );
S1_q_a[22]_PORT_A_data_out_reg = DFFE(S1_q_a[22]_PORT_A_data_out, S1_q_a[22]_clock_0, , , );
S1_q_a[22] = S1_q_a[22]_PORT_A_data_out_reg[0];

--S1_q_b[22] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[22]
S1_q_b[22]_PORT_A_data_in = X1_request_4;
S1_q_b[22]_PORT_A_data_in_reg = DFFE(S1_q_b[22]_PORT_A_data_in, S1_q_b[22]_clock_0, , , );
S1_q_b[22]_PORT_B_data_in = ~GND;
S1_q_b[22]_PORT_B_data_in_reg = DFFE(S1_q_b[22]_PORT_B_data_in, S1_q_b[22]_clock_1, , , );
S1_q_b[22]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[22]_PORT_A_address_reg = DFFE(S1_q_b[22]_PORT_A_address, S1_q_b[22]_clock_0, , , );
S1_q_b[22]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[22]_PORT_B_address_reg = DFFE(S1_q_b[22]_PORT_B_address, S1_q_b[22]_clock_1, , , );
S1_q_b[22]_PORT_A_write_enable = J1_wren_io;
S1_q_b[22]_PORT_A_write_enable_reg = DFFE(S1_q_b[22]_PORT_A_write_enable, S1_q_b[22]_clock_0, , , );
S1_q_b[22]_PORT_B_write_enable = GND;
S1_q_b[22]_PORT_B_write_enable_reg = DFFE(S1_q_b[22]_PORT_B_write_enable, S1_q_b[22]_clock_1, , , );
S1_q_b[22]_clock_0 = U1__clk1;
S1_q_b[22]_clock_1 = U1__clk0;
S1_q_b[22]_PORT_B_data_out = MEMORY(S1_q_b[22]_PORT_A_data_in_reg, S1_q_b[22]_PORT_B_data_in_reg, S1_q_b[22]_PORT_A_address_reg, S1_q_b[22]_PORT_B_address_reg, S1_q_b[22]_PORT_A_write_enable_reg, S1_q_b[22]_PORT_B_write_enable_reg, , , S1_q_b[22]_clock_0, S1_q_b[22]_clock_1, , , , );
S1_q_b[22] = S1_q_b[22]_PORT_B_data_out[0];


--S1_q_a[21] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[21]
S1_q_a[21]_PORT_A_data_in = X1_request_5;
S1_q_a[21]_PORT_A_data_in_reg = DFFE(S1_q_a[21]_PORT_A_data_in, S1_q_a[21]_clock_0, , , );
S1_q_a[21]_PORT_B_data_in = ~GND;
S1_q_a[21]_PORT_B_data_in_reg = DFFE(S1_q_a[21]_PORT_B_data_in, S1_q_a[21]_clock_1, , , );
S1_q_a[21]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[21]_PORT_A_address_reg = DFFE(S1_q_a[21]_PORT_A_address, S1_q_a[21]_clock_0, , , );
S1_q_a[21]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[21]_PORT_B_address_reg = DFFE(S1_q_a[21]_PORT_B_address, S1_q_a[21]_clock_1, , , );
S1_q_a[21]_PORT_A_write_enable = J1_wren_io;
S1_q_a[21]_PORT_A_write_enable_reg = DFFE(S1_q_a[21]_PORT_A_write_enable, S1_q_a[21]_clock_0, , , );
S1_q_a[21]_PORT_B_write_enable = GND;
S1_q_a[21]_PORT_B_write_enable_reg = DFFE(S1_q_a[21]_PORT_B_write_enable, S1_q_a[21]_clock_1, , , );
S1_q_a[21]_clock_0 = U1__clk1;
S1_q_a[21]_clock_1 = U1__clk0;
S1_q_a[21]_PORT_A_data_out = MEMORY(S1_q_a[21]_PORT_A_data_in_reg, S1_q_a[21]_PORT_B_data_in_reg, S1_q_a[21]_PORT_A_address_reg, S1_q_a[21]_PORT_B_address_reg, S1_q_a[21]_PORT_A_write_enable_reg, S1_q_a[21]_PORT_B_write_enable_reg, , , S1_q_a[21]_clock_0, S1_q_a[21]_clock_1, , , , );
S1_q_a[21]_PORT_A_data_out_reg = DFFE(S1_q_a[21]_PORT_A_data_out, S1_q_a[21]_clock_0, , , );
S1_q_a[21] = S1_q_a[21]_PORT_A_data_out_reg[0];

--S1_q_b[21] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[21]
S1_q_b[21]_PORT_A_data_in = X1_request_5;
S1_q_b[21]_PORT_A_data_in_reg = DFFE(S1_q_b[21]_PORT_A_data_in, S1_q_b[21]_clock_0, , , );
S1_q_b[21]_PORT_B_data_in = ~GND;
S1_q_b[21]_PORT_B_data_in_reg = DFFE(S1_q_b[21]_PORT_B_data_in, S1_q_b[21]_clock_1, , , );
S1_q_b[21]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[21]_PORT_A_address_reg = DFFE(S1_q_b[21]_PORT_A_address, S1_q_b[21]_clock_0, , , );
S1_q_b[21]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[21]_PORT_B_address_reg = DFFE(S1_q_b[21]_PORT_B_address, S1_q_b[21]_clock_1, , , );
S1_q_b[21]_PORT_A_write_enable = J1_wren_io;
S1_q_b[21]_PORT_A_write_enable_reg = DFFE(S1_q_b[21]_PORT_A_write_enable, S1_q_b[21]_clock_0, , , );
S1_q_b[21]_PORT_B_write_enable = GND;
S1_q_b[21]_PORT_B_write_enable_reg = DFFE(S1_q_b[21]_PORT_B_write_enable, S1_q_b[21]_clock_1, , , );
S1_q_b[21]_clock_0 = U1__clk1;
S1_q_b[21]_clock_1 = U1__clk0;
S1_q_b[21]_PORT_B_data_out = MEMORY(S1_q_b[21]_PORT_A_data_in_reg, S1_q_b[21]_PORT_B_data_in_reg, S1_q_b[21]_PORT_A_address_reg, S1_q_b[21]_PORT_B_address_reg, S1_q_b[21]_PORT_A_write_enable_reg, S1_q_b[21]_PORT_B_write_enable_reg, , , S1_q_b[21]_clock_0, S1_q_b[21]_clock_1, , , , );
S1_q_b[21] = S1_q_b[21]_PORT_B_data_out[0];


--S1_q_a[18] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[18]
S1_q_a[18]_PORT_A_data_in = X1_request_8;
S1_q_a[18]_PORT_A_data_in_reg = DFFE(S1_q_a[18]_PORT_A_data_in, S1_q_a[18]_clock_0, , , );
S1_q_a[18]_PORT_B_data_in = ~GND;
S1_q_a[18]_PORT_B_data_in_reg = DFFE(S1_q_a[18]_PORT_B_data_in, S1_q_a[18]_clock_1, , , );
S1_q_a[18]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[18]_PORT_A_address_reg = DFFE(S1_q_a[18]_PORT_A_address, S1_q_a[18]_clock_0, , , );
S1_q_a[18]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[18]_PORT_B_address_reg = DFFE(S1_q_a[18]_PORT_B_address, S1_q_a[18]_clock_1, , , );
S1_q_a[18]_PORT_A_write_enable = J1_wren_io;
S1_q_a[18]_PORT_A_write_enable_reg = DFFE(S1_q_a[18]_PORT_A_write_enable, S1_q_a[18]_clock_0, , , );
S1_q_a[18]_PORT_B_write_enable = GND;
S1_q_a[18]_PORT_B_write_enable_reg = DFFE(S1_q_a[18]_PORT_B_write_enable, S1_q_a[18]_clock_1, , , );
S1_q_a[18]_clock_0 = U1__clk1;
S1_q_a[18]_clock_1 = U1__clk0;
S1_q_a[18]_PORT_A_data_out = MEMORY(S1_q_a[18]_PORT_A_data_in_reg, S1_q_a[18]_PORT_B_data_in_reg, S1_q_a[18]_PORT_A_address_reg, S1_q_a[18]_PORT_B_address_reg, S1_q_a[18]_PORT_A_write_enable_reg, S1_q_a[18]_PORT_B_write_enable_reg, , , S1_q_a[18]_clock_0, S1_q_a[18]_clock_1, , , , );
S1_q_a[18]_PORT_A_data_out_reg = DFFE(S1_q_a[18]_PORT_A_data_out, S1_q_a[18]_clock_0, , , );
S1_q_a[18] = S1_q_a[18]_PORT_A_data_out_reg[0];

--S1_q_b[18] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[18]
S1_q_b[18]_PORT_A_data_in = X1_request_8;
S1_q_b[18]_PORT_A_data_in_reg = DFFE(S1_q_b[18]_PORT_A_data_in, S1_q_b[18]_clock_0, , , );
S1_q_b[18]_PORT_B_data_in = ~GND;
S1_q_b[18]_PORT_B_data_in_reg = DFFE(S1_q_b[18]_PORT_B_data_in, S1_q_b[18]_clock_1, , , );
S1_q_b[18]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[18]_PORT_A_address_reg = DFFE(S1_q_b[18]_PORT_A_address, S1_q_b[18]_clock_0, , , );
S1_q_b[18]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[18]_PORT_B_address_reg = DFFE(S1_q_b[18]_PORT_B_address, S1_q_b[18]_clock_1, , , );
S1_q_b[18]_PORT_A_write_enable = J1_wren_io;
S1_q_b[18]_PORT_A_write_enable_reg = DFFE(S1_q_b[18]_PORT_A_write_enable, S1_q_b[18]_clock_0, , , );
S1_q_b[18]_PORT_B_write_enable = GND;
S1_q_b[18]_PORT_B_write_enable_reg = DFFE(S1_q_b[18]_PORT_B_write_enable, S1_q_b[18]_clock_1, , , );
S1_q_b[18]_clock_0 = U1__clk1;
S1_q_b[18]_clock_1 = U1__clk0;
S1_q_b[18]_PORT_B_data_out = MEMORY(S1_q_b[18]_PORT_A_data_in_reg, S1_q_b[18]_PORT_B_data_in_reg, S1_q_b[18]_PORT_A_address_reg, S1_q_b[18]_PORT_B_address_reg, S1_q_b[18]_PORT_A_write_enable_reg, S1_q_b[18]_PORT_B_write_enable_reg, , , S1_q_b[18]_clock_0, S1_q_b[18]_clock_1, , , , );
S1_q_b[18] = S1_q_b[18]_PORT_B_data_out[0];


--S1_q_a[20] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[20]
S1_q_a[20]_PORT_A_data_in = X1_request_6;
S1_q_a[20]_PORT_A_data_in_reg = DFFE(S1_q_a[20]_PORT_A_data_in, S1_q_a[20]_clock_0, , , );
S1_q_a[20]_PORT_B_data_in = ~GND;
S1_q_a[20]_PORT_B_data_in_reg = DFFE(S1_q_a[20]_PORT_B_data_in, S1_q_a[20]_clock_1, , , );
S1_q_a[20]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[20]_PORT_A_address_reg = DFFE(S1_q_a[20]_PORT_A_address, S1_q_a[20]_clock_0, , , );
S1_q_a[20]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[20]_PORT_B_address_reg = DFFE(S1_q_a[20]_PORT_B_address, S1_q_a[20]_clock_1, , , );
S1_q_a[20]_PORT_A_write_enable = J1_wren_io;
S1_q_a[20]_PORT_A_write_enable_reg = DFFE(S1_q_a[20]_PORT_A_write_enable, S1_q_a[20]_clock_0, , , );
S1_q_a[20]_PORT_B_write_enable = GND;
S1_q_a[20]_PORT_B_write_enable_reg = DFFE(S1_q_a[20]_PORT_B_write_enable, S1_q_a[20]_clock_1, , , );
S1_q_a[20]_clock_0 = U1__clk1;
S1_q_a[20]_clock_1 = U1__clk0;
S1_q_a[20]_PORT_A_data_out = MEMORY(S1_q_a[20]_PORT_A_data_in_reg, S1_q_a[20]_PORT_B_data_in_reg, S1_q_a[20]_PORT_A_address_reg, S1_q_a[20]_PORT_B_address_reg, S1_q_a[20]_PORT_A_write_enable_reg, S1_q_a[20]_PORT_B_write_enable_reg, , , S1_q_a[20]_clock_0, S1_q_a[20]_clock_1, , , , );
S1_q_a[20]_PORT_A_data_out_reg = DFFE(S1_q_a[20]_PORT_A_data_out, S1_q_a[20]_clock_0, , , );
S1_q_a[20] = S1_q_a[20]_PORT_A_data_out_reg[0];

--S1_q_b[20] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[20]
S1_q_b[20]_PORT_A_data_in = X1_request_6;
S1_q_b[20]_PORT_A_data_in_reg = DFFE(S1_q_b[20]_PORT_A_data_in, S1_q_b[20]_clock_0, , , );
S1_q_b[20]_PORT_B_data_in = ~GND;
S1_q_b[20]_PORT_B_data_in_reg = DFFE(S1_q_b[20]_PORT_B_data_in, S1_q_b[20]_clock_1, , , );
S1_q_b[20]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[20]_PORT_A_address_reg = DFFE(S1_q_b[20]_PORT_A_address, S1_q_b[20]_clock_0, , , );
S1_q_b[20]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[20]_PORT_B_address_reg = DFFE(S1_q_b[20]_PORT_B_address, S1_q_b[20]_clock_1, , , );
S1_q_b[20]_PORT_A_write_enable = J1_wren_io;
S1_q_b[20]_PORT_A_write_enable_reg = DFFE(S1_q_b[20]_PORT_A_write_enable, S1_q_b[20]_clock_0, , , );
S1_q_b[20]_PORT_B_write_enable = GND;
S1_q_b[20]_PORT_B_write_enable_reg = DFFE(S1_q_b[20]_PORT_B_write_enable, S1_q_b[20]_clock_1, , , );
S1_q_b[20]_clock_0 = U1__clk1;
S1_q_b[20]_clock_1 = U1__clk0;
S1_q_b[20]_PORT_B_data_out = MEMORY(S1_q_b[20]_PORT_A_data_in_reg, S1_q_b[20]_PORT_B_data_in_reg, S1_q_b[20]_PORT_A_address_reg, S1_q_b[20]_PORT_B_address_reg, S1_q_b[20]_PORT_A_write_enable_reg, S1_q_b[20]_PORT_B_write_enable_reg, , , S1_q_b[20]_clock_0, S1_q_b[20]_clock_1, , , , );
S1_q_b[20] = S1_q_b[20]_PORT_B_data_out[0];


--S1_q_a[19] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[19]
S1_q_a[19]_PORT_A_data_in = X1_request_7;
S1_q_a[19]_PORT_A_data_in_reg = DFFE(S1_q_a[19]_PORT_A_data_in, S1_q_a[19]_clock_0, , , );
S1_q_a[19]_PORT_B_data_in = ~GND;
S1_q_a[19]_PORT_B_data_in_reg = DFFE(S1_q_a[19]_PORT_B_data_in, S1_q_a[19]_clock_1, , , );
S1_q_a[19]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[19]_PORT_A_address_reg = DFFE(S1_q_a[19]_PORT_A_address, S1_q_a[19]_clock_0, , , );
S1_q_a[19]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[19]_PORT_B_address_reg = DFFE(S1_q_a[19]_PORT_B_address, S1_q_a[19]_clock_1, , , );
S1_q_a[19]_PORT_A_write_enable = J1_wren_io;
S1_q_a[19]_PORT_A_write_enable_reg = DFFE(S1_q_a[19]_PORT_A_write_enable, S1_q_a[19]_clock_0, , , );
S1_q_a[19]_PORT_B_write_enable = GND;
S1_q_a[19]_PORT_B_write_enable_reg = DFFE(S1_q_a[19]_PORT_B_write_enable, S1_q_a[19]_clock_1, , , );
S1_q_a[19]_clock_0 = U1__clk1;
S1_q_a[19]_clock_1 = U1__clk0;
S1_q_a[19]_PORT_A_data_out = MEMORY(S1_q_a[19]_PORT_A_data_in_reg, S1_q_a[19]_PORT_B_data_in_reg, S1_q_a[19]_PORT_A_address_reg, S1_q_a[19]_PORT_B_address_reg, S1_q_a[19]_PORT_A_write_enable_reg, S1_q_a[19]_PORT_B_write_enable_reg, , , S1_q_a[19]_clock_0, S1_q_a[19]_clock_1, , , , );
S1_q_a[19]_PORT_A_data_out_reg = DFFE(S1_q_a[19]_PORT_A_data_out, S1_q_a[19]_clock_0, , , );
S1_q_a[19] = S1_q_a[19]_PORT_A_data_out_reg[0];

--S1_q_b[19] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[19]
S1_q_b[19]_PORT_A_data_in = X1_request_7;
S1_q_b[19]_PORT_A_data_in_reg = DFFE(S1_q_b[19]_PORT_A_data_in, S1_q_b[19]_clock_0, , , );
S1_q_b[19]_PORT_B_data_in = ~GND;
S1_q_b[19]_PORT_B_data_in_reg = DFFE(S1_q_b[19]_PORT_B_data_in, S1_q_b[19]_clock_1, , , );
S1_q_b[19]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[19]_PORT_A_address_reg = DFFE(S1_q_b[19]_PORT_A_address, S1_q_b[19]_clock_0, , , );
S1_q_b[19]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[19]_PORT_B_address_reg = DFFE(S1_q_b[19]_PORT_B_address, S1_q_b[19]_clock_1, , , );
S1_q_b[19]_PORT_A_write_enable = J1_wren_io;
S1_q_b[19]_PORT_A_write_enable_reg = DFFE(S1_q_b[19]_PORT_A_write_enable, S1_q_b[19]_clock_0, , , );
S1_q_b[19]_PORT_B_write_enable = GND;
S1_q_b[19]_PORT_B_write_enable_reg = DFFE(S1_q_b[19]_PORT_B_write_enable, S1_q_b[19]_clock_1, , , );
S1_q_b[19]_clock_0 = U1__clk1;
S1_q_b[19]_clock_1 = U1__clk0;
S1_q_b[19]_PORT_B_data_out = MEMORY(S1_q_b[19]_PORT_A_data_in_reg, S1_q_b[19]_PORT_B_data_in_reg, S1_q_b[19]_PORT_A_address_reg, S1_q_b[19]_PORT_B_address_reg, S1_q_b[19]_PORT_A_write_enable_reg, S1_q_b[19]_PORT_B_write_enable_reg, , , S1_q_b[19]_clock_0, S1_q_b[19]_clock_1, , , , );
S1_q_b[19] = S1_q_b[19]_PORT_B_data_out[0];


--S1_q_a[23] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[23]
S1_q_a[23]_PORT_A_data_in = X1_request_3;
S1_q_a[23]_PORT_A_data_in_reg = DFFE(S1_q_a[23]_PORT_A_data_in, S1_q_a[23]_clock_0, , , );
S1_q_a[23]_PORT_B_data_in = ~GND;
S1_q_a[23]_PORT_B_data_in_reg = DFFE(S1_q_a[23]_PORT_B_data_in, S1_q_a[23]_clock_1, , , );
S1_q_a[23]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[23]_PORT_A_address_reg = DFFE(S1_q_a[23]_PORT_A_address, S1_q_a[23]_clock_0, , , );
S1_q_a[23]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[23]_PORT_B_address_reg = DFFE(S1_q_a[23]_PORT_B_address, S1_q_a[23]_clock_1, , , );
S1_q_a[23]_PORT_A_write_enable = J1_wren_io;
S1_q_a[23]_PORT_A_write_enable_reg = DFFE(S1_q_a[23]_PORT_A_write_enable, S1_q_a[23]_clock_0, , , );
S1_q_a[23]_PORT_B_write_enable = GND;
S1_q_a[23]_PORT_B_write_enable_reg = DFFE(S1_q_a[23]_PORT_B_write_enable, S1_q_a[23]_clock_1, , , );
S1_q_a[23]_clock_0 = U1__clk1;
S1_q_a[23]_clock_1 = U1__clk0;
S1_q_a[23]_PORT_A_data_out = MEMORY(S1_q_a[23]_PORT_A_data_in_reg, S1_q_a[23]_PORT_B_data_in_reg, S1_q_a[23]_PORT_A_address_reg, S1_q_a[23]_PORT_B_address_reg, S1_q_a[23]_PORT_A_write_enable_reg, S1_q_a[23]_PORT_B_write_enable_reg, , , S1_q_a[23]_clock_0, S1_q_a[23]_clock_1, , , , );
S1_q_a[23]_PORT_A_data_out_reg = DFFE(S1_q_a[23]_PORT_A_data_out, S1_q_a[23]_clock_0, , , );
S1_q_a[23] = S1_q_a[23]_PORT_A_data_out_reg[0];

--S1_q_b[23] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[23]
S1_q_b[23]_PORT_A_data_in = X1_request_3;
S1_q_b[23]_PORT_A_data_in_reg = DFFE(S1_q_b[23]_PORT_A_data_in, S1_q_b[23]_clock_0, , , );
S1_q_b[23]_PORT_B_data_in = ~GND;
S1_q_b[23]_PORT_B_data_in_reg = DFFE(S1_q_b[23]_PORT_B_data_in, S1_q_b[23]_clock_1, , , );
S1_q_b[23]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[23]_PORT_A_address_reg = DFFE(S1_q_b[23]_PORT_A_address, S1_q_b[23]_clock_0, , , );
S1_q_b[23]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[23]_PORT_B_address_reg = DFFE(S1_q_b[23]_PORT_B_address, S1_q_b[23]_clock_1, , , );
S1_q_b[23]_PORT_A_write_enable = J1_wren_io;
S1_q_b[23]_PORT_A_write_enable_reg = DFFE(S1_q_b[23]_PORT_A_write_enable, S1_q_b[23]_clock_0, , , );
S1_q_b[23]_PORT_B_write_enable = GND;
S1_q_b[23]_PORT_B_write_enable_reg = DFFE(S1_q_b[23]_PORT_B_write_enable, S1_q_b[23]_clock_1, , , );
S1_q_b[23]_clock_0 = U1__clk1;
S1_q_b[23]_clock_1 = U1__clk0;
S1_q_b[23]_PORT_B_data_out = MEMORY(S1_q_b[23]_PORT_A_data_in_reg, S1_q_b[23]_PORT_B_data_in_reg, S1_q_b[23]_PORT_A_address_reg, S1_q_b[23]_PORT_B_address_reg, S1_q_b[23]_PORT_A_write_enable_reg, S1_q_b[23]_PORT_B_write_enable_reg, , , S1_q_b[23]_clock_0, S1_q_b[23]_clock_1, , , , );
S1_q_b[23] = S1_q_b[23]_PORT_B_data_out[0];


--S1_q_a[17] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[17]
S1_q_a[17]_PORT_A_data_in = X1_request_9;
S1_q_a[17]_PORT_A_data_in_reg = DFFE(S1_q_a[17]_PORT_A_data_in, S1_q_a[17]_clock_0, , , );
S1_q_a[17]_PORT_B_data_in = ~GND;
S1_q_a[17]_PORT_B_data_in_reg = DFFE(S1_q_a[17]_PORT_B_data_in, S1_q_a[17]_clock_1, , , );
S1_q_a[17]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[17]_PORT_A_address_reg = DFFE(S1_q_a[17]_PORT_A_address, S1_q_a[17]_clock_0, , , );
S1_q_a[17]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[17]_PORT_B_address_reg = DFFE(S1_q_a[17]_PORT_B_address, S1_q_a[17]_clock_1, , , );
S1_q_a[17]_PORT_A_write_enable = J1_wren_io;
S1_q_a[17]_PORT_A_write_enable_reg = DFFE(S1_q_a[17]_PORT_A_write_enable, S1_q_a[17]_clock_0, , , );
S1_q_a[17]_PORT_B_write_enable = GND;
S1_q_a[17]_PORT_B_write_enable_reg = DFFE(S1_q_a[17]_PORT_B_write_enable, S1_q_a[17]_clock_1, , , );
S1_q_a[17]_clock_0 = U1__clk1;
S1_q_a[17]_clock_1 = U1__clk0;
S1_q_a[17]_PORT_A_data_out = MEMORY(S1_q_a[17]_PORT_A_data_in_reg, S1_q_a[17]_PORT_B_data_in_reg, S1_q_a[17]_PORT_A_address_reg, S1_q_a[17]_PORT_B_address_reg, S1_q_a[17]_PORT_A_write_enable_reg, S1_q_a[17]_PORT_B_write_enable_reg, , , S1_q_a[17]_clock_0, S1_q_a[17]_clock_1, , , , );
S1_q_a[17]_PORT_A_data_out_reg = DFFE(S1_q_a[17]_PORT_A_data_out, S1_q_a[17]_clock_0, , , );
S1_q_a[17] = S1_q_a[17]_PORT_A_data_out_reg[0];

--S1_q_b[17] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[17]
S1_q_b[17]_PORT_A_data_in = X1_request_9;
S1_q_b[17]_PORT_A_data_in_reg = DFFE(S1_q_b[17]_PORT_A_data_in, S1_q_b[17]_clock_0, , , );
S1_q_b[17]_PORT_B_data_in = ~GND;
S1_q_b[17]_PORT_B_data_in_reg = DFFE(S1_q_b[17]_PORT_B_data_in, S1_q_b[17]_clock_1, , , );
S1_q_b[17]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[17]_PORT_A_address_reg = DFFE(S1_q_b[17]_PORT_A_address, S1_q_b[17]_clock_0, , , );
S1_q_b[17]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[17]_PORT_B_address_reg = DFFE(S1_q_b[17]_PORT_B_address, S1_q_b[17]_clock_1, , , );
S1_q_b[17]_PORT_A_write_enable = J1_wren_io;
S1_q_b[17]_PORT_A_write_enable_reg = DFFE(S1_q_b[17]_PORT_A_write_enable, S1_q_b[17]_clock_0, , , );
S1_q_b[17]_PORT_B_write_enable = GND;
S1_q_b[17]_PORT_B_write_enable_reg = DFFE(S1_q_b[17]_PORT_B_write_enable, S1_q_b[17]_clock_1, , , );
S1_q_b[17]_clock_0 = U1__clk1;
S1_q_b[17]_clock_1 = U1__clk0;
S1_q_b[17]_PORT_B_data_out = MEMORY(S1_q_b[17]_PORT_A_data_in_reg, S1_q_b[17]_PORT_B_data_in_reg, S1_q_b[17]_PORT_A_address_reg, S1_q_b[17]_PORT_B_address_reg, S1_q_b[17]_PORT_A_write_enable_reg, S1_q_b[17]_PORT_B_write_enable_reg, , , S1_q_b[17]_clock_0, S1_q_b[17]_clock_1, , , , );
S1_q_b[17] = S1_q_b[17]_PORT_B_data_out[0];


--S1_q_a[16] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_a[16]
S1_q_a[16]_PORT_A_data_in = X1_request_10;
S1_q_a[16]_PORT_A_data_in_reg = DFFE(S1_q_a[16]_PORT_A_data_in, S1_q_a[16]_clock_0, , , );
S1_q_a[16]_PORT_B_data_in = ~GND;
S1_q_a[16]_PORT_B_data_in_reg = DFFE(S1_q_a[16]_PORT_B_data_in, S1_q_a[16]_clock_1, , , );
S1_q_a[16]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_a[16]_PORT_A_address_reg = DFFE(S1_q_a[16]_PORT_A_address, S1_q_a[16]_clock_0, , , );
S1_q_a[16]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_a[16]_PORT_B_address_reg = DFFE(S1_q_a[16]_PORT_B_address, S1_q_a[16]_clock_1, , , );
S1_q_a[16]_PORT_A_write_enable = J1_wren_io;
S1_q_a[16]_PORT_A_write_enable_reg = DFFE(S1_q_a[16]_PORT_A_write_enable, S1_q_a[16]_clock_0, , , );
S1_q_a[16]_PORT_B_write_enable = GND;
S1_q_a[16]_PORT_B_write_enable_reg = DFFE(S1_q_a[16]_PORT_B_write_enable, S1_q_a[16]_clock_1, , , );
S1_q_a[16]_clock_0 = U1__clk1;
S1_q_a[16]_clock_1 = U1__clk0;
S1_q_a[16]_PORT_A_data_out = MEMORY(S1_q_a[16]_PORT_A_data_in_reg, S1_q_a[16]_PORT_B_data_in_reg, S1_q_a[16]_PORT_A_address_reg, S1_q_a[16]_PORT_B_address_reg, S1_q_a[16]_PORT_A_write_enable_reg, S1_q_a[16]_PORT_B_write_enable_reg, , , S1_q_a[16]_clock_0, S1_q_a[16]_clock_1, , , , );
S1_q_a[16]_PORT_A_data_out_reg = DFFE(S1_q_a[16]_PORT_A_data_out, S1_q_a[16]_clock_0, , , );
S1_q_a[16] = S1_q_a[16]_PORT_A_data_out_reg[0];

--S1_q_b[16] is ADC_DAC_0:adcdac|pasadac:pdac|pasadac_ram:dacram|altsyncram:altsyncram_component|altsyncram_hpj1:auto_generated|q_b[16]
S1_q_b[16]_PORT_A_data_in = X1_request_10;
S1_q_b[16]_PORT_A_data_in_reg = DFFE(S1_q_b[16]_PORT_A_data_in, S1_q_b[16]_clock_0, , , );
S1_q_b[16]_PORT_B_data_in = ~GND;
S1_q_b[16]_PORT_B_data_in_reg = DFFE(S1_q_b[16]_PORT_B_data_in, S1_q_b[16]_clock_1, , , );
S1_q_b[16]_PORT_A_address = BUS(X1_request_48, X1_request_47, X1_request_46, X1_request_45, X1_request_44);
S1_q_b[16]_PORT_A_address_reg = DFFE(S1_q_b[16]_PORT_A_address, S1_q_b[16]_clock_0, , , );
S1_q_b[16]_PORT_B_address = BUS(J1_addr_sm_0, J1_addr_sm_1, J1_addr_sm_2, J1_addr_sm_3, J1_addr_sm_4);
S1_q_b[16]_PORT_B_address_reg = DFFE(S1_q_b[16]_PORT_B_address, S1_q_b[16]_clock_1, , , );
S1_q_b[16]_PORT_A_write_enable = J1_wren_io;
S1_q_b[16]_PORT_A_write_enable_reg = DFFE(S1_q_b[16]_PORT_A_write_enable, S1_q_b[16]_clock_0, , , );
S1_q_b[16]_PORT_B_write_enable = GND;
S1_q_b[16]_PORT_B_write_enable_reg = DFFE(S1_q_b[16]_PORT_B_write_enable, S1_q_b[16]_clock_1, , , );
S1_q_b[16]_clock_0 = U1__clk1;
S1_q_b[16]_clock_1 = U1__clk0;
S1_q_b[16]_PORT_B_data_out = MEMORY(S1_q_b[16]_PORT_A_data_in_reg, S1_q_b[16]_PORT_B_data_in_reg, S1_q_b[16]_PORT_A_address_reg, S1_q_b[16]_PORT_B_address_reg, S1_q_b[16]_PORT_A_write_enable_reg, S1_q_b[16]_PORT_B_write_enable_reg, , , S1_q_b[16]_clock_0, S1_q_b[16]_clock_1, , , , );
S1_q_b[16] = S1_q_b[16]_PORT_B_data_out[0];


--~GND is ~GND
--operation mode is normal

~GND = GND;


--MSply_ADC_INTn is MSply_ADC_INTn
--operation mode is input

MSply_ADC_INTn = INPUT();


--SC_ADC_INTn is SC_ADC_INTn
--operation mode is input

SC_ADC_INTn = INPUT();


--WT_P4D[0] is WT_P4D[0]
--operation mode is input

WT_P4D[0] = INPUT();


--WT_P4D[1] is WT_P4D[1]
--operation mode is input

WT_P4D[1] = INPUT();


--WT_P4D[2] is WT_P4D[2]
--operation mode is input

WT_P4D[2] = INPUT();


--WT_P4D[3] is WT_P4D[3]
--operation mode is input

WT_P4D[3] = INPUT();


--WT_P4D[4] is WT_P4D[4]
--operation mode is input

WT_P4D[4] = INPUT();


--WT_P4D[5] is WT_P4D[5]
--operation mode is input

WT_P4D[5] = INPUT();


--WT_P4D[6] is WT_P4D[6]
--operation mode is input

WT_P4D[6] = INPUT();


--WT_P4D[7] is WT_P4D[7]
--operation mode is input

WT_P4D[7] = INPUT();


--WT_P4D[8] is WT_P4D[8]
--operation mode is input

WT_P4D[8] = INPUT();


--WT_P4D[9] is WT_P4D[9]
--operation mode is input

WT_P4D[9] = INPUT();


--WT_STR is WT_STR
--operation mode is input

WT_STR = INPUT();


--AD_SYNC_IN[0] is AD_SYNC_IN[0]
--operation mode is input

AD_SYNC_IN[0] = INPUT();


--AD_SYNC_IN[1] is AD_SYNC_IN[1]
--operation mode is input

AD_SYNC_IN[1] = INPUT();


--CLK_gen is CLK_gen
--operation mode is input

CLK_gen = INPUT();


--SER0_IN is SER0_IN
--operation mode is input

SER0_IN = INPUT();


--SER1_IN is SER1_IN
--operation mode is input

SER1_IN = INPUT();


--PAADC_D[0] is PAADC_D[0]
--operation mode is input

PAADC_D[0] = INPUT();


--DDS_SDO is DDS_SDO
--operation mode is input

DDS_SDO = INPUT();


--SC_ADC_SDO is SC_ADC_SDO
--operation mode is input

SC_ADC_SDO = INPUT();


--MSply_ADC_SDO is MSply_ADC_SDO
--operation mode is input

MSply_ADC_SDO = INPUT();


--PAADC_D[1] is PAADC_D[1]
--operation mode is input

PAADC_D[1] = INPUT();


--PAADC_D[2] is PAADC_D[2]
--operation mode is input

PAADC_D[2] = INPUT();


--PAADC_D[3] is PAADC_D[3]
--operation mode is input

PAADC_D[3] = INPUT();


--PAADC_D[4] is PAADC_D[4]
--operation mode is input

PAADC_D[4] = INPUT();


--PAADC_D[5] is PAADC_D[5]
--operation mode is input

PAADC_D[5] = INPUT();


--PAADC_D[6] is PAADC_D[6]
--operation mode is input

PAADC_D[6] = INPUT();


--PAADC_D[7] is PAADC_D[7]
--operation mode is input

PAADC_D[7] = INPUT();


--PAADC_D[8] is PAADC_D[8]
--operation mode is input

PAADC_D[8] = INPUT();


--PAADC_D[9] is PAADC_D[9]
--operation mode is input

PAADC_D[9] = INPUT();


--PAADC_D[10] is PAADC_D[10]
--operation mode is input

PAADC_D[10] = INPUT();


--PAADC_D[11] is PAADC_D[11]
--operation mode is input

PAADC_D[11] = INPUT();


--PAADC_OVR is PAADC_OVR
--operation mode is input

PAADC_OVR = INPUT();


--AD_SYNC_OUT[0] is AD_SYNC_OUT[0]
--operation mode is output

AD_SYNC_OUT[0] = OUTPUT(B1_AD_SYNC_OUT_0);


--AD_SYNC_OUT[1] is AD_SYNC_OUT[1]
--operation mode is output

AD_SYNC_OUT[1] = OUTPUT(B1_AD_SYNC_OUT_1);


--DDS_CSn is DDS_CSn
--operation mode is output

DDS_CSn = OUTPUT(!E1_NOT_DDS_CSn);


--DDS_FSK is DDS_FSK
--operation mode is output

DDS_FSK = OUTPUT(E1_DDS_FSK);


--DDS_IORST is DDS_IORST
--operation mode is output

DDS_IORST = OUTPUT(!E1_NOT_DDS_IORST);


--DDS_MCLK is DDS_MCLK
--operation mode is output

DDS_MCLK = OUTPUT(E1_DDS_MCLK);


--DDS_MRST is DDS_MRST
--operation mode is output

DDS_MRST = OUTPUT(E1_DDS_MRST);


--DDS_SCLK is DDS_SCLK
--operation mode is output

DDS_SCLK = OUTPUT(E1_DDS_SCLK);


--DDS_SDI is DDS_SDI
--operation mode is output

DDS_SDI = OUTPUT(E1_DDS_SDI);


--DDS_ShKey is DDS_ShKey
--operation mode is output

DDS_ShKey = OUTPUT(E1_DDS_ShKey);


--DDS_UDCLK is DDS_UDCLK
--operation mode is output

DDS_UDCLK = OUTPUT(E1_DDS_UDCLK);


--MSply_ADC_nCS is MSply_ADC_nCS
--operation mode is output

MSply_ADC_nCS = OUTPUT(T1_RDY);


--MSply_ADC_nCSStrt is MSply_ADC_nCSStrt
--operation mode is output

MSply_ADC_nCSStrt = OUTPUT(!K1_NOT_ADC_nCSStrt);


--MSply_ADC_SCLK is MSply_ADC_SCLK
--operation mode is output

MSply_ADC_SCLK = OUTPUT(T1_ADC_SCLK);


--MSply_ADC_SDI is MSply_ADC_SDI
--operation mode is output

MSply_ADC_SDI = OUTPUT(T1_ADC_SDI);


--PAADC_CLK is PAADC_CLK
--operation mode is output

PAADC_CLK = OUTPUT(H1_PAADC_CLK);


--PAADC_Msel is PAADC_Msel
--operation mode is output

PAADC_Msel = OUTPUT(H1_PAADC_Msel);


--PAADC_MuxA[0] is PAADC_MuxA[0]
--operation mode is output

PAADC_MuxA[0] = OUTPUT(H1_PAADC_MuxA_0);


--PAADC_MuxA[1] is PAADC_MuxA[1]
--operation mode is output

PAADC_MuxA[1] = OUTPUT(H1_PAADC_MuxA_1);


--PAADC_MuxnRS is PAADC_MuxnRS
--operation mode is output

PAADC_MuxnRS = OUTPUT(H1_PAADC_MuxnRS);


--PAADC_STDP is PAADC_STDP
--operation mode is output

PAADC_STDP = OUTPUT(H1_PAADC_STDP);


--PasaDAC1_CLK is PasaDAC1_CLK
--operation mode is output

PasaDAC1_CLK = OUTPUT(J1_PasaDAC1_CLK);


--PasaDAC2_CLK is PasaDAC2_CLK
--operation mode is output

PasaDAC2_CLK = OUTPUT(J1_PasaDAC2_CLK);


--PasaDAC_D[0] is PasaDAC_D[0]
--operation mode is output

PasaDAC_D[0] = OUTPUT(J1_PasaDAC_D_0);


--PasaDAC_D[1] is PasaDAC_D[1]
--operation mode is output

PasaDAC_D[1] = OUTPUT(J1_PasaDAC_D_1);


--PasaDAC_D[2] is PasaDAC_D[2]
--operation mode is output

PasaDAC_D[2] = OUTPUT(J1_PasaDAC_D_2);


--PasaDAC_D[3] is PasaDAC_D[3]
--operation mode is output

PasaDAC_D[3] = OUTPUT(J1_PasaDAC_D_3);


--PasaDAC_D[4] is PasaDAC_D[4]
--operation mode is output

PasaDAC_D[4] = OUTPUT(J1_PasaDAC_D_4);


--PasaDAC_D[5] is PasaDAC_D[5]
--operation mode is output

PasaDAC_D[5] = OUTPUT(J1_PasaDAC_D_5);


--PasaDAC_D[6] is PasaDAC_D[6]
--operation mode is output

PasaDAC_D[6] = OUTPUT(J1_PasaDAC_D_6);


--PasaDAC_D[7] is PasaDAC_D[7]
--operation mode is output

PasaDAC_D[7] = OUTPUT(J1_PasaDAC_D_7);


--PasaDAC_D[8] is PasaDAC_D[8]
--operation mode is output

PasaDAC_D[8] = OUTPUT(J1_PasaDAC_D_8);


--PasaDAC_D[9] is PasaDAC_D[9]
--operation mode is output

PasaDAC_D[9] = OUTPUT(J1_PasaDAC_D_9);


--PasaDAC_D[10] is PasaDAC_D[10]
--operation mode is output

PasaDAC_D[10] = OUTPUT(J1_PasaDAC_D_10);


--PasaDAC_D[11] is PasaDAC_D[11]
--operation mode is output

PasaDAC_D[11] = OUTPUT(J1_PasaDAC_D_11);


--PasaDAC_D[12] is PasaDAC_D[12]
--operation mode is output

PasaDAC_D[12] = OUTPUT(J1_PasaDAC_D_12);


--PasaDAC_D[13] is PasaDAC_D[13]
--operation mode is output

PasaDAC_D[13] = OUTPUT(J1_PasaDAC_D_13);


--PasaDAC_Sleep is PasaDAC_Sleep
--operation mode is output

PasaDAC_Sleep = OUTPUT(J1_PasaDAC_Sleep);


--PW_CSn[0] is PW_CSn[0]
--operation mode is output

PW_CSn[0] = OUTPUT(!F1_NOT_CSn);


--PW_CSn[1] is PW_CSn[1]
--operation mode is output

PW_CSn[1] = OUTPUT(!F2_NOT_CSn);


--PW_CSn[2] is PW_CSn[2]
--operation mode is output

PW_CSn[2] = OUTPUT(!F3_NOT_CSn);


--PW_CSn[3] is PW_CSn[3]
--operation mode is output

PW_CSn[3] = OUTPUT(!F4_NOT_CSn);


--PW_INCn[0] is PW_INCn[0]
--operation mode is output

PW_INCn[0] = OUTPUT(!F1_NOT_INCn);


--PW_INCn[1] is PW_INCn[1]
--operation mode is output

PW_INCn[1] = OUTPUT(!F2_NOT_INCn);


--PW_INCn[2] is PW_INCn[2]
--operation mode is output

PW_INCn[2] = OUTPUT(!F3_NOT_INCn);


--PW_INCn[3] is PW_INCn[3]
--operation mode is output

PW_INCn[3] = OUTPUT(!F4_NOT_INCn);


--PW_UDn[0] is PW_UDn[0]
--operation mode is output

PW_UDn[0] = OUTPUT(!F1_NOT_UDn);


--PW_UDn[1] is PW_UDn[1]
--operation mode is output

PW_UDn[1] = OUTPUT(!F2_NOT_UDn);


--PW_UDn[2] is PW_UDn[2]
--operation mode is output

PW_UDn[2] = OUTPUT(!F3_NOT_UDn);


--PW_UDn[3] is PW_UDn[3]
--operation mode is output

PW_UDn[3] = OUTPUT(!F4_NOT_UDn);


--SC_ADC_nCS is SC_ADC_nCS
--operation mode is output

SC_ADC_nCS = OUTPUT(T2_RDY);


--SC_ADC_nCSStrt is SC_ADC_nCSStrt
--operation mode is output

SC_ADC_nCSStrt = OUTPUT(!L1_NOT_ADC_nCSStrt);


--SC_ADC_SCLK is SC_ADC_SCLK
--operation mode is output

SC_ADC_SCLK = OUTPUT(T2_ADC_SCLK);


--SC_ADC_SDI is SC_ADC_SDI
--operation mode is output

SC_ADC_SDI = OUTPUT(T2_ADC_SDI);


--SER0_OUT is SER0_OUT
--operation mode is output

SER0_OUT = OUTPUT(W1_d0_to_pl);


--SER1_OUT is SER1_OUT
--operation mode is output

SER1_OUT = OUTPUT(W1_d1_to_pl);


--SlowDAC1_FS is SlowDAC1_FS
--operation mode is output

SlowDAC1_FS = OUTPUT(M1_SSTR);


--SlowDAC1_LDACn is SlowDAC1_LDACn
--operation mode is output

SlowDAC1_LDACn = OUTPUT(!M1_NOT_LDACn);


--SlowDAC1_SCLK is SlowDAC1_SCLK
--operation mode is output

SlowDAC1_SCLK = OUTPUT(M1_SCLK);


--SlowDAC2_FS is SlowDAC2_FS
--operation mode is output

SlowDAC2_FS = OUTPUT(M2_SSTR);


--SlowDAC2_LDACn is SlowDAC2_LDACn
--operation mode is output

SlowDAC2_LDACn = OUTPUT(!M2_NOT_LDACn);


--SlowDAC2_SCLK is SlowDAC2_SCLK
--operation mode is output

SlowDAC2_SCLK = OUTPUT(M2_SCLK);


--SlowDAC_Din is SlowDAC_Din
--operation mode is output

SlowDAC_Din = OUTPUT(B1_SlowDAC_Din);


--VMCM_Shdwn_a is VMCM_Shdwn_a
--operation mode is output

VMCM_Shdwn_a = OUTPUT(OPNDRN(B1_VMCM_Shdwn_a));


--VMCM_Shdwn_d is VMCM_Shdwn_d
--operation mode is output

VMCM_Shdwn_d = OUTPUT(OPNDRN(B1_VMCM_Shdwn_d));


--WT_CTR is WT_CTR
--operation mode is output

WT_CTR = OUTPUT(GND);


--X1L321 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_10~0
--operation mode is normal

X1L321 = !X1_request_10;


--X1L521 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_11~0
--operation mode is normal

X1L521 = !X1_request_11;


--X1L721 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_12~0
--operation mode is normal

X1L721 = !X1_request_12;


--X1L921 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_13~0
--operation mode is normal

X1L921 = !X1_request_13;


--X1L131 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_14~0
--operation mode is normal

X1L131 = !X1_request_14;


--X1L331 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_15~0
--operation mode is normal

X1L331 = !X1_request_15;


--X1L531 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_16~0
--operation mode is normal

X1L531 = !X1_request_16;


--X1L731 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_17~0
--operation mode is normal

X1L731 = !X1_request_17;


--X1L931 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_18~0
--operation mode is normal

X1L931 = !X1_request_18;


--X1L911 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_8~0
--operation mode is normal

X1L911 = !X1_request_8;


--X1L121 is mcm_network_interface:scsn_slave|mcm_nw_nwl:nw_nwl|request_9~0
--operation mode is normal

X1L121 = !X1_request_9;