The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design pasadac_ram.vhd . For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( ..FFF0, ..FFF1, ..FFF2, ..FFF3, ..FFF4, ...). The design pasadac_ram.vhd has two read/write ports. Read/write port A has 32 words of 24 bits each and Read/write port B has 32 words of 24 bits each. The ram block type of the design is AUTO . The output of the read/write port A is registered by clock_a. The output of the read/write port B is unregistered.
The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock.
The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. During a write cycle on a port (A or B), the new data flows through to the output of the same port. Actual write into the RAM happens at the rising edge or falling edge of the write clock, depending on whether the RAM blocks are assigned to M-RAM or not. In the sample waveforms, they are shown to be on the falling edge of the write clock.