-- last modified: 15:04 / 24-May-2005 / V.Angelov Overview: FPGA 1 (ADC + DAC) Address range simulated used in: sdac 1 0x5000 0x503F Y not used V dut_trap enable 0x5080 0x50FF Y mcm+wafer digital poti 0x50C0 0x50FF Y mcm+wafer(w/o 3.3V pasa) sdac 2 0x5100 0x51FF Y mcm+wafer(DDS common mode only) dds 0x5200 0x52FF Y mcm+wafer sc adc 0x5300 0x53FF Y mcm psply adc 0x5400 0x54FF Y mcm+wafer(w/o 3.3V pasa) pasa dac 0x5500 0x55FF Y mcm pasa adc 0x5800 0x5FFF Y mcm NI memory and configuration 0x6000 0x67FF N wafer FPGA 2 (NI_P4, clk, pre out) clock and pretrigger module 0x4000 0x40FF Y mcm jtag master ni up 0x4100 0x41FF Y mcm jtag master ni dn 0x4200 0x42FF Y mcm jtag master dut 0x4300 0x43FF Y mcm general config & status 0x4400 0x44FF Y mcm+wafer(SCSN switch select only) ni2io read only memory 0x4800 0x4FFF Y mcm ******************************************************* FPGA 1 (ADC + DAC) ------------------------------------------------------- sadc power supply 0x5400 0x54FF Offset 0 r ch1 & ch 0 24 bit readonly 1 r ch3 & ch 2 24 bit readonly 2 r ch5 & ch 4 24 bit readonly 3 r ch7 & ch 6 24 bit readonly 0..3 w writing here triggers the measurement cycle 4..5 rw CFR - writing sends the CFR(11:0) to the ADC bits 11. .0 - see TLV2548 datasheet bits 12 - 1/0 continuous/triggered 6 rw ch5 & ch 4 upper limits 12+12 bits 7 rw ch7 & ch 6 upper limits 12+12 bits Power supply ADC TLV2548 ADC channel Connected to 0 Voltage 1V8 digital 1 Voltage 1V8 analog 2 Voltage 3V3 digital IO 3 Voltage 3V3 PASA 4 Current 3V3 PASA 5 Current 3V3 digital IO 6 Current 1V8 analog 7 Current 1V8 digital core The last ADC data are compared with the programmable current limits. If the current limit for 3V3 PASA or 1V8 analog is reached, both voltages will be switched off. If the current limit for 3V3 digital or 1V8 digital is reached, ALL voltages will be switched off. The status (enable=1/disable=0) of the digital and analog supplies can be read as bits 31 and 30, regardless of the address. ------------------------------------------------------- sadc 0x5300 0x53FF Offset 0 r ch1 & ch 0 24 bit readonly 1 r ch3 & ch 2 24 bit readonly 2 r ch5 & ch 4 24 bit readonly 3 r ch7 & ch 6 24 bit readonly 0..3 w writing here triggers the measurement cycle 4..5 rw CFR - writing sends the CFR(11:0) to the ADC bits 11. .0 - see TLV2548 datasheet bits 12 - 1/0 continuous/triggered SC ADC TLV2548 ADC channel Connected to 0 VREF PASA 1 PASA Vcm 2 PASA REFp 3 PASA REFn 4 Vref TRAP ADC 5 unused 6 DC of muxed PASA output (-) 7 DC of muxed PASA output (+) ------------------------------------------------------- sdac power supply TLV5630 0x5000 0x503F write only! Bits 15..12 (Address) 0 DAC 0 1 DAC 1 2 DAC 2 3 DAC 3 4 DAC 4 5 DAC 5 6 DAC 6 7 DAC 7 8 CTRL 0 9 CTRL 1 10 preset 11 reserved 12 DAC 0 and not 1 13 DAC 2 and not 3 14 DAC 4 and not 5 15 DAC 6 and not 7 Bits 11..0 Data CTRL 0 Bit 4 Full device power down Bit 3 DOUT enable Bit 2 R1 0, 1 - external reference Bit 1 R0 2, 3 - internal 1V / 2V Bit 0 IM - input mode - 0 straight binary, 1 two's complement -- Here we need internal reference! CTRL 1 Bit 7 Power Down 6 and 7 Bit 6 Power Down 4 and 5 Bit 5 Power Down 2 and 3 Bit 4 Power Down 0 and 1 Bit 3 Speed 6 and 7 1-fast, 0-slow Bit 3 Speed 4 and 5 1-fast, 0-slow Bit 3 Speed 2 and 3 1-fast, 0-slow Bit 3 Speed 0 and 1 1-fast, 0-slow CTRL 1 - disable DAC 4,5,6,7 0011_0000 = 0x30 -- Here the reset value is OK (all 0). DAC TLV5630 DAC channel Connected to 0 1V8 TRAP digital old, now using digital poti 1 1V8 TRAP analog old, now using digital poti 2 3V3 TRAP IO old, now using digital poti 3 3V3 PASA old, now using digital poti 4 not used 5 not used 6 not used 7 not used ------------------------------------------------------- sdac 2 TLV5630 0x5100 0x51FF write only! DAC2 channel Connected to 0 DDS VCM (TRAP ADC) 1 PASA Vcm 2 PASA Vref p 3 PASA Vref n 4 ADC aux p 5 ADC aux n 6 Vref PASA 7 Vref TRAP CTRL 0 - set the proper external reference! Note: May be it will be possible to write to internal address 14 for setting simultaneously ADC aux p/n! ------------------------------------------------------- Enable all DUT voltages 0x5080 0x50BF write only! Bit 0 analog Bit 1 digital Writing 1 enables the 2 programmable power supply voltages of the DUT. Writing 0 disables the 2 programmable power supply voltages of the DUT. This is a faster way to switch all off instead of programming the DACs. Note: the two enables can be turned off if the current limit is reached. The status can be read in sadc power... digital poti 0x50C0 0x50FF write only! Bits 7.. 0 3.3V analog (PASA) 15.. 8 1.8V analog (ADC) 23..16 3.3V digital (TRAP IO) 31..24 1.8V digital (TRAP core) For each byte: writing with D(7)=0 will program D(6..0) in the dig poti. (if the new value is >99 it will be clipped to 99). writing with D(7)=1 will deselect the poti and program the last value in NV memory (in this case D(6..0) are don't care). The programming needs max 1 ms and runs in parallel for all 4. ------------------------------------------------------- NOTE! This part doesn't exist in the wafer tester version! PASA DACs 0x5500 0x55FF Offset 32..63 w/r time(28..20) & channel(16) & DAC(13..0) 00..31 w/r configuration reg Bit 3 write only, when 1 start Bit 2 enable the pretrigger start (after reset is 1) Bit 1 sleep mode for DAC in idle Bit 0 when 1 run cont The time is measured using the TRAP fast clock / 2 In idle state the DACs are in low power mode. After start the DACs are in full power mode and the timer runs. The state machine waits until the time matches the first programmed time (at address 0). Then it fires the corresponding DAC clock output. Then the state machine reads the next time and waits and so on. If the programmed time is 0 or the address wraps to 0 the state machine stops (if not in cont mode) or starts again. DAC channel 0 is for the odd PASA channels (1,3,...17) DAC channel 1 is for the even PASA channels (2,4,...18) On the MCM PASA channel 1 is connected to ADC channel 2 PASA channel 2 is connected to ADC channel 3 ... PASA channel 18 is connected to ADC channel 19 ------------------------------------------------------- NOTE! This part exists ONLY in wafer tester version! NI memory and configuration 0x6000 - 0x67FF Offset 0x00 rw sel_p(7..4) & sel_s(3..0) 0x02 r the number of 16-bit words, pos_edge_strobe(23..12)/neg_edge_strobe(11..0) add 1 and divide by 2 to get the number of 32-bit words to read. pos_edge and neg_edge must be equal! 0x03 r the number of 16-bit words with wrong parity, pos_edge_strobe(23..12)/neg_edge_strobe(11..0) 0x02 w clear NI input port 0x03 w activate the reset output 0x400..0x7FF D(4*k+3) & D(4*k+2) & D(4*k+1) & D(4*k), k=0..4095 Stored data from the NI output port of the DUT. The next write address (for 16-bit data) for each strobe edge can be read at 0x6002 (see above) The last 16-bit word in trap-mode (not oase mode) can not be read correctly. ------------------------------------------------------- ------------------------------------------------------- PASA ADCs ADS5221 and mux 0x5800 0x5FFF Offset 0 ..511 r 32 bit '0' & ASEL & OVR & sample(2*i+1) & '0' & ASEL & OVR & sample(2*i) sample is 12 bit ASEL see below OVR is overrange 1024 w/r configuration reg Bit 1..0 - ASEL 3 PASA channel 1 1 PASA channel 17 2 PASA channel 18 0 DDS channel 1 Bit 2 - enable duty cycle adjust (see ADS5221 datasheet) Bit 3 - standard power down in idle mode of the state machine Bit 4 - when 0 disconnect the analog mux, useful to measure the offset Bit 5 - invert the clock output Bit 6 - enable pretrigger start (after reset is 1) w Bit 7 - when 1 - start ------------------------------------------------------- dds AD9854 0x5200 0x52FF Offset 0 rw Data to send (bits 31.. 0) 1 rw Data to send (bits 47..32) => 15.. 0 rw Instruction (8 bits) => 23..16 2 r Received data (bits 31.. 0) 3 r Received data (bits 47..32) => 15..0 4 rw Control register Bits 5 4 3 2 1 0 DDS_FSK DDS_ShKey auto udclk DDS_UDCLK DDS_MCLK DDS_MRST enable enable 5 r status register (not used) Note: May be some of the signals controlled by the control register must be faster => implemend in hardware directly. ******************************************************* FPGA 2 (NI_P4, clk, pre out) ------------------------------------------------------- clock and pretrigger module 0x4000 0x40FF jtag master ni up 0x4100 0x41FF jtag master ni dn 0x4200 0x42FF jtag master dut 0x4300 0x43FF general config & status 0x4400 0x44FF ni2io read only memory 0x4800 0x4FFF ------------------------------------------------------- clock and pretrigger module 0x4000 0x40FF Offset reading 0 Pretrigger counters 0 1 Pretrigger counters 1 2 Pretrigger counters 2 3 Pretrigger counters 3 Bits 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0 func7 func6 func5 func4 func3 func2 func1 unknown 4 4 clock counters x 8 bits. The internal timer (running with the internal clock) starts after reading, then resets and enables the 5 counters (with the strobe) for 200 internal clocks. Bits 31..24 23..16 15..8 7..0 counter 3 2 1 0 5 dut_pre(3..0) -> bits (7..4) direct read (useful for JTAG test) 5 dut_clk(3..0) -> bits (3..0) direct read (useful for JTAG test) 6 strobe counter with timer, like the 4 clock counters writing 0..3 reset all pretrigger counters 8..11 pretrigger encoder The pretrigger functions are 0 not used 1 pretrigger 2 clear 3 reserved 4 go to low power mode 5 go to acquisition mode 6 go to test mode 7 start test pulse in PASA 12 L0 time \ 13 L1 time - see the TRAP docu, a pretrigger will be activated 14 L2 time / 15 ni control time - the NI control signal to the DUT will be activated, it is normally > than L1time Note: all 4 times are in 120MHz clock! ------------------------------------------------------- NOTE!!! When reading through JTAG: 1) For inputs these are the input values at the chip pins 2) For outputs are the output values from chip core When writing through jtag: 1) For outputs these are the output values at the chip pins 2) For inputs are the input values to the chip core jtag masters Offset 0 rw JTAG group (see below) 0x20 rw identical to 0, for compatibility only 0x40 rw identical to 0, for compatibility only 0x60 rw identical to 0, for compatibility only 0x80 rw identical to 0, for compatibility only Bit 0xA0 r 0 status of the tms state machine, 0 ready, 1 busy 0xA0+i w 31..0 shifts i+1 bits of the write data (LSB first) to the TMS 0xC0 rw 1..0 speed of the TMS sender, 0 slowest, 3 fastest. rw 2 JTAG enable for chip 1, in addition enables the TCK, TMS and TDI outputsO rw 3 JTAG enable for chip 2 rw 4 JTAG enable for chip 3 rw 5 JTAG enable for chip 4 rw 6 JTAG mask, when 1 => TCK=1, TMS=TDI=0. To check the connectivity of JTAG just set bits 2 & 6, then clear bit 2 and read from offset 0xE0. TCK must be 0, TMS and TDI must be 1. 0xE0 r 4 TDO r 7..5 TCK & TMS & TDI, TCK has pull down, TMS and TDI have pull up in TRAP r 3..0 the expected state of the JTAG state machine in TRAP (see below) JTAG group (for one TRAP3 chip): For x = 0..3 the NI_Px_JTAG register has the following structure: 14 13 12 11 10 9..0 NI_Px_CTRL NI_Px_PREout NI_Px_CLKout - NI_Px_STRB NI_Px_D NI_P4_JTAG 14 13 12 11 10 9..0 NI_P4_CTRL PTRG_IN CLK_DIG_IN NI_P_CTRL NI_P4_STRB NI_P4_D Mapping to the IO: Offset Bits Name 0 14.. 0 NI_P0_JTAG 30..16 NI_P1_JTAG 1 14.. 0 NI_P2_JTAG 30..16 NI_P3_JTAG 2 14.. 0 NI_P4_JTAG 16 SER0_DIN 17 SER0_DOUT 3 1..0 JTAG instr register 4 31..0 identification register The states of the JTAG state machine: 0 0000 Test_Logic_Reset 1 0001 Run_Test_Idle 2 0010 Select_DR_Scan 3 0011 Capture_DR 4 0100 Shift_DR 5 0101 Exit1_DR 6 0110 Pause_DR 7 0111 Exit2_DR 8 1000 Update_DR 9 1001 Select_IR_Scan 10 1010 Capture_IR 11 1011 Shift_IR 12 1100 Exit1_IR 13 1101 Pause_IR 14 1110 Exit2_IR 15 1111 Update_IR --------------------------------------------------- jtag master ni up 0x4100 0x41FF controls chips U1201 connected to NI_0 of DUT (chip 1 in JTAG) and U1301 connected to NI_1 of DUT (chip 2 in JTAG) jtag master ni dn 0x4200 0x42FF controls chips U1401 connected to NI_2 of DUT (chip 1 in JTAG) and U1501 connected to NI_3 of DUT (chip 2 in JTAG) jtag master dut 0x4300 0x43FF controls chip U1001 (DUT) (chip 1 in JTAG) ------------------------------------------------------- general config & status 0x4400 0x44FF Offset 0 rw SCSN switch select(2..0) 0 only the local scsn slave 1 the local and the other fpga slave 2 the local, the other fpga slave and the 4 traps for ni test 3 the local and the DUT 4 the local, the DUT and the 4 traps for ni test 5 the local and the WT 6 the local and the 4 traps for ni test In cases without DUT in the chain, bit3 of the switch determines the static value to SCSN0 input of DUT (useful for JTAG tests) 0x10 rw ni_jtag_mode(10) & ni_ctrl_jtag(9) & oase_mode(8) & ni_sel_s(7..4) & ni_sel_p(3..0) for ni_sel_s and ni_sel_p see the TRAP3 documentation In jtag mode (bit10 set) the ctrl output is directly = bit9 0x20 w ni reset_n reset for the 4 TRAP chips for NI test 0x21 w ni irq_n IRQ for the 4 TRAP chips for NI test 0x30 w dut reset_n reset for the DUT chip 0x31 w dut irq_n IRQ for the DUT chip 0x30 r SE_CNT2(23..16) & SE_CNT1(15.. 8) & SE_CNT0( 7.. 0) logic low duration of SEBD_IN2..0 measured with 120MHz/16 For testing the reset output functionality. The normal value for one of the 10 bit counters is around 0x224. Bit31 is the reset_n to the TRAP, read back Bit30 is the irq_n to the TRAP, read back If SEBD_OE(7) bit is '0', one should read back '1' if the TRAP has proper contact and is powered. 0x40 r SEBD_IN(10..8) & SEBD_OE(7..4) & SEBD_OUT(2..0), bit31 set! 0x40 w SEBD_OE(7..4) & SEBD_OUT(2..0) SEBD_OE(7) is used to control the DUT reset_n and irq_n pins When '0', the two outputs are open drain, otherwise they can drive active high 0x80 r the number of 16-bit words, pos_edge_strobe(23..12)/neg_edge_strobe(11..0) add 1 (but not in oase mode) and divide by 2 to get the number of 32-bit words to read. pos_edge and neg_edge must be equal! 0x81 r the number of 16-bit words with wrong parity, pos_edge_strobe(23..12)/neg_edge_strobe(11..0) The last word can be read only in oase mode. 0x80 w clear NI input port 0x90 r four test pads on the MCM, if MCM present all must be 0. 0xA0 r ni direct read of port 4 of DUT (useful for JTAG tests) bits 16 15..12 11 10 9..0 SER0_DIN 0000 NI_P_CTRL NI_P4_STRB NI_P4_D ------------------------------------------------------- ni2io read only memory 0x4800 0x4FFF Offset 0..0x3FF D(4*k+3) & D(4*k+2) & D(4*k+1) & D(4*k), k=0..4095 Stored data from the NI output port of the DUT. The next write address (for 16-bit data) for each strobe edge can be read at 0x4480 (see above) The last 16-bit word in trap-mode (not oase mode) can not be read correctly. The first stored 16-bit word in trap-mode should be ignored. -------------------------------------------------------