-- TOP for the first FPGA on the MCM tester board. -- This FPGA is connected to the : -- 1) DUT TRAP3 -- SCSN 0,1 in/out -- NI output port; -- clock & pretrigger distribution outputs -- IRQ_n & RESET_n -- 3 x single ended bidirectional pins -- JTAG -- 2) 4 x NI TRAP3 -- SCSN 0,1 in/out -- clk and pretrigger in of one of them -- IRQ_n & RESET_n -- JTAG -- 3) second FPGA controlling ADCs and DACs -- SCSN 0,1 in/out -- 1 in, 1 out for synchronization -- 4) Uplink to PC using SCSN 0,1 -- IO space - no overlap with the TRAP3 chip! -- from to -- clock and pretrigger module 0x4000 0x40FF -- jtag master ni 0x4100 0x41FF -- general config & status 0x4200 0x42FF -- jtag master dut 0x4300 0x41FF -- ni2io read only memory 0x4800 0x4FFF LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; -- Design hierarchie -- top -- \ -- +------- -- | \ -- | mcm_network_interface (ready, trap3 version without hamming) -- | -- +------- -- | \ -- | scsn_switch (ready) -- | -- +------- -- | \ -- | clkpre_counter(ready) -- | +------ -- | | \ -- | | pre_counter (ready) -- | | +---- -- | | | \ -- | | | pre_counter (ready) -- | | +---- -- | | \ -- | | pre_dec (ready) -- | +------ -- | | \ -- | | clk_counter (ready) -- | | -- | +------ -- | | \ -- | | pre_enc (ready) -- | | -- | +------ -- | \ -- | pre_dir (ready) -- | -- +------- -- | \ -- | general_config (ready) -- | +------ -- | | \ -- | | irq_rst for DUT (ready) -- | +------ -- | \ -- | irq_rst for NI (ready) -- | -- +------- -- | \ -- | gio_devices (ready) -- | -- +------- -- | \ -- | pll120 (MegaWizard) -- | -- +------- -- | \ -- | ni2io (ready) -- | +------ -- | | \ -- | | ni_exclude_in (ready) -- | | +--- -- | | \ -- | | reg_clr (ready) -- | +------ -- | | \ -- | | ni2dpm (ready) -- | +------ -- | \ -- | ni_dpram (MegaWizard dual port RAM) -- | -- +------- -- | \ (to the 2 NI upper chips) -- | jtag_master (ready) -- | +------ -- | | \ -- | | 2x jtag_send (ready) -- | +------ -- | | \ -- | | 2x jtag_recv (ready) -- | +------ -- | | \ -- | | jtag_tms (ready) -- | +------ -- | \ -- | jtag_sm (ready) -- +------- -- | \ (to the 2 NI down chips) -- | jtag_master (ready) -- | +------ -- | | \ -- | | 2x jtag_send (ready) -- | +------ -- | | \ -- | | 2x jtag_recv (ready) -- | +------ -- | | \ -- | | jtag_tms (ready) -- | +------ -- | \ -- | jtag_sm (ready) -- +------- -- \ (to the DUT) -- jtag_master (ready) -- +------ -- | \ -- | jtag_send (ready) -- +------ -- | \ -- | jtag_recv (ready) -- +------ -- | \ -- | jtag_tms (ready) -- +------ -- \ -- jtag_sm (ready) entity top is generic( SERNR : Integer := 2; HDVER : Integer := 8); port ( clk_osc_in : in std_logic; clk_osc_out : out std_logic; CLK_gen : in std_logic; -- rst_n : in std_logic; -- to the test socket (DUT) -- 3.3V LVCMOS signals DUT_RST_n : inout std_logic; DUT_IRQ_n : inout std_logic; -- 3.3V LVCMOS signals - JTAG DUT_EN_JTAG : out std_logic; -- out_rng NI_EN_JTAG : out std_logic_vector(3 downto 0); -- out_rng DUT_TCK : inout std_logic; DUT_TMS : inout std_logic; DUT_TDI : inout std_logic; DUT_TDO : in std_logic; -- LVDS signals - clock and pretrigger outputs DUT_CLK : in std_logic_vector(3 downto 0); DUT_PRE : in std_logic_vector(3 downto 0); -- LVDS signals - NI output port DUT_P4_D : in std_logic_vector(9 downto 0); DUT_P4_STR : in std_logic; DUT_OA_CTR : in std_logic; DUT_P4_CTR : out std_logic; -- LVDS signals - SCSN interface DUT_SER0_IN : in std_logic; DUT_SER0_OUT : out std_logic; DUT_SER1_IN : in std_logic; DUT_SER1_OUT : out std_logic; -- the trap in the wafer tester WT_SER0_IN : in std_logic; WT_SER0_OUT : out std_logic; WT_SER1_IN : in std_logic; WT_SER1_OUT : out std_logic; WT_CLK : out std_logic; WT_PRE : out std_logic; -- LVCMOS signals DUT_SEBD : inout std_logic_vector( 2 downto 0); -- TST_PAD : in std_logic_vector( 3 downto 0); -- to the 4 TRAPs -- LVCMOS signals NI_RST_n : out std_logic; NI_IRQ_n : out std_logic; -- 3.3V LVCMOS signals - JTAG NI_TCK_up : inout std_logic; NI_TMS_up : inout std_logic; NI_TDI_up : inout std_logic; NI_TDO_up : in std_logic; NI_TCK_dn : inout std_logic; NI_TMS_dn : inout std_logic; NI_TDI_dn : inout std_logic; NI_TDO_dn : in std_logic; -- LVDS signals NI_CLK_up : out std_logic; NI_CLK_dn : out std_logic; NI_PRE_up : out std_logic; NI_PRE_dn : out std_logic; -- LVDS signals - SCSN interface NI_SER0_IN : in std_logic; NI_SER0_OUT : out std_logic; NI_SER1_IN : in std_logic; NI_SER1_OUT : out std_logic; -- Link to the next FPGA controlling the ADCs/DACs -- LVCMOS signals - SCSN interface AD_SER0_IN : in std_logic; AD_SER0_OUT : out std_logic; AD_SER1_IN : in std_logic; AD_SER1_OUT : out std_logic; -- general purpose synchronization signals AD_SYNC_OUT : out std_logic_vector(1 downto 0); AD_SYNC_IN : in std_logic_vector(1 downto 0); -- Uplink to PC -- LVDS signals - SCSN interface PC_SER0_IN : in std_logic; PC_SER0_OUT : out std_logic; PC_SER1_IN : in std_logic; PC_SER1_OUT : out std_logic; -- LVDS additional links, not used yet PC_0_IN : in std_logic; PC_0_OUT : out std_logic; PC_1_IN : in std_logic; PC_1_OUT : out std_logic ); end top; -------------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------------- architecture a of top is component mcm_network_interface is port( -- external Network Interface ser0_din : in std_logic ; --ring 0 data in ser0_dout : out std_logic ; --ring 0 data out ser1_din : in std_logic ; --ring 1 data in ser1_dout : out std_logic ; --ring 1 data out -- Bus interface bus_addr : out std_logic_vector(15 downto 0); -- address to read/write bus_dout : out std_logic_vector(31 downto 0); -- data out bus_din : in std_logic_vector(31 downto 0); -- data in bus_req : out std_logic; -- bus request bus_we : out std_logic; -- write enable bus_ack : in std_logic; chipRST_n : out std_logic; --- clock and reset Signals reset_n : in std_logic; clk_buf_disable : out std_logic; clk_buf : in std_logic; clk : in std_logic ); end component; component scsn_switch is port( sw_sel : in std_logic_vector( 7 downto 0); -- the trap in the socket DUT_SER0_IN : in std_logic; DUT_SER0_OUT : out std_logic; DUT_SER1_IN : in std_logic; DUT_SER1_OUT : out std_logic; -- the trap in the wafer tester WT_SER0_IN : in std_logic; WT_SER0_OUT : out std_logic; WT_SER1_IN : in std_logic; WT_SER1_OUT : out std_logic; -- the 4 traps NI_SER0_IN : in std_logic; NI_SER0_OUT : out std_logic; NI_SER1_IN : in std_logic; NI_SER1_OUT : out std_logic; -- next FPGA AD_SER0_IN : in std_logic; AD_SER0_OUT : out std_logic; AD_SER1_IN : in std_logic; AD_SER1_OUT : out std_logic; -- internal slave SER0_OUT : in std_logic; SER1_IN : out std_logic; -- Uplink to PC PC_SER0_OUT : out std_logic; PC_SER1_IN : in std_logic); end component; component pll120 IS -- generated with the MegaWizard, all files are in quartus directory -- input frequency 60 or 72 MHz, output frequency 120 MHz PORT ( inclk0 : IN STD_LOGIC := '0'; areset : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC; -- for internal use only e0 : OUT STD_LOGIC -- for use as output to the TRAPs ); END component; component ni2io is port ( clk : in std_logic; reset_n : in std_logic; -- asynchronous reset clear : in std_logic; -- synchronous reset oase_mode : in std_logic; -- from the configuration -- jtag_mode : in std_logic; -- from the configuration -- ctrl_jtag : in std_logic; -- from the configuration -- ctrl : out std_logic; -- control to the trap oa_ctrl : in std_logic; -- oase mode control from the trap strobe : in std_logic; -- incoming DDR strobe/clock signal lvds_data_in : in std_logic_vector( 9 downto 0); -- incoming DDR data sel_s : in std_logic_vector( 3 downto 0); -- from the configuration sel_p : in std_logic_vector( 3 downto 0); -- from the configuration or_mask : in std_logic_vector( 9 downto 0); and_mask : in std_logic_vector( 9 downto 0); xor_mask : in std_logic_vector( 9 downto 0); naddr : out std_logic_vector(23 downto 0); -- next address, to the IO pcnt : out std_logic_vector(23 downto 0); raddr : in std_logic_vector(10 downto 0); -- read address rdata : out std_logic_vector(31 downto 0) -- read data ); end component; -- template for new IO device --component generic_gio_device is -- port ( -- clk : in std_logic; -- reset_n : in std_logic; -- ce : in std_logic; -- -- -- SCSN -- bus_addr : in std_logic_vector( 7 downto 0); -- bus_we : in std_logic; -- write enable -- bus_din : in std_logic_vector(31 downto 0); -- bus_dout : out std_logic_vector(31 downto 0); -- -- -- user IO -- user_in : in std_logic; -- user_out : out std_logic -- ); --end component; component jtag_master is generic (N : Integer := 2); port ( clk : in std_logic; reset_n : in std_logic; ce : in std_logic; -- SCSN bus_addr : in std_logic_vector( 7 downto 0); bus_we : in std_logic; -- write enable bus_din : in std_logic_vector(31 downto 0); bus_dout : out std_logic_vector(31 downto 0); -- user IO EN1 : out std_logic; EN2 : out std_logic; EN3 : out std_logic; EN4 : out std_logic; EN5 : out std_logic; TCK : inout std_logic; TMS : inout std_logic; TDI : inout std_logic; TDO : in std_logic ); end component; component clkpre_counter is port ( clk : in std_logic; reset_n : in std_logic; ce : in std_logic; -- SCSN bus_addr : in std_logic_vector( 7 downto 0); bus_we : in std_logic; -- write enable bus_din : in std_logic_vector(31 downto 0); bus_dout : out std_logic_vector(31 downto 0); -- user IO PRE_SCSN : in std_logic; DUT_CLK : in std_logic_vector( 3 downto 0); DUT_PRE : in std_logic_vector( 3 downto 0); DUT_STRB : in std_logic; AD_SYNC_OUT : out std_logic; AD_SYNC_IN : in std_logic; ctrl_ni : out std_logic; NI_PRE : out std_logic ); end component; component general_config is generic( SERNR : Integer := 0; HDVER : Integer := 0); port ( clk : in std_logic; reset_n : in std_logic; reset_pup_n : in std_logic; ce : in std_logic; -- SCSN bus_addr : in std_logic_vector( 7 downto 0); bus_we : in std_logic; -- write enable bus_din : in std_logic_vector(31 downto 0); bus_dout : out std_logic_vector(31 downto 0); -- user IO sw_sel : out std_logic_vector( 7 downto 0); ni_sel_s : out std_logic_vector( 3 downto 0); ni_sel_p : out std_logic_vector( 3 downto 0); ni_or_mask : out std_logic_vector( 9 downto 0); ni_and_mask : out std_logic_vector( 9 downto 0); ni_xor_mask : out std_logic_vector( 9 downto 0); ni_oase_mode : out std_logic; ni_jtag_mode : out std_logic; ni_ctrl_jtag : out std_logic; ni_irq_n : out std_logic; ni_rst_n : out std_logic; dut_irq_n : inout std_logic; dut_rst_n : inout std_logic; tst_pad : in std_logic_vector( 3 downto 0); sebd_in : in std_logic_vector( 2 downto 0); sebd_out : out std_logic_vector( 2 downto 0); sebd_oe : out std_logic_vector( 2 downto 0); ni_naddr : in std_logic_vector(23 downto 0); ni_pcnt : in std_logic_vector(23 downto 0); ni_direct : in std_logic_vector(16 downto 0); ni_clear : out std_logic ); end component; component gio_devices is port( clk : in std_logic; nif_dout : in std_logic_vector(31 downto 0); gen_dout : in std_logic_vector(31 downto 0); cp_dout : in std_logic_vector(31 downto 0); jtg_ni_up_dout : in std_logic_vector(31 downto 0); jtg_ni_dn_dout : in std_logic_vector(31 downto 0); jtg_dut_dout : in std_logic_vector(31 downto 0); bus_addr : in std_logic_vector(15 downto 8); -- address to read/write bus_req : in std_logic; -- bus request bus_ack : out std_logic; -- request and address decoded ce_nif : out std_logic; -- ni fifo read only ce_gen : out std_logic; -- general config ce_cp : out std_logic; -- clock and pretrigger ce_ni_jtg_up : out std_logic; -- jtag ce_ni_jtg_dn : out std_logic; -- jtag ce_dut_jtg : out std_logic; -- jtag bus_dout : out std_logic_vector(31 downto 0) ); end component; COMPONENT GLOBAL PORT (a_in : IN STD_LOGIC; a_out: OUT STD_LOGIC); END COMPONENT; -- internal scsn interface to switch signal ser0_out : std_logic; signal ser1_in : std_logic; -- the global internal clock signal clk : std_logic; -- Bus interface signal bus_addr : std_logic_vector(15 downto 0); -- address to read/write signal bus_wdata : std_logic_vector(31 downto 0); -- data out signal bus_rdata : std_logic_vector(31 downto 0); -- data in signal bus_req : std_logic; -- bus request signal bus_we : std_logic; -- write enable signal bus_ack : std_logic; signal ni_clear : std_logic; -- synchronous reset signal ni_oase_mode : std_logic; -- from the configuration signal ni_jtag_mode : std_logic; signal ni_ctrl_jtag : std_logic; signal ni_ctrl_sm : std_logic; -- ni control generated with some delay rel. to the pretrigger signal ni_sel_s : std_logic_vector( 3 downto 0); -- configuration signal ni_sel_p : std_logic_vector( 3 downto 0); -- configuration signal ni_or_mask : std_logic_vector( 9 downto 0); signal ni_and_mask : std_logic_vector( 9 downto 0); signal ni_xor_mask : std_logic_vector( 9 downto 0); signal ni_naddr : std_logic_vector(23 downto 0); -- next address, to the IO signal ni_pcnt : std_logic_vector(23 downto 0); -- parity counters signal nif_dout : std_logic_vector(31 downto 0); -- read data signal nic_dout : std_logic_vector(31 downto 0); -- read data signal jtg_dut_dout : std_logic_vector(31 downto 0); -- read data signal jtg_ni_up_dout : std_logic_vector(31 downto 0); -- read data signal jtg_ni_dn_dout : std_logic_vector(31 downto 0); -- read data signal cp_dout : std_logic_vector(31 downto 0); -- read data signal NI_direct : std_logic_vector(16 downto 0); -- read data signal reset_n : std_logic; --signal RST_n : std_logic; signal sw_sel : std_logic_vector( 7 downto 0); signal sebd_in : std_logic_vector( 2 downto 0); signal sebd_out : std_logic_vector( 2 downto 0); signal sebd_oe : std_logic_vector( 2 downto 0); --signal ce_nif : std_logic; -- ni fifo read only signal ce_gen : std_logic; -- general config signal ce_cp : std_logic; -- clock and pretrigger signal ce_ni_jtg_up : std_logic; -- jtag signal ce_ni_jtg_dn : std_logic; -- jtag signal ce_dut_jtg : std_logic; -- jtag signal NI_CLK_i : std_logic; -- jtag signal NI_PRE_i : std_logic; -- jtag signal DUT_P4_STR_g : std_logic; -- jtag signal DUT_CLK_g : std_logic_vector( 3 downto 0); signal areset : std_logic; signal TST_PAD : std_logic_vector( 3 downto 0); --signal WT_SER0_IN : std_logic; --signal WT_SER1_IN : std_logic; signal WT_SER0_OUT_i : std_logic; signal WT_SER1_OUT_i : std_logic; signal chipRST_n : std_logic; signal rst_n : std_logic; signal rst_n_a : std_logic_vector(3 downto 0) := (others => '0'); begin process(clk) begin if clk'event and clk= '1' then rst_n_a <= rst_n_a(2 downto 0) & '1'; rst_n <= rst_n_a(3); end if; end process; -- TST_PAD <= (others => '1'); clk_osc_out <= clk_osc_in; -- areset <= not rst_n; areset <= '0'; PLL: pll120 PORT MAP ( inclk0 => clk_gen, areset => areset, c0 => clk, e0 => NI_CLK_i ); NI_CLK_dn <= NI_CLK_i; NI_CLK_up <= CLK; WT_CLK <= CLK when ni_oase_mode='0' else ni_sel_p(0); WT_PRE <= NI_PRE_i when ni_oase_mode='0' else ni_sel_p(1); WT_SER0_OUT <= WT_SER0_OUT_i when ni_oase_mode='0' else ni_sel_p(2); WT_SER1_OUT <= WT_SER1_OUT_i when ni_oase_mode='0' else ni_sel_p(3); -- WT_SER0_IN <= '0'; -- WT_SER1_IN <= '0'; scsn_sw: scsn_switch port map( sw_sel => sw_sel, -- the trap in the socket DUT_SER0_IN => DUT_SER0_IN, DUT_SER0_OUT => DUT_SER0_OUT, DUT_SER1_IN => DUT_SER1_IN, DUT_SER1_OUT => DUT_SER1_OUT, -- the trap in the wafer tester WT_SER0_IN => WT_SER0_IN, WT_SER0_OUT => WT_SER0_OUT_i, WT_SER1_IN => WT_SER1_IN, WT_SER1_OUT => WT_SER1_OUT_i, -- the 4 traps NI_SER0_IN => NI_SER0_IN, NI_SER0_OUT => NI_SER0_OUT, NI_SER1_IN => NI_SER1_IN, NI_SER1_OUT => NI_SER1_OUT, -- next FPGA AD_SER0_IN => AD_SER0_IN, AD_SER0_OUT => AD_SER0_OUT, AD_SER1_IN => AD_SER1_IN, AD_SER1_OUT => AD_SER1_OUT, -- internal slave SER0_OUT => ser0_out, SER1_IN => ser1_in, -- Uplink to PC PC_SER0_OUT => PC_SER0_OUT, PC_SER1_IN => PC_SER1_IN); scsn_slave: mcm_network_interface port map( -- external Network Interface ser0_din => PC_SER0_IN, ser0_dout => ser0_out, ser1_din => ser1_in, ser1_dout => PC_SER1_OUT, -- Bus interface bus_addr => bus_addr, bus_dout => bus_wdata, bus_din => bus_rdata, bus_req => bus_req, bus_we => bus_we, bus_ack => bus_ack, chipRST_n => chipRST_n, --- clock and reset Signals reset_n => RST_n, clk_buf_disable => open, clk_buf => clk, clk => clk ); reset_n <= rst_n and chipRST_n; stg: GLOBAL PORT MAP(a_in => DUT_P4_STR, a_out => DUT_P4_STR_g ); ni: ni2io port map ( clk => clk, reset_n => reset_n, clear => ni_clear, oase_mode => ni_oase_mode, -- jtag_mode => ni_jtag_mode, -- ctrl_jtag => ni_ctrl_jtag, -- ctrl => DUT_P4_CTR, oa_ctrl => DUT_OA_CTR, strobe => DUT_P4_STR_g, lvds_data_in => DUT_P4_D, sel_s => ni_sel_s, sel_p => ni_sel_p, or_mask => ni_or_mask, and_mask => ni_and_mask, xor_mask => ni_xor_mask, naddr => ni_naddr, pcnt => ni_pcnt, raddr => bus_addr(10 downto 0), rdata => nif_dout ); DUT_P4_CTR <= ni_ctrl_sm when ni_jtag_mode='0' else ni_ctrl_jtag; NI_direct <= DUT_SER0_IN & "0000" & DUT_OA_CTR & DUT_P4_STR_g & DUT_P4_D; cg0: GLOBAL PORT MAP(a_in => DUT_CLK(0), a_out => DUT_CLK_g(0) ); cg1: GLOBAL PORT MAP(a_in => DUT_CLK(1), a_out => DUT_CLK_g(1) ); cg2: GLOBAL PORT MAP(a_in => DUT_CLK(2), a_out => DUT_CLK_g(2) ); cg3: GLOBAL PORT MAP(a_in => DUT_CLK(3), a_out => DUT_CLK_g(3) ); cp: clkpre_counter port map( clk => clk, reset_n => reset_n, ce => ce_cp, -- SCSN bus_addr => bus_addr(7 downto 0), bus_we => bus_we, bus_din => bus_wdata, bus_dout => cp_dout, -- user IO PRE_SCSN => PC_1_IN, DUT_CLK => DUT_CLK_g, DUT_PRE => DUT_PRE, DUT_STRB => DUT_P4_STR_g, AD_SYNC_OUT => AD_SYNC_OUT(1), AD_SYNC_IN => AD_SYNC_IN(0), ctrl_ni => ni_ctrl_sm, NI_PRE => NI_PRE_i ); NI_PRE_up <= NI_PRE_i; NI_PRE_dn <= NI_PRE_i; -- used in wafer tester mode AD_SYNC_OUT(0) <= ni_ctrl_sm; PC_1_OUT <= AD_SYNC_IN(1); -- PC_0_OUT <= AD_SYNC_IN(0) or PC_0_IN; PC_0_OUT <= '0'; DUT_SEBD(0) <= sebd_out(0) when sebd_oe(0)='1' else 'Z'; DUT_SEBD(1) <= sebd_out(1) when sebd_oe(1)='1' else 'Z'; DUT_SEBD(2) <= sebd_out(2) when sebd_oe(2)='1' else 'Z'; sebd_in <= DUT_SEBD; nic: general_config generic map( SERNR => SERNR, HDVER => HDVER) port map( clk => clk, reset_n => reset_n, reset_pup_n => RST_n, ce => ce_gen, -- SCSN bus_addr => bus_addr(7 downto 0), bus_we => bus_we, bus_din => bus_wdata, bus_dout => nic_dout, -- user IO ni_sel_s => ni_sel_s, ni_sel_p => ni_sel_p, ni_or_mask => ni_or_mask, ni_and_mask => ni_and_mask, ni_xor_mask => ni_xor_mask, ni_oase_mode => ni_oase_mode, ni_jtag_mode => ni_jtag_mode, ni_ctrl_jtag => ni_ctrl_jtag, ni_naddr => ni_naddr, ni_pcnt => ni_pcnt, ni_clear => ni_clear, ni_direct => ni_direct, ni_irq_n => NI_IRQ_n, ni_rst_n => NI_RST_n, dut_irq_n => DUT_IRQ_n, dut_rst_n => DUT_RST_n, tst_pad => tst_pad, sebd_in => sebd_in, sebd_out => sebd_out, sebd_oe => sebd_oe, sw_sel => sw_sel ); gio: gio_devices port map( clk => clk, nif_dout => nif_dout, gen_dout => nic_dout, jtg_ni_up_dout => jtg_ni_up_dout, jtg_ni_dn_dout => jtg_ni_dn_dout, jtg_dut_dout => jtg_dut_dout, cp_dout => cp_dout, bus_req => bus_req, bus_ack => bus_ack, bus_addr => bus_addr(15 downto 8), bus_dout => bus_rdata, -- request and address decoded -- ce_nif => ce_nif, ce_nif => open, ce_gen => ce_gen, ce_cp => ce_cp, ce_ni_jtg_up => ce_ni_jtg_up, ce_ni_jtg_dn => ce_ni_jtg_dn, ce_dut_jtg => ce_dut_jtg ); jtag_ni_up: jtag_master generic map(N => 2) port map( clk => clk, reset_n => reset_n, ce => ce_ni_jtg_up, -- SCSN bus_addr => bus_addr(7 downto 0), bus_we => bus_we, bus_din => bus_wdata, bus_dout => jtg_ni_up_dout, -- user IO EN1 => NI_EN_JTAG(0), EN2 => NI_EN_JTAG(1), EN3 => open, EN4 => open, EN5 => open, TCK => NI_TCK_up, TMS => NI_TMS_up, TDI => NI_TDI_up, TDO => NI_TDO_up ); jtag_ni_dn: jtag_master generic map(N => 2) port map( clk => clk, reset_n => reset_n, ce => ce_ni_jtg_dn, -- SCSN bus_addr => bus_addr(7 downto 0), bus_we => bus_we, bus_din => bus_wdata, bus_dout => jtg_ni_dn_dout, -- user IO EN1 => NI_EN_JTAG(2), EN2 => NI_EN_JTAG(3), EN3 => open, EN4 => open, EN5 => open, TCK => NI_TCK_dn, TMS => NI_TMS_dn, TDI => NI_TDI_dn, TDO => NI_TDO_dn ); jtag_dut: jtag_master generic map(N => 1) port map( clk => clk, reset_n => reset_n, ce => ce_dut_jtg, -- SCSN bus_addr => bus_addr(7 downto 0), bus_we => bus_we, bus_din => bus_wdata, bus_dout => jtg_dut_dout, -- user IO EN1 => DUT_EN_JTAG, EN2 => open, EN3 => open, EN4 => open, EN5 => open, TCK => DUT_TCK, TMS => DUT_TMS, TDI => DUT_TDI, TDO => DUT_TDO ); end;