LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -- top -- \ -- +------- -- | \ -- | mcm_network_interface (ready, trap3 version without hamming) -- | -- +------- -- | \ -- | ni2io_wt (used in wafer tester mode only) -- | -- +------- -- \ -- adc_dac -- +------ -- | \ -- | gio_devices_adc (ready) -- | -- +------ -- | \ -- | seradc_auto (ready) -- | \---- -- | \ -- | TLV2548 serial adc (ready) -- +------ -- | \ -- | TLV5630 - slow serial dac (ready) -- | -- +------ -- | \ -- | DDS (ready) -- | -- +------ -- | \ -- | pasaadc - 30 MHz adc with mux and memory buffer (ready) -- | -- +------ -- | \ -- | digpot4 - serial interface to th 4 digital poti controlling the MCM power supply (ready) -- | -- +------ -- \ -- pasadac - 60 MHz DACs (ready) -- -- IO space - no overlap with the TRAP chip -- sadc 1 0x5000 0x50FF -- sadc 2 0x5100 0x51FF -- dds 0x5200 0x52FF -- sc adc 0x5300 0x53FF -- psply adc 0x5400 0x54FF -- pasa dac 0x5500 0x55FF -- pasa adc 0x5800 0x5FFF entity top is generic(wafer_test : Integer := 1); port ( CLK_gen : in std_logic; -- rst_n : in std_logic; -- for wafer tester only (LVDS) WT_STR : in std_logic; WT_P4D : in std_logic_vector(9 downto 0); WT_CTR : out std_logic; PA_SCLK : in std_logic; PA_SDAT : in std_logic; PA_SSTR : in std_logic; PA_VDD : out std_logic; VGND : out std_logic_vector(2 downto 0); WRST_n : inout std_logic; -- Link to the other FPGA -- LVCMOS signals - SCSN interface SER0_IN : in std_logic; SER0_OUT : out std_logic; SER1_IN : in std_logic; SER1_OUT : out std_logic; -- general purpose synchronization signals AD_SYNC_OUT : out std_logic_vector(1 downto 0); AD_SYNC_IN : in std_logic_vector(1 downto 0); -- ADCs and DACs VMCM_Shdwn_a : out std_logic; VMCM_Shdwn_d : out std_logic; PW_INCn : out std_logic_vector(3 downto 0); PW_UDn : out std_logic_vector(3 downto 0); PW_CSn : out std_logic_vector(3 downto 0); -- Power supply ADC TLV2548 -- ADC channel Connected to -- 0 Current 3V3 Pasa -- 1 Voltage 3V3 Pasa -- 2 Current 3V3 digital IO -- 3 Voltage 3V3 digital IO -- 4 Current 1V8 analog -- 5 Voltage 1V8 analog -- 6 Current 1V8 digital core -- 7 Voltage 1V8 digital core MSply_ADC_nCS : out std_logic; MSply_ADC_INTn : in std_logic; MSply_ADC_nCSStrt : out std_logic; MSply_ADC_SDI : out std_logic; MSply_ADC_SDO : in std_logic; MSply_ADC_SCLK : out std_logic; -- DDS for the 3 ADC channels AD9854 DDS_FSK : out std_logic; DDS_ShKey : out std_logic; DDS_CSn : out std_logic; DDS_SCLK : out std_logic; DDS_UDCLK : out std_logic; DDS_SDI : out std_logic; DDS_SDO : in std_logic; -- ?? DDS_IORST : out std_logic; DDS_MRST : out std_logic; DDS_MCLK : out std_logic; -- PASA ADC ADS5221 PAADC_D : in std_logic_vector(11 downto 0); PAADC_OVR : in std_logic; PAADC_CLK : out std_logic; PAADC_Msel : out std_logic; PAADC_STDP : out std_logic; PAADC_MuxnRS : out std_logic; -- 00 - PASA channel 1 -- 01 - PASA channel 17 -- 10 - PASA channel 18 -- 11 - DDS channel 1 PAADC_MuxA : out std_logic_vector(1 downto 0); -- PASA DACs AD9744 PasaDAC1_CLK : out std_logic; PasaDAC2_CLK : out std_logic; PasaDAC_Sleep : out std_logic; PasaDAC_D : out std_logic_vector(13 downto 0); -- Slow DAC 2xTLV5630 -- DAC channel Connected to -- 0 1V8 TRAP digital -- 1 1V8 TRAP analog -- 2 3V3 TRAP IO -- 3 3V3 PASA -- 4 not used -- 5 not used -- 6 not used -- 7 not used -- DAC2 channel Connected to -- 0 DDS VCM (TRAP ADC) -- 1 PASA Vcm -- 2 PASA Vref p -- 3 PASA Vref n -- 4 ADC aux p -- 5 ADC aux n -- 6 Vref PASA -- 7 Vref TRAP SlowDAC1_SCLK : out std_logic; SlowDAC2_SCLK : out std_logic; SlowDAC1_LDACn : out std_logic; SlowDAC2_LDACn : out std_logic; SlowDAC_Din : out std_logic; SlowDAC1_FS : out std_logic; SlowDAC2_FS : out std_logic; -- SC ADC TLV2548 -- ADC channel Connected to -- 0 VREF PASA -- 1 PASA Vcm -- 2 PASA REFp -- 3 PASA REFn -- 4 Vref TRAP ADC -- 5 unused -- 6 DC of muxed PASA output (-) -- 7 DC of muxed PASA output (+) SC_ADC_SDO : in std_logic; SC_ADC_INTn : in std_logic; SC_ADC_nCSStrt : out std_logic; SC_ADC_SCLK : out std_logic; SC_ADC_SDI : out std_logic; SC_ADC_nCS : out std_logic ); end top; -------------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------------- architecture a of top is component ADC_DAC is generic(wafer_test : Integer := 0); port( clk : in std_logic; clk120 : in std_logic; reset_n : in std_logic; -- SCSN bus_addr : in std_logic_vector(15 downto 0); bus_we : in std_logic; -- write enable bus_din : in std_logic_vector(31 downto 0); bus_dout : out std_logic_vector(31 downto 0); bus_req : in std_logic; -- bus request bus_ack : out std_logic; -- general purpose synchronization signals AD_SYNC_OUT : out std_logic_vector(1 downto 0); AD_SYNC_IN : in std_logic_vector(1 downto 0); -- ADCs and DACs VMCM_Shdwn_a : out std_logic; VMCM_Shdwn_d : out std_logic; PW_INCn : out std_logic_vector(3 downto 0); PW_UDn : out std_logic_vector(3 downto 0); PW_CSn : out std_logic_vector(3 downto 0); MSply_ADC_nCS : out std_logic; MSply_ADC_INTn : in std_logic; MSply_ADC_nCSStrt : out std_logic; MSply_ADC_SDI : out std_logic; MSply_ADC_SDO : in std_logic; MSply_ADC_SCLK : out std_logic; -- DDS for the 3 ADC channels AD9854 DDS_FSK : out std_logic; DDS_ShKey : out std_logic; DDS_CSn : out std_logic; DDS_SCLK : out std_logic; DDS_UDCLK : out std_logic; DDS_SDI : out std_logic; DDS_SDO : in std_logic; -- ?? DDS_IORST : out std_logic; DDS_MRST : out std_logic; DDS_MCLK : out std_logic; -- PASA ADC ADS5221 PAADC_D : in std_logic_vector(11 downto 0); PAADC_OVR : in std_logic; PAADC_CLK : out std_logic; PAADC_Msel : out std_logic; PAADC_STDP : out std_logic; PAADC_MuxnRS : out std_logic; PAADC_MuxA : out std_logic_vector(1 downto 0); -- PASA DACs AD9744 PasaDAC1_CLK : out std_logic; PasaDAC2_CLK : out std_logic; PasaDAC_Sleep : out std_logic; PasaDAC_D : out std_logic_vector(13 downto 0); -- Slow DAC 2xTLV5630 SlowDAC1_SCLK : out std_logic; SlowDAC2_SCLK : out std_logic; SlowDAC1_LDACn : out std_logic; SlowDAC2_LDACn : out std_logic; SlowDAC_Din : out std_logic; SlowDAC1_FS : out std_logic; SlowDAC2_FS : out std_logic; -- SC ADC TLV2548 SC_ADC_SDO : in std_logic; SC_ADC_INTn : in std_logic; SC_ADC_nCSStrt : out std_logic; SC_ADC_SCLK : out std_logic; SC_ADC_SDI : out std_logic; SC_ADC_nCS : out std_logic; CE_ni : out std_logic; rdata_ni : in std_logic_vector(31 downto 0) ); end component; component mcm_network_interface is port( -- external Network Interface ser0_din : in std_logic ; --ring 0 data in ser0_dout : out std_logic ; --ring 0 data out ser1_din : in std_logic ; --ring 1 data in ser1_dout : out std_logic ; --ring 1 data out -- Bus interface bus_addr : out std_logic_vector(15 downto 0); -- address to read/write bus_dout : out std_logic_vector(31 downto 0); -- data out bus_din : in std_logic_vector(31 downto 0); -- data in bus_req : out std_logic; -- bus request bus_we : out std_logic; -- write enable bus_ack : in std_logic; chipRST_n : out std_logic; --- clock and reset Signals reset_n : in std_logic; clk_buf_disable : out std_logic; clk_buf : in std_logic; clk : in std_logic ); end component; component pll120 IS -- generated with the MegaWizard, all files are in quartus directory -- input frequency 30 MHz, output frequency 120 MHz PORT ( inclk0 : IN STD_LOGIC := '0'; areset : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC; c1 : OUT STD_LOGIC ); END component; component ni2io_wt is port ( reset_n : in std_logic; -- asynchronous reset clk : in std_logic; -- read clock clk120 : in std_logic; -- read clock -- lvds strobe : in std_logic; -- incoming DDR strobe signal lvds_data_in : in std_logic_vector( 9 downto 0); -- incoming DDR data sync. to strobe PA_SCLK : in std_logic; PA_SDAT : in std_logic; PA_SSTR : in std_logic; wrst_n : out std_logic; wrst_n_in : in std_logic; wrst_n_oe : out std_logic; -- to the internal bus CE : in std_logic; WE : in std_logic; wdata : in std_logic_vector(31 downto 0); addr : in std_logic_vector(11 downto 0); rdata : out std_logic_vector(31 downto 0) -- data output, sync. to internal clk ); end component; -- the global internal clock signal clk120 : std_logic; signal clk : std_logic; -- Bus interface signal bus_addr : std_logic_vector(15 downto 0); -- address to read/write signal bus_wdata : std_logic_vector(31 downto 0); -- data out signal bus_rdata : std_logic_vector(31 downto 0); -- data in signal bus_req : std_logic; -- bus request signal bus_we : std_logic; -- write enable signal bus_ack : std_logic; signal reset_n : std_logic; signal reset_n_s : std_logic; --signal RST_n : std_logic; signal areset : std_logic; signal VMCM_Shdwn_a_i : std_logic; signal VMCM_Shdwn_d_i : std_logic; signal CE_ni : std_logic; signal rdata_ni : std_logic_vector(31 downto 0); signal wrst_n_i : std_logic; signal wrst_n_in : std_logic; signal wrst_n_oe : std_logic; signal rst_n : std_logic; signal rst_n_a : std_logic_vector(3 downto 0) := (others => '0'); begin -- areset <= not rst_n; areset <= '0'; PA_VDD <= '1'; VGND <= (others =>'0'); process(clk) begin if clk'event and clk= '1' then rst_n_a <= rst_n_a(2 downto 0) & '1'; rst_n <= rst_n_a(3); end if; end process; wt: if wafer_test = 1 generate ni: ni2io_wt port map( reset_n => reset_n, clk => clk, clk120 => clk120, -- lvds strobe => WT_STR, lvds_data_in => WT_P4D, PA_SCLK => PA_SCLK, PA_SDAT => PA_SDAT, PA_SSTR => PA_SSTR, wrst_n => wrst_n_i, wrst_n_in => wrst_n_in, wrst_n_oe => wrst_n_oe, -- to the internal bus CE => CE_ni, WE => bus_we, wdata => bus_wdata(31 downto 0), addr => bus_addr(11 downto 0), rdata => rdata_ni ); WT_CTR <= AD_SYNC_IN(0); WRST_n <= wrst_n_i when wrst_n_oe='1' else 'Z'; wrst_n_in <= WRST_n; end generate; nwt: if wafer_test /= 1 generate rdata_ni <= (others => '0'); WT_CTR <= '0'; end generate; -- open drain VMCM_Shdwn_a <= '0' when VMCM_Shdwn_a_i='0' else 'Z'; VMCM_Shdwn_d <= '0' when VMCM_Shdwn_d_i='0' else 'Z'; adcdac: ADC_DAC generic map(wafer_test => wafer_test) port map( clk => clk, clk120 => clk120, reset_n => reset_n, -- SCSN bus_addr => bus_addr, bus_we => bus_we, bus_din => bus_wdata, bus_dout => bus_rdata, bus_req => bus_req, bus_ack => bus_ack, -- general purpose synchronization signals AD_SYNC_OUT => AD_SYNC_OUT, AD_SYNC_IN => AD_SYNC_IN, -- user IO VMCM_Shdwn_a => VMCM_Shdwn_a_i, VMCM_Shdwn_d => VMCM_Shdwn_d_i, PW_INCn => PW_INCn, PW_UDn => PW_UDn, PW_CSn => PW_CSn, -- Power supply ADC MSply_ADC_nCS => MSply_ADC_nCS, MSply_ADC_INTn => MSply_ADC_INTn, MSply_ADC_nCSStrt => MSply_ADC_nCSStrt, MSply_ADC_SDI => MSply_ADC_SDI, MSply_ADC_SDO => MSply_ADC_SDO, MSply_ADC_SCLK => MSply_ADC_SCLK, -- DDS for the 3 ADC channels DDS_FSK => DDS_FSK, DDS_ShKey => DDS_ShKey, DDS_CSn => DDS_CSn, DDS_SCLK => DDS_SCLK, DDS_UDCLK => DDS_UDCLK, DDS_SDI => DDS_SDI, DDS_SDO => DDS_SDO, DDS_IORST => DDS_IORST, DDS_MRST => DDS_MRST, DDS_MCLK => DDS_MCLK, -- PASA ADC PAADC_D => PAADC_D, PAADC_OVR => PAADC_OVR, PAADC_CLK => PAADC_CLK, PAADC_Msel => PAADC_Msel, PAADC_STDP => PAADC_STDP, PAADC_MuxnRS => PAADC_MuxnRS, PAADC_MuxA => PAADC_MuxA, -- PASA DAC PasaDAC1_CLK => PasaDAC1_CLK, PasaDAC2_CLK => PasaDAC2_CLK, PasaDAC_Sleep => PasaDAC_Sleep, PasaDAC_D => PasaDAC_D, -- Slow DAC SlowDAC1_SCLK => SlowDAC1_SCLK, SlowDAC2_SCLK => SlowDAC2_SCLK, SlowDAC1_LDACn => SlowDAC1_LDACn, SlowDAC2_LDACn => SlowDAC2_LDACn, SlowDAC_Din => SlowDAC_Din, SlowDAC1_FS => SlowDAC1_FS, SlowDAC2_FS => SlowDAC2_FS, -- SC ADC SC_ADC_SDO => SC_ADC_SDO, SC_ADC_INTn => SC_ADC_INTn, SC_ADC_nCSStrt => SC_ADC_nCSStrt, SC_ADC_SCLK => SC_ADC_SCLK, SC_ADC_SDI => SC_ADC_SDI, SC_ADC_nCS => SC_ADC_nCS, CE_ni => CE_ni, rdata_ni => rdata_ni ); PLL: pll120 PORT MAP ( inclk0 => clk_gen, areset => areset, c0 => clk120, -- 120 MHz for scsn c1 => clk -- 30 or 40 MHz for all other modules ); -- RST_n <= '1'; scsn_slave: mcm_network_interface port map( -- external Network Interface ser0_din => SER0_IN, ser0_dout => SER0_OUT, ser1_din => SER1_IN, ser1_dout => SER1_OUT, -- Bus interface bus_addr => bus_addr, bus_dout => bus_wdata, bus_din => bus_rdata, bus_req => bus_req, bus_we => bus_we, bus_ack => bus_ack, chipRST_n => reset_n_s, --- clock and reset Signals reset_n => RST_n, clk_buf_disable => open, clk_buf => clk120, clk => clk120 ); reset_n <= rst_n and reset_n_s; end;