--
-- Transition Radiation Detector --
-- MCM Control Unit - Configuration Network --
--
--
-- $Id$
--
-- Robin Gareus, Kirchhoff Institute for Physics, Heidelberg
-- rgareus@kip.uni-heidelberg.de
--
------------------------------------------------------------
--
-- MCM Netrwork - Physical Layer Filter Implementation
--
--
-- Data is filtered and synchronized to internal clock here.
--
-- The filter length can be specified as a generic. A data change is
-- only assumed if the (new) data has not changed for
-- at least 'len +1 ' internal clock-cycles.
-- since the fastest transmit-speed is 1/4 of the internal clock.
-- We can savely have len to be > 1.
-- but the value should always be smaller than the data-link-layer's
-- generic 'timing_count_range' / 2.
-- so we are a a little more protected against noise on the wire, but setting
-- this  value too high, may also cause some data to be corrupted.


--------------------------------------------------
-- standard includes, library definitions.
--------------------------------------------------

library ieee,work;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

--------------------------------------------------
-- ENTITY
--------------------------------------------------

entity mcm_nw_pl is
 generic ( len    : integer := 1);  -- len > 0 !
 port(
        -- Signals from outside
        ser0_din        : in std_logic; -- data in
        ser1_din        : in std_logic;

        -- Signals to Data Link Layer
        d0_to_dll       : out std_logic; -- data out
        d1_to_dll       : out std_logic;

        clk_dis         : out std_logic;

        reset_n         : in std_logic;
        clk             : in std_logic

     );
end mcm_nw_pl;

--------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------

architecture structural of mcm_nw_pl is

 CONSTANT hi     : STD_LOGIC_VECTOR(len downto 0) := (OTHERS => '1');
 CONSTANT lo     : STD_LOGIC_VECTOR(len downto 0) := (OTHERS => '0');

 SIGNAL SAMPLES0 : STD_LOGIC_VECTOR(len downto 0);
 SIGNAL SAMPLES1 : STD_LOGIC_VECTOR(len downto 0);

 signal count_to   : std_logic_vector(5 downto 0);
 constant count_lo : std_logic_vector(5 downto 0) := (OTHERS => '0');

 begin

 -- Synchronize arriving data to internal clock
 -- and filter them.
 input_ff0: process(clk,reset_n)
 begin
        if (reset_n = '0') then
                d0_to_dll <= '0';
                SAMPLES0 <= (OTHERS => '0');
        elsif (clk'event and clk='1') then
                SAMPLES0(len downto 0) <= SAMPLES0(len-1 downto 0) & ser0_din;
                if    ( SAMPLES0 = hi ) then d0_to_dll <= '1';
                elsif ( SAMPLES0 = lo ) then d0_to_dll <= '0';
                else NULL; end if;
        end if;
 end process input_ff0;

 input_ff1: process(clk,reset_n)
 begin
        if (reset_n = '0') then
                d1_to_dll <= '0';
                SAMPLES1 <= (OTHERS => '0');
        elsif (clk'event and clk='1') then
                SAMPLES1(len downto 0) <= SAMPLES1(len-1 downto 0) & ser1_din;
                if    ( SAMPLES1 = hi ) then d1_to_dll <= '1';
                elsif ( SAMPLES1 = lo ) then d1_to_dll <= '0';
                else NULL; end if;
        end if;
 end process input_ff1;

 process(clk, reset_n)
 begin
    if reset_n = '0' then
        count_to <= (others => '1');
        clk_dis  <= '1';
    elsif clk'event and clk= '1'  then
        if (SAMPLES1=hi) or (SAMPLES0=hi) then
             count_to <= (others => '1');
             clk_dis  <= '0';
        else
             if count_to /= count_lo then count_to <= count_to - 1;
             else clk_dis  <= '1';
             end if;
        end if;
    end if;
end process;

end structural;

--------------------------------------------------
-- CONFIGURATION
--------------------------------------------------

-- synopsys translate_off
CONFIGURATION mcm_nw_pl_CFG of mcm_nw_pl is
 for structural
 end for;
end mcm_nw_pl_CFG;
-- synopsys translate_on