-- -- Transition Radiation Detector -- -- MCM Control Unit - Configuration Network -- -- -- -- $Id$ -- -- Robin Gareus, Kirchhoff Institute for Physics, Heidelberg -- rgareus@kip.uni-heidelberg.de -- ------------------------------------------------------------ -- -- This is the top level entity of the Serial-Slow-Control -- In here we just connect all the internal networklayer components. -- and define generic values. -- -- -- Generics are descibed in detail in .../report_2/main.ps and -- in the files that describe the entity. -- Here's a summary to get along for a while: -- -- -- Physical Layer: -- 'len' : length of filter-logic-chain -- : if data on wire changes faster than 'len+1' times -- : internal clock, the change is not forwarded to -- : the upper layer. -- : must be < than (timing_count_range+1)/2 -- -- len = 1 in TRAP2 -- -- Data Link Layer: -- 'timing_count_range' : defines the network speed in fractions -- : of internal clock. -- : internally the timing is done with a counter -- : that starts counting at ZERO, up to -- : 'timing_count_range'. -- : the fastest possible speed is 1/('timing_count_range' + 1) of -- : internal clock. so this value -- : has to be >2. -- -- timing_count_range = 4 in TRAP2 -- -- 'timing_recv_on' : timing-offset. after detecting clock edge -- : on the data in, the bittiming waits for -- : ('timing_recv_on' + 1) internal clocks -- : before strobing data into buffer. -- : needs to be < ('timing_count_range'-2) -- -- timing_recv_on = 2 in TRAP2 -- -- 'stuff_length' : specifies how many identical bits are sent/recv -- : without inserting/removing a stuff bit. -- : since a bitstuff error is treated as EndOfTransmission -- : this indirectly defines the timeout. -- : timeout is (stuff_length*(timing_count_range+1)) -- -- stuff_length = 7 in TRAP2 -- -- 'timing_sleep_length': after transmitting a frame, wait 'timing_sleep_length' -- : internal clock cycles before allowing to send -- : the next frame. -- : must be >MAX(timeout,'BUFHALF'*'timing_count_range'+1) -- -- timing_sleep_length = 63 in TRAP2 -- -- !!! do not change the values of the generics -- !!! below since the buffer-size is hardcoded -- !!! in network and data link layer. -- -- 'BUFSIZ' : size of the input/output buffers (BUFSIZ = 69) -- -- 'BUFHALF' : send error when we are still sending out data and -- : 'BUFSIZ'-'BUFHALF bits of a new frame have already -- : been recieved. (BUFHALF = 4) -- -- 'COUNTER' : number of bits needed to store the bitcounter. -- : the bitcounter has to count from 0 to (BUFSIZ+CRCLEN) -- (COUNTER = 7) -------------------------------------------------- -- standard includes, library definitions. -------------------------------------------------- library ieee,work; use ieee.std_logic_1164.all; use work.mcm_nw_pl; use work.mcm_nw_dll; use work.mcm_nw_nwl; use work.mcm_nw_apl; -------------------------------------------------- -- ENTITY -------------------------------------------------- entity mcm_network_interface is port( -- external Network Interface ser0_din : in std_logic ; --ring 0 data in ser0_dout : out std_logic ; --ring 0 data out ser1_din : in std_logic ; --ring 1 data in ser1_dout : out std_logic ; --ring 1 data out -- Bus interface bus_addr : out std_logic_vector(15 downto 0); -- address to read/write bus_dout : out std_logic_vector(31 downto 0); -- data out bus_din : in std_logic_vector(31 downto 0); -- data in bus_req : out std_logic; -- bus request bus_we : out std_logic; -- write enable bus_ack : in std_logic; chipRST_n: out std_logic; --- clock and reset Signals reset_n : in std_logic; clk_buf_disable : out std_logic; clk_buf : in std_logic; clk : in std_logic ); end mcm_network_interface; -------------------------------------------------- -- ARCHITECTURE -------------------------------------------------- architecture structural of mcm_network_interface is -------------------------------------------------- -- internal signals -------------------------------------------------- SIGNAL d0_sd : std_logic_vector(68 downto 0); SIGNAL d0_rd : std_logic_vector(68 downto 0); SIGNAL d0_buffer_ready,d0_send,d0_we,d0_err,d0_half,d0_strb : std_logic; SIGNAL d1_sd : std_logic_vector(68 downto 0); SIGNAL d1_rd : std_logic_vector(68 downto 0); SIGNAL d1_buffer_ready,d1_send,d1_we,d1_err,d1_half,d1_strb : std_logic; SIGNAL bridge : std_logic; SIGNAL apl_rq : std_logic_vector(52 downto 0); SIGNAL apl_ry : std_logic_vector(52 downto 0); SIGNAL rq_valid, ry_valid : std_logic; SIGNAL b_alter,b_mode : std_logic; SIGNAL altered_frame : std_logic; SIGNAL data_in_0,data_in_1: std_logic; signal clk_dis : std_logic; --signal clk_buf : std_logic; signal clk_buf_dis : std_logic; -------------------------------------------------- -- components -------------------------------------------------- COMPONENT mcm_nw_pl is generic ( len : integer := 1); port( -- Signals from outside ser0_din : in std_logic; ser1_din : in std_logic; -- Signals to Data Link Layer d0_to_dll : out std_logic; d1_to_dll : out std_logic; reset_n : in std_logic; clk_dis : out std_logic; clk : in std_logic ); END COMPONENT; COMPONENT mcm_nw_dll is generic (timing_count_range : integer := 7; timing_recv_on : integer := 2; stuff_length : integer := 4; timing_sleep_length : integer := 63; BUFSIZ : integer := 69; BUFHALF : integer := 4; COUNTER : integer := 7); port( -- Signals to phyiscal layer d0_fr_pl : in std_logic; d0_to_pl : out std_logic; d1_fr_pl : in std_logic; d1_to_pl : out std_logic; -- Signals to Network Layer (recv) d0_to_nwl : out std_logic_vector(BUFSIZ-1 downto 0); s0_to_nwl : out std_logic ; buf0_half : out std_logic ; buf0_err : out std_logic ; d1_to_nwl : out std_logic_vector(BUFSIZ-1 downto 0); s1_to_nwl : out std_logic ; buf1_half : out std_logic ; buf1_err : out std_logic ; -- Signals from Network Layer (send) d0_fr_nwl : in std_logic_vector(BUFSIZ-1 downto 0); d0_we : in std_logic; d0_send : in std_logic; d0_buffer_ready : out std_logic; d1_fr_nwl : in std_logic_vector(BUFSIZ-1 downto 0); d1_we : in std_logic; d1_send : in std_logic; d1_buffer_ready : out std_logic; -- X-bar data paths bridge : in std_logic; reset_n : in std_logic; clk_buf : in std_logic; clk : in std_logic ); END COMPONENT; COMPONENT mcm_nw_nwl is port( -- Signals from Data Link Layer d0_fr_dll : in std_logic_vector(68 downto 0); s0_fr_dll : in std_logic; buf0_half : in std_logic; buf0_err : in std_logic; d1_fr_dll : in std_logic_vector(68 downto 0); s1_fr_dll : in std_logic; buf1_half : in std_logic; buf1_err : in std_logic; -- Signals to Data Link Layer d0_buffer_ready : in std_logic; d0_to_dll : out std_logic_vector(68 downto 0); d0_to_dll_we : out std_logic; d0_to_dll_send : out std_logic; d1_buffer_ready : in std_logic; d1_to_dll : out std_logic_vector(68 downto 0); d1_to_dll_we : out std_logic; d1_to_dll_send : out std_logic; -- bridge to dll bridge : out std_logic; -- Signals to Application Layer request : out std_logic_vector(52 downto 0); request_valid : out std_logic; -- Signals from Application Layer reply : in std_logic_vector(52 downto 0); reply_valid : in std_logic; altered_frame : in std_logic; bridge_alter : in std_logic; bridge_mode : in std_logic; reset_n : in std_logic; clk_buf_dis : out std_logic; clk : in std_logic ); END COMPONENT; COMPONENT mcm_nw_apl is port( -- Signals from Network Layer request : in std_logic_vector(52 downto 0); request_valid : in std_logic; -- Signals to Network Layer reply : out std_logic_vector(52 downto 0); reply_valid : out std_logic; altered_frame : out std_logic; bridge_alter : out std_logic; bridge_mode : out std_logic; --- Bus interface bus_addr : out std_logic_vector(15 downto 0); bus_dout : out std_logic_vector(31 downto 0); bus_din : in std_logic_vector(31 downto 0); bus_req : out std_logic; bus_we : out std_logic; bus_ack : in std_logic; chipRST_n: out std_logic; reset_n : in std_logic; clk : in std_logic ); END COMPONENT; -------------------------------------------------- -- port maps -------------------------------------------------- begin nw_pl: mcm_nw_pl generic map ( len => 1 ) port map( ser0_din => ser0_din, ser1_din => ser1_din, d0_to_dll => data_in_0, d1_to_dll => data_in_1, clk_dis => clk_dis, reset_n => reset_n, clk => clk); clk_buf_disable <= clk_dis and clk_buf_dis; -- clock gating -- clk_buf <= clk; -- no clock gating --data_in_0 <= ser0_din; -- skip physical layer filter --data_in_1 <= ser1_din; nw_dll: mcm_nw_dll generic map( timing_count_range => 4, timing_recv_on => 2, stuff_length => 7, timing_sleep_length=> 63) port map( d0_fr_pl => data_in_0 , d0_to_pl => ser0_dout, s0_to_nwl => d0_strb, buf0_err => d0_err, buf0_half => d0_half, d0_to_nwl => d0_rd, d0_fr_nwl => d0_sd, d0_we => d0_we, d0_send => d0_send, d0_buffer_ready => d0_buffer_ready, d1_fr_pl => data_in_1 , d1_to_pl => ser1_dout, s1_to_nwl => d1_strb, buf1_err => d1_err, buf1_half => d1_half, d1_to_nwl => d1_rd, d1_fr_nwl => d1_sd, d1_we => d1_we, d1_send => d1_send, d1_buffer_ready => d1_buffer_ready, bridge => bridge, reset_n => reset_n, clk_buf => clk_buf, clk => clk ); nw_nwl: mcm_nw_nwl port map ( d0_fr_dll => d0_rd, s0_fr_dll => d0_strb, buf0_err => d0_err, buf0_half => d0_half, d0_buffer_ready => d0_buffer_ready, d0_to_dll => d0_sd, d0_to_dll_we => d0_we, d0_to_dll_send => d0_send, d1_fr_dll => d1_rd, s1_fr_dll => d1_strb, buf1_err => d1_err, buf1_half => d1_half, d1_buffer_ready => d1_buffer_ready, d1_to_dll => d1_sd, d1_to_dll_we => d1_we, d1_to_dll_send => d1_send, bridge => bridge, request => apl_rq, request_valid => rq_valid, reply => apl_ry, reply_valid => ry_valid, altered_frame => altered_frame, bridge_alter => b_alter, bridge_mode => b_mode, reset_n => reset_n, clk_buf_dis => clk_buf_dis, clk => clk ); nw_apl: mcm_nw_apl port map ( request => apl_rq, request_valid => rq_valid, reply => apl_ry, reply_valid => ry_valid, altered_frame => altered_frame, bridge_alter => b_alter, bridge_mode => b_mode, bus_addr => bus_addr, bus_dout => bus_dout, bus_din => bus_din, bus_req => bus_req, bus_we => bus_we, bus_ack => bus_ack, chipRST_n => chipRST_n, reset_n => reset_n, clk => clk ); end structural; -------------------------------------------------- -- CONFIGURATION -------------------------------------------------- -- synopsys translate_off CONFIGURATION mcm_network_interface_CFG of mcm_network_interface is for structural for ALL : mcm_nw_dll use configuration WORK.mcm_nw_dll_CFG; end for; for ALL : mcm_nw_nwl use configuration WORK.mcm_nw_nwl_CFG; end for; for ALL : mcm_nw_apl use configuration WORK.mcm_nw_apl_CFG; end for; end for; end mcm_network_interface_CFG; -- synopsys translate_on