----------------------------------------------------------------------
-- HAMMING state machine - an example
----------------------------------------------------------------------
LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

-- V.Angelov, 7 Feb 2002

entity hamm_reg is
generic(Nbits : Integer := 4; Init_value : Integer := 0; Bypass : Integer := 1);
port
        (clk, rst_n : in std_logic;
         data_in    : in  std_logic_vector(Nbits-1 downto 0);
         data_out   : out std_logic_vector(Nbits-1 downto 0)
        );
end hamm_reg;

architecture a of hamm_reg is

component hamm67dec34 is
generic( Nbits : Integer range 2 to 4 := 4);
port
        (code   : in  std_logic_vector(Nbits+3 downto 0);
         data   : out std_logic_vector(Nbits-1 downto 0);
         status : out std_logic_vector(1 downto 0)
        );
end component;

component hamm34enc67 is
generic( Nbits : Integer range 2 to 4 := 4);
port
        (data : in  std_logic_vector(Nbits-1 downto 0);
         code : out std_logic_vector(Nbits+3 downto 0)
        );
end component;

signal init_state : std_logic_vector(Nbits-1 downto 0);
signal hm_state0_in, hm_state_in, hm_state_out : std_logic_vector(Nbits+3 downto 0);
signal status : std_logic_vector(1 downto 0);
signal rst_n_i, hm_rst_n : std_logic;

begin
b0:     if Bypass=0 generate

        init_state <= CONV_STD_LOGIC_VECTOR(Init_Value, Nbits);
h0: hamm34enc67
        generic map(Nbits => Nbits)
        port map
        (data => init_state, -- generate the constant 0 in hamming
         code => hm_state0_in);

h1: hamm34enc67
        generic map(Nbits => Nbits)
        port map
        (data => data_in, -- state => hamming
         code => hm_state_in);

h2: hamm67dec34
        generic map(Nbits => Nbits)
        port map
        (code => hm_state_out, -- hamming => state
         data => data_out,
         status => status);

        process(clk, rst_n_i, hm_state0_in) -- register for the hamming bits
        begin
                if rst_n_i = '0' then hm_state_out <= hm_state0_in;
                elsif clk'event and clk='1' then
                        hm_state_out <= hm_state_in;
                end if;
        end process;

        process(clk, rst_n)
        begin
            if rst_n = '0' then hm_rst_n <= '0';
                elsif clk'event and clk='1' then
                        if status="10" then hm_rst_n <= '0';
                        else hm_rst_n <= '1'; end if;
                end if;
        end process;
        rst_n_i <= hm_rst_n and rst_n;
        end generate;

b1:     if Bypass=1 generate

        process(clk, rst_n) -- register for the hamming bits
        begin
                if rst_n = '0' then data_out <= (others => '0');
                elsif clk'event and clk='1' then
                        data_out <= data_in;
                end if;
        end process;

        end generate;
end;