library IEEE; use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity ni2nios is GENERIC (StrobeMode : Integer := 0); port ( clk : in std_logic; -- internal clock reset_n : in std_logic; -- asynchronous reset strobe : in std_logic; -- incoming DDR strobe signal ctrl : in std_logic; -- incoming DDR enable -- clk_n : in std_logic; -- incoming DDR clock lvds_data_in : in std_logic_vector( 9 downto 0); -- incoming DDR data sync. to strobe sel_s : in std_logic_vector( 3 downto 0); sel_p : in std_logic_vector( 3 downto 0); we_n : out std_logic; -- outgoing data valid signal data_out : out std_logic_vector(31 downto 0)); -- data output, sync. to internal clk end ni2nios; architecture a of ni2nios is component ni_exclude_in is generic ( width : integer := 10; -- word width incl. spare & parity bit depth : integer := 4); -- position selection word width port ( din : in std_logic_vector(width-1 downto 0); -- data in sel_s : in std_logic_vector(depth-1 downto 0); -- the spare bit position, -- will be selected out first ("1001") sel_p : in std_logic_vector(depth-1 downto 0); -- the parity bit position, -- will be selected out next ("1000") dout : out std_logic_vector(width-3 downto 0); -- data out prty_bit : out std_logic); -- parity bit output end component; component ni_resync is generic( width : integer := 10); -- width of the external interface port( clk : in std_logic; -- internal clock reset_n : in std_logic; -- asynchronous reset strobe : in std_logic; -- incoming DDR strobe signal data_in : in std_logic_vector(width-1 downto 0); -- incoming DDR data sync. to strobe we_n : out std_logic; -- outgoing data valid signal data_out : out std_logic_vector((2*width)-1 downto 0)); -- data output, sync. to internal clk end component; component ddr_sync is generic( width : integer := 10); -- width of the external interface port( clk : in std_logic; -- internal clock -- reset_n : in std_logic; -- asynchronous reset clk_n : in std_logic; -- incoming DDR clock signal ctrl : in std_logic; -- enable data_in : in std_logic_vector(width-1 downto 0); -- incoming DDR data sync. to strobe we_n : out std_logic; -- outgoing data valid signal data_out : out std_logic_vector((2*width)-1 downto 0)); -- data output, sync. to internal clk end component; component reg_clr is generic(Ndata : Integer := 32); port ( clk : in std_logic; ce : in std_logic; rst_n : in std_logic; d : in std_logic_vector(Ndata-1 downto 0); q : out std_logic_vector(Ndata-1 downto 0) ); end component; signal fifo_data0in : std_logic_vector(31 downto 0); signal fifo_data_in : std_logic_vector(31 downto 0); signal sync_data_out : std_logic_vector(19 downto 0); signal csync_data_out : std_logic_vector(21 downto 0); signal sync_data_2s : std_logic_vector(19 downto 0); signal strp_data_out : std_logic_vector(15 downto 0); --signal sel_s : std_logic_vector( 3 downto 0); --signal sel_p : std_logic_vector( 3 downto 0); signal prty_L : std_logic; signal prty_H : std_logic; signal we_L : std_logic; signal we_H : std_logic; signal we1H : std_logic; signal we_n_s : std_logic; signal we_n_c : std_logic; signal we_s : std_logic; --signal we2s : std_logic; signal bank : std_logic; begin -- sel_s <= "1001"; -- sel_p <= "1000"; sm: if StrobeMode=1 generate sync: ni_resync generic map(width => 10) port map( clk => clk, reset_n => reset_n, strobe => strobe, data_in => lvds_data_in, we_n => we_n_s, data_out => sync_data_out); end generate; cm: if StrobeMode =0 generate ck: ni_resync generic map(width => 11) port map( clk => clk, reset_n => reset_n, strobe => clk, data_in => ctrl & lvds_data_in, we_n => we_n_c, data_out => csync_data_out); sync_data_out <= csync_data_out(20 downto 11) & csync_data_out(9 downto 0); we_n_s <= not (csync_data_out(21) and csync_data_out(10) ); --csync: ddr_sync --generic map(width => 10) --port map( -- clk => clk, -- clk_n => clk_n, -- reset_n : in std_logic; -- asynchronous reset -- clk_in => clk_in, -- ctrl => ctrl, -- data_in => lvds_data_in, -- we_n => we_n_s, -- data_out => sync_data_out); end generate; we_s <= not we_n_s; rg_s: reg_clr generic map(Ndata => sync_data_out'length) port map(clk => clk, ce => we_s, rst_n => reset_n, d => sync_data_out, q => sync_data_2s ); we2: process(clk, reset_n) begin if reset_n='0' then -- we2s <= '0'; we_L <= '0'; we_H <= '0'; bank <= '0'; we1H <= '0'; we_n <= '1'; elsif clk'event and clk='1' then -- we2s <= we_s; we_L <= we_s and not bank; we_H <= we_s and bank; we1H <= we_H; if we_s='1' then bank <= not bank; end if; we_n <= not (we1H); end if; end process; excl0: ni_exclude_in generic map( width => 10, depth => 4) port map( din => sync_data_2s(9 downto 0), sel_s => sel_s, sel_p => sel_p, dout => strp_data_out(7 downto 0), prty_bit => prty_L); excl1: ni_exclude_in generic map( width => 10, depth => 4) port map( din => sync_data_2s(19 downto 10), sel_s => sel_s, sel_p => sel_p, dout => strp_data_out(15 downto 8), prty_bit => prty_H); -- par <= prty_H & prty_L; rg_L: reg_clr generic map(Ndata => strp_data_out'length) port map(clk => clk, ce => we_L, rst_n => reset_n, d => strp_data_out, q => fifo_data0in(15 downto 0) ); rg_H: reg_clr generic map(Ndata => strp_data_out'length) port map(clk => clk, ce => we_H, rst_n => reset_n, d => strp_data_out, q => fifo_data0in(31 downto 16) ); rg_o: reg_clr generic map(Ndata => fifo_data_in'length) port map(clk => clk, ce => we1H, rst_n => reset_n, d => fifo_data0in, q => fifo_data_in ); data_out <= fifo_data_in; end;