library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
--use IEEE.STD_LOGIC_UNSIGNED.all;

entity ni2io is
  port (
    reset_n       : in  std_logic;                      -- asynchronous reset

    clk           : in  std_logic;                      -- read clock
    strobe        : in  std_logic;                      -- incoming DDR strobe signal
    lvds_data_in  : in  std_logic_vector( 9 downto 0);  -- incoming DDR data sync. to strobe

    clear         : in  std_logic;                      -- synchronous reset

    oase_mode     : in  std_logic;                      -- from the configuration

    ctrl          : out std_logic;                      -- control to the trap
    oa_ctrl       : in  std_logic;                      -- oase mode control from the trap

    sel_s         : in  std_logic_vector( 3 downto 0);
    sel_p         : in  std_logic_vector( 3 downto 0);

    naddr         : out std_logic_vector(21 downto 0);
    rdreq         : in  std_logic;
    raddr         : in  std_logic_vector( 9 downto 0);
    rdata         : out std_logic_vector(31 downto 0)   -- data output, sync. to internal clk
    );
end ni2io;

architecture a of ni2io is

component reg_clr is
generic(Ndata : Integer := 32);
port (  clk   : in  std_logic;
        ce    : in  std_logic;
        rst_n : in  std_logic;
        d     : in  std_logic_vector(Ndata-1 downto 0);
        q     : out std_logic_vector(Ndata-1 downto 0)
     );
end component;

component ni2dpm is
generic (Abits : Integer := 11);
  port (
    reset_n       : in  std_logic;                      -- asynchronous reset

    clk_read      : in  std_logic;                      -- read clock
    strobe        : in  std_logic;                      -- incoming DDR strobe signal
    lvds_data_in  : in  std_logic_vector( 9 downto 0);  -- incoming DDR data sync. to strobe

    sel_s         : in  std_logic_vector( 3 downto 0);
    sel_p         : in  std_logic_vector( 3 downto 0);

    naddr         : out std_logic_vector(Abits-1 downto 0);
    raddr         : in  std_logic_vector(Abits-1 downto 0);
    rdata         : out std_logic_vector( 7 downto 0)   -- data output, sync. to internal clk
    );
end component;

signal raddr_i   : std_logic_vector(raddr'length downto 0); -- 1 bit more
signal naddr_pos : std_logic_vector(raddr'length downto 0); -- 1 bit more
signal naddr_neg : std_logic_vector(raddr'length downto 0); -- 1 bit more

signal rdata_neg : std_logic_vector(7 downto 0);
signal rdata_pos : std_logic_vector(7 downto 0);
signal qdata_neg : std_logic_vector(7 downto 0);
signal qdata_pos : std_logic_vector(7 downto 0);

signal low_bit   : std_logic;
signal reg_en    : std_logic;
signal strobe_n  : std_logic;

begin

    strobe_n <= not strobe;
    ctrl     <= '1';

ni_pos:  ni2dpm
generic map(Abits => raddr'length+1)
  port map(
    reset_n       => reset_n,

    clk_read      => clk,
    strobe        => strobe,
    lvds_data_in  => lvds_data_in,

    sel_s         => sel_s,
    sel_p         => sel_p,

    naddr         => naddr_pos,
    raddr         => raddr_i,
    rdata         => rdata_pos
    );

ni_neg:  ni2dpm
generic map(Abits => raddr'length+1)
  port map(
    reset_n       => reset_n,

    clk_read      => clk,
    strobe        => strobe_n,
    lvds_data_in  => lvds_data_in,

    sel_s         => sel_s,
    sel_p         => sel_p,

    naddr         => naddr_neg,
    raddr         => raddr_i,
    rdata         => rdata_neg
    );

    raddr_i <= raddr & low_bit;

    process(clk)
    begin
        if clk'event and clk= '1'  then
            low_bit <= rdreq;
            reg_en  <= not low_bit; -- address and data registered
        end if;
    end process;

rg0_pos: reg_clr
    generic map(Ndata => 8)
    port map(
        clk   => clk,
        ce    => reg_en,
        rst_n => '1',
        d     => rdata_pos,
        q     => qdata_pos
     );

rg0_neg: reg_clr
    generic map(Ndata => 8)
    port map(
        clk   => clk,
        ce    => reg_en,
        rst_n => '1',
        d     => rdata_neg,
        q     => qdata_neg
     );

    rdata <= rdata_pos & rdata_neg & qdata_pos & qdata_neg;
    naddr <= naddr_pos & naddr_neg;

end;