library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
--use IEEE.STD_LOGIC_UNSIGNED.all;

entity ni2dpm is
generic (Abits : Integer := 11);
  port (
    reset_n       : in  std_logic;                      -- asynchronous reset

    clk_read      : in  std_logic;                      -- read clock
    strobe        : in  std_logic;                      -- incoming DDR strobe signal
    lvds_data_in  : in  std_logic_vector( 9 downto 0);  -- incoming DDR data sync. to strobe

    sel_s         : in  std_logic_vector( 3 downto 0);
    sel_p         : in  std_logic_vector( 3 downto 0);

    naddr         : out std_logic_vector(Abits-1 downto 0);
    raddr         : in  std_logic_vector(Abits-1 downto 0);
    rdata         : out std_logic_vector( 7 downto 0)   -- data output, sync. to internal clk
    );
end ni2dpm;

architecture a of ni2dpm is

component ni_exclude_in is
  generic (
    width    : integer := 10;                           -- word width incl. spare & parity bit
    depth    : integer := 4);                           -- position selection word width
  port (
    din      : in  std_logic_vector(width-1 downto 0);  -- data in
    sel_s    : in  std_logic_vector(depth-1 downto 0);  -- the spare bit position,
                                                        -- will be selected out first ("1001")
    sel_p    : in  std_logic_vector(depth-1 downto 0);  -- the parity bit position,
                                                        -- will be selected out next ("1000")
    dout     : out std_logic_vector(width-3 downto 0);  -- data out
    prty_bit : out std_logic);                          -- parity bit output
end component;

component reg_clr is
generic(Ndata : Integer := 32);
port (  clk   : in  std_logic;
        ce    : in  std_logic;
        rst_n : in  std_logic;
        d     : in  std_logic_vector(Ndata-1 downto 0);
        q     : out std_logic_vector(Ndata-1 downto 0)
     );
end component;

COMPONENT lpm_counter
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_MODULUS: NATURAL := 0;
      LPM_DIRECTION: STRING := "UNUSED";
      LPM_AVALUE: STRING := "UNUSED";
      LPM_SVALUE: STRING := "UNUSED";
      LPM_PVALUE: STRING := "UNUSED";
      LPM_TYPE: STRING := "LPM_COUNTER";
      LPM_HINT : STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
      clock: IN STD_LOGIC;
      clk_en, cnt_en, updown: IN STD_LOGIC := '1';
      sload, sset, sclr, aload, aset, aclr, cin: IN STD_LOGIC := '0';
      cout: OUT STD_LOGIC;
      --eq: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

COMPONENT lpm_ram_dp
   GENERIC ( LPM_WIDTH: POSITIVE;
             LPM_WIDTHAD: POSITIVE;
--             LPM_NUMWORDS: NATURAL;
             LPM_TYPE: STRING := "LPM_RAM_DP";
             LPM_INDATA: STRING := "REGISTERED";
             LPM_OUTDATA: STRING := "REGISTERED";
             LPM_RDADDRESS_CONTROL: STRING := "REGISTERED";
             LPM_WRADDRESS_CONTROL: STRING := "REGISTERED"
           );

   PORT    ( rdaddress, wraddress: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
             rdclock, wrclock: IN STD_LOGIC := '0';
             rden, rdclken, wrclken: IN STD_LOGIC := '1';
             wren: IN STD_LOGIC;
             data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
             q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

signal we_p          : std_logic;
signal LogH          : std_logic;
signal reset         : std_logic;
signal data_1p       : std_logic_vector(lvds_data_in'range);
signal data_2p       : std_logic_vector(7 downto 0);
signal rdata_int     : std_logic_vector(7 downto 0);
signal waddr_p       : std_logic_vector(naddr'range);
signal waddr_f       : std_logic_vector(naddr'range);

begin
     LogH <= '1';
     reset <= not reset_n;
     waddr_f <= (0 => '0', others => '1');

     process(strobe, reset_n)
     begin
         if reset_n = '0' then
            we_p <= '1';
         elsif strobe'event and strobe = '1'  then
            if (waddr_p = waddr_f) then we_p <= '0'; end if;
         end if;
     end process;


rg1p: reg_clr
   generic map(Ndata => lvds_data_in'length)
   port map(clk   => strobe,
            ce    => LogH,
            rst_n => reset_n,
            d     => lvds_data_in,
            q     => data_1p
   );

ex_p: ni_exclude_in
  generic map(
    width    => 10,
    depth    =>  4)
  port map(
    din      => data_1p,
    sel_s    => sel_s,
    sel_p    => sel_p,
    dout     => data_2p,
    prty_bit => open);

wa_p: lpm_counter
   GENERIC map(LPM_WIDTH => waddr_p'length,
               LPM_DIRECTION => "UP")
   PORT map(
      clock  => strobe,
      cnt_en => we_p,
      aclr   => reset,
      q      => waddr_p);

      naddr <= waddr_p;

dpram: lpm_ram_dp
   GENERIC map( LPM_WIDTH => 8,
             LPM_WIDTHAD => Abits,
             LPM_INDATA => "REGISTERED",
             LPM_OUTDATA => "REGISTERED",
             LPM_RDADDRESS_CONTROL => "REGISTERED",
             LPM_WRADDRESS_CONTROL => "REGISTERED"
           )
   PORT map( rdaddress  => raddr(10 downto 0),
             wraddress  => waddr_p(10 downto 0),
             rdclock    => clk_read,
             wrclock    => strobe,
             wren       => we_p,
             data       => data_2p,
--           data       => lvds_data_in(7 downto 0),
             q          => rdata_int);

       rdata <= rdata_int;
end;