-------------------------------------------------------------------------------
-- Title      : ni_resync
-- Project    : Network Interface (NI) for the ALICE TRD TRAP2
-------------------------------------------------------------------------------
-- File       : ni_resync.vhd
-- Author     : Rolf Schneider  <rolf.schneider@kip.uni-heidelberg.de>
-- Company    : University Heidelberg - KIP
-- Last update: 2003-03-19
-- Platform   : Synopsys - v2003.03
-------------------------------------------------------------------------------
-- Description: resynchronization unit from DDR input to sync. output
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2003/03/06  1.0      schneide        Created
-------------------------------------------------------------------------------
-- last modified: 18:09 / 26 May 2003 / V.Angelov
-- additional output register stage for FPGA implementation only

library IEEE;
use IEEE.std_logic_1164.all;

----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
entity ddr_sync is
  generic(
    width : integer := 10);                              -- width of the external interface
  port(
    clk      : in  std_logic;                            -- internal clock
--    reset_n  : in  std_logic;                            -- asynchronous reset
    clk_n    : in  std_logic;                            --
    ctrl     : in  std_logic;                            -- enable
    data_in  : in  std_logic_vector(width-1 downto 0);   -- incoming DDR data sync. to strobe
    we_n     : out std_logic;                            -- outgoing data valid signal
    data_out : out std_logic_vector((2*width)-1 downto 0));  -- data output, sync. to internal clk
end ddr_sync;

----------------------------------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------------------------------
architecture v of ddr_sync is

component reg_clr is
generic(Ndata : Integer := 32);
port (  clk   : in  std_logic;
        ce    : in  std_logic;
        rst_n : in  std_logic;
        d     : in  std_logic_vector(Ndata-1 downto 0);
        q     : out std_logic_vector(Ndata-1 downto 0)
     );
end component;

  -- SIGNALS ---------------------------------------------------------------------------------------
  signal data_neg : std_logic_vector(width-1 downto 0);
  signal data1neg : std_logic_vector(width-1 downto 0);
  signal data_pos : std_logic_vector(width-1 downto 0);
--  signal clk_n    : std_logic;
  signal ctrl1    : std_logic;
  signal LogH     : std_logic;

  -- STRUCTURE -------------------------------------------------------------------------------------
begin

        LogH <= '1';
--        clk_n <= not clk;

rg_neg: reg_clr
        generic map(Ndata => width)
        port map(clk   => clk_n,
                 ce    => LogH,
                 rst_n => LogH,
                 d     => data_in,
                 q     => data_neg );

rg_np : reg_clr
        generic map(Ndata => width)
        port map(clk   => clk,
                 ce    => LogH,
                 rst_n => LogH,
                 d     => data_neg,
                 q     => data1neg );

rg1pos: reg_clr
        generic map(Ndata => width)
        port map(clk   => clk,
                 ce    => LogH,
                 rst_n => LogH,
                 d     => data_in,
                 q     => data_pos);

rg2pos: reg_clr
        generic map(Ndata => 2*width)
        port map(clk   => clk,
                 ce    => ctrl1,
                 rst_n => LogH,
                 d     => data_pos & data1neg,
                 q     => data_out );

  process(clk)
  begin
    if rising_edge(clk) then
       ctrl1 <= ctrl;
       we_n <= not ctrl1;
    end if;
  end process;

end;