library IEEE;
use IEEE.std_logic_1164.all;

entity ni2io is
  port (
    reset_n       : in  std_logic;                      -- asynchronous reset

    clk           : in  std_logic;                      -- read clock
    strobe        : in  std_logic;                      -- incoming DDR strobe signal
    lvds_data_in  : in  std_logic_vector( 9 downto 0);  -- incoming DDR data sync. to strobe

    clear         : in  std_logic;                      -- synchronous reset

    oase_mode     : in  std_logic;                      -- from the configuration
    oa_ctrl       : in  std_logic;                      -- oase mode control from the trap

    sel_s         : in  std_logic_vector( 3 downto 0);
    sel_p         : in  std_logic_vector( 3 downto 0);
    or_mask       : in  std_logic_vector( 9 downto 0);
    and_mask      : in  std_logic_vector( 9 downto 0);
    xor_mask      : in  std_logic_vector( 9 downto 0);

    naddr         : out std_logic_vector(23 downto 0);
    pcnt          : out std_logic_vector(23 downto 0);
    raddr         : in  std_logic_vector(10 downto 0);
    rdata         : out std_logic_vector(31 downto 0)   -- data output, sync. to internal clk
    );
end ni2io;

architecture a of ni2io is

component ni2dpm is
generic (Abits : Integer := 12);
  port (
    reset_n       : in  std_logic;                      -- asynchronous reset

    clk_read      : in  std_logic;                      -- read clock
    strobe        : in  std_logic;                      -- incoming DDR strobe signal
    lvds_data_in  : in  std_logic_vector( 9 downto 0);  -- incoming DDR data sync. to strobe

    oase_mode     : in  std_logic;                      -- from the configuration
    oa_ctrl       : in  std_logic;                      -- oase mode control from the trap

    sel_s         : in  std_logic_vector( 3 downto 0);
    sel_p         : in  std_logic_vector( 3 downto 0);
    or_mask       : in  std_logic_vector( 9 downto 0);
    and_mask      : in  std_logic_vector( 9 downto 0);
    xor_mask      : in  std_logic_vector( 9 downto 0);

    naddr         : out std_logic_vector(Abits-1 downto 0);
    par_cnt       : out std_logic_vector(Abits-1 downto 0);
    raddr         : in  std_logic_vector(Abits-2 downto 0);
    rdata         : out std_logic_vector(15 downto 0)   -- data output, sync. to internal clk
    );
end component;

signal rdata_pos : std_logic_vector(15 downto 0);
signal rdata_neg : std_logic_vector(15 downto 0);

signal naddr_pos : std_logic_vector(raddr'length downto 0); -- 1 bit more
signal naddr_neg : std_logic_vector(raddr'length downto 0); -- 1 bit more

signal par_cnt_pos : std_logic_vector(raddr'length downto 0); -- 1 bit more
signal par_cnt_neg : std_logic_vector(raddr'length downto 0); -- 1 bit more

signal strobe_n  : std_logic;
signal reset_clr_n : std_logic;

begin
    reset_clr_n <= not clear;
    strobe_n <= not strobe;

ni_pos:  ni2dpm
generic map(Abits => raddr'length+1)
  port map(
    reset_n       => reset_clr_n,

    clk_read      => clk,
    strobe        => strobe,
    lvds_data_in  => lvds_data_in,

    oase_mode     => oase_mode,
    oa_ctrl       => oa_ctrl,

    sel_s         => sel_s,
    sel_p         => sel_p,
    or_mask       => or_mask,
    and_mask      => and_mask,
    xor_mask      => xor_mask,

    naddr         => naddr_pos,
    par_cnt       => par_cnt_pos,
    raddr         => raddr,
    rdata         => rdata_pos
    );

ni_neg:  ni2dpm
generic map(Abits => raddr'length+1)
  port map(
    reset_n       => reset_clr_n,

    clk_read      => clk,
    strobe        => strobe_n,
    lvds_data_in  => lvds_data_in,

    oase_mode     => oase_mode,
    oa_ctrl       => oa_ctrl,

    sel_s         => sel_s,
    sel_p         => sel_p,
    or_mask       => or_mask,
    and_mask      => and_mask,
    xor_mask      => xor_mask,

    naddr         => naddr_neg,
    par_cnt       => par_cnt_neg,
    raddr         => raddr,
    rdata         => rdata_neg
    );

    rdata <= rdata_pos(15 downto 8) & rdata_neg(15 downto 8) & rdata_pos(7 downto 0) & rdata_neg(7 downto 0);
    naddr <= naddr_pos & naddr_neg;
    pcnt  <= par_cnt_pos & par_cnt_neg;

end;