library IEEE;
use IEEE.std_logic_1164.all;

LIBRARY lpm;
USE lpm.lpm_components.all;


entity ni2dpm is
generic (Abits : Integer := 12);
  port (
    reset_n       : in  std_logic;                      -- asynchronous reset

    clk_read      : in  std_logic;                      -- read clock
    strobe        : in  std_logic;                      -- incoming DDR strobe signal
    lvds_data_in  : in  std_logic_vector( 9 downto 0);  -- incoming DDR data sync. to strobe

    oase_mode     : in  std_logic;                      -- from the configuration
    oa_ctrl       : in  std_logic;                      -- oase mode control from the trap

    sel_s         : in  std_logic_vector( 3 downto 0);
    sel_p         : in  std_logic_vector( 3 downto 0);
    or_mask       : in  std_logic_vector( 9 downto 0);
    and_mask      : in  std_logic_vector( 9 downto 0);
    xor_mask      : in  std_logic_vector( 9 downto 0);

    naddr         : out std_logic_vector(Abits-1 downto 0);
    par_cnt       : out std_logic_vector(Abits-1 downto 0);
    raddr         : in  std_logic_vector(Abits-2 downto 0);
    rdata         : out std_logic_vector(15 downto 0)   -- data output, sync. to internal clk
    );
end ni2dpm;

architecture a of ni2dpm is

component ni_exclude_in is
  generic (
    width    : integer := 10;                           -- word width incl. spare & parity bit
    depth    : integer := 4);                           -- position selection word width
  port (
    din      : in  std_logic_vector(width-1 downto 0);  -- data in
    sel_s    : in  std_logic_vector(depth-1 downto 0);  -- the spare bit position,
                                                        -- will be selected out first ("1001")
    sel_p    : in  std_logic_vector(depth-1 downto 0);  -- the parity bit position,
                                                        -- will be selected out next ("1000")
    dout     : out std_logic_vector(width-3 downto 0);  -- data out
    prty_bit : out std_logic);                          -- parity bit output
end component;

component reg_clr is
generic(Ndata : Integer := 32);
port (  clk   : in  std_logic;
        ce    : in  std_logic;
        rst_n : in  std_logic;
        d     : in  std_logic_vector(Ndata-1 downto 0);
        q     : out std_logic_vector(Ndata-1 downto 0)
     );
end component;

component counter is
GENERIC (N : Integer := 10);
    port (
           clk                        : in    std_logic;
           clk_en                     : in    std_logic;
           sclr                       : in    std_logic;
           aclr                       : in    std_logic;
           Q                          : out   std_logic_vector(N-1 downto 0)
           );
end component;

component ni_dpram
        PORT
        (
                data            : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0);
                wren            : IN STD_LOGIC  := '1';
                wraddress       : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                rdaddress       : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
                wrclock         : IN STD_LOGIC ;
                rdclock         : IN STD_LOGIC ;
                wr_aclr         : IN STD_LOGIC  := '0';
                q               : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
        );
end component;

signal oa_ctrl_s     : std_logic;
signal we_eff        : std_logic;
signal we_p          : std_logic;
signal we_p_r        : std_logic;
signal LogH          : std_logic;
signal reset         : std_logic;
signal prty_bit      : std_logic;
signal par_en        : std_logic;
signal data_1p       : std_logic_vector(lvds_data_in'range);
signal data_1p_m     : std_logic_vector(lvds_data_in'range);
signal data_2p       : std_logic_vector(7 downto 0);
signal waddr_p       : std_logic_vector(naddr'range);
signal waddr_f       : std_logic_vector(naddr'range);
signal waddr_f1      : std_logic_vector(naddr'high-1 downto 0);

begin
     LogH <= '1';
     reset <= not reset_n;
     waddr_f1 <= (others => '1');
     waddr_f <= '0' & waddr_f1;

     process(strobe, reset_n)
     begin
         if reset_n = '0' then
            we_p      <= '0';
            we_p_r    <= '1';
         elsif strobe'event and strobe = '1'  then
            if (waddr_p = waddr_f) then we_p   <= '0';
                                        we_p_r <= '0';
                                   else we_p <= we_p_r;
            end if;
         end if;
     end process;

     process(strobe)
     begin
         if strobe'event and strobe = '1'  then
            oa_ctrl_s <= oa_ctrl;
         end if;
     end process;

    we_eff <= we_p and ( (oase_mode and not oa_ctrl_s) or not oase_mode );


rg1p: reg_clr
   generic map(Ndata => lvds_data_in'length)
   port map(clk   => strobe,
            ce    => LogH,
            rst_n => reset_n,
            d     => lvds_data_in,
            q     => data_1p
   );


    data_1p_m <= ( (data_1p xor xor_mask) and and_mask) or or_mask;

ex_p: ni_exclude_in
  generic map(
    width    => 10,
    depth    =>  4)
  port map(
    din      => data_1p_m,
    sel_s    => sel_s,
    sel_p    => sel_p,
    dout     => data_2p,
    prty_bit => prty_bit);

--wa_p: lpm_counter
--   GENERIC map(LPM_WIDTH => waddr_p'length,
--               LPM_DIRECTION => "UP")
--   PORT map(
--      clock  => strobe,
--      cnt_en => we_eff,
--      aclr   => reset,
--      q      => waddr_p);
--
    par_en <= we_eff and (prty_bit xor data_2p(7) xor data_2p(6) xor data_2p(5) xor data_2p(4)
                                   xor data_2p(3) xor data_2p(2) xor data_2p(1) xor data_2p(0) );

parc: counter
      GENERIC map(N => par_cnt'length)
      port map(
           clk                        => strobe,
           clk_en                     => par_en,
           sclr                       => '0',
           aclr                       => reset,
           Q                          => par_cnt
           );

      naddr <= waddr_p;

wa_p: counter
      GENERIC map(N => waddr_p'length)
      port map(
           clk                        => strobe,
           clk_en                     => we_eff,
           sclr                       => '0',
           aclr                       => reset,
           Q                          => waddr_p
           );

dpram: ni_dpram
        PORT map
        (
                data            => data_2p,
                wren            => we_eff,
                wraddress       => waddr_p,
                rdaddress       => raddr,
                wrclock         => strobe,
                rdclock         => clk_read,
                wr_aclr         => reset,
                q               => rdata
        );

end;