-- not completely ready - switching must be done when the packet is out!

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- switch

--  0       only the local scsn slave
--  1       the local and the other fpga slave
--  2       the local, the other fpga slave and the 4 traps for ni test
--  3       the local and the DUT
--  4       the local, the DUT and the 4 traps for ni test
--  5       the local and the WT
--  6       the local and the 4 traps for ni test
--  7       the local, the other fpga and the WT

-- In cases without DUT in the chain, bit3 of the switch determins
-- the static value to SCSN0 input of DUT/WT

-- switch bit 4 is wafer tester DUT input invert
-- switch bit 5 is wafer tester DUT output invert
-- switch bit 6 is DUT inputs crossing
-- switch bit 7 is DUT outputs crossing

entity scsn_switch is
port(
           sw_sel                     : in    std_logic_vector( 7 downto 0);
        -- the trap in the socket
           DUT_SER0_IN                : in    std_logic;
           DUT_SER0_OUT               : out   std_logic;

           DUT_SER1_IN                : in    std_logic;
           DUT_SER1_OUT               : out   std_logic;

        -- the trap in the wafer tester
           WT_SER0_IN                 : in    std_logic;
           WT_SER0_OUT                : out   std_logic;

           WT_SER1_IN                 : in    std_logic;
           WT_SER1_OUT                : out   std_logic; -- + and - swapped on wafer board

        -- the 4 traps
           NI_SER0_IN                 : in    std_logic; -- + and - swapped on board!
           NI_SER0_OUT                : out   std_logic;

           NI_SER1_IN                 : in    std_logic;
           NI_SER1_OUT                : out   std_logic;

        -- next FPGA
           AD_SER0_IN                 : in    std_logic;
           AD_SER0_OUT                : out   std_logic;

           AD_SER1_IN                 : in    std_logic;
           AD_SER1_OUT                : out   std_logic;

        -- internal slave
           SER0_OUT                   : in    std_logic;

           SER1_IN                    : out   std_logic;
--           SER1_OUT                   : in    std_logic;

        -- Uplink to PC
           PC_SER0_OUT                : out   std_logic;

           PC_SER1_IN                 : in    std_logic);
end scsn_switch;

architecture a of scsn_switch is

signal WT_out_inv       : std_logic;
signal WT_in_inv        : std_logic;
signal DUT_SER0_OUT_cr  : std_logic;
signal DUT_SER1_OUT_cr  : std_logic;
signal DUT_SER0_IN_cr   : std_logic;
signal DUT_SER1_IN_cr   : std_logic;
signal WT_SER0_OUT_cr   : std_logic;
signal WT_SER1_OUT_cr   : std_logic;
signal WT_SER0_IN_cr    : std_logic;
signal WT_SER1_IN_cr    : std_logic;

begin

    WT_out_inv <= sw_sel(5);
    WT_in_inv  <= sw_sel(4);

    process(sw_sel, DUT_SER0_IN_cr, DUT_SER1_IN_cr, NI_SER0_IN, NI_SER1_IN, AD_SER0_IN, AD_SER1_IN,
            SER0_OUT, PC_SER1_IN, WT_SER0_IN_cr, WT_SER1_IN_cr)
    begin
        -- default values
           DUT_SER0_OUT_cr <= sw_sel(3);
           DUT_SER1_OUT_cr <= '0';
           WT_SER0_OUT_cr  <= sw_sel(3);
           WT_SER1_OUT_cr  <= '1'; -- + and - swapped on wafer board
           NI_SER0_OUT  <= '0';
           NI_SER1_OUT  <= '0';
           AD_SER0_OUT  <= '0';
           AD_SER1_OUT  <= '0';
           SER1_IN      <= '0';
        case sw_sel(2 downto 0) is
        -- only the local slave
        when "000"  =>
                        SER1_IN     <= PC_SER1_IN;
                        PC_SER0_OUT <= SER0_OUT;
        -- the two FPGAs
        when "001"  =>  SER1_IN     <= AD_SER1_IN;  -- ring 1
                        AD_SER1_OUT <= PC_SER1_IN;

                        AD_SER0_OUT <= SER0_OUT;    -- ring 0
                        PC_SER0_OUT <= AD_SER0_IN;

        when "010"  =>  SER1_IN     <= AD_SER1_IN;  -- ring 1
                        AD_SER1_OUT <= NI_SER1_IN;
                        NI_SER1_OUT <= PC_SER1_IN;

                        AD_SER0_OUT <= SER0_OUT;    -- ring 0
                        NI_SER0_OUT <= AD_SER0_IN;
                        PC_SER0_OUT <= not NI_SER0_IN;  -- + and - swapped on board!

        when "011"  =>  SER1_IN      <= DUT_SER1_IN_cr;  -- ring 1
                        DUT_SER1_OUT_cr <= PC_SER1_IN;

                        DUT_SER0_OUT_cr <= SER0_OUT;    -- ring 0
                        PC_SER0_OUT  <= DUT_SER0_IN_cr;

        when "101"  =>  SER1_IN      <= WT_SER1_IN_cr;  -- ring 1
                        WT_SER1_OUT_cr  <= PC_SER1_IN; -- + and - swapped on wafer board

                        WT_SER0_OUT_cr  <= SER0_OUT;    -- ring 0
                        PC_SER0_OUT  <= WT_SER0_IN_cr;

        when "100"  =>  SER1_IN      <= DUT_SER1_IN_cr;  -- ring 1
                        DUT_SER1_OUT_cr <= NI_SER1_IN;
                        NI_SER1_OUT  <= PC_SER1_IN;

                        DUT_SER0_OUT_cr <= SER0_OUT;    -- ring 0
                        NI_SER0_OUT  <= DUT_SER0_IN_cr;
                        PC_SER0_OUT  <= not NI_SER0_IN; -- + and - swapped on board!

        when "110"  =>  SER1_IN      <= NI_SER1_IN;  -- ring 1
                        NI_SER1_OUT  <= PC_SER1_IN;

                        NI_SER0_OUT  <= SER0_OUT;    -- ring 0
                        PC_SER0_OUT  <= not NI_SER0_IN; -- + and - swapped on board!

        when "111"  =>  SER1_IN      <= AD_SER1_IN;  -- ring 1
                        AD_SER1_OUT  <= WT_SER1_IN_cr;  -- ring 1
                        WT_SER1_OUT_cr  <= PC_SER1_IN; -- + and - swapped on wafer board

                        AD_SER0_OUT  <= SER0_OUT;    -- ring 0
                        WT_SER0_OUT_cr  <= AD_SER0_IN;    -- ring 0
                        PC_SER0_OUT  <= WT_SER0_IN_cr;

        when others =>  PC_SER0_OUT  <= '-';
        end case;
    end process;

    process(sw_sel, DUT_SER0_IN,     DUT_SER1_IN,     WT_SER0_IN,     WT_SER1_IN,
                    DUT_SER0_OUT_cr, DUT_SER1_OUT_cr, WT_SER0_OUT_cr, WT_SER1_OUT_cr)
    begin
        if sw_sel(6)='1' then
            DUT_SER0_IN_cr <= DUT_SER1_IN;
            DUT_SER1_IN_cr <= DUT_SER0_IN;
            WT_SER0_IN_cr  <= WT_SER1_IN xor WT_out_inv;
            WT_SER1_IN_cr  <= WT_SER0_IN;
        else
            DUT_SER0_IN_cr <= DUT_SER0_IN;
            DUT_SER1_IN_cr <= DUT_SER1_IN;
            WT_SER0_IN_cr  <= WT_SER0_IN;
            WT_SER1_IN_cr  <= WT_SER1_IN xor WT_out_inv;
        end if;
        if sw_sel(7)='1' then
            DUT_SER0_OUT   <= DUT_SER1_OUT_cr;
            DUT_SER1_OUT   <= DUT_SER0_OUT_cr;
            WT_SER0_OUT    <= WT_SER1_OUT_cr;
            WT_SER1_OUT    <= WT_SER0_OUT_cr xor WT_in_inv;
        else
            DUT_SER0_OUT   <= DUT_SER0_OUT_cr;
            DUT_SER1_OUT   <= DUT_SER1_OUT_cr;
            WT_SER0_OUT    <= WT_SER0_OUT_cr;
            WT_SER1_OUT    <= WT_SER1_OUT_cr xor WT_in_inv;
        end if;
    end process;

end;