LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

-- Pre-trigger input decoder
-- last modified: 17:43 / 27/Apr/2004 / V.Angelov
-- all outputs are active for exact 1 clock

-- The pretrigger functions are
--  0   nothing
--  1   pretrigger
--  2   clear
--  3   reserved
--  4   go to low power mode
--  5   go to acquisition mode
--  6   go to test mode
--  7   start test pulse in PASA

ENTITY pre_dec IS
PORT(
     CLK             : IN  STD_LOGIC; -- fast clock 120MHz
     RSTn            : IN  STD_LOGIC; -- global reset (active low)
     PRETRIGG        : IN  STD_LOGIC; -- pre-trigger input
     -- decoded outputs
     PTRGG           : OUT STD_LOGIC; -- pre-trigger detected
     CLEAR           : OUT STD_LOGIC; -- clear detected
     RESRV           : OUT STD_LOGIC; -- reserve function
     FUNC            : OUT STD_LOGIC_VECTOR(3 downto 0); -- global functions 0..3
     UNKNOWN         : OUT STD_LOGIC  -- reserve function
        );
END pre_dec;

architecture a of pre_dec is

CONSTANT L_PTR : Integer :=  1; -- 2-3
CONSTANT L_CLR : Integer :=  4; -- 5-6
CONSTANT L_RES : Integer :=  7; -- 8-9??
CONSTANT L_FUN : Integer := 10; -- global functions;
CONSTANT L_ERR : Integer := 13; -- error

type sm is (idle, rec1, rec_ptr, rec_clr, rec_res, rec_fun1, rec_fun2, rec_fun3, rec_func, ends);
signal rec_sm : sm;

signal counter : Integer range 0 to 15;

signal ptrf, fc : STD_LOGIC_VECTOR(1 downto 0);

begin
        process(CLK, RSTn)
        begin
                if RSTn='0' then
                                     rec_sm  <= idle;
                                     counter <= 0;
                                     ptrf    <= "00";
                                     fc      <= "00";
                                     PTRGG   <= '0';
                                     CLEAR   <= '0';
                                     RESRV   <= '0';
                                     UNKNOWN <= '0';

                elsif clk'event and clk='1' then
                        ptrf <=  ptrf(0) & PRETRIGG;
                        PTRGG   <= '0';
                        CLEAR   <= '0';
                        RESRV   <= '0';
                        UNKNOWN <= '0';
                        case rec_sm is
                        when idle => counter <=  0;
                                     if ptrf="11" then rec_sm <= rec1; end if;

                        when rec1 =>
                                         if    counter = L_ERR then rec_sm <= ends;
                                         else
                                           if ptrf="00" then
                                             if    counter >= L_FUN then rec_sm <= rec_fun1; counter <= 0;
                                             elsif counter >= L_RES then rec_sm <= rec_res ; RESRV <= '1';
                                             elsif counter >= L_CLR then rec_sm <= rec_clr ; CLEAR <= '1';
                                             elsif counter >= L_PTR then rec_sm <= rec_ptr ; counter <= 0; PTRGG <= '1';
                                             else UNKNOWN <= '1'; rec_sm <= idle;
                                             end if;
                                           else counter <= counter + 1; end if;
                                         end if;

                        when rec_ptr => rec_sm <= ends;

                        when rec_clr => rec_sm <= ends;

                        when rec_res => rec_sm <= ends;

                        when rec_fun1=> counter<=counter+1; if counter=2 then fc(1)<=ptrf(0); rec_sm <= rec_fun2; end if;

                        when rec_fun2=> counter<=counter+1; if counter=5 then fc(0)<=ptrf(0); rec_sm <= rec_func; end if;

                        when rec_func=> counter<=counter+1;
                                        if counter=9 then
                                            if ptrf="00" then rec_sm <= rec_fun3;
                                                         else UNKNOWN <= '1'; rec_sm <= idle;

                                            end if;
                                        end if;

                        when rec_fun3=> rec_sm <= ends;

                        when ends    => if ptrf="00" then rec_sm <= idle; else UNKNOWN <= '1'; end if;

                        when others =>  rec_sm <= idle;
                        end case;
                end if;
        end process;

        process(CLK, RSTn)
        begin
           if RSTn = '0' then
               FUNC <= (others => '0');
           elsif clk'event and clk='1' then
               if rec_sm=rec_fun3 then
                       case fc is
                               when "00"   => FUNC <= "0001";
                               when "01"   => FUNC <= "0010";
                               when "10"   => FUNC <= "0100";
                               when others => FUNC <= "1000";
                       end case;
               else FUNC <= (others => '0'); end if;
           end if;
        end process;
end;