LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

LIBRARY lpm;
USE lpm.lpm_components.all;


-- Pretrigger decoder with counters for all possible outputs (see below).
-- The counters will wrap if more than 15 decoded commands from the same type come.
-- last modified: 13:53 / 02/Jun/2004 / V.Angelov

-- The pretrigger functions are
--  0   nothing
--  1   pretrigger
--  2   clear
--  3   reserved
--  4   go to low power mode
--  5   go to acquisition mode
--  6   go to test mode
--  7   start test pulse in PASA

entity pre_counter is
    port (
        clk             : in  std_logic;    -- 120 MHz clock
        reset_n         : in  std_logic;    -- async reset
        sreset          : in  std_logic;    -- sync reset

        dout            : out std_logic_vector(31 downto 0);
        --  31..28  27..24  23..20  19..16  15..12  11..8   7..4    3..0
        --  func7   func6   func5   func4   func3   func2   func1   unknown

        pre_in          : in  std_logic     -- pretrigger input
        );
end pre_counter;

architecture a of pre_counter is

component counter is
GENERIC (N : Integer := 10);
    port (
           clk                        : in    std_logic;
           clk_en                     : in    std_logic;
           sclr                       : in    std_logic;
           aclr                       : in    std_logic;
           Q                          : out   std_logic_vector(N-1 downto 0)
           );
end component;

COMPONENT lpm_counter
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_MODULUS: NATURAL := 0;
      LPM_DIRECTION: STRING := "UNUSED";
      LPM_AVALUE: STRING := "UNUSED";
      LPM_SVALUE: STRING := "UNUSED";
      LPM_PVALUE: STRING := "UNUSED";
      LPM_TYPE: STRING := "LPM_COUNTER";
      LPM_HINT : STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
      clock: IN STD_LOGIC;
      clk_en, cnt_en, updown: IN STD_LOGIC := '1';
      sload, sset, sclr, aload, aset, aclr, cin: IN STD_LOGIC := '0';
      cout: OUT STD_LOGIC;
      --eq: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

COMPONENT pre_dec IS
PORT(
     CLK             : IN  STD_LOGIC; -- fast clock 120MHz
     RSTn            : IN  STD_LOGIC; -- global reset (active low)
     PRETRIGG        : IN  STD_LOGIC; -- pre-trigger input
     -- decoded outputs
     PTRGG           : OUT STD_LOGIC; -- pre-trigger detected
     CLEAR           : OUT STD_LOGIC; -- clear detected
     RESRV           : OUT STD_LOGIC; -- reserve function
     FUNC            : OUT STD_LOGIC_VECTOR(3 downto 0); -- global functions 0..3
     UNKNOWN         : OUT STD_LOGIC  -- reserve function
        );
END COMPONENT;

signal  reset           : std_logic;
signal  f               : std_logic_vector( 7 downto 0);

begin
    reset <= not reset_n;

dec: pre_dec
     PORT map(
     CLK             => CLK,
     RSTn            => reset_n,
     PRETRIGG        => pre_in,
     -- decoded outputs
     PTRGG           => f(1),
     CLEAR           => f(2),
     RESRV           => f(3),
     FUNC            => f(7 downto 4),
     UNKNOWN         => f(0)
        );

cnt: for i in 0 to 7 generate
--cnt_i: lpm_counter
cnt_i: counter
--       GENERIC map(LPM_WIDTH => 4,
       GENERIC map(N => 4)
--                   LPM_DIRECTION => "UP")
       PORT map(
--                   clock  => clk,
                   clk    => clk,
                   clk_en => f(i),
                   sclr   => sreset,
                   aclr   => reset,
                   q      => dout(i*4+3 downto i*4)
                );

    end generate;
end;