LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity irq_rst is
    port (
        clk             : in  std_logic;
        reset_n         : in  std_logic;
        irq_start       : in  std_logic;
        rst_start       : in  std_logic;
        irq_n           : out std_logic;
        rst_n           : out std_logic);
end irq_rst;

architecture a of irq_rst is

signal  cnt_irq         : std_logic_vector( 1 downto 0);
signal  irq_full        : std_logic_vector(cnt_irq'range);
signal  cnt_rst         : std_logic_vector( 8 downto 0);
signal  rst_full        : std_logic_vector(cnt_rst'range);

type irq_sm_type is (idle, irq, finish);
signal irq_sm : irq_sm_type;

begin

    rst_full <= (others => '1');

    process(clk, reset_n)
    begin
        if reset_n = '0' then
            cnt_rst <= (others => '0');
        elsif clk'event and clk= '1' then
            if rst_start = '1' then cnt_rst <= (others => '0');
            elsif cnt_rst /= rst_full then cnt_rst <= cnt_rst + 1; end if;
        end if;
    end process;
    rst_n <= cnt_rst(cnt_rst'high-1);

    irq_full <= (others => '1');
    process(clk, reset_n)
    begin
        if reset_n = '0' then
            irq_sm <= idle;
            cnt_irq <= (others => '0');
            irq_n <= '1';
        elsif clk'event and clk= '1'  then
            cnt_irq <= (others => '0');
            irq_n <= '1';
            case irq_sm is
                when idle   =>  if irq_start = '1' then irq_sm <= irq; end if;
                when irq    =>
                                cnt_irq <= cnt_irq + 1;
                                irq_n <= '0';
                                if cnt_irq = irq_full then irq_sm <= finish;
                                end if;
                when finish =>  if irq_start = '0' then irq_sm <= idle; end if;
                when others =>  irq_sm <= idle;
            end case;
        end if;
    end process;

end;