LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- IO space - no overlap with the TRAP chip

-- clock and pretrigger module      0x4000  0x40FF
-- jtag master ni up                0x4100  0x41FF
-- jtag master ni dn                0x4200  0x42FF
-- jtag master dut                  0x4300  0x43FF
-- general config & status          0x4400  0x44FF
-- ni2io read only memory           0x4800  0x4FFF

entity gio_devices is
    port(
        clk             : in  std_logic;
        nif_dout        : in  std_logic_vector(31 downto 0);
        gen_dout        : in  std_logic_vector(31 downto 0);
        cp_dout         : in  std_logic_vector(31 downto 0);
        jtg_ni_up_dout  : in  std_logic_vector(31 downto 0);
        jtg_ni_dn_dout  : in  std_logic_vector(31 downto 0);
        jtg_dut_dout    : in  std_logic_vector(31 downto 0);

        bus_addr        : in  std_logic_vector(15 downto 8); -- address to read/write
        bus_req         : in  std_logic; -- bus request
        bus_ack         : out std_logic;

        -- request and address decoded
        ce_nif          : out std_logic; -- ni fifo read only
        ce_gen          : out std_logic; -- general config
        ce_cp           : out std_logic; -- clock and pretrigger
        ce_ni_jtg_up    : out std_logic; -- jtag
        ce_ni_jtg_dn    : out std_logic; -- jtag
        ce_dut_jtg      : out std_logic; -- jtag

        bus_dout        : out std_logic_vector(31 downto 0)
        );
end gio_devices;

architecture a of gio_devices is

signal sel          : std_logic_vector(5 downto 0);
signal rdy          : std_logic_vector(3 downto 0);
signal ce_nif_i     : std_logic; -- ni fifo read only
signal ce_gen_i     : std_logic; -- general config
signal ce_cp_i      : std_logic; -- clock and pretrigger
signal ce_ni_jtg_up_i  : std_logic; -- jtag
signal ce_ni_jtg_dn_i  : std_logic; -- jtag
signal ce_dut_jtg_i : std_logic; -- jtag

signal bus_dout_i   : std_logic_vector(bus_dout'range);

begin

    -- fifo read only
    ce_nif_i        <= bus_req when bus_addr(15 downto 11) = "01001"    else '0'; -- 0x4800..0x4FFF
    ce_gen_i        <= bus_req when bus_addr(15 downto  8) = "01000100" else '0'; -- 0x4400..0x44FF
    ce_dut_jtg_i    <= bus_req when bus_addr(15 downto  8) = "01000011" else '0'; -- 0x4300..0x43FF
    ce_ni_jtg_dn_i  <= bus_req when bus_addr(15 downto  8) = "01000010" else '0'; -- 0x4200..0x42FF
    ce_ni_jtg_up_i  <= bus_req when bus_addr(15 downto  8) = "01000001" else '0'; -- 0x4100..0x41FF
    ce_cp_i         <= bus_req when bus_addr(15 downto  8) = "01000000" else '0'; -- 0x4000..0x40FF

    with sel select

    bus_dout_i <=
                nif_dout        when "100000",
                gen_dout        when "010000",
                jtg_dut_dout    when "001000",
                jtg_ni_dn_dout  when "000100",
                jtg_ni_up_dout  when "000010",
                cp_dout         when "000001",
                (others => '0') when "000000",
                (others => '-') when others;

    process(clk)
    begin
        if clk'event and clk= '1'  then
            sel <= ce_nif_i & ce_gen_i & ce_dut_jtg_i & ce_ni_jtg_dn_i & ce_ni_jtg_up_i & ce_cp_i;
            rdy <= rdy(rdy'high-1 downto 0) & bus_req;
            ce_nif <= ce_nif_i;
            ce_gen <= ce_gen_i;
            ce_cp  <= ce_cp_i;
            ce_dut_jtg <= ce_dut_jtg_i;
            ce_ni_jtg_up  <= ce_ni_jtg_up_i;
            ce_ni_jtg_dn  <= ce_ni_jtg_dn_i;
            if rdy(rdy'high)='1' then bus_dout <= bus_dout_i; end if;
        end if;
    end process;
    bus_ack <= rdy(rdy'high);
end;