LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

LIBRARY lpm;
USE lpm.lpm_components.all;

-- 5 counters x 8 bits. The internal counter starts after ce and
-- resets and enables the 5 counters until count 200 reached.

entity clk_counter is
    port (
        clk             : in  std_logic;
        reset_n         : in  std_logic;

        ce              : in  std_logic;

        dout            : out std_logic_vector(31 downto 0);
        -- Bits     31..24  23..16  15..8   7..0
        -- counter     3       2       1      0
        strb_dout       : out std_logic_vector( 7 downto 0);

        strb_clk        : in  std_logic;
        clk_in          : in  std_logic_vector( 3 downto 0)
        );
end clk_counter;

architecture a of clk_counter is

component counter is
GENERIC (N : Integer := 10);
    port (
           clk                        : in    std_logic;
           clk_en                     : in    std_logic;
           aclr                       : in    std_logic;
           sclr                       : in    std_logic;
           Q                          : out   std_logic_vector(N-1 downto 0)
           );
end component;

COMPONENT lpm_counter
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_MODULUS: NATURAL := 0;
      LPM_DIRECTION: STRING := "UNUSED";
      LPM_AVALUE: STRING := "UNUSED";
      LPM_SVALUE: STRING := "UNUSED";
      LPM_PVALUE: STRING := "UNUSED";
      LPM_TYPE: STRING := "LPM_COUNTER";
      LPM_HINT : STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
      clock: IN STD_LOGIC;
      clk_en, cnt_en, updown: IN STD_LOGIC := '1';
      sload, sset, sclr, aload, aset, aclr, cin: IN STD_LOGIC := '0';
      cout: OUT STD_LOGIC;
      --eq: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

signal  count_en_s      : std_logic;
signal  ce_s            : std_logic;
signal  count_en_c      : std_logic;
signal  restart_s       : std_logic;
signal  reset_cnt       : std_logic;
signal  count_rdy       : std_logic;
signal  count_en        : std_logic_vector( 3 downto 0);
signal  qc              : std_logic_vector( 7 downto 0);

type sm_type is (idle, clear, start, count);

signal sm : sm_type;

begin

    process(clk, reset_n)
    begin
        if reset_n = '0' then
            sm        <= idle;
            count_rdy <='0';
            restart_s <='0';
            reset_cnt <='1';
            count_en_c <='0';
            ce_s      <= '0';
        elsif clk'event and clk= '1'  then
            ce_s      <= ce;
            restart_s <= ce_s and not ce;
            reset_cnt <='0';
            count_en_c <='0';
            if qc=conv_std_logic_vector(199, qc'length) then count_rdy <='1';
                                                        else count_rdy <='0'; end if;
            case sm is
            when idle   => if restart_s='1' then sm <= clear; reset_cnt <='1'; end if;
            when clear  => sm <= count;
            when count  => count_en_c <= '1';
                           if count_rdy='1' then sm <= idle; end if;
            when others => sm <= idle;
            end case;
        end if;
    end process;

--cnt_c: lpm_counter
cnt_c: counter
--       GENERIC map(LPM_WIDTH => 8,
       GENERIC map(N => 8)
--                   LPM_DIRECTION => "UP")
       PORT map(
--                   clock  => clk,
                   clk    => clk,
                   clk_en => count_en_c,
                   aclr   => reset_cnt,
                   sclr   => '0',
                   q      => qc);


cnt: for i in 0 to 3 generate

sync:
    process(clk_in(i), reset_cnt)
    begin
        if reset_cnt = '1' then
             count_en(i) <= '0';
        elsif clk_in(i)'event and clk_in(i)= '1'  then
             count_en(i) <= count_en_c;
        end if;
    end process;

--cnt_i: lpm_counter
cnt_i: counter
--       GENERIC map(LPM_WIDTH => 8,
       GENERIC map(N => 8)
--                   LPM_DIRECTION => "UP")
       PORT map(
--                   clock  => clk_in(i),
                   clk    => clk_in(i),
                   clk_en => count_en(i),
                   aclr   => reset_cnt,
                   sclr   => '0',
                   q      => dout(i*8+7 downto i*8)
                );

    end generate;

    process(strb_clk, reset_cnt)
    begin
        if reset_cnt = '1' then
             count_en_s <= '0';
        elsif strb_clk'event and strb_clk= '1'  then
             count_en_s <= count_en_c;
        end if;
    end process;

cnt_s: counter
       GENERIC map(N => 8)
       PORT map(
                   clk    => strb_clk,
                   clk_en => count_en_s,
                   aclr   => reset_cnt,
                   sclr   => '0',
                   q      => strb_dout
                );


end;