LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- IO space - no overlap with the TRAP chip

-- sdac 1                           0x5000  0x503F
-- V shut down                      0x5080  0x50BF
-- digital poti                     0x50C0  0x50FF
-- sdac 2                           0x5100  0x51FF
-- dds                              0x5200  0x52FF
-- sc adc                           0x5300  0x53FF
-- psply adc                        0x5400  0x54FF
-- pasa dac                         0x5500  0x55FF

-- pasa adc                         0x5800  0x5FFF

entity gio_devices_adc is
    port(
        clk             : in  std_logic;
        rdata_sc_adc    : in  std_logic_vector(31 downto 0);
        rdata_psply_adc : in  std_logic_vector(31 downto 0);
        rdata_dds       : in  std_logic_vector(31 downto 0);
        rdata_pasa_adc  : in  std_logic_vector(31 downto 0);
        rdata_pasa_dac  : in  std_logic_vector(31 downto 0);

        bus_addr        : in  std_logic_vector(15 downto 6); -- address to read/write
        bus_req         : in  std_logic; -- bus request
        bus_ack         : out std_logic;

        ce_1sdac        : out std_logic;
        ce_shutdn       : out std_logic;
        ce_2sdac        : out std_logic;
        ce_digpot       : out std_logic;
        ce_dds          : out std_logic;
        ce_sc_adc       : out std_logic;
        ce_psply_adc    : out std_logic;
        ce_pasa_dac     : out std_logic;
        ce_wtnip4       : out std_logic;
        ce_pasa_adc     : out std_logic;

        bus_dout        : out std_logic_vector(31 downto 0)
        );
end gio_devices_adc;

architecture a of gio_devices_adc is

signal sel            : std_logic_vector(4 downto 0);
signal rdy            : std_logic_vector(3 downto 0);
signal ce_pasa_adc_i  : std_logic;
signal ce_1sdac_i     : std_logic;
signal ce_shutdn_i    : std_logic;
signal ce_2sdac_i     : std_logic;
signal ce_dds_i       : std_logic;
signal ce_digpot_i    : std_logic;
signal ce_sc_adc_i    : std_logic;
signal ce_psply_adc_i : std_logic;
signal ce_pasa_dac_i  : std_logic;
signal ce_wtnip4_i    : std_logic;

begin
    ce_pasa_adc_i  <= bus_req when bus_addr(15 downto 11) = "01011"    else '0'; -- 0x5800..0x5FFF

    ce_wtnip4_i    <= bus_req when bus_addr(15 downto 12) = "0110"     else '0'; -- 0x6000..0x6FFF

    ce_1sdac_i     <= bus_req when bus_addr(15 downto  6) = "0101000000" else '0'; -- 0x5000..0x503F
    ce_shutdn_i    <= bus_req when bus_addr(15 downto  6) = "0101000010" else '0'; -- 0x5080..0x50BF
    ce_digpot_i    <= bus_req when bus_addr(15 downto  6) = "0101000011" else '0'; -- 0x50C0..0x50FF
    ce_2sdac_i     <= bus_req when bus_addr(15 downto  8) = "01010001" else '0'; -- 0x5100..0x51FF
    ce_dds_i       <= bus_req when bus_addr(15 downto  8) = "01010010" else '0'; -- 0x5200..0x52FF
    ce_sc_adc_i    <= bus_req when bus_addr(15 downto  8) = "01010011" else '0'; -- 0x5300..0x53FF
    ce_psply_adc_i <= bus_req when bus_addr(15 downto  8) = "01010100" else '0'; -- 0x5400..0x54FF
    ce_pasa_dac_i  <= bus_req when bus_addr(15 downto  8) = "01010101" else '0'; -- 0x5500..0x55FF

    with sel select

    bus_dout <=
                rdata_pasa_adc  when "10000",
                rdata_dds       when "01000",
                rdata_sc_adc    when "00100",
                rdata_psply_adc when "00010",
                rdata_pasa_dac  when "00001",
                (others => '-') when others;

    process(clk)
    begin
        if clk'event and clk= '1'  then
            sel <= ce_pasa_adc_i & ce_dds_i & ce_sc_adc_i & ce_psply_adc_i & (ce_pasa_dac_i or ce_wtnip4_i);
            rdy <= rdy(rdy'high-1 downto 0) & bus_req;
            ce_1sdac     <= ce_1sdac_i;
            ce_shutdn    <= ce_shutdn_i;
            ce_2sdac     <= ce_2sdac_i;
            ce_digpot    <= ce_digpot_i;
            ce_dds       <= ce_dds_i;
            ce_sc_adc    <= ce_sc_adc_i;
            ce_psply_adc <= ce_psply_adc_i;
            ce_pasa_dac  <= ce_pasa_dac_i;
            ce_pasa_adc  <= ce_pasa_adc_i;
            ce_wtnip4    <= ce_wtnip4_i;
        end if;
    end process;
    bus_ack <= rdy(rdy'high);
end;