LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dig_cntrl2 IS
GENERIC (Ndac : Integer := 8; Nch : Integer := 18); -- Ndac < Nch !!!
PORT(
		CLK		: IN  STD_LOGIC; -- serial clock
		DIN		: IN  STD_LOGIC; -- serial data
		STR		: IN  STD_LOGIC; -- strobe, trigger the pulser
		DAC		: OUT STD_LOGIC_VECTOR( 7 downto 0); -- to the DAC
		EN		: OUT STD_LOGIC_VECTOR(17 downto 0)  -- to the trigger of each channel
	);
END dig_cntrl2;

architecture a of dig_cntrl2 is

SIGNAL SHREG : STD_LOGIC_VECTOR(Nch-1 downto 0); -- shift register
SIGNAL cnt  : Integer range 0 to Nch+Ndac;
SIGNAL cnt_z, cnt_zf : STD_LOGIC;
begin
	cnt_z <= '1' when cnt=0 else '0';
	process(CLK, STR) -- counter
	begin
		if STR='1' then cnt<=Ndac+Nch;-- cnt_zf <= '0';
		elsif clk'event and clk='1' then
--			cnt_zf <= cnt_z;
			if cnt_z /='1' then cnt<=cnt-1; end if;
		end if;
	end process;
	
	process(CLK) -- shift register
	begin
		if clk'event and clk='1' then
			if cnt_z /= '1' then 
				shreg <= shreg(Nch-2 downto 0) & DIN; 
			end if; -- MSB first
		end if;
	end process;

	process(CLK) -- parallel output register for the DAC
	begin
		if clk'event and clk='1' then
			if cnt=Nch then -- copy as soon as possible the DAC value
				DAC <= shreg(Ndac-1 downto 0); -- DAC is in MSB part
			end if;
		end if;
	end process;

i:  for i in 0 to Nch-1 generate
g:		EN(i) <= not (shreg(i) and STR);       -- channel triggers
	end generate;

end;