LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

entity counter is
GENERIC (N : Integer := 10);
    port (
           clk                        : in    std_logic;
           clk_en                     : in    std_logic;
           sclr                       : in    std_logic;
           aclr                       : in    std_logic;
           Q                          : out   std_logic_vector(N-1 downto 0)
           );
end counter;

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-- ARCHITECTURE
--------------------------------------------------------------------------------------------------------
architecture a of counter is

constant all1   : std_logic_vector(Q'range) := (others => '1');
signal   Q_int  : std_logic_vector(Q'range);

begin

    process(clk, aclr)
    begin
        if aclr='1' then q_int <= (others => '0');
        elsif clk'event and clk='1' then
          if sclr='1' then
            q_int <= (others => '0');
          elsif clk_en='1' then
            q_int <= q_int + 1;
          end if;
        end if;
    end process;
    q <= q_int;

end;