LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; -- $Id$: -- sdac 1 0x5000 0x507F -- V dut_trap enable 0x5080 0x50FF -- sdac 2 0x5100 0x51FF -- dds 0x5200 0x52FF -- sc adc 0x5300 0x53FF -- psply adc 0x5400 0x54FF -- pasa dac 0x5500 0x55FF -- pasa adc 0x5800 0x5FFF entity ADC_DAC is generic(wafer_test : Integer := 0; TesterNum : Positive := 4); -- 1,2,3 are old design, 4,5.. are new design port( clk : in std_logic; clk120 : in std_logic; reset_n : in std_logic; -- SCSN bus_addr : in std_logic_vector(15 downto 0); bus_we : in std_logic; -- write enable bus_din : in std_logic_vector(31 downto 0); bus_dout : out std_logic_vector(31 downto 0); bus_req : in std_logic; -- bus request bus_ack : out std_logic; -- general purpose synchronization signals AD_SYNC_OUT : out std_logic_vector(1 downto 0); AD_SYNC_IN : in std_logic_vector(1 downto 0); -- ADCs and DACs VMCM_Shdwn_a : out std_logic; VMCM_Shdwn_d : out std_logic; PW_INCn : out std_logic_vector(3 downto 0); PW_UDn : out std_logic_vector(3 downto 0); PW_CSn : out std_logic_vector(3 downto 0); MSply_ADC_nCS : out std_logic; MSply_ADC_INTn : in std_logic; MSply_ADC_nCSStrt : out std_logic; MSply_ADC_SDI : out std_logic; MSply_ADC_SDO : in std_logic; MSply_ADC_SCLK : out std_logic; -- DDS for the 3 ADC channels AD9854 DDS_FSK : out std_logic; DDS_ShKey : out std_logic; DDS_CSn : out std_logic; DDS_SCLK : out std_logic; DDS_UDCLK : out std_logic; DDS_SDI : out std_logic; DDS_SDO : in std_logic; -- ?? DDS_IORST : out std_logic; DDS_MRST : out std_logic; DDS_MCLK : out std_logic; -- PASA ADC ADS5221 PAADC_D : in std_logic_vector(11 downto 0); PAADC_OVR : in std_logic; PAADC_CLK : out std_logic; PAADC_Msel : out std_logic; PAADC_STDP : out std_logic; PAADC_MuxnRS : out std_logic; PAADC_MuxA : out std_logic_vector(1 downto 0); -- PASA DACs AD9744 PasaDAC1_CLK : out std_logic; PasaDAC2_CLK : out std_logic; PasaDAC_Sleep : out std_logic; PasaDAC_D : out std_logic_vector(13 downto 0); -- Slow DAC 2xTLV5630 SlowDAC1_SCLK : out std_logic; SlowDAC2_SCLK : out std_logic; SlowDAC1_LDACn : out std_logic; SlowDAC2_LDACn : out std_logic; SlowDAC_Din : out std_logic; SlowDAC1_FS : out std_logic; SlowDAC2_FS : out std_logic; -- SC ADC TLV2548 SC_ADC_SDO : in std_logic; SC_ADC_INTn : in std_logic; SC_ADC_nCSStrt : out std_logic; SC_ADC_SCLK : out std_logic; SC_ADC_SDI : out std_logic; SC_ADC_nCS : out std_logic; CE_ni : out std_logic; rdata_ni : in std_logic_vector(31 downto 0) ); end ADC_DAC; architecture a of ADC_DAC is component gio_devices_adc is port( clk : in std_logic; rdata_sc_adc : in std_logic_vector(31 downto 0); rdata_psply_adc : in std_logic_vector(31 downto 0); rdata_dds : in std_logic_vector(31 downto 0); rdata_pasa_adc : in std_logic_vector(31 downto 0); rdata_pasa_dac : in std_logic_vector(31 downto 0); bus_addr : in std_logic_vector(15 downto 6); -- address to read/write bus_req : in std_logic; -- bus request bus_ack : out std_logic; ce_1sdac : out std_logic; ce_shutdn : out std_logic; ce_digpot : out std_logic; ce_2sdac : out std_logic; ce_dds : out std_logic; ce_sc_adc : out std_logic; ce_psply_adc : out std_logic; ce_pasa_dac : out std_logic; ce_wtnip4 : out std_logic; ce_pasa_adc : out std_logic; bus_dout : out std_logic_vector(31 downto 0) ); end component; component digpot4 IS PORT(clk : IN std_logic; rst_n : IN std_logic; WE : IN std_logic; CE : IN std_logic; D : IN std_logic_vector(7 downto 0); INCn : out std_logic; UDn : out std_logic; CSn : out std_logic ); END component; component TLV5630 is GENERIC ( WIDTH : Integer := 16 -- Width of the 'Byte' ); PORT ( CLK : IN STD_LOGIC; -- Clock, 30 or 40 MHz RESET_n : IN STD_LOGIC; -- reset CE : IN STD_LOGIC; -- Chip enable WE : IN STD_LOGIC; -- Write enable D : IN STD_LOGIC_VECTOR(WIDTH downto 0); -- Data input bus, MSB = load DAC after serial shift PQ : OUT STD_LOGIC_VECTOR(WIDTH downto 0); -- Parallel outputs LDACn : OUT STD_LOGIC; -- load dac SCLK : OUT STD_LOGIC; -- Serial Clock SDAT : OUT STD_LOGIC; -- Serial Data SSTR : OUT STD_LOGIC);-- Serial Strobe end component; component seradc_auto is PORT ( CLK : in std_logic; -- Clock, 30 or 40 MHz RESET_n : in std_logic; -- reset -- to the internal bus CE : in std_logic; WE : in std_logic; ADDR : in std_logic_vector( 2 downto 0); WDATA : in std_logic_vector(23 downto 0); RDATA : out std_logic_vector(31 downto 0); -- ext status status : in std_logic_vector( 1 downto 0); cl : out std_logic_vector( 1 downto 0); -- current limit reached -- to the ADC ADC_INTn : in std_logic; ADC_nCSStrt : out std_logic; ADC_nCS : out std_logic; ADC_SCLK : out std_logic; ADC_SDI : out std_logic; ADC_SDO : in std_logic); end component; component pasadac is port ( CLK120 : in std_logic; -- Clock, 120 MHz CLK : in std_logic; -- Clock, 30 or 40 MHz RESET_n : in std_logic; -- reset start : in std_logic; -- to the internal bus CE : in std_logic; WE : in std_logic; ADDR : in std_logic_vector( 5 downto 0); WDATA : in std_logic_vector(28 downto 0); RDATA : out std_logic_vector(31 downto 0); -- to the DACs PasaDAC1_CLK : out std_logic; PasaDAC2_CLK : out std_logic; PasaDAC_Sleep : out std_logic; PasaDAC_D : out std_logic_vector(13 downto 0) ); end component; component pasaadc is generic(TesterNum : Positive := 4); -- 1,2,3 are old design, 4,5.. are new design port ( CLK : in std_logic; -- Clock, 30 or 40 MHz RESET_n : in std_logic; -- reset start : in std_logic; -- to the internal bus CE : in std_logic; WE : in std_logic; ADDR : in std_logic_vector(10 downto 0); WDATA : in std_logic_vector(23 downto 0); RDATA : out std_logic_vector(31 downto 0); -- to the ADC PAADC_D : in std_logic_vector(11 downto 0); PAADC_OVR : in std_logic; PAADC_CLK : out std_logic; PAADC_Msel : out std_logic; PAADC_STDP : out std_logic; PAADC_MuxnRS : out std_logic; -- 00 - PASA channel 1 -- 01 - PASA channel 17 -- 10 - PASA channel 18 -- 11 - DDS channel 1 PAADC_MuxA : out std_logic_vector(1 downto 0) ); end component; component DDS is port ( CLK : in std_logic; -- Clock, 30 or 40 MHz RESET_n : in std_logic; -- reset start : in std_logic; -- to the internal bus CE : in std_logic; WE : in std_logic; ADDR : in std_logic_vector( 7 downto 0); WDATA : in std_logic_vector(31 downto 0); RDATA : out std_logic_vector(31 downto 0); -- DDS for the 3 ADC channels AD9854 DDS_FSK : out std_logic; DDS_ShKey : out std_logic; DDS_CSn : out std_logic; DDS_SCLK : out std_logic; DDS_UDCLK : out std_logic; DDS_SDI : out std_logic; DDS_SDO : in std_logic; -- ?? DDS_IORST : out std_logic; DDS_MRST : out std_logic; DDS_MCLK : out std_logic ); end component; signal rdata_sc_adc : std_logic_vector(31 downto 0); signal rdata_psply_adc : std_logic_vector(31 downto 0); signal rdata_dds : std_logic_vector(31 downto 0); signal rdata_pasa_adc : std_logic_vector(31 downto 0); signal rdata_pasa_dac : std_logic_vector(31 downto 0); signal rdata_pasa_dac_mux : std_logic_vector(31 downto 0); signal ce_1sdac : std_logic; signal ce_shutdn : std_logic; signal ce_digpot : std_logic; signal ce_2sdac : std_logic; signal ce_dds : std_logic; signal ce_sc_adc : std_logic; signal ce_psply_adc : std_logic; signal ce_pasa_dac : std_logic; signal ce_pasa_adc : std_logic; signal SlowDAC1_Din : std_logic; signal SlowDAC2_Din : std_logic; signal shutdown_n : std_logic_vector(1 downto 0); signal CurrentLimit : std_logic_vector(1 downto 0); begin wt: if wafer_test=1 generate rdata_pasa_dac_mux <= rdata_ni; PasaDAC1_CLK <= '0'; PasaDAC2_CLK <= '0'; PasaDAC_Sleep <= '1'; PasaDAC_D <= (others => '0'); -- why was 1? end generate; nw: if wafer_test/=1 generate -- DAC1 channel Connected to -- 0 1V8 TRAP digital -- 1 1V8 TRAP analog -- 2 3V3 TRAP IO -- 3 3V3 PASA -- 4 DDS VCM (TRAP ADC) -- 5 Vref PASA -- 6 Vref TRAP -- 7 SDAC not used slow_dac1: TLV5630 GENERIC map( WIDTH => 16) PORT map( CLK => CLK, RESET_n => RESET_n, CE => ce_1sdac, WE => bus_we, D => bus_din(16 downto 0), PQ => open, LDACn => SlowDAC1_LDACn, SCLK => SlowDAC1_SCLK, SDAT => SlowDAC1_Din, SSTR => SlowDAC1_FS); pdac: pasadac port map( CLK120 => CLK120, CLK => CLK, RESET_n => RESET_n, start => AD_SYNC_IN(1), -- to the internal bus CE => ce_pasa_dac, WE => bus_we, ADDR => bus_addr(5 downto 0), WDATA => bus_din(28 downto 0), RDATA => rdata_pasa_dac, -- to the ADC PasaDAC1_CLK => PasaDAC1_CLK, PasaDAC2_CLK => PasaDAC2_CLK, PasaDAC_Sleep => PasaDAC_Sleep, PasaDAC_D => PasaDAC_D ); rdata_pasa_dac_mux <= rdata_pasa_dac; end generate; gio: gio_devices_adc port map( clk => clk, rdata_sc_adc => rdata_sc_adc, rdata_psply_adc => rdata_psply_adc, rdata_dds => rdata_dds, rdata_pasa_adc => rdata_pasa_adc, rdata_pasa_dac => rdata_pasa_dac_mux, bus_addr => bus_addr(15 downto 6), bus_req => bus_req, bus_ack => bus_ack, ce_1sdac => ce_1sdac, ce_shutdn => ce_shutdn, ce_digpot => ce_digpot, ce_2sdac => ce_2sdac, ce_dds => ce_dds, ce_sc_adc => ce_sc_adc, ce_psply_adc => ce_psply_adc, ce_pasa_dac => ce_pasa_dac, ce_wtnip4 => ce_ni, ce_pasa_adc => ce_pasa_adc, bus_dout => bus_dout ); -- DAC2 channel Connected to -- 0 PASA Vbias -- 1 PASA Vcm -- 2 PASA Vref p -- 3 PASA Vref n -- 4 ADC aux p -- 5 ADC aux n -- 6 SDAC 2 not used -- 7 SDAC 2 not used slow_dac2: TLV5630 GENERIC map( WIDTH => 16) PORT map( CLK => CLK, RESET_n => RESET_n, CE => ce_2sdac, WE => bus_we, D => bus_din(16 downto 0), PQ => open, LDACn => SlowDAC2_LDACn, SCLK => SlowDAC2_SCLK, SDAT => SlowDAC2_Din, SSTR => SlowDAC2_FS); -- psply adc 0x5400 0x54FF power_adc: seradc_auto PORT map( CLK => CLK, RESET_n => RESET_n, -- to the internal bus CE => ce_psply_adc, WE => bus_we, ADDR => bus_addr(2 downto 0), WDATA => bus_din(23 downto 0), RDATA => rdata_psply_adc, -- ext status status => shutdown_n, cl => CurrentLimit, -- to the ADC ADC_INTn => MSply_ADC_INTn, ADC_nCSStrt => MSply_ADC_nCSStrt, ADC_nCS => MSply_ADC_nCS, ADC_SCLK => MSply_ADC_SCLK, ADC_SDI => MSply_ADC_SDI, ADC_SDO => MSply_ADC_SDO); sc_adc: seradc_auto PORT map( CLK => CLK, RESET_n => RESET_n, -- to the internal bus CE => ce_sc_adc, WE => bus_we, ADDR => bus_addr(2 downto 0), WDATA => bus_din(23 downto 0), RDATA => rdata_sc_adc, -- ext status status => "00", cl => open, -- to the ADC ADC_INTn => SC_ADC_INTn, ADC_nCSStrt => SC_ADC_nCSStrt, ADC_nCS => SC_ADC_nCS, ADC_SCLK => SC_ADC_SCLK, ADC_SDI => SC_ADC_SDI, ADC_SDO => SC_ADC_SDO); SlowDAC_Din <= SlowDAC1_Din or SlowDAC2_Din; -- Shutdown output process(clk, reset_n) begin if reset_n = '0' then shutdown_n <= "00"; elsif clk'event and clk= '1' then if ce_shutdn = '1' and bus_we = '1' then shutdown_n <= bus_din(1 downto 0); end if; -- analog without digital is not usable if CurrentLimit(0)='1' or CurrentLimit(1)='1' then shutdown_n(0) <= '0'; end if; -- digital without analog is usable (board merger) if CurrentLimit(1)='1' then shutdown_n(1) <= '0'; end if; end if; end process; VMCM_Shdwn_a <= shutdown_n(0); VMCM_Shdwn_d <= shutdown_n(1); padc: pasaadc generic map(TesterNum => TesterNum) port map( CLK => CLK, RESET_n => RESET_n, start => AD_SYNC_IN(1), -- to the internal bus CE => ce_pasa_adc, WE => bus_we, ADDR => bus_addr(10 downto 0), WDATA => bus_din(23 downto 0), RDATA => rdata_pasa_adc, -- to the ADC PAADC_D => PAADC_D, PAADC_OVR => PAADC_OVR, PAADC_CLK => PAADC_CLK, PAADC_Msel => PAADC_Msel, PAADC_STDP => PAADC_STDP, PAADC_MuxnRS => PAADC_MuxnRS, -- 3 PASA channel 1 -- 2 PASA channel 17 -- 1 PASA channel 18 -- 0 DDS channel 1 PAADC_MuxA => PAADC_MuxA ); ddsi: DDS port map( CLK => CLK, RESET_n => RESET_n, start => AD_SYNC_IN(1), -- to the internal bus CE => ce_dds, WE => bus_we, ADDR => bus_addr(7 downto 0), WDATA => bus_din(31 downto 0), RDATA => rdata_dds, -- DDS for the 3 ADC channels AD9854 DDS_FSK => DDS_FSK, DDS_ShKey => DDS_ShKey, DDS_CSn => DDS_CSn, DDS_SCLK => DDS_SCLK, DDS_UDCLK => DDS_UDCLK, DDS_SDI => DDS_SDI, DDS_SDO => DDS_SDO, DDS_IORST => DDS_IORST, DDS_MRST => DDS_MRST, DDS_MCLK => DDS_MCLK ); dgi: for i in 0 to 3 generate dgpot: digpot4 PORT map( clk => clk, rst_n => RESET_n, ce => ce_digpot, WE => bus_we, D => bus_din(7+i*8 downto i*8), INCn => PW_INCn(i), UDn => PW_UDn(i), CSn => PW_CSn(i) ); end generate; -- still dummy, sync outputs ? process(clk) begin if clk'event and clk= '1' then AD_SYNC_OUT <= AD_SYNC_IN; end if; end process; end;