library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

-- ADC

entity TLV2548 is
PORT (
        CLK            : in  std_logic; -- Clock, 30 or 40 MHz
        RESET_n        : in  std_logic; -- reset

        CE             : in  std_logic;
        CMD            : in  std_logic_vector( 3 downto 0);
        WDATA          : in  std_logic_vector(11 downto 0);
        RDATA          : out std_logic_vector(11 downto 0);
        RDY            : out std_logic; -- and ADC_nCS

        ADC_SCLK       : out std_logic;
        ADC_SDI        : out std_logic;
        ADC_SDO        : in  std_logic);
end TLV2548;

architecture a of TLV2548 is

type sm_type is (idle, load, setclock, shift, finish);
signal sm      : sm_type;
signal fifo_rd : std_logic;
signal counter : std_logic_vector( 3 downto 0);
signal datasr  : std_logic_vector(15 downto 0);
signal datarc  : std_logic_vector(11 downto 0);

begin
        process(clk)
        begin
            if clk'event and clk='1' then
                case sm is
                when idle =>
                    if ce = '1' then
                        if cmd = "1010" then datasr <= cmd & wdata;
                                        else datasr <= cmd & "000000000000";
                        end if;
                        if cmd = "1110" then fifo_rd <= '1'; else fifo_rd <= '0'; end if;
                    end if;
                when shift =>
                    datasr <= datasr(14 downto 0) & '0';
                    if (fifo_rd='1' and counter > 3) or (fifo_rd='0') then
                         datarc <= datarc(10 downto 0) & ADC_SDO;
                    end if;
                when others => NULL;
                end case;
            end if;
        end process;

        ADC_SDI <= datasr(15);
        RDATA   <= datarc;

        process(clk, reset_n)
        begin
            if reset_n = '0' then
                sm <= idle;
                counter <= "0000";
                rdy <= '0';
                ADC_SCLK <= '0';
            elsif clk'event and clk='1' then
                rdy <= '0';
                ADC_SCLK <= '0';
                case sm is
                when idle =>
                    if ce='1' then sm <= load;
                              else rdy <= '1';
                    end if;
                    counter <= "0000";
                when load =>
                    counter <= "0000";
                    sm <= setclock;
                when setclock =>
                    counter <= counter - 1;
                    sm <= shift;
                    ADC_SCLK <= '1';
                when shift =>
                    if counter = 0 then sm <= finish;
                    else sm <= setclock;
                    end if;
                when finish =>
                    sm <= idle;
                end case;
            end if;
        end process;
end;