// switch
//
//  0       only the local scsn slave
//  1       the local and the other fpga slave
//  2       the local, the other fpga slave and the 4 traps for ni test
//  3       the local and the DUT
//  4       the local, the DUT and the 4 traps for ni test
//  5       the local and the WT

include chip_def.tcs

write 0x4400, 3; // or 3 for DUT only
wait 80;
reset;
nop;
wait 80;
nop;

// test the reset
// 1. activate the reset output at the FPGA2
write fpga2, 0x4440, 0;
bridge fpga2, 1
nop
write fpga2, 0x4430, 0;
wait 50;                  // this delay is for simulation only
bridge fpga2, 0

// 2. read the 3 x 10 bit counters - the width of the reset outputs pulses from TRAP
nop
read  fpga2, 0x4430;
// check in the software, if the numbers represented by bits 29..20, 19..10 and 9..0
// are around 0x224

read  fpga2, 0x4440;
// 3. check if bits 9..7 (the reset outputs) are "111".
read  fpga2, 0x4440;

// 4. write something in the TRAP, which will be cleared by reset
write  dut, 0x0C00, 0xAA; // here one of the programmable constants
expect dut, 0x0C00, 0xAA; // and read back
wait 50;                  // this delay is for simulation only
nop
//nop
//nop
// 5. activate reset at the FPGA2
bridge fpga2, 1
write fpga2, 0x4430, 0;
wait 50;                  // this delay is for simulation only
nop
bridge fpga2, 0
nop

// 6. read the 3 x 10 bit counters - the width of the reset outputs pulses from TRAP
read  fpga2, 0x4430;
// check in the software, if the numbers represented by bits 29..20, 19..10 and 9..0
// are around 0x22
read  fpga2, 0x4430;

// 7. check if the programmed register in the TRAP was cleared by the reset
expect dut, 0x0C00, 0x0;

// 8. check the SEBD of TRAP pins as simple output pins
write dut,  SEBDEN, 0x7;                // enable all 3 outputs of the TRAP
write dut,  SEBDOU, 0x1;                // and activate bit 0
expect dut, SEBDIN, 1;                  // read from the TRAP
read  fpga2, 0x4440;                    // read from the FPGA

write dut,  SEBDOU, 0x2;                // and activate bit 1
expect dut, SEBDIN, 2;                  // read from the TRAP
read  fpga2, 0x4440;                    // read from the FPGA

write dut,  SEBDOU, 0x4;                // and activate bit 2
expect dut, SEBDIN, 4;                  // read from the TRAP
read  fpga2, 0x4440;                    // read from the FPGA

write dut,  SEBDOU, 0x0;                // and clear all bits
expect dut, SEBDIN, 0;                  // read from the TRAP
read  fpga2, 0x4440;                    // read from the FPGA

write dut,  SEBDOU, 0x7;                // and set all bits
expect dut, SEBDIN, 7;                  // read from the TRAP
read  fpga2, 0x4440;                    // read from the FPGA

// 9. check the SEBD of TRAP pins as simple input pins
write dut,  SEBDEN, 0x0;                // disable the TRAP outputs
write fpga2, 0x4440, (0x7 << 4) | 1;    // enable the FPGA outputs and set bit 0
read  fpga2, 0x4440;                    // read from the FPGA
expect dut,  SEBDIN, 1;                 // read from the TRAP

write fpga2, 0x4440, (0x7 << 4) | 2;    // enable the FPGA outputs and set bit 1
read  fpga2, 0x4440;                    // read from the FPGA
expect dut,  SEBDIN, 2;                 // read from the TRAP

write fpga2, 0x4440, (0x7 << 4) | 4;    // enable the FPGA outputs and set bit 2
read  fpga2, 0x4440;                    // read from the FPGA
expect dut,  SEBDIN, 4;                 // read from the TRAP

write fpga2, 0x4440, (0x7 << 4) | 0;    // enable the FPGA outputs and clear all bits
read  fpga2, 0x4440;                    // read from the FPGA
expect dut,  SEBDIN, 0;                 // read from the TRAP

write fpga2, 0x4440, (0x7 << 4) | 7;    // enable the FPGA outputs and set all bits
read  fpga2, 0x4440;                    // read from the FPGA
expect dut,  SEBDIN, 7;                 // read from the TRAP