/**************************************/
/* ALICE TRD                          */
/* Read-out board                     */
/* SCSN Configuration File            */
/*                                    */
/* 2004-03-08                         */
/* Jan de Cuveland, Venelin Angelov   */
/**************************************/

const padrow_range = 0; // 0..3

// ------------------------
//  set constant registers
// ------------------------

// c12 - z-pos 4 bit, here test pattern

// hamming correction for all memories!
write MEMCOR, 0x01FF;
// arbiter timing
write ARBTIM, 1101b;

write ni0,  0x0C04, 0xFF00C040;
write ni1,  0x0C04, 0xFE01C040;
write ni2,  0x0C04, 0xFD02C040;
write ni3,  0x0C04, 0xFC03C040;
write dut,  0x0C04, 0xFB04C040;

// -------------------------
//  set int entry addresses
// -------------------------

write IA0,    0x0100;         // set int_clr start addr for cpu0
write IA1,    0x0100;         // set int_clr start addr for cpu1
write IA2,    0x0100;         // set int_clr start addr for cpu2
write IA3,    0x0100;         // set int_clr start addr for cpu3

write IA0+2,  0x0200;         // set int_acq start addr for cpu0
write IA1+2,  0x0200;         // set int_acq start addr for cpu1
write IA2+2,  0x0200;         // set int_acq start addr for cpu2
write IA3+2,  0x0200;         // set int_acq start addr for cpu3

write IA0+4,  0x0400;         // set int_raw start addr for cpu0
write IA1+4,  0x0400;         // set int_raw start addr for cpu1
write IA2+4,  0x0400;         // set int_raw start addr for cpu2
write IA3+4,  0x0400;         // set int_raw start addr for cpu3

// ---------------
//  set int masks
// ---------------

write IRQHW0, 00010101b;      // set irq_hw mask for cpu0
write IRQHL0, 00010101b;      // set irq_hl mask cor cpu0
write IRQHW1, 00010101b;      // set irq_hw mask for cpu1
write IRQHL1, 00010101b;      // set irq_hl mask cor cpu1
write IRQHW2, 00010101b;      // set irq_hw mask for cpu2
write IRQHL2, 00010101b;      // set irq_hl mask cor cpu2
write IRQHW3, 00010101b;      // set irq_hw mask for cpu3
write IRQHL3, 00010101b;      // set irq_hl mask cor cpu3

// ------------------------------
//  enable/disable LVDS clock and pretrigger fanout LVDS cells
// ------------------------------

// switching the unused pre & clk & ni ports off
// normal chips 2, 6, 10, 14
write ni0 , SMMODE, 0x80E2; // port 3 clk, pre -> ni1
write ni1 , SMMODE, 0x00E2;
write ni2 , SMMODE, 0x20E2; // port 1 clk, pre -> ni3
write ni3 , SMMODE, 0x10E2; // port 0 clk, pre -> dut

write dut , SMMODE, 0xF0E2; // all clk, pre outs must be counted in FPGA

// -------------------------
//  configure clock control
// -------------------------

write         CPU0CLK, 0x3F;
write         CPU1CLK, 0x3F;
write         CPU2CLK, 0x3F;
write         CPU3CLK, 0x3F;

// -----------------------------
//  configure network interface
// -----------------------------

// NI output excludes and ctrl delay: chip_rm is root in optical link mode
write          NDLY,    0x12492492; // all data bits delay 2

// all chips, all input ports, exclude bits
write          NP0,    0x03CC; // excluce bit 7
write          NP1,    0x03CC; // excluce bit 7
write          NP2,    0x03CC; // excluce bit 7
write          NP3,    0x03CC; // excluce bit 7

write          NED,    0x1E40; // incl bm, bm0,1 now

// output delays optimized for the FPGA
// change to strobe mode for NI - ACEX board !!!

write dut, NED,(root_flag << 14) | (oase_mode << 15) | (parit_bit << 10) | (false_bit << 6) | (ctrl_delay << 3) | strb_delay;
write dut, NDLY, (data_delay) | (data_delay << 3) | (data_delay << 6) | (data_delay << 9) | (data_delay << 12) | (data_delay << 15) | (data_delay << 18) | (data_delay << 21) | (data_delay << 24) | (data_delay << 27);

// readout order configuration constants
//const niro_dut    = 0x0003c688; // 0 -> 1 -> 2 -> 3 -> 4(own data)
const niro_dut    = 0x0003c7d0; // 0      -> 2 -> 3 -> 4(own data)
// 1 -> 0 -> own -> 3
const niro_ni0123 = 0x0003fffc; // own data only

// set NI tracklet readout order
write           NTRO, niro_ni0123;
write dut,      NTRO, niro_dut;

// set NI raw data readout order
write           NRRO, niro_ni0123;
write dut,      NRRO, niro_dut;

// set end signature (rr: 0x----0000, tr: 0x----1000)
write NES, 0x0000AAAA;

// timers for NI signals
write           NITM0, 0x01D0; // 0x153;   // NI timer 0 (clock)
write           NITM1, 0x01E2; // 0x165;   // NI timer 1 (IO data)
write           NITM2, 0x022F+24+100;   // NI timer 2 (clock)

write           NIP4D, 0x0F;   // delays
write dut,      NIP4D, 0xFF;   // delays

// configuration of the NI clock
write           NICLK,  0x3F;

// configuration of the NI output data port
write           NIODE,  11011b;
write dut,      NIODE,  00010b;

// configuration of the NI output control port
write           NIOCE,  0x3F;
write dut,      NIOCE,  0x01; // was 3 // was 7

// configuration of the NI input data ports
write           NIIDE,  0x3F;

// configuration of the NI input control ports
write           NIICE,  0x3F;

// ---------------------
//  misc. configuration
// ---------------------

// ADC off
// mask the ADCs with open inputs, first mask all
write         ADCMSK, 0x0

// Drift time
write TPPT0,  0x0D; // skip first 10 samples
write TPPAE,  0x15; // acquire 21 samples
write TPPGR,  0x14; // start CPUs after 20 samples

// --------------------------------
//  configure global state machine
// --------------------------------

write SML0, 0x00004050;         // consider L0 & L0_time = 0x050 (80)
write SML1, 0x00004230+24+100;  // consider L1 & L1_time = 0x200 (512)
write SML2, 0x000042BC+100;     // consider L2 & L2_time = 0x2BC (700)

// init the PSRG counters
write 0xF03F, 0x100
write 0xF07F, 0x200
write 0xF0BF, 0x300
write 0xF0FF, 0x400