include chip_def.tcs

const oase_mode  = 1; // 1 or 0
const root_flag  = 1; // 1 or 0
// all delays canbe from 0 to 7
const f_ctrl_delay = 3; // 1..4 stable
const f_data_delay = 3; // , 2..5 stable (at strb_delay=0)
const f_strb_delay = 0; //
const f_false_bit  = 0; // 0..9
const f_parit_bit  = 2; // 0..9

const t_ctrl_delay = 3; // 0..7 egal
const t0_data_delay = 2; // 1 .. 4
const t1_data_delay = 1; // 1 is the only stable setting (at strb 0)
const t2_data_delay = 1; // 0 .. 3
const t3_data_delay = 2; // 1 .. 2
const t_strb_delay = 0; // 0
const t_false_bit  = 0; // 0..9
const t_parit_bit  = 2; // 0..9

include main.tcs

// read the status of all chips
//read 127, 0x0A04
// later in the other script
//pretrigger 5
//wait 0
write fpga2, 0x4008, 5
//write ni1, 0x0A04, 0x012;
//write ni1, NIODE, 1;
//read 127, NIODE;
//wait 10;
//pretrigger 1
// exclude and parity bits
write fpga2, 0x4410, (f_false_bit << 0) | (f_parit_bit << 4) | (oase_mode << 8);
// start the events
//include event.tcs
read 127, ADCPAR
//write ADCPAR, b01 1001 0101 1110 1111
//write ADCPAR, 0x195EF
//wait 0
//write ADCPAR, b011001011111111111
//write ADCPAR, 0x0197FF