include chip_def.tcs

const root_flag  = 1; // 1 or 0
const root_ni    = 1; // 1 or 0

// all delays can be from 0 to 7

// configuration for DUT -> FPGA readout
// all delays:    min .best. max
const f_ctrl_delay = 3;  // 2 .3. 4 stable

const f_data_delay0 = 3; // 2 .3. 5
const f_data_delay1 = 3; // 2 .4. 6
const f_data_delay2 = 3; // 2 .3. 5
const f_data_delay3 = 3; // 1 .3. 5
const f_data_delay4 = 3; // 1 .3. 5
const f_data_delay5 = 3; // 1 .3. 4
const f_data_delay6 = 3; // 1 .3. 5
const f_data_delay7 = 3; // 1 .3. 5
const f_data_delay8 = 2; // 1 .3. 5
const f_data_delay9 = 3; // 1 .3. 4

const f_strb_delay = 0; //
const f_false_bit  = 9; // 0..9
const f_parit_bit  = 8; // 0..9

const t_ctrl_delay = 0; // 0..7 egal

const t0_data_delay0 = 2; // 0 .2. 4
const t0_data_delay1 = 2; // 1 .2. 4
const t0_data_delay2 = 2; // 0 .2. 4
const t0_data_delay3 = 2; // 0 .2. 4
const t0_data_delay4 = 2; // 0 .2. 4
const t0_data_delay5 = 2; // 0 .2. 4
const t0_data_delay6 = 2; // 0 .2. 4
const t0_data_delay7 = 2; // 0 .2. 4
const t0_data_delay8 = 2; // 0 .2. 4
const t0_data_delay9 = 2; // 0 .2. 4

const t1_data_delay0 = 1; // 0 .1. 1
const t1_data_delay1 = 1; // 0 .1. 1
const t1_data_delay2 = 1; // 0 .1. 1
const t1_data_delay3 = 1; // 0 .1. 1
const t1_data_delay4 = 1; // 0 .1. 1
const t1_data_delay5 = 1; // 0 .1. 1
const t1_data_delay6 = 1; // 0 .1. 1
const t1_data_delay7 = 1; // 0 .1. 1
const t1_data_delay8 = 1; // 0 .1. 1
const t1_data_delay9 = 1; // 0 .1. 1

const t2_data_delay0 = 1; // 0 .1. 3
const t2_data_delay1 = 1; // 0 .1. 3
const t2_data_delay2 = 1; // 0 .1. 3
const t2_data_delay3 = 1; // 0 .1. 3
const t2_data_delay4 = 1; // 0 .1. 3
const t2_data_delay5 = 1; // 0 .1. 3
const t2_data_delay6 = 1; // 0 .1. 3
const t2_data_delay7 = 1; // 0 .1. 3
const t2_data_delay8 = 1; // 0 .1. 2
const t2_data_delay9 = 1; // 0 .1. 3

const t3_data_delay0 = 1; // 0 .1. 3
const t3_data_delay1 = 1; // 0 .1. 3
const t3_data_delay2 = 1; // 1 .1. 2, err(0) < err(3)
const t3_data_delay3 = 1; // 0 .1. 2
const t3_data_delay4 = 1; // 0 .1. 2
const t3_data_delay5 = 1; // 0 .1. 2
const t3_data_delay6 = 1; // 0 .1. 2
const t3_data_delay7 = 1; // 0 .1. 2
const t3_data_delay8 = 1; // 0 .1. 2
const t3_data_delay9 = 1; // 0 .1. 2

const t0_strb_delay = 0; // 0
const t1_strb_delay = 0; // 0
const t2_strb_delay = 0; // 0
const t3_strb_delay = 0; // 0

const t_false_bit  = 9; // 0..9
const t_parit_bit  = 8; // 0..9

include main.tcs

//pretrigger 5
write fpga2, 0x4008, 5
// exclude and parity bits in FPGA design
write fpga2, 0x4410, (f_false_bit << 0) | (f_parit_bit << 4) | (oase_mode << 8);