# clean the work library
exec vdel -lib work -all
exec vlib work
exec vmap work work

# compile simulation model for some ADCs and DACs
# dummy
vcom -quiet -work work -93 -explicit ./SRC/adcs_dacs.vhd

# scsn serial master
do cser_int.do

# compile the top of all TRAP chips
# dummy
vcom -quiet -work work -93 -explicit ./SRC/ni_port_stim.vhd
vcom -quiet -work work -93 -explicit ./SRC/traps.vhd
# still no traps in simulation!

# compile top testbench
vcom -quiet -work work -93 -explicit ./SRC/top_tb.vhd