exec vdel -lib fpga2 -all
exec vlib fpga2
exec vmap fpga2 fpga2

# altera components
# this pll model is wrong!
#vcom -quiet -work fpga2 -93 -explicit ../quartus_lvds/pll120.vhd

# this is pathced model from VST PLL
vcom -quiet -work fpga2 -93 -explicit ./SRC/pll4.vhd
vcom -quiet -work fpga2 -93 -explicit ./SRC/pll120_2.vhd

# generated RAM for FPGA
vcom -quiet -work fpga2 -93 -explicit ../quartus_lvds/ni_dpram.vhd

# scsn slave
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/hamm34enc67.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/hamm67dec34.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/hamm_reg.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_apl.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_timer.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_destuffing.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_stuffing.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_outbuf.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_inbuf.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_bittiming.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_sendtiming.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_dll.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_nwsl.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_nwl.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_nw_pl.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/SCSN/mcm_network_interface.vhd

# fpga design
# pretrigger and clock
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/pre_enc.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/pre_dec.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/pre_dir.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/counter.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/pre_counter.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/clk_counter.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/clkpre_counter.vhd
# NI receiver
vcom -quiet -work fpga2 -93 -explicit ../SRC/RESYNC/reg_clr.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/RESYNC/ni_exclude_in.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/RESYNC/ni2dpm.vhd
vcom -quiet -work fpga2 -93 -explicit ../SRC/RESYNC/ni2io.vhd
# general configuration registers
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/general_config.vhd
# scsn switch
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/scsn_switch.vhd
# device decoders (writing) and muxes (reading)
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/gio_devices.vhd
# jtag master for trap3 - not ready
vcom -quiet -work fpga2 -93 -explicit ../SRC/LVDS/jtag_master.vhd
# top of this fpga
vcom -quiet -work fpga2 -93 -explicit ../SRC/TOP_LVDS/top.vhd