const fpga2 = 1;
const dut   = 2;
const ni0   = 3;
const ni1   = 4;
const ni2   = 5;
const ni3   = 6;

// scsn ring fpga2+DUT
//  0       only the local scsn slave (after reset)
//  3       the local and the DUT
//  4       the local, the DUT and the 4 traps for ni test
write fpga2, 0x4400, 4;
wait 80;
reset;
nop;
wait 80;

include

// mask the ADCs with open inputs, first mask all
write         ADCMSK, 0x0


// specific to the Marcus Program:
// board no
const board_no = 4;

// Chip Position (ROB specific soon)
write ni0, 0x0C00, 12+16*board_no
write ni1, 0x0C00, 13+16*board_no
write ni2, 0x0C00, 14+16*board_no
write ni3, 0x0C00, 15+16*board_no
write dut, 0x0C00, 8+16*board_no

// Readout Flag, bit1: NI readout enable, bit0: SCSN readout enable (ROB specific soon)
write ni0, 0x0C02, 3
write ni0, 0x0C0A, 3
write ni0, 0x0C12, 3
write ni0, 0x0C1A, 3
write ni1, 0x0C02, 3
write ni1, 0x0C0A, 3
write ni1, 0x0C12, 3
write ni1, 0x0C1A, 3
write ni2, 0x0C02, 3
write ni2, 0x0C0A, 3
write ni2, 0x0C12, 3
write ni2, 0x0C1A, 3
write ni3, 0x0C02, 3
write ni3, 0x0C0A, 3
write ni3, 0x0C12, 3
write ni3, 0x0C1A, 3
write dut, 0x0C02, 3
write dut, 0x0C0A, 3
write dut, 0x0C12, 3
write dut, 0x0C1A, 3

// output delays optimized for the FPGA
// change to strobe mode for NI - ACEX board !!!
write dut, NED,    0x61D0;
write dut, NDLY, 0x024924924; // all 4