//***************************
//* ADCs                    *
//***************************
// ADC parameters, IRQ, sampling phase, en inp buffer, autozero, power

const power_backgr = 7; // 0..7
const power_pretr  = 7; // 0..7
const irq_phase    = 6; // 0..11
const smp_phase    = 5; // 0..11
const enibf_backgr = 0; // 0 or 1
const enibf_pretr  = 0; // 0 or 1
const az_backgr    = 1; // 0 or 1
const az_pretr     = 1; // 0 or 1

write ADCPAR, power_backgr | (az_backgr << 3) | (enibf_backgr << 4) | (power_pretr << 5) | (az_pretr << 8) | (enibf_pretr << 9) | (smp_phase << 10) | (irq_phase << 14)

// ADC parameters for simulation
//write ADCPAR, 011001010011100000b;

// invert bits
write ADCINB, 10b;

// ADC DAC 5-bit
// write ADCDAC, 11111b;
write ADCDAC, 10000b;
expect 1, ADCDAC, 10000b;

// ADC MASK - avoid storing bad data in filter
write ADCMSK, 0;

// permanent enable for ADC
write ADCEN, 1;

write ADCTST, 0;
expect 1, ADCTST, 0;

//***************************
//* CPUs                    *
//***************************

// speed up the transaction on the global bus, this is the maximal speed!
write ARBTIM, 0x0E;

// include the label information from the compilation, here are defined the addresses
// of the IRQ clear and IRQ acq

include cpu_labels.tcs

// switch off all unused clocks and LVDS cells
write NICLK,  0x00;
write FILCLK, 0x00;
write PRECLK, 0x00;
write NIODE,  0x00;
write NIOCE,  0x00;
write NIIDE,  0x00;
write NIICE,  0x00;

// Clock configuration CPUs - enable 2 CPUs!!!

//write CPU0CLK, 0x00;
write CPU1CLK, 0x00;
write CPU2CLK, 0x00;
//write CPU3CLK, 0x00;

//      CON[ 8] is the ADC address in local IO
//      CON[ 9] is the GIO start address to store the data
//      CON[12] number of samples
const constc = 0x0C00;
// CON[12] is the address in LIO
// select the ADC channel by writing the proper address
// 0x100..0x107 : CPU 0, ADC 0.. 7
// 0x100..0x107 : CPU 1, ADC 5..12
// 0x100..0x107 : CPU 2, ADC 9..16
// 0x100..0x107 : CPU 3, ADC13..20

write constc+0, 0x0100; // c8 of CPU0
write constc+1, 0x9000; // c9 of CPU0

write constc+0x18, 0x0106; // c8 of CPU3
write constc+0x19, 0xA000; // c9 of CPU3
//
// CON[13] is the number of samples
write constc+4, 0xFFC; // c12

const irq_clr = 0; // Note irq_clr is 4 in trap2!
const irq_acq = 2;
const irq_tst = 1;
const irq_eoc = 7;
const irq_mskhw = (1 << irq_tst) | (1 << irq_eoc);
const irq_mskhl = (1 << irq_tst);

//CPU0
//
// start address IRQ1 - tst
write IA0+irq_tst, lbl_TST_all;
// start address IRQ7 - eoc
write IA0+irq_eoc, lbl_EOC_all;
// enable hardw IRQ tst, eoc
write IRQHW0, irq_mskhw;
// set high level IRQ tst
write IRQHL0, irq_mskhl;

//CPU1
//
// start address IRQ1 - tst
write IA1+irq_tst, lbl_TST_all;
// start address IRQ7 - eoc
write IA1+irq_eoc, lbl_EOC_all;
// enable hardw IRQ tst, eoc
write IRQHW1, irq_mskhw;
// set high level IRQ tst
write IRQHL1, irq_mskhl;

//CPU2
//
// start address IRQ1 - tst
write IA2+irq_tst, lbl_TST_all;
// start address IRQ7 - eoc
write IA2+irq_eoc, lbl_EOC_all;
// enable hardw IRQ tst, eoc
write IRQHW2, irq_mskhw;
// set high level IRQ tst
write IRQHL2, irq_mskhl;

//CPU3
//
// start address IRQ1 - tst
write IA3+irq_tst, lbl_TST_all;
// start address IRQ7 - eoc
write IA3+irq_eoc, lbl_EOC_all;
// enable hardw IRQ tst, eoc
write IRQHW3, irq_mskhw;
// set high level IRQ tst
write IRQHL3, irq_mskhl;