LIBRARY IEEE;
library trap2;
library fpga2;
USE IEEE.STD_LOGIC_1164.all;

entity traps is
 generic (bdelay : time  :=  3 ns);  -- board delay
    port (
      -- to the test socket (DUT)
           -- 3.3V LVCMOS signals
           DUT_RST_n                  : in    std_logic;
           DUT_IRQ_n                  : in    std_logic;

           -- 3.3V LVCMOS signals - JTAG
           DUT_EN_JTAG                : in    std_logic; -- out_rng
           NI_EN_JTAG                 : in    std_logic_vector(3 downto 0); -- out_rng

           DUT_TCK                    : in    std_logic;
           DUT_TMS                    : in    std_logic;
           DUT_TDI                    : in    std_logic;
           DUT_TDO                    : out   std_logic;

           -- LVDS signals - clock and pretrigger outputs
           DUT_CLK                    : out   std_logic_vector(3 downto 0);
           DUT_PRE                    : out   std_logic_vector(3 downto 0);

           -- LVDS signals - NI output port
           DUT_P4_D                   : out   std_logic_vector(9 downto 0);
           DUT_P4_STR                 : out   std_logic;
           DUT_OA_CTR                 : out   std_logic;
           DUT_P4_CTR                 : in    std_logic;

           -- LVDS signals - SCSN interface
           DUT_SER0_IN                : out   std_logic;
           DUT_SER0_OUT               : in    std_logic;

           DUT_SER1_IN                : out   std_logic;
           DUT_SER1_OUT               : in    std_logic;
           -- LVCMOS signals
           DUT_SEBD                   : inout std_logic_vector( 2 downto 0);

        -- to the 4 TRAPs
           -- LVCMOS signals
           NI_RST_n                   : in    std_logic;
           NI_IRQ_n                   : in    std_logic;
           -- 3.3V LVCMOS signals - JTAG
           NI_TCK_up                  : in    std_logic;
           NI_TMS_up                  : in    std_logic;
           NI_TDI_up                  : in    std_logic;
           NI_TDO_up                  : out   std_logic;
           NI_TCK_dn                  : in    std_logic;
           NI_TMS_dn                  : in    std_logic;
           NI_TDI_dn                  : in    std_logic;
           NI_TDO_dn                  : out   std_logic;
           -- LVDS signals
           NI_CLK_up                  : in    std_logic;
           NI_CLK_dn                  : in    std_logic;
           NI_PRE_up                  : in    std_logic;
           NI_PRE_dn                  : in    std_logic;

           -- LVDS signals - SCSN interface
           NI_SER0_IN                 : out   std_logic;
           NI_SER0_OUT                : in    std_logic;

           NI_SER1_IN                 : out   std_logic;
           NI_SER1_OUT                : in    std_logic
           );
end traps;

architecture sim of traps is

component ni_port_stim is
  generic (
    filename    : string := "DATA/port_stim_tr.txt";       -- stimulus filename
    start       : integer := 5;                            -- start time
    period_time : time    := 10 ns;
    width       : integer := 10);                          -- port width
  port (
    start_n        : in  STD_LOGIC;
    p_strobe_in_0  : out STD_LOGIC;
    p_d_in_0       : out STD_LOGIC_VECTOR(width-1 downto 0);
    p_strobe_in_1  : out STD_LOGIC;
    p_d_in_1       : out STD_LOGIC_VECTOR(width-1 downto 0);
    p_strobe_in_2  : out STD_LOGIC;
    p_d_in_2       : out STD_LOGIC_VECTOR(width-1 downto 0);
    p_strobe_in_3  : out STD_LOGIC;
    p_d_in_3       : out STD_LOGIC_VECTOR(width-1 downto 0);
    p_ctrl_in      : out STD_LOGIC);
end component;

component pre_dec IS
PORT(
     CLK             : IN  STD_LOGIC; -- fast clock 120MHz
     RSTn            : IN  STD_LOGIC; -- global reset (active low)
     PRETRIGG        : IN  STD_LOGIC; -- pre-trigger input
     -- decoded outputs
     PTRGG           : OUT STD_LOGIC; -- pre-trigger detected
     CLEAR           : OUT STD_LOGIC; -- clear detected
     RESRV           : OUT STD_LOGIC; -- reserve function
     FUNC            : OUT STD_LOGIC_VECTOR(3 downto 0); -- global functions 0..3
     UNKNOWN         : OUT STD_LOGIC  -- reserve function
        );
END component;

signal PTRGG   : std_logic;
signal start_n : std_logic;

begin
        DUT_TDO     <= '0';

        -- LVDS signals - clock and pretrigger outputs
        DUT_CLK     <= transport (others => NI_CLK_up) after 1 ns;
        DUT_PRE     <= transport (others => NI_PRE_up) after 1 ns;

        -- LVDS signals - NI output port
--        DUT_P4_D    <= (others => '0');
--        DUT_P4_STR  <= '1';
--        DUT_OA_CTR  <= '0';

        -- LVDS signals - SCSN interface
        DUT_SER0_IN <= '0';

        DUT_SER1_IN <= '0';
        -- LVCMOS signals
        DUT_SEBD    <= (others => 'H');

        -- to the 4 TRAPs
        -- LVCMOS signals
        -- 3.3V LVCMOS signals - JTAG
        NI_TDO_up  <= '0';
        NI_TDO_dn  <= '0';

        -- LVDS signals - SCSN interface
        NI_SER0_IN <= '0';

        NI_SER1_IN <= '0';

pdec: pre_dec
      PORT map(
     CLK             => NI_CLK_up,
     RSTn            => NI_RST_n,
     PRETRIGG        => NI_PRE_up,
     -- decoded outputs
     PTRGG           => PTRGG,
     CLEAR           => open,
     RESRV           => open,
     FUNC            => open,
     UNKNOWN         => open);

    start_n <= not PTRGG;

trpni: ni_port_stim
--generic (
--  filename    : string := "DATA/port_stim_tr.txt";       -- stimulus filename
--  start       : integer := 5;                            -- start time
--  period_time : time    := 10 ns;
--  width       : integer := 10);                          -- port width
  port map(
    start_n        => start_n,
    p_strobe_in_0  => DUT_P4_STR,
    p_d_in_0       => DUT_P4_D,
    p_strobe_in_1  => open,
    p_d_in_1       => open,
    p_strobe_in_2  => open,
    p_d_in_2       => open,
    p_strobe_in_3  => open,
    p_d_in_3       => open,
    p_ctrl_in      => DUT_OA_CTR);
end;